Fourier transform device and wireless communication device

Abstract

This Fourier transform device for performing an N-point fast Fourier transform or inverse fast Fourier transform is provided with a rotator (222) that performs an rotation operation and a rotation memory (28) that stores twiddle factors. The rotation memory (28) includes: a first rotation memory (43) that stores a plurality of first twiddle factors corresponding to rotation positions obtained by dividing 2π into N1 equal parts (where N1 is an integer equal to the n1th power of 2 with n1 being an integer equal to or greater than 3); and a second rotation memory (44) that stores a plurality of second twiddle factors corresponding to rotation positions obtained by dividing 2π / N1 into N2 equal parts, where N / N1 is N2 (where N2 is an integer equal to the n2th power of 2 with n2 being an integer equal to or greater than 1). The rotator (222) is provided with: a first complex multiplier (41) in which one of the plurality of first twiddle factors is selectively set; and a second complex multiplier (42) that is connected in series to the first complex multiplier (41) and in which one of the plurality of second twiddle factors is selectively set.

Description

Fourier transform device and wireless communication device

[0001] The present invention relates to a Fourier transform device and a communication device that perform a fast Fourier transform (including an inverse fast Fourier transform). [Reference to Related Applications] This application claims the benefit of priority from Japanese Patent Application JP2023-209086, filed on December 12, 2023, the entire disclosure of which is incorporated herein by reference.

[0002] Fast Fourier transform (hereinafter also referred to as "FFT") has been used in various fields. When implementing FFT in hardware, various studies have been conducted with the aim of increasing the processing speed, improving efficiency, reducing memory usage, etc., as shown in Mario Garrido, "A Survey on Pipelined FFT Hardware Architectures", Journal of Signal Processing Systems (2022) 94:1345-1364 (Reference 1). One of the architectures for efficiently executing FFT is "Radix-2" (Radix-2). ｋ " (Mario Garrido and three others, "Pipelined Radix-2 k "Feedforward FFT Architectures", IEEE TRANS. VLSI SYSTEMS, VOL. 21, NO. 1, pp. 23-32, JANUARY 2013 (Reference 2)).Radix-2 ｋ k represents an integer of 2 or more, for example, Radix-2 ４ The algorithm was proposed by Jung-Yeol OH and another author, "New Radix-2 to the 4th Power Pipeline FFT Processor," IEICE TRANS. ELECTRON., VOL. E88-C, NO. 8, pp. 1740-1746, AUGUST 2005 (Reference 3). ｋ By adopting this algorithm, it is possible to simplify the calculation of the rotation factor in the FFT. ｋThe "k" in the above is not related to the variable k in the Fourier transform described below.

[0003] On the other hand, methods for reducing the area for storing twiddle factors in FFT have also been proposed. For example, Japanese Patent Laid-Open Publication No. 5-324697 (Document 4) discloses a technique for reducing memory usage by focusing on the phase shift between a cos function and a sin function with respect to twiddle factors and the symmetry between positive and negative values ​​thereof, and storing only the positive values ​​of trigonometric functions in memory without duplicating twiddle factors. Furthermore, Japanese Patent Laid-Open Publication No. 4-177461 (Document 5) discloses a technique for realizing faster calculations and reduced memory capacity for storing data by using fixed-point calculations using integer arithmetic instead of double-precision floating-point calculations in FFT calculations.

[0004] Incidentally, FFT uses a rotation matrix called a twiddle factor, which corresponds to the rotation positions obtained by dividing a unit circle on a complex plane into N equal parts. The twiddle factor is a combination of the values ​​of a cos function and a sine function, and in order to achieve high frequency differentiation in FFT, it is necessary to store a large number of twiddle factors. This requires a storage device with a large storage capacity, which increases the manufacturing cost of the Fourier transform device. However, simply utilizing the symmetry of the cos function and the sine function, as in Reference 4, has a limit to the reduction in the storage capacity required to store the twiddle factors.

[0005] Reducing the storage capacity for storing twiddle factors is particularly important when implementing an FFT in a field programmable gate array (FPGA) or the like, where the paths for reading out twiddle factors are limited by hardware. Note that the reduction in storage capacity for storing twiddle factors also applies to an inverse fast Fourier transform (IFFT).

[0006] The object of the present invention is to reduce the storage capacity required to store twiddle factors in a Fourier transform device.

[0007] A first aspect of the present invention is a Fourier transform device that performs an N-point (where N is the nth power of 2 and n is an integer of 5 or greater) fast Fourier transform or inverse fast Fourier transform, and includes a rotator that performs a rotation operation and a rotation memory that stores twiddle factors.

[0008] The rotation memory includes a first rotation memory that stores a plurality of first twiddle factors corresponding to rotation positions obtained by dividing 2π into N1 equal parts (where n1 is an integer greater than or equal to 3 and N1 is an integer that is 2 to the n1 power), and a second rotation memory that stores a plurality of second twiddle factors corresponding to rotation positions obtained by dividing 2π / N1 into N2 equal parts (where N / N1 is an integer greater than or equal to 1 and N2 is an integer that is 2 to the n2 power), and the rotator performs a rotation operation combining a first twiddle factor selected from the plurality of first twiddle factors and a second twiddle factor selected from the plurality of second twiddle factors.

[0009] According to the present invention, it is possible to reduce the storage capacity required to store twiddle factors in a Fourier transform device.

[0010] A second aspect of the present invention is the Fourier transform device of the first aspect, which is characterized by the fact that Radix-2 ｋ Radix-2 performs calculations using algorithms ｋ a circuit, and the rotator is the Radix-2 ｋ or connected to the circuit ｋ Included in the circuit.

[0011] Aspect 3 of the present invention is the Fourier transform device of aspect 2, further comprising a plurality of sub-Fourier transform circuits arranged in parallel, each of which is a circuit for performing a Fourier transform or an inverse Fourier transform with a single input / output, and the Radix-2 is provided downstream of the plurality of sub-Fourier transform circuits. ｋ A circuit is arranged, and a plurality of rotators including the rotator are arranged to rotate the plurality of fractional Fourier transform circuits and the Radix-2 ｋ It is a multipath-delay-feedback type placed between the circuits.

[0012] A fourth aspect of the present invention is the Fourier transform device of the third aspect, wherein the number of the plurality of sub-Fourier transform circuits is P (where P is the pth power of 2, and p is an integer equal to or greater than 2), and (P-1) rotators including the rotator are connected to the plurality of sub-Fourier transform circuits and the Radix-2 ｋ It is a multipath-delay-feedback type placed between the circuits.

[0013] A fifth aspect of the present invention is the Fourier transform device of the second aspect, further comprising 16 sub-Fourier transform circuits arranged in parallel, each of which is a circuit for performing a Fourier transform or an inverse Fourier transform with a single input / output, and the Radix-2 sub-Fourier transform circuit is arranged downstream of the plurality of sub-Fourier transform circuits. ｋ Radix-2 is a circuit ４ The circuit is arranged such that 15 rotators including the rotator are connected to the 16 sub-Fourier transform circuits and the Radix-2 ４ It is a multipath-delay-feedback type placed between the circuits.

[0014] A sixth aspect of the present invention is a Fourier transform device according to the first aspect (which may be any one of the first to fifth aspects), in which a digital signal obtained by digitally converting an analog signal having a bandwidth of 4 GHz or more is input, and the frequency resolution at the output is 100 kHz or less, or the frequency resolution of the input frequency information is 100 kHz or less, and the bandwidth of the analog signal obtained by analog converting the digital signal to be output is 4 GHz or more.

[0015] A seventh aspect of the present invention is the Fourier transform device of the sixth aspect, wherein the frequency resolution in the output is 50 kHz or less, or the frequency resolution in the input frequency information is 50 kHz or less.

[0016] Aspect 8 of the present invention is a Fourier transform device according to any one of aspects 1 to 7, which performs frequency analysis on a digital signal converted from a high-frequency analog signal of 300 MHz or more and 300 GHz or less, and which performs the fast Fourier transform.

[0017] A ninth aspect of the present invention is a wireless communication device comprising an analog-to-digital converter or a digital-to-analog converter connected to an antenna, and the Fourier transform device according to any one of the first to seventh aspects, which performs a Fourier transform on a digital signal output from the analog-to-digital converter, or performs an inverse Fourier transform on digital information and sends it to the digital-to-analog converter.

[0018] The above and other objects, features, aspects and advantages will become more apparent from the following detailed description of the invention which proceeds with reference to the accompanying drawings.

[0019] FIG. 1 is a diagram showing a schematic configuration of a frequency analysis device including a Fourier transform device; FIG. 2 is a diagram showing a configuration of an FFT circuit; FIG. 3 is a diagram showing a butterfly computing unit; FIG. 4 is a diagram illustrating a small FFT circuit; FIG. 5 is a diagram showing a configuration of a (first) rotator and a rotation memory connected thereto; FIG. 6 is a diagram showing another configuration example of an FFT circuit; FIG. 7 is a diagram showing yet another configuration example of an FFT circuit; FIG. 8 is a diagram illustrating a configuration of a communication system; FIG. 9 is a diagram showing another example of a rotator and a rotation memory connected thereto.

[0020] FIG. 1 is a diagram showing a schematic configuration of a frequency analysis device 10 including a Fourier transform device 12 according to one embodiment of the present invention. The frequency analysis device 10 includes an A / D (analog-to-digital) converter 11, a Fourier transform device 12, an analysis processing unit 13, and a display unit 14. The A / D converter 11 is electrically connected to an antenna 15. The antenna 15 may be considered to be part of the frequency analysis device 10. Conversely, the A / D converter 11 may be considered to be separate from the frequency analysis device 10. The device that inputs a signal to the A / D converter 11 is not limited to the antenna 15; a high-frequency analog signal, such as a high-frequency signal generating circuit or noise components generated in an electrical circuit, may also be input to the A / D converter 11. In other words, the frequency analysis device 10 may be used to measure high-frequency signal (RF) circuits.

[0021] The antenna 15 converts the electromagnetic waves into an electrical analog signal and outputs it to the A / D converter 11. The A / D converter 11 samples the analog signal at high speed and at regular intervals and converts it into a digital signal, i.e., an array of time-series numerical values. Note that the analog signal may be input to the A / D converter 11 after the frequency band of the analog signal is shifted to a lower frequency by a mixer.

[0022] The Fourier transform device 12 receives the array of numerical values ​​(hereinafter also referred to as "input data") from the A / D converter 11, converts the input data into an array of numerical values ​​(hereinafter also referred to as "output data") indicating the amplitude for each frequency, and outputs the converted data. That is, it performs a fast Fourier transform (FFT) on the input data indicating values ​​that change over time, and converts the input data into output data indicating the magnitude of components in the frequency domain.

[0023] The analysis processing unit 13 converts the output data from the Fourier transform device 12 into information suitable for display on the display unit 14. For example, the analysis processing unit 13 averages the output data repeatedly output at high speed from the Fourier transform device 12 for each frequency at regular time intervals and outputs the averaged data. This allows a person observing the display unit 14 to properly grasp the analysis results in real time.

[0024] The frequency analysis device 10 can be used for a variety of purposes, and is particularly suitable for cases where wideband and continuous measurement is required. The frequency analysis device 10 can be applied, for example, to frequency measurement in radio astronomy observations, multiplexed readout technology for superconducting detectors, communication technology, etc. The details of the antenna 15 and the frequency analysis device 10 are appropriately configured according to the application. For example, the antenna 15 may be an antenna for receiving radio waves from space, an antenna used for wireless communication, or the like. Of course, the frequency analysis device 10 can be used in various other frequency analysis fields.

[0025] As will be described later, the Fourier transform device 12 included in the frequency analysis device 10 can reduce the storage capacity required to store twiddle factors, thereby reducing the manufacturing cost of the analysis device. This effect is particularly noticeable when the Fourier transform device 12 is implemented as hardware. Power consumption is also reduced.

[0026] For example, in the field of radio astronomy, dark matter observation in outer space requires real-time frequency analysis of radio waves from outer space. Therefore, high-speed FFT calculations must be implemented as hardware using electrical circuits such as FPGAs and ASICs (Application Specific Integrated Circuits). However, performing FFTs at high speed and with high frequency resolution requires a huge amount of storage capacity for twiddle factors, which is impossible to achieve with commercially available hardware such as FPGAs. The Fourier transform device 12 described below can significantly reduce the storage capacity required to store twiddle factors while suppressing a decrease in calculation speed, thereby reducing the circuit scale on the hardware, including memory, and enabling implementation on commercially available hardware.

[0027] FIG. 2 is a diagram showing the configuration of the FFT circuit 2 included in the Fourier transform device 12. In FIG. 2, the left side is the input side of the FFT circuit 2, and the right side is the output side. From the input side to the output side, the FFT circuit 2 includes a small FFT circuit group 211, a first rotator group 212, a first butterfly operator group 213, a second rotator group 214, a second butterfly operator group 215, a third rotator group 216, a third butterfly operator group 217, a fourth rotator group 218, and a fourth butterfly operator group 219. Note that a "group" refers to a collection of one or more identical or similar elements. The small FFT circuit group 211 includes 16 small FFT circuits 221, each of which performs an FFT operation. As described below, each small FFT circuit 221 is a single-input / single-output FFT circuit.

[0028] The first rotator group 212 includes 15 first rotators 222, each of which can be set to a selected rotation factor, as described below. A "rotator" is a circuit that performs a rotation operation by multiplying a rotation matrix. The second rotator group 214 includes four second rotators 224, but the rotation performed by the second rotators 224 is fixed to a 90-degree rotation operation. In FIG. 2, a rotator that performs a 90-degree rotation operation is represented by "-i" (the same applies below). The fourth rotator group 218 is similar to the second rotator group 214 and includes four first rotators 228 that perform a 90-degree rotation operation. The third rotator group 216 includes nine third rotators 226. These rotators perform rotation operations of various rotation angles, but the rotation angle of each third rotator 226 is fixed.

[0029] The first butterfly operator group 213 has eight first butterfly operators 223. The second butterfly operator group 215 has eight second butterfly operators 225. The third butterfly operator group 217 has eight third butterfly operators 227. The fourth butterfly operator group 219 has eight fourth butterfly operators 229. In FIG. 2, the butterfly operators are indicated by "R2" (the same applies below). FIG. 3 is a diagram showing one butterfly operator 30 (corresponding to the first to fourth butterfly operators 223, 225, 227, 229). When values ​​A and B are input to the butterfly operator 30, the butterfly operator 30 outputs values ​​(A+B) and (A-B).

[0030] Next, we will explain the calculations corresponding to the configuration of the FFT circuit 2. Mathematical formula 1 represents a discrete Fourier transform of size N, i.e., a formula for Fourier transforming N samples. Here, N is the nth power of 2, and in this embodiment, n is an integer equal to or greater than 5. Through the Fourier transform, a function x(t) with time t as a variable is converted into a function x tilde(k) with frequency k as a variable (hereinafter, x tilde with ~ added above x will also be expressed as "x~"). In other words, through the Fourier transform, time series data x(t) is converted into spectrum data x~(k).

[0031]

[0032] Here, the right-hand side shows the sum of the equations in Σ when t is changed from 0 to (N-1), but if we set t = t' + 16t'', and divide Equation 1 by the remainder t' when t is divided by 16, we get Equation 2.

[0033]

[0034] In Equation 2, the left Σ of the two Σ indicates division into 16, and the right Σ portion indicates the remainder t' term extracted. The size of the right Σ portion is N / 16.

[0035] Here, if we let k = (N / 16)k' + k'', then Equation 2 becomes Equation 3. Furthermore, e to the (-2πi) power is a rotation of 2π, that is, 1, and e to the (-2πi) power of an integer multiple is also 1, so the right-hand side of Equation 3 becomes Equation 4.

[0036]

[0037]

[0038] In Equation 4, the rightmost x(t'+16t") marked with (4-1) indicates the input value. The Σ part to the left of it marked with (4-2) indicates an N / 16-point discrete Fourier transform that converts a function of t" into a function of k". The next part, e raised to the (-2πi(k"t' / N)) power marked with (4-3), indicates a twiddle factor.

[0039] For the leftmost Σ part marked with (4-4), k' = 8k' ０ +4k' １ +2k' ２ +k' ３ (where k' ０ , k' １ , k' ２ , k' ３ is 0 or 1.) and t' = t' ０ +2t' １ +4t' ２ +8t' ３ (However, t' ０ , t' １ , t' ２ , t' ３ is 0 or 1. If we set (4-4) in equation 4, the part with (4-4) becomes equation 5. Here too, we use the fact that the integral multiple of e to the power of (-2πi) is 1.４ This indicates the (main) calculation part to which the algorithm is applied.

[0040]

[0041] Next, the correspondence between the FFT circuit 2 in FIG. 2 and Equations 4 and 5 will be described.

[0042] 2 corresponds to (4-1) in Equation 4. The small FFT circuit group 211 corresponds to (4-2) in Equation 4. That is, each small FFT circuit 221 performs an N / 16-point discrete fast Fourier transform, converting a function of t" into a function of k".

[0043] FIG. 4 illustrates one small FFT circuit 221. The small FFT circuit 221 in FIG. 4 is a one-input, one-output Fourier transform circuit. Various configurations other than that shown in FIG. 4 can be adopted for the small FFT circuit 221. The small FFT circuit 221 in FIG. 4 includes multiple butterfly operators 31. Each butterfly operator 31 performs the same calculation as the butterfly operator 30 shown in FIG. 3. A delay memory 32 is connected to each butterfly operator 31, and the values ​​input to and output from the butterfly operator 31 are appropriately stored so that they can be output at the desired timing. Rotators 33 and rotators 35 (denoted by "-i") fixed at 90° rotation are provided between the serially connected butterfly operators 31 as needed. One of multiple twiddle factors stored in a rotation memory 34 is selected and set in the rotator 33. The rotation memory 34 stores rotation factors for performing N / 16-point FFT calculations.

[0044] The first rotator group 212 in FIG. 2 corresponds to the part indicated by (4-3) in Equation 4, and rotates 2π (m / N) by W Ｎ ｍ Each W Ｎ ｍ m is k"t'. Each first rotator 222 has W Ｎ ｍ The twiddle factor is set for each operation.

[0045] The first butterfly computing unit group 213 corresponds to the rightmost Σ part shown in (5-1) of the formula 5. Each first butterfly computing unit 223 has a t' ２ , t' １ and t' ０ are the same value, and t' ３ The first rotator group 212 and the first butterfly operator group 213 are connected so that values ​​of 0 and 1 are input. For example, the topmost first butterfly operator 223 receives as input a value from the topmost small FFT circuit 221 and a value derived from the ninth small FFT circuit 221 from the top. The ninth input is the first input and t' ３ The first butterfly operation unit group 213 differs only in the value of t'. ３ かk' ３ (To be precise, t' ３ The function k' is ３ It is converted into a function with variables. The same expression will be used below.)

[0046] The second rotator group 214 corresponds to the part indicated by (5-2) in Equation 5. Here, k' ３ t' ２ is 0 or 1, a rotation operation of 0 (i.e., no rotation) or 2π / 4 (=90°) is performed in (the position of) the second rotator group 214. Only four second rotators 224 are provided as the second rotator group 214, and each second rotator 224 performs a fixed operation.

[0047] The second butterfly computing unit group 215 corresponds to the second Σ part from the right shown in (5-3) of the formula 5. Each second butterfly computing unit 225 has k' ３ , t' １ and t' ０ are the same value, and t' ２ The second rotator group 214 and the second butterfly operator group 215 are connected so that t' is input as 0 and t' is input as 1. ２ かk' ２ is converted to

[0048] The third rotator group 216 corresponds to the part indicated by (5-4) in equation 5. Here, (2k' ２ +k'３ ) (t' ０ +2t' １ ) / 16 is 0, 1, 2, 3, 4, 6, or 9, so the third rotator group 216 (at its position) performs rotation operations of 0 (i.e., no rotation), 2π / 16 (=22.5°), 2π / 8 (=45°), 2π 3 / 16 (=67.5°), 2π / 4 (=90°), 2π 3 / 8 (=135°), and 2π 9 / 16 (=202.5°). Only nine third rotators 226 are provided as the third rotator group 216, and each third rotator 226 performs a fixed operation.

[0049] The third butterfly computing unit group 217 corresponds to the third Σ part from the right shown in (5-5) of the equation 5. Each third butterfly computing unit 227 has k' ３ , k' ２ and t' ０ are the same value, and t' １ The third rotator group 216 and the third butterfly operator group 217 are connected so that t' is input as 0 and t' is input as 1. １ かk' １ is converted to

[0050] The fourth rotator group 218 corresponds to the part indicated by (5-6) in Equation 5. Here, k' １ t' ０ is 0 or 1, a rotation operation of 0 (i.e., no rotation) or 2π / 4 (=90°) is performed in (the position of) the fourth rotator group 218. Only four fourth rotators 228 are provided as the fourth rotator group 218, and each fourth rotator 228 performs a fixed operation.

[0051] The fourth butterfly operator group 219 corresponds to the fourth Σ part from the right shown in (5-7) of the equation 5. Each fourth butterfly operator 229 has k' ３ , k' ２ and k' １ are the same value, and t' ０ The fourth rotator group 218 and the fourth butterfly operator group 219 are connected so that t' is input as 0 and t' is input as 1. ０ かk' ０is converted to

[0052] Through the above processing, when the inputs x(16t"), x(16t"+1), x(16t"+2), ..., x(16t"+15) are input sequentially in parallel, x~(k"), x~(k"+(1 / 16)N), x~(k"+(2 / 16)N), ..., x~(k"+(15 / 16)N) (however, the output order is as shown on the right side of Figure 2 (Output)) is output sequentially in parallel.

[0053] Next, the first rotator group 212 will be described. FIG. 5 is a diagram showing the configuration of one first rotator 222 and the rotation memory 28 connected thereto. The rotation memory 28 stores twiddle factors. The rotation memory 28 is shared by all the first rotators 222 in the first rotator group 212. That is, one rotation memory 28 (more precisely, a set of a first complex multiplier 41 and a second complex multiplier 42, described later) is provided for the first rotator group 212. The first rotator 222 includes a first complex multiplier 41 and a second complex multiplier 42. The first complex multiplier 41 and the second complex multiplier 42 are connected in series. Each of the first complex multiplier 41 and the second complex multiplier 42 is an arithmetic unit that multiplies a rotation matrix, and each is a rotator. That is, the first rotator 222 is two rotators connected in series. The rotation memory 28 includes a first rotation memory 43 and a second rotation memory 44. The first complex multiplier 41 is connected to the first rotation memory 43. The second complex multiplier 42 is connected to the second rotation memory 44.

[0054] The first rotation memory 43 stores N1 first twiddle factors corresponding to rotation positions (rotation positions on a unit circle centered at the origin, which can also be expressed as rotation angles or rotation amounts from the 0° position) obtained by dividing 2π into N1 equal parts. Here, n1 is an integer equal to or greater than 3, and N1 is an integer equal to 2 to the n1th power. A "twiddle factor corresponding to a rotation position" refers to a twiddle factor that rotates by an angle from the 0° position on a unit circle in a complex plane to a rotation position of interest. Meanwhile, the second rotation memory 44 stores N2 second twiddle factors corresponding to rotation positions obtained by dividing 2π / N1 into N2 equal parts, where N2 is an integer equal to or greater than 1, and N2 is an integer equal to 2 to the n2th power. n is n1 + n2, and is 5 or greater.

[0055] In other words, the first rotation memory 43 stores a first twiddle factor that rotates by (2π / N1)·a (where a is an integer and 0≦a<N1), and the second rotation memory 44 stores a second twiddle factor that rotates by (2π / N)·b (where b is an integer and 0≦b<N2). In this way, the second twiddle factor corresponds to a precise rotation angle that interpolates between coarse rotation positions corresponding to the plurality of first twiddle factors. One of the plurality of first twiddle factors is selectively set in the first complex multiplier 41, and one of the plurality of second twiddle factors is selectively set in the second complex multiplier 42. By connecting the first complex multiplier 41 and the second complex multiplier 42 in series, multiplication of the rotation matrices that are the first and second twiddle factors is performed, and a rotation calculation is performed using the rotation angle obtained by adding the rotation angles indicated by both twiddle factors.

[0056] In the actually fabricated FFT circuit 2, N is 2 to the power of 17 (2 １７ ), and N1 is 2 to the power of 10 (2 １０ ), and N2 is 2 to the power of 7 (2 ７ ) in the first rotation memory 43. １０ complex numbers are stored (effectively), and 2 real numbers are stored. １１ The second rotation memory 44 stores 2 ７ complex numbers are stored, and 2 real numbers are stored. ８However, in reality, the number of complex numbers stored in the first rotation memory 43 can be reduced to 1 / 4 due to the symmetry of every π / 2 rotation, and further, the number of real numbers to be stored can be further reduced to 1 / 2 based on the symmetry of the sine function and the cosine function. In other words, the number of real numbers required to store the first twiddle factors in the first rotation memory 43 is 2 １０ × 2 / 8 (= 2 ８ )

[0057] If the first rotator 222 is implemented by one complex arithmetic unit (hereinafter, this case will be referred to as a "comparative example"), the number of real numbers required to store the twiddle factors is 2. １５ (=2 １７ However, in the case of the first rotator 222 of FIG. 5, the number of real numbers to be stored in the first rotation memory 43 and the second rotation memory 44 is 2 ９ (=2 ８ +2 ８ ) and 2 ６ It will be reduced to one-fifth.

[0058] The small FFT circuit 221 also uses Radix-2 ｋ algorithm (hereinafter simply referred to as "Radix-2 ｋ "). By constructing the Radix-2 as a single-input / output circuit that applies Radix-2, the number of rotators to be applied, which is N / 16, can be reduced to one for each small FFT circuit 221. Such rotators exist in parallel in 16 small FFT circuits 221, and refer to the rotation memory that stores the twiddle factors set in the rotators at the same time, so that the rotation memory can be shared by multiple rotators. ｋ By applying this, the number of twiddle factors set in the other rotators of each small FFT circuit 221 can be set to, for example, N / 64 or less, although this depends on the method of implementation in hardware, and the number of twiddle factors (complex numbers) to be stored in the small FFT circuit group 211 as a whole can be set to N / 8 to N / 16. As mentioned above, the number of real numbers actually stored is 1 / 4 of the number of complex numbers, and when N is 2, １７ In this case, the number of real numbers stored is 2 １２ ~2 １１ is.

[0059] On the other hand, when the first rotator 222 is divided into the first complex multiplier 41 and the second complex multiplier 42, the number of real numbers to be stored in the rotation memory 28 is N=2. １７ In the case of 2 １５ From 2 ９ Therefore, even in the entire FFT circuit 2 taking the small FFT circuit group 211 into consideration, the effect of reducing the storage capacity by the structure of FIG. 5 is high.

[0060] Next, considering the increase in the amount of calculation, the first rotator 222 in the comparative example performs one multiplication (more precisely, multiplication of a rotation matrix having real numbers as elements, and the same applies below), whereas the first rotator 222 in FIG. 5 performs two multiplications. １７ In this case, N / 16 is 2 １３ 4 is six, the small FFT circuit 221 performs six multiplications. The 90° rotator 35 only swaps the sign, so no multiplications are performed. Furthermore, downstream of the first rotator group 212 in FIG. 2, only the third rotator group 216 performs real multiplications. Therefore, when the first rotator 222 is configured with one complex multiplier, the number of multiplications is eight, but when it is configured with the first complex multiplier 41 and the second complex multiplier 42, the number of multiplications is nine, which means that the amount of calculations increases by only about 1.1 times.

[0061] In this way, the FFT circuit 2 can significantly reduce the storage capacity required to store the twiddle factors while suppressing an increase in the amount of calculations, and this also makes it possible to implement the FFT circuit 2 at low cost using commercially available hardware such as FPGA.

[0062] Next, another example configuration of the FFT circuit 2 will be described with reference to Fig. 6. The FFT circuit 2 in Fig. 6 has, in order from the input side to the output side, a small FFT circuit group 231, a first rotator group 232, a first butterfly operator group 233, a second rotator group 234, and a second butterfly operator group 235. The small FFT circuit group 231 consists of four small FFT circuits 241, each of which performs an FFT operation. Each small FFT circuit 241 is a one-input, one-output Fourier transform circuit.

[0063] The first rotator group 232 has three rotators 242, each of which can be set to a selected twiddle factor, as described below. The second rotator group 234 has one second rotator 244, but the rotation by the second rotator 244 is fixed to a 90° rotation operation. The first butterfly operator group 233 has two first butterfly operators 243. The second butterfly operator group 235 has two second butterfly operators 245.

[0064] Next, the calculation corresponding to the configuration of the FFT circuit 2 in Fig. 6 will be described. Equation 6 shows a discrete Fourier transform of size N, which represents the transform portion of Equation 1. Here, N is the nth power of 2, and in this embodiment, n is an integer equal to or greater than 5. By the Fourier transform, a function x(t) with time t as a variable to be transformed is transformed into a function x~(k) with frequency k as a variable (see the input (Input) on the left side and the output (Output) on the right side of Fig. 6).

[0065]

[0066] Here, if k=(N / 4)k'+k'' and t=t'+4t'', and the discrete Fourier transform of size N is divided into discrete Fourier transforms of size (N / 4) and size 4, then Equation 7 is obtained.

[0067]

[0068] In Equation 7, the Σ part on the left side shown by (7-3) indicates a four-way division, and the Σ part on the right side shown by (7-1) indicates an N / 4-point discrete Fourier transform that transforms a function of t" into a function of k". The (-2πi(k"t' / N)) power of e, which is given by (7-2), indicates a rotation factor.

[0069] For the leftmost Σ part labeled (7-3), k' = 2k' ０ +k' １ (where k' ０ , k' １ is 0 or 1.) and t' = t' ０ +2t' １ (However, t' ０ , t' １ is 0 or 1.) Then, the part of number 7 marked with (7-3) becomes number 8. Number 8 is Radix-2２ indicates the (main) calculation part to which

[0070]

[0071] Next, the correspondence between the FFT circuit 2 in FIG. 6 and Equations 7 and 8 will be described.

[0072] The leftmost input in FIG. 6 is x(t), that is, x(4t"+t'). The small FFT circuit group 231 corresponds to the portion shown by (7-1) in equation 7. That is, each small FFT circuit 241 performs an N / 4-point discrete fast Fourier transform, and converts a function of t" into a function of k". Various specific configurations can be adopted for the single-input / output small FFT circuit 241.

[0073] The first rotator group 232 corresponds to (7-2) in Equation 7. Ｎ ｍ m is k"t'. Each first rotator 242 has W Ｎ ｍ The twiddle factor is set for each operation.

[0074] The first group of butterfly operators 233 corresponds to the rightmost Σ part shown as (8-1) in equation 8. The first group of butterfly operators 233 calculates t' １ かk' １ The second rotator group 234 corresponds to the part indicated by (8-2) in Equation 8. Here, k' １ t' ０ is 0 or 1, a rotation operation of 0 (i.e., no rotation) or 2πi / 4 (=90°) is performed at (the position of) the second rotator group 234. As described above, only one second rotator 244 is provided as the second rotator group 234.

[0075] The second group of butterfly operators 235 corresponds to the rightmost Σ part shown in (8-3) of equation 8. The second group of butterfly operators 235 calculates t' ０ かk' ０ is converted to

[0076] With the above processing, when the inputs x(4t"), x(4t"+1), x(4t"+2), and x(4t"+3) are input sequentially in parallel, x~(k"), x~(k"+(1 / 4)N), x~(k"+(2 / 4)N), and x~(k"+(3 / 4)N) (however, the output order is as shown in FIG. 6) are output sequentially in parallel.

[0077] The configuration of FIG. 5 is also employed for each first rotator 242 in FIG. 6 . That is, the first rotator 242 includes a first complex multiplier 41 and a second complex multiplier 42, each of which is a rotator. The first complex multiplier 41 and the second complex multiplier 42 are connected in series. A first rotation memory 43 is connected to the first complex multiplier 41, and a second rotation memory 44 is connected to the second complex multiplier 42. The first rotation memory 43 stores N1 first twiddle factors corresponding to rotation positions obtained by dividing 2π into N1 equal parts, where n1 is an integer equal to or greater than 3 and N1 is an integer equal to 2 to the n1 power. Meanwhile, the second rotation memory 44 stores N2 second twiddle factors corresponding to rotation positions obtained by dividing 2π / N1 into N2 equal parts, where N2 is an integer equal to or greater than 1 and N2 is an integer equal to 2 to the n2 power, with N2 = N / N1 (i.e., N = N1 × N2). Here, n is n1+n2 and is equal to or greater than 5. Any one of a plurality of first twiddle factors is selectively set in the first complex multiplier 41, and any one of a plurality of second twiddle factors is selectively set in the second complex multiplier 42.

[0078] The twiddle factors set in the first rotator 242 are stored in a first rotation memory 43 that stores first twiddle factors corresponding to coarse rotation positions, and a second rotation memory 44 that stores second twiddle factors corresponding to rotation angles that interpolate between the coarse rotation positions, thereby making it possible to significantly reduce the storage capacity required to store the twiddle factors. １７ In this case, as in the case of FIG. 2, the number of real numbers to be stored in the first rotation memory 43 and the second rotation memory 44 is twice as large as in the case where the rotation factors are not stored separately for the coarse rotation position and the interpolated rotation angle. ６ It will be reduced to one-fifth.

[0079] The small FFT circuit 241 also uses Radix-2 ｋBy constructing the circuit as a single input / output circuit applying Radix-2, the number of rotators to be applied, which is N / 4, can be reduced to one. Furthermore, since such rotators exist in parallel in the four small FFT circuits 221, the rotation memory that stores the twiddle factors set in the rotators can be shared. The small FFT circuit 241 also uses Radix-2 ｋ When the above-mentioned structure is applied, the storage capacity required for storing the rotators in the small FFT circuit group 231 is reduced, and therefore the storage capacity required for the entire FFT circuit 2 is reduced. Therefore, the reduction rate of the storage capacity for the entire FFT circuit 2 when the structure of FIG. 5 is provided is large.

[0080] Furthermore, by using the configuration of FIG. 5 for the rotator in which the number of twiddle factors to be applied in the sub-FFT circuit 241 is N / 4, the required storage capacity can be further reduced.

[0081] Next, when considering the increase in the amount of calculation, in the small FFT circuit 241, N=2 １７ In this case, N / 4 is 2 １５ 4 , assuming that the number of rotators 33 is seven, seven multiplications are performed in the small FFT circuit 241. The 90° rotator 35 only swaps signs, so no multiplications are performed. Furthermore, no multiplications are substantially performed downstream of the first rotator group 232 in FIG. 6 . Therefore, if the first rotator 242 is configured with one complex multiplier, eight multiplications are performed, but if it is configured with the first complex multiplier 41 and the second complex multiplier 42, nine multiplications are performed, resulting in an increase in the amount of calculations of only about 1.1 times. Even if the configuration of FIG. 5 is further adopted for the rotator to which the largest number of twiddle factors is applied within the small FFT circuit 241, the amount of calculations increases by only about 1.25 times.

[0082] 6, the storage capacity required to store the twiddle factors can be significantly reduced while suppressing an increase in the amount of calculations, which makes it possible to realize the FFT circuit 2 at low cost using commercially available hardware such as FPGA.

[0083] Next, another example configuration of the FFT circuit 2 will be described with reference to Fig. 7. The FFT circuit 2 in Fig. 7 includes, in order from the input side to the output side, a small FFT circuit group 251, a first rotator group 252, a first butterfly operator group 253, a second rotator group 254, a second butterfly operator group 255, a third rotator group 256, a third butterfly operator group 257, a fourth rotator group 258, and a fourth butterfly operator group 259. The small FFT circuit group 251 includes 16 small FFT circuits 261, each of which performs an FFT operation. Each small FFT circuit 261 is a single-input / output Fourier transform circuit.

[0084] The first rotator group 252 includes twelve first rotators 262, each of which can be set to a selected twiddle factor. The second rotator group 254 includes four second rotators 264, but the rotation by the second rotators 264 is fixed to a 90° rotation operation. The third rotator group 256 includes twelve third rotators 266, each of which can be set to a selected twiddle factor. The fourth rotator group 258 includes four fourth rotators 268, but the rotation by the fourth rotators 268 is fixed to a 90° rotation operation.

[0085] The first butterfly operator group 253 has eight first butterfly operators 263. The second butterfly operator group 255 has eight second butterfly operators 265. The third butterfly operator group 257 has eight third butterfly operators 267. The fourth butterfly operator group 259 has eight fourth butterfly operators 269.

[0086] Next, the calculation corresponding to the configuration of the FFT circuit 2 in Fig. 7 will be described. First, let k = (N / 16) k' + k'', t = t' + 16'', and then let k' = 8k' ０ +4k' １ +2k' ２ +k' ３ (where k' ０ , k' １ , k' ２ , k' ３ is 0 or 1.) and t' = t' ０ +2t' １ +4t' ２ +8t' ３(However, t' ０ , t' １ , t' ２ , t' ３ is 0 or 1.) and divide the discrete Fourier transform of size N in equation (6) into discrete Fourier transforms of size (N / 16) and size 4 to obtain equation (9).

[0087]

[0088] In Equation 9, the Σ part on the left side indicated by (9-3) represents a four-way division, and the Σ part on the right side indicated by (9-1) represents an N / 4-point discrete Fourier transform. The power of e indicated by (9-2) represents a twiddle factor.

[0089] If we further divide the rightmost Σ part labeled (9-1) into discrete Fourier transforms of size (N / 16) and size 4, we get equation 10. In equation 10, the rightmost part labeled (10-1) represents the N / 16-point discrete Fourier transform. The part labeled (10-2) represents the twiddle factor. The parts from (10-3) to (10-5) represent Radix-2. ２ indicates the (main) calculation part to which

[0090]

[0091] On the other hand, (9-3) of Equation 9 can be transformed into Equation 11, which is similar to Equation 8, and Equation 11 is Radix-2 ２ indicates the (main) calculation part to which

[0092]

[0093] Next, the correspondence between the FFT circuit 2 in FIG. 7 and Equations 9 to 11 will be described.

[0094] The leftmost input in FIG. 6 is x(t), that is, x(16t"+t'). The small FFT circuit group 251 corresponds to (10-1) in equation 10. That is, each small FFT circuit 261 performs an N / 16-point discrete fast Fourier transform, and converts a function of t" into a function of k". Various specific configurations can be adopted for the small FFT circuit 261.

[0095] The first rotator group 252 corresponds to the part indicated by (10-2) in Equation 10. Ｎ／４ｍ The m in k" (t' ２ +2t' ３ Each first rotator 262 is provided with a W Ｎ／４ ｍ Therefore, a rotation memory connected to the first rotator 262 stores information necessary to set N / 4 rotation factors corresponding to a rotation of 2π / (N / 4) points in the first rotator 262.

[0096] The first group of butterfly operators 253 corresponds to the Σ part shown in (10-3) of equation 10. The first group of butterfly operators 253 calculates t' ３ かk' ３ The second rotator group 254 corresponds to the part indicated by (10-4) in equation 10. Here, k' ３ t' ２ is 0 or 1, the second rotator group 254 (at its position) performs a rotation operation of 0 (i.e., no rotation) or 2πi / 4 (=90°). Only four second rotators 264 are provided as the second rotator group 254. The second butterfly operator group 255 corresponds to the rightmost Σ portion indicated by (10-5) in equation 10. The second butterfly operator group 255 calculates t' ２ かk' ２ is converted to

[0097] The third rotator group 256 corresponds to the part indicated by (9-2) in Equation 9. Ｎ ｍ The twiddle factor is set for each operation.

[0098] The third group of butterfly operators 257 corresponds to the Σ part shown in (11-1) of equation 11. The third group of butterfly operators 257 calculates t' １ かk' １ The fourth rotator group 258 corresponds to the part shown as (11-2) in Equation 11. Here, k' １ t' ０is 0 or 1, the third rotator group 258 (at its position) performs a rotation operation of 0 (i.e., no rotation) or 2πi / 4 (=90°). Only four third rotators 268 are provided as the third rotator group 258. The fourth butterfly operator group 259 corresponds to the rightmost Σ portion shown as (11-3) in equation 11. The fourth butterfly operator group 259 calculates t' ０ かk' ０ is converted to

[0099] As a result of the above processing, similarly to the case of FIG. 2, when the inputs x(16t"), x(16t"+1), x(16t"+2), ..., x(16t"+15) are input sequentially in parallel, x~(k"), x~(k"+(1 / 16)N), x~(k"+(2 / 16)N), ..., x~(k"+(15 / 16)N) (however, the output order is as shown in FIG. 7) are output sequentially in parallel.

[0100] The configuration of FIG. 5 is also employed for each third rotator 266 in FIG. 7 . That is, the third rotator 266 includes a first complex multiplier 41 and a second complex multiplier 42, each of which is a rotator. The first complex multiplier 41 and the second complex multiplier 42 are connected in series. A first rotation memory 43 is connected to the first complex multiplier 41, and a second rotation memory 44 is connected to the second complex multiplier 42. The first rotation memory 43 stores N1 first twiddle factors corresponding to rotation positions obtained by dividing 2π into N1 equal parts, where n1 is an integer equal to or greater than 3 and N1 is an integer equal to 2 to the n1 power. Meanwhile, the second rotation memory 44 stores N2 second twiddle factors corresponding to rotation positions obtained by dividing 2π / N1 into N2 equal parts, where N2 is an integer equal to or greater than 1 and N2 is an integer equal to 2 to the n2 power. Here, n is n1+n2 and is equal to or greater than 5. Any one of a plurality of first twiddle factors is selectively set in the first complex multiplier 41, and any one of a plurality of second twiddle factors is selectively set in the second complex multiplier 42.

[0101] By dividing and storing the twiddle factors set in the third rotator 266 into a first rotation memory 43 that stores first twiddle factors corresponding to coarse rotation positions and a second rotation memory 44 that stores second twiddle factors corresponding to rotation angles that interpolate between coarse rotation positions, it is possible to significantly reduce the memory capacity required to store the twiddle factors, as in the case of FIG. 2. In particular, the Radix-2 ｋ When the structure shown in Fig. 5 is applied, the storage capacity required for storing the rotators in the small FFT circuit group 251 is reduced, thereby reducing the storage capacity of the entire FFT circuit 2. Therefore, when the structure shown in Fig. 5 is provided, the reduction rate of the storage capacity of the entire FFT circuit 2 is large. Also, as in the case of Fig. 2, the amount of calculation does not increase significantly even when the structure shown in Fig. 5 is adopted.

[0102] 7, the configuration of FIG. 5 may also be adopted for each first rotator 262. This makes it possible to reduce the capacity required to store the twiddle factors required for the first rotator group 252 and the third rotator group 256.

[0103] In this way, by employing the rotator having the structure of Fig. 5 in the FFT circuit 2 of Fig. 7, it is possible to suppress an increase in the amount of calculation and to significantly reduce the storage capacity required to store the twiddle factors. This also makes it possible to realize the FFT circuit 2 at low cost using commercially available hardware such as FPGA.

[0104] Fig. 8 is a diagram illustrating the configuration of a communication system 5 having a Fourier transform device including the FFT circuit 2 illustrated in Fig. 2, Fig. 6, and Fig. 7. The communication system 5 in Fig. 8 includes a transmitting device 51 that transmits information by electromagnetic waves and a receiving device 52 that receives the electromagnetic waves and acquires information. Both the transmitting device 51 and the receiving device 52 are wireless communication devices.

[0105] The transmitting device 51 includes an input unit 511, an encoding unit 512, a D / A (digital-to-analog) converter 513, and an antenna 514. The encoding unit 512 includes an information conversion unit 611 and an inverse Fourier transform device 612. The input unit 511 accepts information input from an information source. The encoding unit 512 encodes the information and sends it to the D / A converter 513. The D / A converter 513 converts the encoded information into an analog signal. The antenna 514 is connected to the D / A converter 513. The antenna 514 converts the analog signal from the D / A converter 513 into an electromagnetic wave and sends it out.

[0106] The information conversion unit 611 of the encoding unit 512 converts the information from the input unit 511 into a format suitable for inverse Fourier transform. For example, if OFDM (orthogonal frequency division multiplexing) is adopted as the communication method, the information conversion unit 611 maps the information bit stream onto a complex plane. Then, the inverse Fourier transform device 612 performs an inverse Fourier transform on the mapped digital information and sends it to the D / A converter 513. That is, the inverse Fourier transform device 612 encodes the mapped information by converting it into information having time as a parameter.

[0107] The inverse Fourier transform device 612 uses a circuit in which the signs of the twiddle factors in the above-mentioned FFT circuit 2 are inverted. For this reason, in the description of this embodiment, the inverse Fourier transform device is regarded as a type of Fourier transform device, and is represented as an "(inverse) Fourier transform device 612" in Fig. 8. The Fourier transform devices including the FFT circuit 2 shown in Figs. 2, 6, and 7 can be used as Fourier transform devices that perform N-point fast Fourier transforms, and can also be used as Fourier transform devices that perform N-point inverse fast Fourier transforms.

[0108] The receiving device 52 includes an output unit 521, a decoding unit 522, an A / D (analog-to-digital) converter 523, and an antenna 524. The decoding unit 522 includes an information acquisition unit 621 and a Fourier transform device 622. The antenna 524 is connected to the A / D converter 523. The antenna 524 receives electromagnetic waves from the transmitting device 51 and transmits an electrical analog signal to the A / D converter 523. The A / D converter 523 converts the analog signal into a digital signal. In other words, it samples the analog signal. The decoding unit 522 decodes the digital signal and acquires information. The output unit 521 outputs the information from the decoding unit 522 to a desired device.

[0109] The Fourier transform device 622 of the decoding unit 522 performs a Fourier transform on the digital signal output from the A / D converter 523, converting it into, for example, information on the complex plane indicating multiple frequencies and their amplitudes. The information acquisition unit 621 converts the information from the Fourier transform device 622 into a format suitable for output. The Fourier transform device 622 uses the FFT circuit 2 illustrated above. Of course, various other configurations may be employed for the inverse Fourier transform device 612 and the Fourier transform device 622, as long as they are configured as shown in FIG. 5 and include a first complex multiplier 41, a second complex multiplier 42, a first rotation memory 43, and a second rotation memory 44, thereby reducing the capacity required to store twiddle factors. This reduces the required storage capacity while suppressing an increase in the amount of calculations in the transmitting device 51 and the receiving device 52, thereby reducing the manufacturing costs of the device. Power consumption is also reduced.

[0110] The communication system 5 may be used for various purposes, and may be used not only for communication using electromagnetic waves propagating in the atmosphere or a vacuum, but also for communication transmitting and receiving high-frequency signals that travel through a coaxial cable. The communication devices, namely the transmitter 51 and the receiver 52, may employ various other communication methods.

[0111] The Fourier transform device having a rotator and rotation memory with the configuration shown in FIG. 5 (hereinafter referred to as the "Fourier transform device according to the present invention" and including an inverse Fourier transform device) is not limited to the FFT circuit 2 with the configuration described in the above embodiment, but can be applied to any Fourier transform device that performs a Fourier transform or an inverse Fourier transform. In a Fourier transform device, the number of combinations of a rotator and rotation memory with the configuration shown in FIG. 5 may be one or more. The configuration shown in FIG. 5 makes it possible to reduce the memory capacity required to store twiddle factors while suppressing an increase in the amount of calculation. In other words, it is possible to ensure bandwidth and improve frequency resolution while reducing the required memory capacity. As a result, the manufacturing cost of the Fourier transform device can be reduced.

[0112] In particular, in a hardware FFT circuit that performs high-speed calculations, the arrangement of read lines from the rotating memory and the read timing are restricted, so it is not possible to reduce the storage capacity by sharing the rotating memory between rotators with different calculation timings. Therefore, the reduction in storage capacity achieved by the configuration in Figure 5 is effective in a hardware FFT circuit.

[0113] In addition, the Fourier transform device is Radix-2 ｋ Radix-2 performs calculations using algorithms ｋ When the Radix-2 circuit is provided, the number of rotators (hereinafter referred to as the "general rotator group") that need to perform rotation operations at rotation angles that are integer multiples of 2π / N (i.e., each of 0 to (N-1) times) can be reduced to only one. Therefore, by applying the rotator and rotation memory of FIG. 5 to the general rotator group, it is possible to obtain a significant reduction in the required storage capacity. ｋ Depending on which part of the FFT circuit the circuit is considered to be, the general rotator group to which the configuration of Figure 5 is applied is called Radix-2. ｋ If we consider it as a separate part from the circuit (main part), the general rotor group is Radix-2 ｋ The entire FFT circuit is connected before or after the Radix-2 ｋ When viewed as a circuit, the general rotor group to which the configuration of Figure 5 is applied is called Radix-2. ｋ Included in the circuit.

[0114] In addition, the above "Radix-2 ｋ The expression "circuit (main part)" is used in Radix-2. ｋ The circuit that characterizes the algorithm is called Radix-2. ｋ 2, the parts denoted by reference numerals 213 to 219, the parts denoted by reference numerals 232 to 235, and the parts denoted by reference numerals 253 to 255 and 257 to 259 in FIG. 7 are Radix-2 circuits. ｋ In other words, Radix-2 ｋ The main part of the circuit is Radix-2 ｋ This refers to the calculation part where the rotation calculation is fixed by the algorithm. ｋ When performing operations in an algorithm, N is 2 ｋ The above is subject to the constraint that the number must be a power of two.

[0115] Furthermore, Radix-2 ｋ To perform high-speed calculations while utilizing circuits, a multipath-delay-feedback type Fourier transform device, such as those shown in Figures 2, 7, and 8, is preferable. Generally speaking, in such a Fourier transform device, multiple sub-Fourier transform circuits (small FFT circuits) are arranged in parallel on the input side. Each sub-Fourier transform circuit is a circuit that performs a single-input / output Fourier transform or an inverse Fourier transform. In addition, a Radix-2 sub-Fourier transform circuit is provided downstream (on the output side) of the multiple sub-Fourier transform circuits. ｋ The circuit is arranged. Then, the rotator group to which the configuration of FIG. 5 is applied is arranged to form a plurality of small Fourier transform circuits and Radix-2 ｋ It is placed between the circuit.

[0116] If the number of the plurality of sub-Fourier transform circuits is P, then the circuit is expressed as (P-1) rotators, which are the sub-Fourier transform circuits and the Radix-2 ｋ It is placed between the circuit. However, P is the pth power of 2, and p is an integer equal to or greater than 2. p is "Radix-2 ｋWhen the above expression is applied to the FFT circuit 2 in FIG. 2, 16 sub-FFT circuits (sub-FFT circuits 221) are arranged in parallel, and Radix-2 is placed downstream of the 16 sub-FFT circuits. ４ The circuit is arranged such that 15 rotators (first rotators 222) are connected to 16 small Fourier transform circuits and Radix-2 ４ It is placed between the circuit.

[0117] As is clear from a comparison of Figures 2 and 6, the smaller the value of p, the larger the storage capacity required to store the twiddle factors in the paralleled sub-Fourier transform circuits. ｋ The larger the value of k in the circuit (i.e., the value of p), the more preferably the configuration of Fig. 5 is applied. The value of p is preferably 4 or more, more preferably 5 or more, and even more preferably 6 or more.

[0118] In addition, Radix-2 is used in the small Fourier transform circuit. ｋ The circuit may be adopted, and the configuration of FIG. 5 may be adopted.

[0119] Next, we will further explain how to reduce the memory capacity required to store the twiddle factors. ｎ , the number of first twiddle factors is 2 ｎ１ , the number of second twiddle factors is 2 ｎ２ (where n, n1, and n2 are positive integers, n = n1 + n2), if we consider only the number of twiddle factors, by dividing the twiddle factors into first twiddle factors and second twiddle factors, the number becomes 2. ｎ１＋ｎ２ From 2 ｎ１ +2 ｎ２ is reduced to

[0120] For example, if the number of first twiddle factors is 2 ４ (=16), and the number of second twiddle factors is 2 ４ (=16), if you do not divide them, the number of rotation factors will be 2 ８ (=256), so by dividing the rotation factors, the required storage capacity can be reduced by about 12 percent by simple calculation. ｎ (where n is an even number greater than or equal to 6), and the number of first twiddle factors is 2 ｎ／２The number of second twiddle factors is 2 ｎ／２ Then, the number of twiddle factors goes from N to 2.N. １／２ is reduced to

[0121] When the capacity required to store the twiddle factors is considered as the number of real numbers, the number of first twiddle factors is 2 ｎ１ , the number of second twiddle factors is 2 ｎ２ Then the number of real numbers is 2.2 ｎ１＋ｎ２ From 2 (2 ｎ１ +2 ｎ２ ) Here, considering the symmetry of the sine function and the cosine function, the number of real numbers to be stored as the original twiddle factors and the first twiddle factors can be reduced to 1 / 8. ｎ１＋ｎ２－２ (=2.2 ｎ１＋ｎ２ / 8) to 2 ｎ１－２ +2.2 ｎ２ (=2 * (2 ｎ１ / 8+2 ｎ２ )) The above N is reduced to 2 １７ In the example, n1 = 10, n2 = 7, and the number of real numbers to be stored is 2 １５ From 2 ９ has been reduced to.

[0122] As explained above, the number of real numbers actually stored as the first twiddle factors may be twice the number of the first twiddle factors, or may not be twice the number in consideration of symmetry. In the above explanation, "the first twiddle memory 43 stores the first twiddle factors" means that the first twiddle factors are stored in a state that allows them to be quickly read out, and the first twiddle memory 43 does not need to store a plurality of first twiddle factors themselves.

[0123] From the viewpoint of reducing the required storage capacity, that is, reducing the scale of the implemented circuit (including memory), n2 is preferably 3 or more, and more preferably 5 or more. n1 is also preferably 3 or more, and more preferably 5 or more. Furthermore, n is preferably 10 or more, and even more preferably 15 or more. There is no need to set an upper limit for n, but from a technical viewpoint, it is, for example, 30 or less. The real numbers stored as twiddle factors may be floating-point or fixed-point, and may be single-precision or double-precision.

[0124] Considering the symmetry of the sine function and the cosine function, the required storage capacity can be reduced by making at least one of n1 and n2 larger than the combination of n1 = 3 and n2 = 1 (the number of first twiddle factors is 8 and the number of second twiddle factors is 2). That is, n1 is an integer equal to or greater than 3, n2 is an integer equal to or greater than 1, and n is an integer equal to or greater than 5.

[0125] Next, we will explain the preferred performance of a Fourier transform device to which the present invention is applied. Conventional devices that perform high-speed Fourier transforms have, for example, a bandwidth of 2 GHz and a frequency resolution of approximately 80 kHz. In contrast, the inventors have achieved a Fourier transform device with an FFT circuit 2 shown in FIG. 2, achieving a bandwidth of 4 GHz and a frequency resolution of 32 kHz. Specifically, the above performance is achieved by operating 16 parallel sub-FFT circuits 221 at a 300 MHz operating clock within the FPGA. This reduces the required storage capacity while improving performance by approximately four times compared to conventional devices.

[0126] Thus, in the Fourier transform device according to the present invention, a digital signal obtained by digitally converting an analog signal having a bandwidth of 4 GHz or more is input, and the frequency resolution at the output is preferably 100 kHz or less. More preferably, the frequency resolution at the output is 50 kHz or less. When the Fourier transform device performs an inverse Fourier transform, it is preferable that the frequency resolution of the input frequency information is 100 kHz or less, and the bandwidth of the analog signal obtained by analog converting the digital signal to be output is 4 GHz or more. More preferably, the frequency resolution of the input frequency information is 50 kHz or less. Furthermore, when the Fourier transform device according to the present invention is applied to a frequency analysis device, it is preferable that the frequency analysis device performs frequency analysis on a digital signal converted from a high-frequency analog signal having a frequency of 300 MHz or more and 300 GHz or less.

[0127] The configuration of the rotator (first rotator 222) (and rotation memory 28) shown in Fig. 5 may be modified in various ways as long as a rotation calculation using a rotation angle obtained by adding the rotation angles indicated by the first and second twiddle factors is performed. For example, in Fig. 5, the positions of the combination of the first complex multiplier 41 and the first rotation memory 43 and the combination of the second complex multiplier 42 and the second rotation memory 44 may be interchanged. Furthermore, as shown in Fig. 9, a complex multiplier 45 may be provided to which a first twiddle factor selected from a plurality of first twiddle factors stored in the first rotation memory 43 and a second twiddle factor selected from a plurality of second twiddle factors stored in the second rotation memory 44 are input. The complex multiplier 45 may obtain a composite twiddle factor corresponding to the rotation angle obtained by adding the rotation angles indicated by both twiddle factors. Thereafter, a complex multiplier 46 may perform a rotation calculation using the composite twiddle factor. That is, various configurations can be adopted for the rotator and rotation memory shown in FIG. 5 as long as they perform a rotation operation combining a first twiddle factor selected from a plurality of first twiddle factors and a second twiddle factor selected from a plurality of second twiddle factors.

[0128] In the above embodiment, a one-dimensional Fourier transform has been described. However, the first twiddle factor corresponding to the coarse rotation position in FIG. 5 and the second twiddle factor corresponding to the precise rotation angle that interpolates the coarse rotation position can be applied to a rotator and rotation memory for two- or more-dimensional Fourier transform (including an inverse Fourier transform).

[0129] The configurations of the above-described embodiment and each modification may be combined as appropriate as long as they are not mutually contradictory.

[0130] While the invention has been particularly illustrated and described, it should be understood that the foregoing description is illustrative and not restrictive, and that numerous modifications and variations are possible without departing from the scope of the invention.

[0131] 12,612,622 Fourier transform device 28 Rotation memory 41 First complex multiplier 42 Second complex multiplier 43 First rotation memory 44 Second rotation memory 45, 46 Complex multiplier 51 Transmitting device 52 Receiving device 211, 231, 251 Small FFT circuit group 212, 232, 252 First rotator group 213, 233, 253 First butterfly operator group 214, 234, 254 Second rotator group 215, 235, 255 Second butterfly operator group 216, 256 Third rotator group 217, 257 Third butterfly operator group 218, 258 Third rotator group 219, 259 Third butterfly operator group 221, 241, 261 Small FFT circuit (small Fourier transform circuit) 222, 242 First rotator 266 Third rotator 513 D / A (digital-to-analog) converter 514, 525 Antenna 523 A / D (analog-to-digital) converter

Claims

1. A Fourier transform device that performs an N-point (where N is the nth power of 2 and n is an integer equal to or greater than 5) fast Fourier transform or inverse fast Fourier transform, comprising: a rotator that performs a rotation operation; and a rotation memory that stores twiddle factors, wherein the rotation memory includes: a first rotation memory that stores a plurality of first twiddle factors corresponding to rotation positions obtained by dividing 2π into N1 equal parts (where n1 is an integer equal to or greater than 3 and N1 is an integer that is the n1th power of 2), and a second rotation memory that stores a plurality of second twiddle factors corresponding to rotation positions obtained by dividing 2π / N1 into N2 equal parts, where N / N1 is N2 (where n2 is an integer equal to or greater than 1 and N2 is an integer that is the n2th power of 2), wherein the rotator performs a rotation operation combining a first twiddle factor selected from the plurality of first twiddle factors and a second twiddle factor selected from the plurality of second twiddle factors.

2. The Fourier transform device according to claim 1, ｋ Radix-2 performs calculations using algorithms ｋ A circuit is provided, and the rotator is the Radix-2 ｋ or connected to the circuit, ｋ A Fourier transform device included in the circuit.

3. The Fourier transform device according to claim 2, further comprising a plurality of sub-Fourier transform circuits arranged in parallel, each of which is a circuit for performing a single-input / output Fourier transform or an inverse Fourier transform, and the Radix-2 is disposed downstream of the plurality of sub-Fourier transform circuits. ｋ A circuit is arranged, and a plurality of rotators including the rotator are arranged to rotate the plurality of fractional Fourier transform circuits and the Radix-2 ｋ A multipath-delay-feedback type Fourier transform device is disposed between the circuit.

4. A Fourier transform device according to claim 3, wherein the number of the plurality of small Fourier transform circuits is P (where P is the pth power of 2, and p is an integer equal to or greater than 2), and (P-1) rotators including the rotator are connected to the plurality of small Fourier transform circuits and the Radix-2 ｋ A multipath-delay-feedback type Fourier transform device is disposed between the circuit.

5. The Fourier transform device according to claim 2, further comprising 16 small Fourier transform circuits arranged in parallel, each of which is a circuit for performing a single-input / output Fourier transform or an inverse Fourier transform, and the Radix-2 is disposed downstream of the plurality of small Fourier transform circuits. ｋ Radix-2 is a circuit ４ A circuit is arranged, and 15 rotators including the rotator are arranged to rotate the 16 sub-Fourier transform circuits and the Radix-2 ４ A multipath-delay-feedback type Fourier transform device is disposed between the circuit.

6. A Fourier transform device according to claim 1, wherein a digital signal obtained by digitally converting an analog signal with a bandwidth of 4 GHz or more is input, and the frequency resolution at the output is 100 kHz or less, or the frequency resolution of the input frequency information is 100 kHz or less, and the bandwidth of the analog signal obtained by analog converting the digital signal to be output is 4 GHz or more.

7. A Fourier transform device according to claim 6, wherein the frequency resolution in the output is 50 kHz or less, or the frequency resolution in the input frequency information is 50 kHz or less.

8. The Fourier transform device according to any one of claims 1 to 7, which performs the fast Fourier transform in a device for frequency analysis of a digital signal converted from a high-frequency analog signal of 300 MHz or more and 300 GHz or less.

9. A wireless communication device comprising: an analog-to-digital converter or a digital-to-analog converter connected to an antenna; and a Fourier transform device according to any one of claims 1 to 7, which performs a Fourier transform on a digital signal output from the analog-to-digital converter, or performs an inverse Fourier transform on digital information and sends it to the digital-to-analog converter.

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