Display system, display apparatus, and driving method

Abstract

A display system, a display apparatus, and a driving method. The display system comprises: multiple lens sets (LS), the lens sets (LS) being configured to be used for 3D display when opened, and used for 2D display when closed; a pixel circuit (PC), comprising multiple pixel islands (PI) arranged in the form of a matrix, the multiple pixel islands (PI) being disposed below the lens sets (LS), each pixel island (PI) among the multiple pixel islands (PI) corresponding to a lens set (LS), and a pixel island (PI) comprising a number 4M of sub-pixels (P), M being an integer greater than or equal to 1; a scan driving circuit (SDC), configured to provide a scanning signal to the pixel circuit (PC); a data driving circuit (DDC), configured to provide a pixel signal (OP) to the pixel circuit (PC); multiple control lines (CL); and multiple drive circuit sets (DCS), the drive circuit sets (DCS) comprising multiple drive circuits (DC), output ends (O) of the drive circuits (DC) being connected to the sub-pixels (P) in the pixel islands (PI), and input ends (I) of the drive circuits (DC) being connected to the data drive circuit (DDS). A first control line (CL1) and a second control line (CL2) in the multiple control lines (CL) are connected to control electrodes (G) of drive circuits (DC) in drive circuit sets (DCS) corresponding to an odd-numbered column of pixel islands (PI). A third control line (CL3) and a fourth control line (CL4) in the multiple control lines (CL) are connected to control electrodes (G) of drive circuits (DC) in drive circuit sets (DCS) corresponding to an even-numbered column of pixel islands (PI).

Description

Display system, display device, and driving method Technical Field

[0001] The present disclosure relates to the field of display technology, and more particularly, to a display system configured to be switchable between 2D display and 3D display, a display device, and a driving method for the display system. Background Art

[0002] Display technology is gradually developing from 2D display to 3D display, and display devices that can switch between 2D and 3D display have become a future development trend. Existing display solutions compatible with 2D / 3D can design conventional 2D display panels as pixel islands. For example, a conventional 2D pixel point is used as a pixel island, and a pixel island is split into multiple sub-pixels. In a 3D scene, each sub-pixel point is assigned different viewpoint information to achieve 3D display. In addition, a controllable lens is set above the 2D display panel to create a 2D and 3D switchable effect. In 3D display mode, the controllable lens is turned on so that after the light from the sub-pixel passes through the controllable lens, only a part of the sub-pixels representing the corresponding viewpoint information can enter the human eye to achieve 3D display. In 2D display mode, the lens is turned off to restore 2D display.

[0003] Summary of the Invention

[0004] Embodiments of the present disclosure provide a display system configured to be switchable between 2D display and 3D display, a display device, and a driving method for the display system.

[0005] In a first aspect of the present disclosure, there is provided a display system configured to be switchable between 2D display and 3D display. The display system includes: a plurality of lens groups, each configured to be used for 3D display when turned on and for 2D display when turned off; a pixel circuit, including a plurality of pixel islands arranged in a matrix, the plurality of pixel islands being disposed below the lens groups, each of the plurality of pixel islands corresponding to the lens groups, the pixel islands including 4M sub-pixels, where M is an integer greater than or equal to 1; a scan drive circuit configured to provide a scan signal to the pixel circuit; a data drive circuit configured to provide a pixel signal to the pixel circuit; a plurality of control lines; and a plurality of drive circuit groups, each including a plurality of drive circuits, the output ends of the drive circuits being connected to the sub-pixels in the pixel islands, and the input ends of the drive circuits being connected to the data drive circuits; wherein a first control line and a second control line among the plurality of control lines are connected to a control electrode of a drive circuit in a drive circuit group corresponding to an odd-numbered column of pixel islands, and a third control line and a fourth control line among the plurality of control lines are connected to a control electrode of a drive circuit in a drive circuit group corresponding to an even-numbered column of pixel islands.

[0006] In an embodiment of the present disclosure, the driving circuit includes a first transistor and a second transistor, and wherein the first electrode of the first transistor is connected to the output end of the driving circuit, and the second electrode of the first transistor is connected to the input end of the driving circuit, wherein, in each driving circuit group, the first electrode of the first transistor of the 4i-3rd and 4i-1th driving circuits is respectively connected to the first electrode of the second transistor of the 4i-2nd and 4i-1th driving circuits, the second electrode of the first transistor of the 4i-3rd and 4i-1th driving circuits is respectively connected to the second electrode of the second transistor of the 4i-3rd and 4i-1th driving circuits, the first electrode of the first transistor of the 4i-2nd and 4i-1th driving circuits is respectively connected to the first electrode of the second transistor of the 4i-3rd and 4i-1th driving circuits, and the second electrode of the first transistor of the 4i-2nd and 4i-1th driving circuits is respectively connected to the second electrode of the second transistor of the 4i-2nd and 4i-1th driving circuits, wherein i=1,2…M.

[0007] In an embodiment of the present disclosure, the first transistor and the second transistor are transistors of different types, wherein, in the driving circuit group corresponding to the odd-numbered column pixel islands, the gates of the first transistor and the second transistor of the 4i-3th driving circuit and the 4i-2th driving circuit are connected to the first control line, and the gates of the first transistor and the second transistor of the 4i-1th driving circuit and the 4i-th driving circuit are connected to the second control line, wherein, in the driving circuit group corresponding to the even-numbered column pixel islands, the gates of the first transistor and the second transistor of the 4i-3th driving circuit and the 4i-2th driving circuit are connected to the third control line, and the gates of the first transistor and the second transistor of the 4i-1th driving circuit and the 4i-th driving circuit are connected to the fourth control line.

[0008] In an embodiment of the present disclosure, the first transistor and the second transistor are transistors of the same type, wherein, in the driving circuit group corresponding to the odd-numbered column pixel islands, the gate of the first transistor of the 4i-3th driving circuit and the 4i-2th driving circuit is connected to the first sub-control line of the first control line and the gate of the second transistor is connected to the second sub-control line of the first control line, the gate of the first transistor of the 4i-1th driving circuit and the 4ith driving circuit is connected to the first sub-control line of the second control line and the gate of the second transistor is connected to the second sub-control line of the second control line, wherein, in the driving circuit group corresponding to the even-numbered column pixel islands, the gate of the first transistor of the 4i-3th driving circuit and the 4i-2th driving circuit is connected to the first sub-control line of the third control line and the gate of the second transistor is connected to the second sub-control line of the third control line, the gate of the first transistor of the 4i-1th driving circuit and the 4ith driving circuit is connected to the first sub-control line of the fourth control line and the gate of the second transistor is connected to the second sub-control line of the fourth control line.

[0009] In an embodiment of the present disclosure, the lens group includes a plurality of liquid crystal lenses.

[0010] In an embodiment of the present disclosure, each pixel island includes 16 sub-pixels, and each lens group includes 2 lenses.

[0011] In an embodiment of the present disclosure, each pixel island includes 32 sub-pixels, and each lens group includes 3 lenses.

[0012] In an embodiment of the present disclosure, each pixel island includes 64 sub-pixels, and each lens group includes 5 lenses.

[0013] In an embodiment of the present disclosure, a display device is provided. The display device includes: a pixel circuit including a plurality of pixel islands arranged in a matrix, each of the plurality of pixel islands including 4M sub-pixels, where M is an integer greater than or equal to 1; a scan driver circuit configured to provide a scan signal to the pixel circuit; a data driver circuit configured to provide a pixel signal to the pixel circuit; a plurality of control lines; and a plurality of driver circuit groups, the driver circuit groups including a plurality of driver circuits, the output ends of the driver circuits being connected to the sub-pixels of the pixel islands, and the input ends of the driver circuits being connected to the data driver circuits; wherein a first control line and a second control line of the plurality of control lines are connected to gate electrodes of driver circuits in the driver circuit group corresponding to odd-numbered pixel islands, and a third control line and a fourth control line of the plurality of control lines are connected to gate electrodes of driver circuits in the driver circuit group corresponding to even-numbered pixel islands.

[0014] In an embodiment of the present disclosure, the driving circuit includes a first transistor and a second transistor, and wherein the first electrode of the first transistor is connected to the output end of the driving circuit, and the second electrode of the first transistor is connected to the input end of the driving circuit, wherein, in each driving circuit group, the first electrode of the first transistor of the 4i-3rd and 4i-1th driving circuits is respectively connected to the first electrode of the second transistor of the 4i-2nd and 4i-1th driving circuits, the second electrode of the first transistor of the 4i-3rd and 4i-1th driving circuits is respectively connected to the second electrode of the second transistor of the 4i-3rd and 4i-1th driving circuits, the first electrode of the first transistor of the 4i-2nd and 4i-1th driving circuits is respectively connected to the first electrode of the second transistor of the 4i-3rd and 4i-1th driving circuits, and the second electrode of the first transistor of the 4i-2nd and 4i-1th driving circuits is respectively connected to the second electrode of the second transistor of the 4i-2nd and 4i-1th driving circuits, wherein i=1,2…M.

[0015] In an embodiment of the present disclosure, the first transistor and the second transistor are transistors of different types, wherein, in the driving circuit group corresponding to the odd-numbered column pixel islands, the gates of the first transistor and the second transistor of the 4i-3th driving circuit and the 4i-2th driving circuit are connected to the first control line, and the gates of the first transistor and the second transistor of the 4i-1th driving circuit and the 4i-th driving circuit are connected to the second control line, wherein, in the driving circuit group corresponding to the even-numbered column pixel islands, the gates of the first transistor and the second transistor of the 4i-3th driving circuit and the 4i-2th driving circuit are connected to the third control line, and the gates of the first transistor and the second transistor of the 4i-1th driving circuit and the 4i-th driving circuit are connected to the fourth control line.

[0016] In an embodiment of the present disclosure, the first transistor and the second transistor are transistors of the same type, wherein, in the driving circuit group corresponding to the odd-numbered column pixel islands, the gate of the first transistor of the 4i-3th driving circuit and the 4i-2th driving circuit is connected to the first sub-control line of the first control line and the gate of the second transistor is connected to the second sub-control line of the first control line, the gate of the first transistor of the 4i-1th driving circuit and the 4ith driving circuit is connected to the first sub-control line of the second control line and the gate of the second transistor is connected to the second sub-control line of the second control line, wherein, in the driving circuit group corresponding to the even-numbered column pixel islands, the gate of the first transistor of the 4i-3th driving circuit and the 4i-2th driving circuit is connected to the first sub-control line of the third control line and the gate of the second transistor is connected to the second sub-control line of the third control line, the gate of the first transistor of the 4i-1th driving circuit and the 4ith driving circuit is connected to the first sub-control line of the fourth control line and the gate of the second transistor is connected to the second sub-control line of the fourth control line.

[0017] In a third aspect of the present disclosure, a driving method for the display system described in the first aspect is provided. The driving method includes: providing control signals to the first control line, the second control line, the third control line, and the fourth control line of the plurality of control lines to turn on the driving circuit; and providing pixel signals to the pixel circuit via the driving circuit by the data driving circuit.

[0018] Further aspects and scope of adaptability become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented individually or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are intended for illustrative purposes and are not intended to limit the scope of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings described herein are for illustrative purposes only of selected embodiments and not all possible implementations, and are not intended to limit the scope of the present application, wherein:

[0020] FIG1 shows the polarity of each sub-pixel in a display panel using a column-by-column inversion method;

[0021] 2A , 2B and 2C are schematic diagrams showing polarities of sub-pixels in a display panel when a conventional driving circuit is used to drive a 2D display panel;

[0022] FIG3 shows a schematic diagram of a display system according to an embodiment of the present disclosure;

[0023] FIG4 shows a partial enlarged view of the display system shown in FIG3 ;

[0024] FIG5 shows a schematic diagram of a display system according to another embodiment of the present disclosure;

[0025] FIG6 shows a schematic diagram of a display system according to yet another embodiment of the present disclosure; and

[0026] 7 to 9 are schematic diagrams illustrating polarities of sub-pixels in various control modes of a display system according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] First, it should be noted that, unless the context clearly indicates otherwise, the singular form of the words used in this document and the appended claims includes the plural form, and vice versa. Thus, when referring to the singular, the plural form of the corresponding term is generally included. Similarly, the words "comprise" and "include" are to be interpreted as inclusive rather than exclusive. Likewise, the terms "include" and "or" should be interpreted as inclusive unless such interpretation is expressly prohibited herein. Where the term "example" is used in this document, particularly when it is placed after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or comprehensive.

[0028] In addition, in the drawings, the thickness and area of ​​each layer are exaggerated for clarity. It should be understood that the terms "longitudinal," "radial," "upper," "lower," "front," "back," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like, indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the drawings and are intended solely to facilitate and simplify the description of the present invention. They do not indicate or imply that the components referred to must have a specific orientation, be constructed, or operate in a specific orientation, and are therefore not to be construed as limiting the present invention.

[0029] When displaying images using a liquid crystal display (LCD), due to factors such as the positive and negative polarization characteristics of liquid crystal molecules and process uniformity, simply adjusting the common voltage VCOM cannot guarantee that the positive and negative polarization angles of the liquid crystal molecules in the LCD panel are exactly the same. Consequently, it cannot guarantee that the brightness of positive and negative frames within the same grayscale is exactly the same. The pixel signal is used to drive the liquid crystal molecules to rotate, and the pixel signal cannot be fixed at a specific value. Otherwise, the liquid crystal molecules will polarize over time and gradually lose their optical properties. Therefore, it is necessary to polarize the pixel signal to prevent the characteristics of the liquid crystal molecules from being affected. This requires that the pixel signal can be divided into two polarities: positive and negative. When the pixel signal causes the voltage on the pixel electrode of a subpixel to be higher than the voltage on the common electrode, the pixel signal is positive and the subpixel also has positive polarity (referred to herein as a positive polarity subpixel). When the pixel signal causes the voltage on the pixel electrode of a subpixel to be lower than the voltage on the common electrode, the pixel signal is negative and the subpixel has negative polarity (referred to herein as a negative polarity subpixel). Whether the subpixel has positive or negative polarity, it can still have the same grayscale. When the absolute value of the voltage difference across the sub-pixels is the same, the displayed grayscale is exactly the same. However, in both cases, the rotation directions of the liquid crystal molecules are completely opposite, thus preventing the rotation direction of the liquid crystal molecules from always being fixed in one direction, which would destroy their characteristics. There are four common polarity inversion methods: frame-by-frame inversion, row-by-row inversion, column-by-column inversion (for example, Figure 1 shows the polarity of each sub-pixel in the display panel using a column-by-column inversion method), and point-by-point inversion. In addition, the flickering pattern design concept is to only light up sub-pixels of the same polarity within a frame. For example, in a positive frame, only all positive polarity sub-pixels are lit, and negative polarity sub-pixels are not lit; in a negative frame, only all negative polarity sub-pixels are lit, and positive polarity sub-pixels are not lit. This creates the largest liquid crystal flip difference between the positive and negative frames, resulting in asymmetric brightness between the positive and negative frames, and periodic brightness jumps. The visual effect of the brightness changes is accumulated, resulting in a flicker phenomenon that is perceptible to the human eye.

[0030] In order to utilize the existing 2D display panel to realize the switching between 2D display mode and 3D display mode, a controllable lens (for example, a liquid crystal lens) is usually set above the 2D display panel. The controllable lens is turned on in 3D display mode and turned off in 2D display mode. In addition, one pixel of the 2D display panel is split into multiple sub-pixels. As shown in Figure 1, conventional 2D pixel points (for example, red 2D pixel points (R), green 2D pixel points (G), blue 2D pixel points (B)) are changed from a horizontal arrangement to a vertical arrangement, and one 2D pixel is split into 8 sub-pixels. In 3D display mode, the sub-pixels at each viewpoint are given different viewpoint information (i.e., 8 viewpoint information) so that the corresponding viewpoint information enters the left eye and the right eye respectively, thereby realizing 3D display. For example, at the viewing position corresponding to viewpoint 1, viewpoint information of the 1st / 9th / 17th / ... columns of sub-pixels with the same polarity enters the human eye; at the viewing position corresponding to viewpoint 3, viewpoint information of the 3rd / 11th / 19th / ... columns of sub-pixels with the same polarity enters the human eye, resulting in severe flicker, that is, the 3D display screen is a flickering pattern.

[0031] Typically, a 2D display panel is designed in a manner such that m pixel islands correspond to n lenses to form a 2D / 3D display switchable smart display device. In 2D display mode, the resolution of the display panel is an integer multiple of m, and in 3D display mode, the resolution of the display panel is an integer multiple of n. Figures 2A, 2B, and 2C show schematic diagrams of the polarity of sub-pixels in a display panel when a 2D display panel is driven by an existing driving circuit. Specifically, the display panel shown in Figure 2A is designed so that one pixel island corresponds to two lenses, the display panel shown in Figure 2B is designed so that two pixel islands correspond to three lenses, and the display panel shown in Figure 2C is designed so that four pixel islands correspond to five lenses. Under the existing display chip drive design, when the above three display panels are switched from 2D display mode to 3D display mode, according to the periodic viewpoint law, after the sub-pixels pass through the lenses, the ratio of positive polarity pixels to negative polarity pixels entering the eye is 2:0, 2:1, and 3:2, respectively. For a design with m pixel islands corresponding to n lenses, the ratio of positive to negative polarity pixels entering the eye can be determined as (n+1) / (n-1) according to the above rule. This shows that the polarity ratio entering the eye is very unbalanced, resulting in severe flicker.

[0032] FIG3 shows a schematic diagram of a display system according to an embodiment of the present disclosure. As shown in FIG3 , the display system includes multiple lens groups LS, pixel circuits PC, a scan driver circuit SDC, a data driver circuit DDC, multiple control lines CL (CL1, CL2, CL3, and CL4), and multiple driver circuit groups DCS. The lens group LS is configured to be used for 3D display when turned on and for 2D display when turned off, thereby enabling the display system to switch between 2D and 3D display. The pixel circuit PC includes multiple pixel islands PI arranged in a matrix form. The pixel islands PI are disposed below the lens group LS, and the pixel islands PI correspond to the lens groups LS. The pixel islands PI include 4M sub-pixels P, where M is an integer greater than or equal to 1. The scan driver circuit SDC is configured to provide a scan signal to the pixel circuit PC to turn on the sub-pixels P. The data driver circuit DDC is configured to provide a pixel signal OP to the pixel circuit PC. The driver circuit group DCS includes multiple driver circuits DC, whose output terminals O are connected to the sub-pixels P in the pixel islands PI. An input terminal I of the drive circuit DC is connected to the data drive circuit DDC. A first control line CL1 and a second control line CL2 of the plurality of control lines CL are connected to a gate G of the drive circuit DC of the drive circuit group DCS corresponding to the odd-numbered pixel islands PI, and a third control line CL3 and a fourth control line CL4 are connected to a gate G of the drive circuit DC of the drive circuit group DCS corresponding to the even-numbered pixel islands PI.

[0033] In an embodiment of the present disclosure, as shown in FIG3 , a sub-pixel P includes a pixel transistor T p and storage capacitor C, pixel transistor T p The drain of the pixel transistor T is connected to the first plate of the storage capacitor C (ie, the pixel electrode). p The gate of the pixel transistor T is connected to the data drive circuit DDC. p The source of the capacitor is connected to the output terminal O of the driving circuit DC. The second plate (ie, the common electrode) of the storage capacitor is connected to the common electrode signal line.

[0034] In an embodiment of the present disclosure, the driving circuit DC may include a first transistor T1 and a second transistor T2. FIG4 shows a partial enlarged view of the display system shown in FIG3. As shown in FIG4, the first electrode D of the first transistor T1 is connected to the output terminal O of the driving circuit DC, and the second electrode S of the first transistor T1 is connected to the input terminal I of the driving circuit DC. In the driving circuit group DCS, the 4i-3 (in this article, i = 1, 2 ... M) driving circuits DC 4i-3 The first electrode D of the first transistor T1 is connected to the 4i-2th driving circuit DC 4i-2 The first electrode D of the second transistor T2 is connected to the 4i-1th drive circuit DC 4i-1The first electrode D of the first transistor T1 is connected to the 4i-th driving circuit DC 4i The first electrode D of the second transistor T2 is connected to the 4i-3 drive circuit DC 4i-3 The second electrode S of the first transistor T1 is connected to the 4i-3 driving circuit DC 4i-3 The second electrode S of the second transistor T2 is connected to the 4i-1th drive circuit DC 4i-1 The second electrode S of the first transistor T1 is connected to the 4i-1th driving circuit DC 4i-1 The second electrode S of the second transistor T2 is connected to the 4i-2 drive circuit DC 4i-2 The first electrode D of the first transistor T1 is connected to the 4i-3 driving circuit DC 4i-3 The first electrode D of the second transistor T2 is connected to the 4i-th drive circuit DC 4i The first electrode D of the first transistor T1 is connected to the 4i-1th driving circuit DC 4i-1 The first electrode D of the second transistor T2 is connected to the 4i-2 drive circuit DC 4i-2 The second electrode S of the first transistor T1 is connected to the 4i-2th driving circuit DC 4i-2 The second electrode S of the second transistor T2 is connected to the 4i-th drive circuit DC 4i The second electrode S of the first transistor T1 is connected to the 4i-th drive circuit DC 4i The second electrode S of the second transistor T2 is connected.

[0035] In the embodiment of the present disclosure, the first transistor and the second transistor may be different types of transistors. In the example shown in FIG3 , the first transistor may be a P-type transistor and the second transistor may be an N-type transistor. Continuing to refer to FIG3 , in the drive circuit group DCS corresponding to the odd-numbered pixel islands PI, the 4i-3rd drive circuit DCS 4i-3 and the 4i-2nd drive circuit DC 4i-2 The gates G of the first transistor T1 and the second transistor T2 are connected to the first control line CL1, and the 4i-1th driving circuit DC 4i-1 and the 4ith drive circuit DC 4i The gates G of the first transistor T1 and the second transistor T2 are connected to the second control line CL2. In the driving circuit group DCS corresponding to the even-numbered pixel islands PI, the 4i-3rd driving circuit DCS is connected to the second control line CL2. 4i-3 and the 4i-2nd drive circuit DC 4i-2 The gates G of the first transistor T1 and the second transistor T2 are connected to the third control line CL3, and the 4i-1th driving circuit DC 4i-1 and the 4ith drive circuit DC 4iThe gates G of the first transistor T1 and the second transistor T2 are connected to the fourth control line CL4.

[0036] In an embodiment of the present disclosure, as shown in FIG3 , the data drive circuit DDC is connected to each drive circuit via a data signal line DL, thereby providing a positive polarity pixel signal OP to a positive polarity pixel via the data signal line DL and the corresponding drive circuit, and providing a negative polarity pixel signal OP to a negative polarity pixel via the data signal line DL and the corresponding drive circuit. Furthermore, during the display period, the polarity (e.g., positive or negative) of the pixel signal OP on a single data signal line DL remains unchanged, while the polarities of the pixel signals OP on two adjacent data signal lines DL are opposite. In this way, since there is a 180° phase difference between the flicker waveforms of the sub-pixels in adjacent columns in the same pixel island, flicker can be suppressed, thereby achieving a better display effect.

[0037] In addition, in an embodiment of the present disclosure, as shown in FIG3 , two adjacent pixel islands (i.e., an odd-numbered pixel island and an adjacent even-numbered pixel island) constitute a new minimum unit, and control signals are respectively provided to the first control line, the second control line, the third control line, and the fourth control line to turn on the drive circuit, and the data drive circuit provides pixel signals to the pixel circuit via the drive circuit, so that for the new minimum unit, the ratio of positive polarity pixels to negative polarity pixels entering the eye is 1:1, thereby solving the flickering problem in the 3D display mode and achieving a better display effect.

[0038] In addition, in other embodiments of the present disclosure, the first transistor and the second transistor can be transistors of the same type. Figures 5 and 6 respectively show schematic diagrams of display systems according to other embodiments of the present disclosure. In the display system shown in Figure 5, the first transistor and the second transistor are both P-type transistors. In the display system shown in Figure 6, the first transistor and the second transistor are both N-type transistors. As shown in the figure, in the drive circuit group DCS corresponding to the odd-numbered pixel island PI, the 4i-3rd drive circuit DCS 4i-3 and the 4i-2nd drive circuit DC 4i-2 The gate G of the first transistor T1 is connected to the first sub-control line CL11 of the first control line CL1 and the gate G of the second transistor T2 is connected to the second sub-control line CL12 of the first control line CL1. The 4i-1th driving circuit DC 4i-1 and the 4ith drive circuit DC 4i The gate G of the first transistor T1 is connected to the first sub-control line CL21 of the second control line CL2, and the gate G of the second transistor T2 is connected to the second sub-control line CL22 of the second control line CL2. In the driving circuit group DCS corresponding to the even-numbered pixel islands PI, the 4i-3rd driving circuit DCS is connected to the first sub-control line CL21 of the second control line CL2.4i-3 and the 4i-2nd drive circuit DC 4i-2 The gate G of the first transistor T1 is connected to the first sub-control line CL31 of the third control line CL3 and the gate G of the second transistor T2 is connected to the second sub-control line CL32 of the third control line CL3. The 4i-1th driving circuit DC 4i-1 and the 4ith drive circuit DC 4i The gate G of the first transistor T1 is connected to the first sub-control line CL41 of the fourth control line CL4, and the gate G of the second transistor T2 is connected to the second sub-control line CL42 of the fourth control line CL4. The structures of the other elements in the display systems shown in Figures 5 and 6 are the same as those of the display system shown in Figure 3, and will not be repeated here.

[0039] In an embodiment of the present disclosure, the pixel island may include 16 sub-pixels (i.e., M=4), and the lens group includes 2 lenses. In another embodiment of the present disclosure, the pixel island may include 32 sub-pixels (i.e., M=8), and the lens group includes 3 lenses. In yet another embodiment of the present disclosure, the pixel island may include 64 sub-pixels (i.e., M=16), and the lens group includes 5 lenses. It should be noted that those skilled in the art can set any number of sub-pixels and lenses in the pixel island and the lens group, respectively, according to actual needs.

[0040] In addition, it should be noted that the sub-pixels mentioned in this article may include only sub-pixels that can be used for display, or may include both sub-pixels that can be used for display and dummy (pseudo) sub-pixels. In the latter case, the connection method of the dummy sub-pixels is the same as the connection method of the sub-pixels shown in Figure 3, but no pixel signal is provided on the data signal line DL connected to the dummy sub-pixel.

[0041] It should be noted that the display system described above may also include other components, which are not limited in the embodiments of the present disclosure. For the sake of clarity and brevity, the embodiments of the present disclosure do not provide all the components of the display system. To achieve the basic functions of the display system, those skilled in the art may provide and configure other structures not shown according to specific needs, and the embodiments of the present disclosure do not limit this.

[0042] Embodiments of the present disclosure provide a display device. The display device includes a pixel circuit, a scan driver circuit, a data driver circuit, multiple control lines, and multiple driver circuit groups. The specific structures and functions of these components are the same as those of the corresponding components in the aforementioned display system and are not described again here.

[0043] Embodiments of the present disclosure also provide a driving method for the above-mentioned display system. The method includes: providing control signals to a first control line, a second control line, a third control line, and a fourth control line among a plurality of control lines to turn on a driving circuit; and providing a pixel signal from a data driving circuit to a pixel circuit via the driving circuit.

[0044] The operating principle of the display system shown in Figure 3 is described in detail below, wherein the first transistor is a P-type transistor and the second transistor is an N-type transistor, and the P-type transistor is turned on when a low-level signal is applied, and the N-type transistor is turned on when a high-level signal is applied. Depending on whether the lens group in the display system is turned on or off, the display system can operate in 3D display mode or 2D display mode. Furthermore, by providing different control modes for each control line in 3D or 2D display mode, polarity balance in 3D display and uniform polarity in 2D display are achieved.

[0045] In the 3D display mode, the following exemplary control modes may be provided.

[0046] 1. Control mode 1 (CL1 / 2 / 3 / 4=0011)

[0047] In control mode 1, a low level signal (CL1=0) is provided to the first control line CL1 to turn on the 4i-3 th driving circuit DC corresponding to the odd-numbered pixel islands PI. 4i-3 and the 4i-2nd drive circuit DC 4i-2 The first transistor T1 of the transistor is turned on, so that the pixel signal OP is transmitted on the black solid line path; a low level signal (CL2=0) is provided to the second control line CL2 to turn on the 4i-1th driving circuit DC corresponding to the odd-numbered pixel island PI. 4i-1 and the 4ith drive circuit DC 4i The first transistor T1 of the pixel island PI is also transmitted on the black solid line path; a high level signal (CL3=1) is provided to the third control line CL3 to turn on the 4i-3th driving circuit DC corresponding to the even column pixel island PI. 4i-3 and the 4i-2nd drive circuit DC 4i-2 The second transistor T2 is turned on, so that the pixel signal OP is transmitted on the black dotted line path; and a high level signal (CL4=1) is provided to the fourth control line CL4 to turn on the 4i-1th driving circuit DC corresponding to the even column pixel island PI. 4i-1 and the 4ith drive circuit DC 4i Similarly, the pixel signal OP is transmitted on the black dotted line path.

[0048] In this control mode, since the 4i-3th data signal line DL corresponding to the even-numbered pixel islands PI 4i-3is connected to the 4i-2 th driving circuit corresponding to the even-numbered pixel islands PI, and therefore, the 4i-3 th data signal line DL corresponding to the even-numbered pixel islands PI is swapped. 4i-3 and the 4i-2th data signal line DL 4i-2 In addition, since the 4i-1th data signal line DL corresponding to the even-numbered pixel island PI 4i-1 is connected to the 4i-th driving circuit corresponding to the even-numbered pixel island PI. Therefore, the 4i-1-th data signal line DL corresponding to the even-numbered pixel island PI is connected to the 4i-th driving circuit corresponding to the even-numbered pixel island PI. 4i-1 and the 4ith data signal line DL 4i pixel signal.

[0049] FIG7 shows the polarity of each sub-pixel in control mode 1 in an embodiment in which one pixel island includes 16 sub-pixels and one lens group includes two lenses. In FIG7 , the symbol "0" represents a low-level signal, the symbol "1" represents a high-level signal, the symbol "+" represents a positive-polarity pixel, the symbol "-" represents a negative-polarity pixel, and the symbol "X" represents a swapped pixel signal.

[0050] Specifically, under control mode 1, the polarities of the 16 sub-pixels corresponding to pixel island 1 (i.e., odd-column pixel islands) are +-+-+-+-+-+-+-+-, and the polarity entering the eye at viewpoint V1 is ++; the polarities of the 16 sub-pixels corresponding to pixel island 2 (i.e., even-column pixel islands) are -+-+-+-+-+-+-+-+, and the polarity entering the eye at viewpoint V1 is --.

[0051] It can be seen that pixel island 1 and pixel island 2 constitute a new minimum unit. For the new minimum unit, the ratio of positive polarity pixels (++) to negative polarity pixels (--) entering the eye is 1:1, thus solving the flickering problem in 3D display mode and achieving better display effects.

[0052] Furthermore, as shown in FIG7 , in control mode 1, the pixel signals on the 17th data signal line DL and the 18th data signal line DL corresponding to pixel island 2 are swapped, and the pixel signals on the 19th data signal line DL and the 20th data signal line DL corresponding to pixel island 2 are swapped. The pixel signals on the 21st data signal line DL and the 22nd data signal line DL corresponding to pixel island 2 are swapped, and the pixel signals on the 23rd data signal line DL and the 24th data signal line DL corresponding to pixel island 2 are swapped. The pixel signals on the 25th data signal line DL and the 26th data signal line DL corresponding to pixel island 2 are swapped, and the pixel signals on the 27th data signal line DL and the 28th data signal line DL corresponding to pixel island 2 are swapped. The pixel signals on the 29th data signal line DL and the 30th data signal line DL corresponding to pixel island 2 are swapped, and the pixel signals on the 31st data signal line DL and the 32nd data signal line DL corresponding to pixel island 2 are swapped.

[0053] In addition, Figure 8 shows the polarity of each subpixel in an embodiment where a pixel island includes 32 subpixels and a lens group includes 3 lenses, and Figure 9 shows the polarity of each subpixel in an embodiment where a pixel island includes 64 subpixels and a lens group includes 5 lenses. As shown in Figures 8 and 9, in control mode 1, pixel islands 1 and 2 form a new minimum unit. In this new minimum unit, the ratio of positive polarity pixels (++) to negative polarity pixels (--) entering the eye is 1:1, which also solves the flicker problem in 3D display mode.

[0054] 2. Control mode 2 (CL1 / 2 / 3 / 4=0110)

[0055] In control mode 2, a low level signal is provided to the first control line CL1 and the fourth control line CL4, and a high level signal is provided to the second control line CL2 and the third control line CL3, so that the corresponding transistors are turned on. 4i-1 and the 4ith data signal line DL 4i The pixel signals of the even-numbered columns PI are exchanged and the 4i-3 data signal lines DL corresponding to the even-numbered pixel islands PI are switched. 4i-3 and the 4i-2 data signal line DL 4i-2 pixel signal exchange.

[0056] In control mode 2, as shown in Figure 7, the polarities of the 16 sub-pixels corresponding to pixel island 1 (i.e., odd-numbered column pixel islands) are +--++--++--++--+, and the polarity entering the eye at viewpoint V1 is ++; the polarities of the 16 sub-pixels corresponding to pixel island 2 (i.e., even-numbered column pixel islands) are -++--++--++--++-, and the polarity entering the eye at viewpoint V1 is --.

[0057] It can be seen that pixel island 1 and pixel island 2 constitute a new minimum unit. For the new minimum unit, the ratio of positive polarity pixels (++) to negative polarity pixels (--) entering the eye is 1:1, thus solving the flickering problem in 3D display mode and achieving better display effects.

[0058] 3. Control mode 3 (CL1 / 2 / 3 / 4=1001)

[0059] In control mode 3, a high level signal is provided to the first control line CL1 and the fourth control line CL4; a low level signal is provided to the second control line CL2 and the third control line CL3; and the 4i-3rd data signal lines DL corresponding to the odd-numbered pixel islands PI are swapped. 4i-3 and the 4i-2th data signal line DL 4i-2 and exchange pixel signals corresponding to the even-numbered columns of pixel islands PI 4i-1 data signal lines DL 4i-1 and the 4ith data signal line DL 4i pixel signal.

[0060] In control mode 3, as shown in Figure 7, the polarities of the 16 sub-pixels corresponding to pixel island 1 (i.e., odd-numbered column pixel islands) are -++--++--++--++-, and the polarity entering the eye at viewpoint V1 is --; the polarities of the 16 sub-pixels corresponding to pixel island 2 (i.e., even-numbered column pixel islands) are +--++--++--++--+, and the polarity entering the eye at viewpoint V1 is ++.

[0061] It can be seen that pixel island 1 and pixel island 2 constitute a new minimum unit. For the new minimum unit, the ratio of positive polarity pixels (--) to negative polarity pixels (++) entering the eye is 1:1, thus solving the flickering problem in 3D display mode and achieving better display effects.

[0062] 4. Control mode 4 (CL1 / 2 / 3 / 4=1100)

[0063] In control mode 4, a high level signal is provided to the first control line CL1 and the second control line CL2; a low level signal is provided to the third control line CL3 and the fourth control line CL4; and the 4i-3 data signal lines DL corresponding to the odd-numbered pixel islands PI are swapped. 4i-3and the 4i-2th data signal line DL 4i-2 and exchange pixel signals corresponding to the odd-numbered columns of pixel islands PI 4i-1 data signal lines DL 4i-1 and the 4ith data signal line DL 4i pixel signal.

[0064] Under control mode 3, as shown in Figure 7, the polarities of the 16 sub-pixels corresponding to pixel island 1 (i.e., odd-numbered column pixel islands) are -+-+-+-+-+-+-+-+, and the polarity entering the eye at viewpoint V1 is --; the polarities of the 16 sub-pixels corresponding to pixel island 2 (i.e., even-numbered column pixel islands) are +-+-+-+-+-+-+-+-, and the polarity entering the eye at viewpoint V1 is ++.

[0065] It can be seen that pixel island 1 and pixel island 2 constitute a new minimum unit. For the new minimum unit, the ratio of positive polarity pixels (--) to negative polarity pixels (++) entering the eye is 1:1, thus solving the flickering problem in 3D display mode and achieving better display effects.

[0066] In the 2D display mode, the following exemplary control modes may be provided.

[0067] 5. Control mode 5 (CL1 / 2 / 3 / 4=1111)

[0068] In control mode 5, a high level signal is provided to the first control line CL1, the second control line CL2, the third control line CL3 and the fourth control line CL4; the 4i-3 data signal lines DL corresponding to the odd-numbered pixel islands PI are exchanged. 4i-3 and the 4i-2 data signal line DL 4i-2 Exchange pixel signals corresponding to the odd-numbered pixel island PI 4i-1 data signal line DL 4i-1 and the 4ith data signal line DL 4i Exchange pixel signal with even columns corresponding to the pixel island PI 4i-3 data signal line DL 4i-3 and the 4i-2 data signal line DL 4i-2 and exchange pixel signals corresponding to the even-numbered columns of pixel islands PI 4i-1 data signal lines DL 4i-1 and the 4ith data signal line DL 4i pixel signal.

[0069] 6. Control mode 6 (CL1 / 2 / 3 / 4=1010)

[0070] In control mode 6, a high level signal is provided to the first control line CL1 and the third control line CL3; a low level signal is provided to the second control line CL2 and the fourth control line CL4; and the 4i-3th data signal line DL corresponding to the odd-numbered pixel islands PI is swapped. 4i-3 and the 4i-2th data signal line DL 4i-2 and exchange pixel signals corresponding to the even-numbered columns of pixel islands PI 4i-3 data signal lines DL 4i-3 and the 4i-2th data signal line DL 4i-2 pixel signal.

[0071] 7. Control mode 7 (CL1 / 2 / 3 / 4=0101)

[0072] In control mode 7, a low level signal is provided to the first control line CL1 and the third control line CL3; a high level signal is provided to the second control line CL2 and the fourth control line CL4; and the 4i-1th data signal line DL corresponding to the odd-numbered pixel islands PI is swapped. 4i-1 and the 4ith data signal line DL 4i and exchange pixel signals corresponding to the even-numbered columns of pixel islands PI 4i-1 data signal lines DL 4i-1 and the 4ith data signal line DL 4i pixel signal.

[0073] 8. Control mode 8 (CL1 / 2 / 3 / 4=0000)

[0074] In the control mode 8 , a low-level signal is supplied to the first control line CL1 , the second control line CL2 , the third control line CL3 , and the fourth control line CL4 .

[0075] By adopting control modes 1 to 8 according to the embodiments of the present disclosure, it is possible to achieve uniform polarity of sub-pixels entering the human eye in 2D display mode, and to ensure that the number of positive polarity pixels and negative polarity pixels entering the human eye is the same in 3D display mode, thereby eliminating the flicker effect and fundamentally solving the 3D flicker screen problem.

[0076] Although control modes 1 to 8 are described above, those skilled in the art will appreciate that other control modes may also be employed.

[0077] Furthermore, consistently using a single control mode during display can easily lead to issues such as uneven brightness and bright / dark stripes across the display system. To address this, various control modes can be switched per frame / row to jitter the stripe positions, creating visual complementarity at high frequencies for better display quality.

[0078] In addition, the eight control modes described above are also applicable to the display systems shown in FIG. 5 and FIG. 6 .

[0079] For the display system shown in FIG5 , in various modes, the level signals on the first sub-control line CL11 of the first control line CL1, the first sub-control line CL21 of the second control line CL2, the first sub-control line CL31 of the third control line CL3, and the first sub-control line CL41 of the fourth control line CL4 are respectively the same as the level signals on the first control line CL1, the second control line CL2, the third control line CL3, and the fourth control line CL4 used in the display system shown in FIG3 . Furthermore, the level signals on the second sub-control line CL12 of the first control line CL1, the second sub-control line CL22 of the second control line CL2, the second sub-control line CL32 of the third control line CL3, and the second sub-control line CL42 of the fourth control line CL4 are respectively opposite to the level signals on the first sub-control line CL11 of the first control line CL1, the first sub-control line CL21 of the second control line CL2, the first sub-control line CL31 of the third control line CL3, and the first sub-control line CL41 of the fourth control line CL4.

[0080] For the display system shown in FIG6 , in various modes, the level signals on the second sub-control line CL12 of the first control line CL1, the second sub-control line CL22 of the second control line CL2, the second sub-control line CL32 of the third control line CL3, and the second sub-control line CL42 of the fourth control line CL4 are respectively the same as the level signals on the first control line CL1, the second control line CL2, the third control line CL3, and the fourth control line CL4 for the display system shown in FIG3 . Furthermore, the level signals on the first sub-control line CL11 of the first control line CL1, the first sub-control line CL21 of the second control line CL2, the first sub-control line CL31 of the third control line CL3, and the first sub-control line CL41 of the fourth control line CL4 are respectively opposite to the level signals on the second sub-control line CL12 of the first control line CL1, the second sub-control line CL22 of the second control line CL2, the second sub-control line CL32 of the third control line CL3, and the second sub-control line CL42 of the fourth control line CL4.

[0081] Those skilled in the art will appreciate that various aspects of the present application can be implemented as systems, methods, or program products. Therefore, various aspects of the present application can be specifically implemented in the following forms: a complete hardware implementation, a complete software implementation (including firmware, microcode, etc.), or an implementation that combines hardware and software aspects, which may be collectively referred to herein as a "circuit," "module," or "system."

[0082] The foregoing description is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present disclosure shall be included within the scope of protection of the present disclosure.

Claims

1. A display system configured to be able to switch between 2D display and 3D display, comprising: A plurality of lens groups, the lens groups being configured to be used for 3D display when turned on and for 2D display when turned off; A pixel circuit including a plurality of pixel islands arranged in a matrix form, the plurality of pixel islands being disposed under the lens groups, each pixel island in the plurality of pixel islands corresponding to the lens group, and each pixel island including 4M sub-pixels, where M is an integer greater than or equal to 1; A scan driving circuit configured to provide a scan signal to the pixel circuit; A data driving circuit configured to provide a pixel signal to the pixel circuit; A plurality of control lines; and A plurality of driving circuit groups, the driving circuit groups including a plurality of driving circuits, the output ends of the driving circuits being connected to the sub-pixels in the pixel islands, and the input ends of the driving circuits being connected to the data driving circuit; Wherein, the first control line and the second control line among the plurality of control lines are connected to the control electrodes of the driving circuits in the driving circuit group corresponding to the odd-numbered pixel islands, and the third control line and the fourth control line among the plurality of control lines are connected to the control electrodes of the driving circuits in the driving circuit group corresponding to the even-numbered pixel islands.

2. The display system according to claim 1, wherein, The driving circuit includes a first transistor and a second transistor, and wherein, the first pole of the first transistor is connected to the output end of the driving circuit, and the second pole of the first transistor is connected to the input end of the driving circuit, Wherein, in each driving circuit group, the first poles of the first transistors of the 4i - 3rd and 4i - 1st driving circuits are respectively connected to the first poles of the second transistors of the 4i - 2nd and 4i - th driving circuits, the second poles of the first transistors of the 4i - 3rd and 4i - 1st driving circuits are respectively connected to the second poles of the second transistors of the 4i - 3rd and 4i - 1st driving circuits, the first poles of the first transistors of the 4i - 2nd and 4i - th driving circuits are respectively connected to the first poles of the second transistors of the 4i - 3rd and 4i - 1st driving circuits, and the second poles of the first transistors of the 4i - 2nd and 4i - th driving circuits are respectively connected to the second poles of the second transistors of the 4i - 2nd and 4i - th driving circuits, where i = 1, 2... M.

3. The display system according to claim 2, wherein, The first transistor and the second transistor are transistors of different types, Wherein, in the driving circuit group corresponding to the odd-numbered pixel islands, the gates of the first transistors and the second transistors of the 4i - 3rd and 4i - 2nd driving circuits are connected to the first control line, and the gates of the first transistors and the second transistors of the 4i - 1st and 4i - th driving circuits are connected to the second control line, Wherein, in the driving circuit group corresponding to the even-numbered pixel islands, the gates of the first transistors and the second transistors of the 4i - 3rd and 4i - 2nd driving circuits are connected to the third control line, and the gates of the first transistors and the second transistors of the 4i - 1st and 4i - th driving circuits are connected to the fourth control line.

4. The display system according to claim 2, wherein, The first transistor and the second transistor are transistors of the same type, Among them, in the driving circuit group corresponding to the odd-numbered pixel islands, the gates of the first transistors of the (4i - 3)-th driving circuit and the (4i - 2)-th driving circuit are connected to the first sub-control line of the first control line, and the gates of the second transistors are connected to the second sub-control line of the first control line. The gates of the first transistors of the (4i - 1)-th driving circuit and the 4i-th driving circuit are connected to the first sub-control line of the second control line, and the gates of the second transistors are connected to the second sub-control line of the second control line. Among them, in the driving circuit group corresponding to the even-numbered pixel islands, the gates of the first transistors of the (4i - 3)-th driving circuit and the (4i - 2)-th driving circuit are connected to the first sub-control line of the third control line, and the gates of the second transistors are connected to the second sub-control line of the third control line. The gates of the first transistors of the (4i - 1)-th driving circuit and the 4i-th driving circuit are connected to the first sub-control line of the fourth control line, and the gates of the second transistors are connected to the second sub-control line of the fourth control line.

5. The display system according to any one of claims 1 to 4, wherein, The lens group includes a plurality of liquid crystal lenses.

6. The display system according to any one of claims 1 to 5, wherein, Each pixel island includes 16 sub-pixels, and each lens group includes 2 lenses.

7. The display system according to any one of claims 1 to 5, wherein, Each pixel island includes 32 sub-pixels, and each lens group includes 3 lenses.

8. The display system according to any one of claims 1 to 5, wherein Each pixel island includes 64 sub-pixels, and each lens group includes 5 lenses.

9. A display device, comprising: A pixel circuit, including a plurality of pixel islands arranged in a matrix form, and each pixel island in the plurality of pixel islands includes 4M sub-pixels, where M is an integer greater than or equal to 1; A scan driving circuit configured to provide a scan signal to the pixel circuit; A data driving circuit configured to provide a pixel signal to the pixel circuit; A plurality of control lines; and A plurality of driving circuit groups, the driving circuit groups include a plurality of driving circuits, the output ends of the driving circuits are connected to the sub-pixels of the pixel islands, and the input ends of the driving circuits are connected to the data driving circuit; Among them, the first control line and the second control line in the plurality of control lines are connected to the control poles of the driving circuits in the driving circuit group corresponding to the odd-numbered pixel islands, and the third control line and the fourth control line in the plurality of control lines are connected to the control poles of the driving circuits in the driving circuit group corresponding to the even-numbered pixel islands.

10. The display device according to claim 9, wherein, The driving circuit includes a first transistor and a second transistor, and among them, the first pole of the first transistor is connected to the output end of the driving circuit, and the second pole of the first transistor is connected to the input end of the driving circuit. Among them, in each driving circuit group, the first poles of the first transistors of the (4i - 3)-th and (4i - 1)-th driving circuits are respectively connected to the first poles of the second transistors of the (4i - 2)-th and 4i-th driving circuits, the second poles of the first transistors of the (4i - 3)-th and (4i - 1)-th driving circuits are respectively connected to the second poles of the second transistors of the (4i - 3)-th and (4i - 1)-th driving circuits, the first poles of the first transistors of the (4i - 2)-th and 4i-th driving circuits are respectively connected to the first poles of the second transistors of the (4i - 3)-th and (4i - 1)-th driving circuits, and the second poles of the first transistors of the (4i - 2)-th and 4i-th driving circuits are respectively connected to the second poles of the second transistors of the (4i - 2)-th and 4i-th driving circuits, where i = 1, 2... M.

11. The display device according to claim 10, wherein, The first transistor and the second transistor are transistors of different types. Among them, in the driving circuit group corresponding to the pixel islands in odd-numbered columns, the gates of the first and second transistors of the (4i - 3)-th and (4i - 2)-th driving circuits are connected to the first control line, and the gates of the first and second transistors of the (4i - 1)-th and 4i-th driving circuits are connected to the second control line. Among them, in the driving circuit group corresponding to the pixel islands in even-numbered columns, the gates of the first and second transistors of the (4i - 3)-th and (4i - 2)-th driving circuits are connected to the third control line, and the gates of the first and second transistors of the (4i - 1)-th and 4i-th driving circuits are connected to the fourth control line.

12. The display device according to claim 10, wherein, The first transistor and the second transistor are transistors of the same type. Among them, in the driving circuit group corresponding to the pixel islands in odd-numbered columns, the gate of the first transistor of the (4i - 3)-th and (4i - 2)-th driving circuits is connected to the first sub-control line of the first control line and the gate of the second transistor is connected to the second sub-control line of the first control line, the gate of the first transistor of the (4i - 1)-th and 4i-th driving circuits is connected to the first sub-control line of the second control line and the gate of the second transistor is connected to the second sub-control line of the second control line. Among them, in the driving circuit group corresponding to the pixel islands in even-numbered columns, the gate of the first transistor of the (4i - 3)-th and (4i - 2)-th driving circuits is connected to the first sub-control line of the third control line and the gate of the second transistor is connected to the second sub-control line of the third control line, the gate of the first transistor of the (4i - 1)-th and 4i-th driving circuits is connected to the first sub-control line of the fourth control line and the gate of the second transistor is connected to the second sub-control line of the fourth control line.

13. A driving method for the display system according to any one of claims 1 to 8, comprising: Providing control signals to the first control line, the second control line, the third control line, and the fourth control line among the multiple control lines respectively to turn on the driving circuit; And Providing pixel signals to the pixel circuit by the data driving circuit via the driving circuit.

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