Display panel and display device

Abstract

The present invention provides a display panel and a display device. The display panel comprises: a base substrate, and a first shift register and a second shift register which are located on the base substrate. The first shift register and the second shift register each comprise a first output transistor, a second output transistor, and a plurality of adapter holes; and the adapter holes are used for bridging an active region of the first output transistor and an active region of the second output transistor by means of a conductive layer. The number of the adapter holes in the second shift register is greater than the number of the adapter holes in the first shift register; and / or the size of each adapter hole in the second shift register is larger than the size of each adapter hole in the first shift register. A threshold voltage of the first output transistor in the second shift register is negatively biased relative to a threshold voltage of the first output transistor in the first shift register; and a threshold voltage of the second output transistor in the second shift register is negatively biased relative to a threshold voltage of the second output transistor in the first shift register.

Description

Display panel and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on December 19, 2023, with application number 202311747427.3 and application name “Display Panel and Display Device,” the entire contents of which are incorporated by reference into this disclosure. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0004] With the rapid development of display technology, display panels are showing a trend towards high integration and low cost. Gate Driver On Array (GOA) technology has been widely used in various display panels. Existing gate drive circuits are subject to unstable performance due to factors such as threshold voltage drift of thin-film transistors (TFTs), which in turn affects the display quality of the display panel. For example, when the gate drive circuit is powered on in an electrostatic field or at high temperatures, the threshold voltage of the TFTs in the gate drive circuit is prone to positive bias, resulting in leakage, causing signal anomalies, and thus affecting the display effect.

[0005] Summary of the Invention

[0006] Some embodiments of the present disclosure provide a display panel comprising: a base substrate, a first shift register and a second shift register located on the base substrate; the first shift register and the second shift register each comprising a first output transistor, a second output transistor, and a plurality of transfer holes; the transfer holes being used to bridge an active area of ​​the first output transistor and an active area of ​​the second output transistor through a conductive layer; wherein the number of transfer holes in the second shift register is greater than the number of transfer holes in the first shift register; and / or the size of the transfer holes in the second shift register is greater than the size of the transfer holes in the first shift register;

[0007] The threshold voltage of the first output transistor in the second shift register is negatively biased compared to the threshold voltage of the first output transistor in the first shift register; the threshold voltage of the second output transistor in the second shift register is negatively biased compared to the threshold voltage of the second output transistor in the first shift register.

[0008] In some possible implementations of the present disclosure, orthographic projections of a portion of the transfer holes on the substrate overlap with orthographic projections of the active areas of the first output transistor and the second output transistor on the substrate.

[0009] In some possible implementations of the present disclosure, the size of the transfer hole in the first shift register is between 2.3 microns and 3.5 microns; the size of the transfer hole in the second shift register is between 2.5 microns and 4 microns.

[0010] In some possible embodiments of the present disclosure, the second shift register further includes: a plurality of virtual transfer holes; the virtual transfer holes are adjacent to the orthographic projections of the active layer of the first output transistor and the orthographic projections of the active layer of the second output transistor on the substrate.

[0011] In some possible implementations of the present disclosure, the gate of the first output transistor is coupled to the first node, the first electrode of the first output transistor is coupled to the first level signal line, and the second electrode of the first output transistor is coupled to the cascade output signal line;

[0012] A gate of the second output transistor is coupled to the second node, a first electrode of the second output transistor is coupled to the second level signal line, and a second electrode of the second output transistor is coupled to the cascade output signal line.

[0013] In some possible embodiments of the present disclosure, the present invention further includes: a semiconductor layer located on the substrate, a gate insulating layer located on the side of the semiconductor layer facing away from the substrate, a gate conductive layer located on the side of the gate insulating layer facing away from the substrate, a first insulating layer located on the side of the gate conductive layer facing away from the substrate, a first conductive layer located on the side of the first insulating layer facing away from the substrate, a second insulating layer located on the side of the first conductive layer facing away from the substrate, and a second conductive layer located on the side of the second insulating layer facing away from the substrate.

[0014] In some possible embodiments of the present disclosure, the gate conductive layer includes: a gate of the first output transistor and a gate of the second output transistor; the semiconductor layer includes: an active region of the first output transistor and an active region of the second output transistor; the active region of the first output transistor includes: a first electrode and a second electrode of the first output transistor; the active region of the second output transistor includes: a first electrode and a second electrode of the second output transistor;

[0015] The conductive layer includes: the first conductive layer and the second conductive layer;

[0016] The first-level signal line and the second-level signal line are located in the second conductive layer; the cascade output signal line is located in the first conductive layer or the second conductive layer.

[0017] In some possible implementations of the present disclosure, when the cascade output signal line is located in the first conductive layer, an orthographic projection of a portion of the transfer hole on the base substrate overlaps with an orthographic projection of the cascade output signal line on the base substrate.

[0018] In some possible implementations of the present disclosure, when the cascade output signal line is located in the second conductive layer, an orthographic projection of a portion of the transfer hole on the base substrate overlaps with an orthographic projection of the gate conductive layer on the base substrate.

[0019] Some embodiments of the present disclosure provide a display device including the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] FIG1 is a schematic diagram of some structures of a display device provided by an embodiment of the present disclosure;

[0021] FIG2 is a schematic diagram of another structure of a display device provided by an embodiment of the present disclosure;

[0022] FIG3 is a schematic diagram of some structures of thin film transistors provided by embodiments of the present disclosure;

[0023] FIG4 is a schematic diagram of another structure of a thin film transistor provided by an embodiment of the present disclosure;

[0024] FIG5 is a schematic diagram of some further structures of thin film transistors provided by embodiments of the present disclosure;

[0025] FIG6 is a schematic diagram of some further structures of thin film transistors provided by embodiments of the present disclosure;

[0026] FIG7 is a schematic diagram of some structures of a first shift register provided by an embodiment of the present disclosure;

[0027] FIG8 is a schematic diagram of some structures of a second shift register provided by an embodiment of the present disclosure;

[0028] FIG9 is a schematic diagram of another structure of a second shift register provided by an embodiment of the present disclosure;

[0029] FIG10 is a schematic diagram of some further structures of the second shift register provided by an embodiment of the present disclosure;

[0030] FIG11 is an equivalent circuit diagram provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0032] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0033] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0034] For example, as shown in FIG1 , a display device may include a display panel 100 and a source driver circuit 120. The display panel 100 may include a plurality of pixel units arranged in an array, a plurality of gate lines GA (e.g., GA1, GA2, GA3, GA4), a plurality of data lines DA (e.g., DA1, DA2, DA3), and a gate driver circuit 110. The gate driver circuit 110 is coupled to the gate lines GA1, GA2, GA3, and GA4, respectively, and the source driver circuit 120 is coupled to the data lines DA1, DA2, and DA3, respectively. For example, each pixel unit includes a plurality of sub-pixels SPX. For example, a pixel unit may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, so that a color display can be achieved by mixing red, green, and blue. Alternatively, a pixel unit may also include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, so that a color display can be achieved by mixing red, green, blue, and white. Of course, in actual applications, the luminous colors of the sub-pixels in the pixel unit can be designed and determined based on the actual application environment, and are not limited here.

[0035] For example, two source driver circuits 120 may be provided, wherein one source driver circuit 120 is connected to half the number of data lines DA, and the other source driver circuit 120 is connected to the other half of the number of data lines DA. Of course, three, four, or more source driver circuits 120 may also be provided, which can be designed and determined according to the needs of actual applications and is not limited here.

[0036] For example, as shown in FIG1 , each sub-pixel SPX includes a driving transistor 01 and a pixel electrode 02. A row of sub-pixels SPX corresponds to a gate line GA, and a column of sub-pixels SPX corresponds to a data line DA. The gate of the driving transistor 01 is electrically connected to the corresponding gate line GA, the source of the driving transistor 01 is electrically connected to the corresponding data line DA, and the drain of the driving transistor 01 is electrically connected to the pixel electrode 02. It should be noted that the pixel array structure disclosed herein can also be a dual-gate structure, that is, two gate lines GA are set between two adjacent rows of sub-pixels SPX. This arrangement can reduce the number of data lines DA by half, that is, some adjacent columns of sub-pixels SPX include data lines DA, while some adjacent columns of sub-pixels SPX do not include data lines DA. The specific sub-pixel SPX arrangement structure and the data lines DA and gate line GA arrangement are not limited.

[0037] For example, as shown in FIG2 , the display panel 100 may further include a plurality of clock signal lines, and the plurality of clock signal lines are coupled to the gate drive circuit 110. In this way, a corresponding clock signal can be input to the gate drive circuit 110 through the clock signal line, thereby loading the signal to the gate line GA. For example, the display panel 100 may include clock signal lines CK1 to CK12, and the clock signal lines CK1 to CK12 are coupled to the gate drive circuit 110. For example, if the display panel 100 is designed with a single gate drive circuit 110, the gate drive circuit 110 can be coupled to 12 clock signal lines CK1 to CK12. If the display panel 100 is designed with a dual gate drive circuit 110, each gate drive circuit 110 can be coupled to 12 clock signal lines CK1 to CK12. It should be noted that FIG2 is only used as an example for explanation of 12 clock signal lines. In actual applications, the specific number of clock signal lines can be determined according to the actual application requirements and is not limited here. For example, it can also be another number of clock signal lines that is an integer multiple of 2, such as 2, 4, 6, 8, 10, etc. The gate drive circuit 110 includes multiple shift registers, each of which corresponds to at least one clock signal line.

[0038] Exemplarily, the gate drive circuit 110 generally includes a plurality of thin film transistors. After testing, it was found that the threshold voltage of the thin film transistor is correlated with the transfer hole, and the test values ​​are shown in Table 1 below. Since the polysilicon semiconductor in the thin film transistor (TFT) contains a small amount of hydrogen bonds, during the heat treatment process, a small amount of hydrogen bonds will overflow through the transfer hole, thereby affecting the threshold voltage of the thin film transistor. Therefore, the design difference of the transfer hole will affect the threshold voltage of the thin film transistor, thereby affecting the gate drive circuit and the display quality of the display panel. How to adjust the threshold voltage in the thin film transistor and thus improve the display effect of the display panel is a problem that needs to be solved urgently by those skilled in the art.

[0039] For example, as shown in Figures 3 to 6, the active area 10 of the thin film transistor (e.g., TFT1, TFT2, TFT3, TFT4) includes a source region, a drain region, and a channel region G10 located between the source region and the drain region. The channel region G10 is located at the intersection of the gate conductive layer 20 and the active area 10. The thin film transistors TFT1, TFT2, TFT3, and TFT4 include transfer holes K1-1, K1-2, and K1-3; the distance between the center of the transfer hole K1-1 and the channel region G10 is a, the distance between the center of the transfer hole K1-2 and the channel region G10 is b, the distance between the center of the transfer hole K1-3 and the channel region G10 is c, and the size of the transfer holes K1-1, K1-2, and K1-3 is e. The thin film transistor TFT1 also includes two dummy transfer holes K2, each having a size d. It should be noted that the channel width-to-length ratio W / L of thin film transistors TFT1, TFT2, TFT3, and TFT4 is the same. The values ​​of a, b, c, d, and e in thin film transistors TFT1, TFT2, TFT3, and TFT4 are shown in Table 1 below.

[0040] Table 1

[0041] Table 1 shows that the threshold voltages Vth of thin-film transistors TFT1, TFT2, TFT3, and TFT4 differ from one another. Since TFT2 lacks two dummy transfer holes K2 compared to TFT1, the threshold voltage Vth of TFT1 is more negatively biased than the threshold voltage Vth of TFT1. Since the distances a, b, and c between the center of the transfer hole and the channel region in TFT2 are smaller than the distances a, b, and c between the center of the transfer hole and the channel region in TFT3, the threshold voltage Vth of TFT2 is more negatively biased than the threshold voltage Vth of TFT3. Since the size e of the transfer hole in TFT2 is smaller than the size e of the transfer hole in TFT4, the threshold voltage Vth of TFT4 is more negatively biased than the threshold voltage Vth of TFT2. The values ​​in Table 1 show that the greater the number of transfer holes and dummy transfer holes, the smaller the distances a, b, and c between the center of the transfer hole and the channel region, and the larger the size of the transfer hole, the more negative the threshold voltage Vth. Therefore, the embodiment of the present disclosure adjusts the design of the transfer hole to adjust the threshold voltage of the thin film transistor.

[0042] For example, if the threshold voltage of the thin film transistor is positively biased, the threshold voltage of the thin film transistor can be made as negatively biased as possible by increasing the number of transfer holes and virtual transfer holes, reducing the distance between the center of the transfer hole and the channel region, and increasing the size of the transfer hole. The negative bias and the positive bias are then neutralized, thereby improving the drift of the threshold voltage of the thin film transistor.

[0043] For example, if the threshold voltage of the thin film transistor is negatively biased, the threshold voltage of the thin film transistor can be made as positively biased as possible by reducing the number of transfer holes and virtual transfer holes, increasing the distance between the center of the transfer hole and the channel region, and reducing the size of the transfer hole, thereby neutralizing the positive bias and the negative bias, thereby improving the drift of the threshold voltage of the thin film transistor.

[0044] The display panel provided by the embodiment of the present disclosure, as shown in FIG7 and FIG8 , includes: a base substrate, a first shift register 111 and a second shift register 112 located on the base substrate; the first shift register 111 and the second shift register 112 each include a first output transistor M1, a second output transistor M2, and a plurality of transfer holes K1; the transfer holes K1 are used to bridge the active area of ​​the first output transistor M1 and the active area of ​​the second output transistor M2 through a conductive layer; wherein the number of transfer holes K1 in the second shift register 112 is greater than the number of transfer holes K1 in the first shift register 112;

[0045] The threshold voltage of the first output transistor M1 in the second shift register 112 is more negative than the threshold voltage of the first output transistor M1 in the first shift register 111; the threshold voltage of the second output transistor M2 in the second shift register 112 is more negative than the threshold voltage of the second output transistor M2 in the first shift register 111.

[0046] In the embodiment of the present disclosure, the number of transfer holes K1 in the second shift register 112 is greater than the number of transfer holes K1 in the first shift register 111, thereby achieving a negative bias in the threshold voltage of the first output transistor M1 in the second shift register 112 compared to the threshold voltage of the first output transistor M1 in the first shift register 111; and a negative bias in the threshold voltage of the second output transistor M2 in the second shift register 112 compared to the threshold voltage of the second output transistor M2 in the first shift register 111. As a result, the threshold voltage of the first output transistor M1 and the threshold voltage of the second output transistor M2 can be relatively negative, avoiding the influence of the positive bias of the threshold voltage during electrostatic field or high temperature power-up. That is, the negative bias and the positive bias are neutralized, thereby avoiding leakage and signal abnormalities, thereby improving the display effect.

[0047] For example, as shown in Figures 7 and 8, the number of transfer holes K1 on the right side of the first output transistor M1 in the first shift register 111 is 6, and the number of transfer holes K1 on the right side of the second output transistor M2 in the first shift register 111 is 4; the number of transfer holes K1 on the right side of the first output transistor M1 in the second shift register 112 is 5, and the number of transfer holes K1 on the right side of the second output transistor M2 in the second shift register 112 is 10; that is, the number of transfer holes K1 in the second shift register 112 is greater than the number of transfer holes K1 in the first shift register 111. Of course, the number of transfer holes K1 in the first shift register 111 and the number of transfer holes K1 in the second shift register 112 can also be other values, which are not limited here.

[0048] In some embodiments of the present disclosure, as shown in FIG. 7 and FIG. 9 , the size of the transfer hole K1 - 1 in the second shift register 112 is larger than the size of the transfer hole K1 in the first shift register 111 .

[0049] For example, as shown in Figures 7 and 9, the size of the transfer hole K1-1 in the second shift register 112 is larger than the size of the transfer hole K1-2 in the second shift register 112. The size of the transfer hole K1-2 in the second shift register 112 can be the same as the size of the transfer hole K1 in the first shift register 111. Of course, the size of the transfer hole K1-2 in the second shift register 112 can also be different from the size of the transfer hole K1 in the first shift register 111, which is not limited here.

[0050] In some embodiments of the present disclosure, as shown in FIG7 and FIG9 , the size K1 of the transfer hole in the first shift register 111 is between 2.3 microns and 3.5 microns; the size of the transfer hole K1 - 1 in the second shift register 112 is between 2.5 microns and 4 microns.

[0051] Exemplarily, the size of the transfer hole K1 - 2 in the second shift register 112 is between 2.3 microns and 3.5 microns.

[0052] In some embodiments of the present disclosure, as shown in FIG. 7 to FIG. 10 , orthographic projections of some transfer holes K1 and K1 - 1 on the substrate overlap with orthographic projections of active areas of the first output transistor M1 and the second output transistor M2 on the substrate.

[0053] In some embodiments of the present disclosure, as shown in Figure 10, the second shift register 112 also includes: a plurality of virtual transfer holes K2; the orthographic projections of the virtual transfer holes K2 on the substrate are adjacent to the active layer of the first output transistor M1 and the orthographic projections of the active layer of the second output transistor M2 on the substrate.

[0054] Exemplarily, as shown in FIG10 , a column of dummy vias K2 is provided on the left side of the active layer of the first output transistor M1 and the active layer of the second output transistor M2 .

[0055] In some embodiments of the present disclosure, as shown in Figures 7 to 11, the gate of the first output transistor M1 is coupled to the first node N1, the first electrode of the first output transistor M1 is coupled to the first level signal line VGH, and the second electrode of the first output transistor M1 is coupled to the cascade output signal line Out; the gate of the second output transistor M2 is coupled to the second node N2, the first electrode of the second output transistor M2 is coupled to the second level signal line VGL, and the second electrode of the second output transistor M2 is coupled to the cascade output signal line Out. Figure 11 is an equivalent circuit diagram of Figures 7 to 10.

[0056] Exemplarily, as shown in Figures 7 to 11, the display panel further includes: a first clock signal line CK, a second clock signal line CB, a frame start signal line STV, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, a first capacitor C1, a second capacitor C2, and a third capacitor C3; wherein the gate of the first transistor T1 is coupled to the first clock signal line CK, the first electrode of the first transistor T1 is coupled to the frame start signal line STV, and the second electrode of the first transistor T1 is coupled to the gate of the second transistor T2. The gate of the fourth transistor T4 is coupled to the second node N2, the first electrode of the fourth transistor T4 is coupled to the second electrode of the fifth transistor T5, and the second electrode of the fourth transistor T4 is coupled to the second clock signal line CB; the gate of the fifth transistor T5 is coupled to the second electrode of the third transistor T3, and the first electrode of the fifth transistor T5 is coupled to the first clock signal line VGH; the gate of the second transistor T3 is coupled to the first clock signal line CK, and the first electrode of the third transistor T3 is coupled to the second level signal line VGL; the gate of the fourth transistor T4 is coupled to the second node N2, the first electrode of the fourth transistor T4 is coupled to the second electrode of the fifth transistor T5, and the second electrode of the fourth transistor T4 is coupled to the second clock signal line CB; the gate of the fifth transistor T5 is coupled to the second electrode of the third transistor T3, and the first electrode of the fifth transistor T5 is coupled to the first level signal line VGH; A first electrode of the capacitor C2 is coupled to the second electrode of the fifth transistor T5, and the second electrode of the second capacitor C2 is coupled to the second node N2; a gate of the sixth transistor T6 is coupled to the first electrode of the first capacitor C1, a first electrode of the sixth transistor T6 is coupled to the second clock signal line CB, and a second electrode of the sixth transistor T6 is coupled to the second electrode of the first capacitor C1; a gate of the seventh transistor T7 is coupled to the second clock signal line CB, a first electrode of the seventh transistor T7 is coupled to the second electrode of the sixth transistor T6, and a second electrode of the seventh transistor T7 is coupled to the first node N1; a first electrode of the third capacitor C3 is coupled to the first level signal line VGH, and a second electrode of the third capacitor C3 is coupled to the first level signal line VGH. The first node N1 is coupled; the gate of the eighth transistor T8 is coupled to the second electrode of the first transistor T1, the first electrode of the eighth transistor T8 is coupled to the first node N1, and the second electrode of the eighth transistor T8 is coupled to the first level signal line VGH; the gate of the ninth transistor T9 is coupled to the second level signal line VGL, the first electrode of the ninth transistor T9 is coupled to the gate of the fifth transistor T5, and the second electrode of the ninth transistor T9 is coupled to the gate of the sixth transistor T6; the gate of the tenth transistor T10 is coupled to the second level signal line VGL, the first electrode of the tenth transistor T10 is coupled to the gate of the eighth transistor T8, and the second electrode of the tenth transistor T10 is coupled to the second node N2.

[0057] For example, the first electrode of the transistor can be its source electrode, and the second electrode can be its drain electrode. Alternatively, the first electrode can be its drain electrode, and the second electrode can be its source electrode. This is not limited here.

[0058] Generally, transistors using low-temperature polysilicon (LTPS) as active layers have high mobility and can be made thinner and smaller, with lower power consumption. In a specific implementation, the active layer of at least one of the transistors can be made of low-temperature polysilicon. This allows the transistor to be an LTPS transistor, thereby achieving high mobility in the pixel circuit, and allowing it to be made thinner and smaller, with lower power consumption.

[0059] Generally, transistors using metal oxide semiconductor materials as their active layers have low leakage current. Therefore, to reduce leakage current, in some embodiments of the present disclosure, the active layer of at least one of the transistors may include a metal oxide semiconductor material, such as IGZO (Indium Gallium Zinc Oxide). Of course, other metal oxide semiconductor materials are also possible and are not limited here. In this way, the transistor can be configured as an oxide thin film transistor, thereby reducing leakage current in the pixel circuit.

[0060] Exemplarily, all transistors may be configured as LTPS transistors.

[0061] Alternatively, all transistors can be configured as oxide-type transistors. Since metal oxides are relatively inexpensive, there is no need to use laser equipment for crystallization.

[0062] Alternatively, some transistors may be configured as oxide-type transistors, and the remaining transistors may be configured as LTPS-type transistors.

[0063] In some embodiments of the present disclosure, the present invention also includes: a semiconductor layer located on the substrate, a gate insulating layer located on the side of the semiconductor layer facing away from the substrate, a gate conductive layer located on the side of the gate insulating layer facing away from the substrate, a first insulating layer located on the side of the gate conductive layer facing away from the substrate, a first conductive layer located on the side of the first insulating layer facing away from the substrate, a second insulating layer located on the side of the first conductive layer facing away from the substrate, and a second conductive layer located on the side of the second insulating layer facing away from the substrate.

[0064] In some embodiments of the present disclosure, the gate conductive layer includes: a gate of the first output transistor M1 and a gate of the second output transistor M2; the semiconductor layer includes: an active area of ​​the first output transistor M1 and an active area of ​​the second output transistor M2; the active area of ​​the first output transistor M1 includes: a first electrode and a second electrode of the first output transistor M1; the active area of ​​the second output transistor M2 includes: a first electrode and a second electrode of the second output transistor M2; the conductive layer includes: a first conductive layer and a second conductive layer; wherein the first level signal line VGH and the second level signal line VGL are located in the second conductive layer; and the cascade output signal line Out is located in the first conductive layer or the second conductive layer.

[0065] Exemplarily, as shown in FIG. 7 to FIG. 9 , the cascade output signal line Out is located in the first conductive layer.

[0066] Exemplarily, as shown in FIG10 , the cascade output signal line Out is located in the second conductive layer.

[0067] Exemplarily, the gate conductive layer further includes: a gate of the first transistor T1, a gate of the second transistor T2, a gate of the third transistor T3, a gate of the fourth transistor T4, a gate of the fifth transistor T5, a gate of the sixth transistor T6, a gate of the seventh transistor T7, a gate of the eighth transistor T8, a gate of the ninth transistor T9, and a gate of the tenth transistor T10;

[0068] Exemplarily, the semiconductor layer also includes: an active area of ​​the first transistor T1, an active area of ​​the second transistor T2, an active area of ​​the third transistor T3, an active area of ​​the fourth transistor T4, an active area of ​​the fifth transistor T5, an active area of ​​the sixth transistor T6, an active area of ​​the seventh transistor T7, an active area of ​​the eighth transistor T8, an active area of ​​the ninth transistor T9, and an active area of ​​the tenth transistor T10.

[0069] Exemplarily, the active region of a transistor includes a source region, a drain region, and a channel region located between the source region and the drain region. The source region can be the first electrode of the transistor, and the drain region can be the second electrode of the transistor; alternatively, the source region can be the second electrode of the transistor, and the drain region can be the first electrode of the transistor; this is not limited here.

[0070] Exemplarily, if the first electrode of the first capacitor C1 is located in the gate conductive layer, the second electrode of the first capacitor C1 is located in the first conductive layer; if the second electrode of the first capacitor C1 is located in the gate conductive layer, the first electrode of the first capacitor C1 is located in the first conductive layer; if the first electrode of the second capacitor C2 is located in the gate conductive layer, the second electrode of the second capacitor C2 is located in the first conductive layer; if the second electrode of the second capacitor C2 is located in the gate conductive layer, the first electrode of the second capacitor C2 is located in the first conductive layer; if the first electrode of the third capacitor C3 is located in the gate conductive layer, the second electrode of the third capacitor C3 is located in the first conductive layer; if the second electrode of the third capacitor C3 is located in the gate conductive layer, the first electrode of the third capacitor C3 is located in the first conductive layer.

[0071] Exemplarily, the first clock signal line CK, the second clock signal line CB, and the frame start signal line STV are all located in the second conductive layer.

[0072] For example, the semiconductor layer can be formed by patterning a semiconductor material. The semiconductor layer can be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc., without limitation herein. It should be noted that the source region and drain region can be conductive regions formed by doping with n-type impurities or p-type impurities.

[0073] Exemplarily, the materials of the first conductive layer and the second conductive layer may be conductive materials. For example, the conductive material may include metal materials or alloy materials such as aluminum, molybdenum, and titanium, or metal oxides such as indium tin oxide (ITO). The embodiments of the present disclosure do not limit the materials of the functional layers.

[0074] Exemplarily, the gate insulating layer, the first insulating layer, and the second insulating layer are all formed of insulating materials. As needed, organic insulating materials such as polyimide, resin materials, etc. can be selected, or inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, etc. can be selected. The embodiments of the present disclosure do not specifically limit the materials of each functional layer.

[0075] In some embodiments of the present disclosure, as shown in FIG. 7 to FIG. 9 , when the cascade output signal line Out is located in the first conductive layer, the orthographic projections of some transfer holes K1 and K1 - 1 on the base substrate overlap with the orthographic projections of the cascade output signal line Out on the base substrate.

[0076] In some embodiments of the present disclosure, as shown in FIG10 , when the cascade output signal line Out is located in the second conductive layer, the orthographic projection of a portion of the transfer hole K1 on the base substrate overlaps with the orthographic projection of the gate conductive layer on the base substrate.

[0077] Based on the same inventive concept, the present disclosure also provides a display device comprising the display panel described above. The principles of this display device are similar to those of the aforementioned display panel, so the implementation of this display device can refer to the implementation of the aforementioned display panel, and any repetitions will not be repeated here.

[0078] In specific implementations, in the embodiments of the present disclosure, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigation system, or the like. Other essential components of the display device are well understood by those skilled in the art and are not detailed here, nor should they be construed as limitations of the present disclosure.

[0079] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0080] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. A display panel, characterized in that: include: A base substrate, a first shift register and a second shift register located on the base substrate; the first shift register and the second shift register each include a first output transistor, a second output transistor and a plurality of transfer holes; The transfer hole is used to bridge the active area of ​​the first output transistor and the active area of ​​the second output transistor through a conductive layer; wherein the number of the transfer holes in the second shift register is greater than the number of transfer holes in the first shift register; and / or the size of the transfer holes in the second shift register is greater than the size of the transfer holes in the first shift register; The threshold voltage of the first output transistor in the second shift register is negatively biased compared to the threshold voltage of the first output transistor in the first shift register; the threshold voltage of the second output transistor in the second shift register is negatively biased compared to the threshold voltage of the second output transistor in the first shift register.

2. The display panel according to claim 1, wherein: The orthographic projection of a portion of the transfer hole on the substrate overlaps with the orthographic projection of the active area of ​​the first output transistor and the active area of ​​the second output transistor on the substrate.

3. The display panel according to claim 2, wherein: The size of the transfer hole in the first shift register is between 2.3 microns and 3.5 microns; the size of the transfer hole in the second shift register is between 2.5 microns and 4 microns.

4. The display panel according to any one of claims 1 to 3, characterized in that: The second shift register further includes: a plurality of virtual switching holes; The orthographic projection of the virtual via on the substrate is adjacent to the orthographic projection of the active layer of the first output transistor and the orthographic projection of the active layer of the second output transistor on the substrate.

5. The display panel according to claim 4, wherein: The gate of the first output transistor is coupled to the first node, the first electrode of the first output transistor is coupled to the first level signal line, and the second electrode of the first output transistor is coupled to the cascade output signal line; The gate of the second output transistor is coupled to the second node, and the One electrode is coupled to the second level signal line, and the second electrode of the second output transistor is coupled to the cascade output signal line.

6. The display panel according to claim 5, wherein: Also includes: A semiconductor layer located on the substrate, a gate insulating layer located on the side of the semiconductor layer facing away from the substrate, a gate conductive layer located on the side of the gate insulating layer facing away from the substrate, a first insulating layer located on the side of the gate conductive layer facing away from the substrate, a first conductive layer located on the side of the first insulating layer facing away from the substrate, a second insulating layer located on the side of the first conductive layer facing away from the substrate, and a second conductive layer located on the side of the second insulating layer facing away from the substrate.

7. The display panel according to claim 6, wherein: The gate conductive layer includes: a gate of the first output transistor and a gate of the second output transistor; the semiconductor layer includes: an active region of the first output transistor and an active region of the second output transistor; the active region of the first output transistor includes: a first electrode and a second electrode of the first output transistor; the active region of the second output transistor includes: a first electrode and a second electrode of the second output transistor; The conductive layer comprises: the first conductive layer and the second conductive layer; The first level signal line and the second level signal line are located in the second conductive layer; the cascade output signal line is located in the first conductive layer or the second conductive layer.

8. The display panel according to claim 7, wherein: When the cascade output signal line is located in the first conductive layer, an orthographic projection of a portion of the transfer hole on the base substrate overlaps with an orthographic projection of the cascade output signal line on the base substrate.

9. The display panel according to claim 7, wherein: When the cascade output signal line is located in the second conductive layer, the orthographic projection of a portion of the transfer hole on the base substrate overlaps with the orthographic projection of the gate conductive layer on the base substrate.

10. A display device, characterized in that: Comprising a display panel as described in any one of claims 1 to 9.

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