Quantum state preparation method and apparatus, device, and storage medium

Abstract

A quantum state preparation method and apparatus, a device, and a storage medium, relating to the field of quantum technology. The method comprises: determining initial quantum states of n quantum bits, n being a positive integer (201); on the basis of the n quantum bits and a Hamming weight k, constructing an initial quantum state unitary transformation circuit by means of recursive decomposition (202); on the basis of idle quantum bits in the initial quantum state unitary transformation circuit, compressing a circuit depth of a weight allocation transformation operator, so as to obtain a quantum state unitary transformation circuit (203); and applying the quantum state unitary transformation circuit to the initial quantum states, so as to obtain a first quantum state circuit (204).

Description

Quantum state preparation method, device, equipment and storage medium

[0001] This application claims priority to Chinese patent application No. 202311770930.0, filed on December 21, 2023, entitled “Method, device, equipment and storage medium for preparing quantum states”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the quantum field, and in particular to a method, device, equipment and storage medium for preparing a quantum state. Background Art

[0003] The Dicke state is a special quantum state that has a wide range of applications in various directions of quantum computing and quantum algorithms. The Dicke state of an n-qubit circuit is usually expressed as Where k represents the number of qubits in the system in the |1> state (excited state), while the remaining nk qubits are in the |0> state (ground state). The Dicke state is a superposition of these excited states symmetrically distributed across all qubits.

[0004] In the related art, the circuit framework for preparing Dicke states consists of a weight distribution transformation and a smaller Dicke state unitary matrix. In this framework, when implementing multi-layer weight distribution transformations, some quantum bits are idle. The idle quantum bits cannot be fully utilized during the weight distribution transformation, resulting in a larger circuit depth of the prepared Dicke state circuit.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a method, apparatus, device, and storage medium for preparing a quantum state. The technical solution is as follows:

[0007] According to one aspect of an embodiment of the present application, a method for preparing a quantum state is provided, the method comprising:

[0008] Determine the initial quantum state of n quantum bits, where n is a positive integer;

[0009] Based on n quantum bits and a Hamming weight k, an initial quantum state unitary transformation circuit is constructed by recursive decomposition, wherein the initial quantum state unitary transformation circuit includes a recursively obtained weight distribution transformation operator and a k-qubit unitary transformation operator, wherein the weight distribution transformation operator is used to distribute the Hamming weight of a first quantum state to multiple quantum bit strings, and the unitary transformation operator is used to evolve the quantum state of the quantum bit string to the first quantum state, and the initial quantum state unitary transformation circuit also includes idle quantum bits not occupied by the weight distribution transformation operator;

[0010] Compressing the circuit depth of the weight distribution transformation operator based on the idle quantum bits in the initial quantum state unitary transformation circuit to obtain a quantum state unitary transformation circuit, wherein the quantum state unitary transformation circuit is used to act on the initial quantum state to obtain a first quantum state circuit;

[0011] The quantum state unitary transformation circuit is applied to the initial quantum state to obtain a first quantum state circuit, wherein the first quantum state circuit includes k excited state quantum bits.

[0012] According to one aspect of an embodiment of the present application, a device for preparing a quantum state is provided, the device comprising:

[0013] An initial quantum state acquisition module is used to determine the initial quantum state of n quantum bits, where n is a positive integer;

[0014] a recursive decomposition module, configured to construct an initial quantum state unitary transformation circuit by recursive decomposition based on n quantum bits and a Hamming weight k, wherein the initial quantum state unitary transformation circuit includes a recursively obtained weight distribution transformation operator and a k-qubit unitary transformation operator, wherein the weight distribution transformation operator is configured to distribute the Hamming weight of a first quantum state to multiple quantum bit strings, the unitary transformation operator is configured to cause the quantum state of the quantum bit string to evolve to the first quantum state, and the initial quantum state unitary transformation circuit also includes idle quantum bits not occupied by the weight distribution transformation operator;

[0015] a depth compression module, configured to compress the circuit depth of the weight distribution transformation operator based on idle quantum bits in the initial quantum state unitary transformation circuit to obtain a quantum state unitary transformation circuit, wherein the quantum state unitary transformation circuit is configured to act on the initial quantum state to obtain a first quantum state circuit;

[0016] A quantum state preparation module is used to apply the quantum state unitary transformation circuit to the initial quantum state to obtain a first quantum state circuit, wherein the first quantum state circuit includes k excited state quantum bits.

[0017] According to one aspect of an embodiment of the present application, a computer device is provided, comprising a processor and a memory, wherein a computer program is stored in the memory, and the computer program is loaded and executed by the processor to implement the above method.

[0018] According to one aspect of an embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored. The computer program is loaded and executed by a processor to implement the above method.

[0019] According to one aspect of an embodiment of the present application, a computer program product is provided, the computer program product including a computer program stored in a computer-readable storage medium. A processor of a computer device reads the computer program from the computer-readable storage medium and executes the computer program, causing the computer device to perform the above method.

[0020] The technical solutions provided by the embodiments of the present application may have the following beneficial effects:

[0021] First, based on n quantum bits and Hamming weight k, an initial quantum state unitary transformation circuit is constructed through recursive decomposition, and the idle quantum bits in the initial quantum state unitary transformation circuit that are not occupied by the weight distribution transformation operator are used as auxiliary quantum bits. Part of the circuit functions in the first quantum state circuit preparation process are realized through the auxiliary quantum bits, which improves the operational parallelism of the quantum state preparation operator, and performs circuit depth compression on the weight distribution transformation circuit, thereby compressing the circuit depth of the quantum state unitary transformation circuit. On this basis, the depth of the first quantum state circuit is compressed, thereby improving the circuit operation efficiency of the first quantum state circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] FIG1 is a schematic diagram of an implementation environment of a solution provided by an embodiment of the present application;

[0023] FIG2 is a flow chart of a method for preparing a quantum state provided in one embodiment of the present application;

[0024] FIG3 is a schematic diagram of a Dicke state unitary matrix circuit framework provided by one embodiment of the present application;

[0025] FIG4 is a flow chart of a method for preparing a quantum state according to another embodiment of the present application;

[0026] FIG5 is a schematic diagram of a Toffoli gate circuit grouping method provided by one embodiment of the present application;

[0027] FIG6 is a schematic diagram of a Toffoli gate circuit grouping method provided by another embodiment of the present application;

[0028] FIG7 is a block diagram of a quantum state preparation device provided by one embodiment of the present application;

[0029] FIG8 is a block diagram of a quantum state preparation device provided by another embodiment of the present application;

[0030] FIG9 is a structural block diagram of a computer device provided in one embodiment of the present application. DETAILED DESCRIPTION

[0031] Before introducing the technical solution of this application, some terms involved in this application are explained.

[0032] 1. Quantum computing: A computing method based on quantum logic, where the basic unit of data storage is the quantum bit (Qubit).

[0033] 2. Qubit: It is the basic unit of quantum computing. Traditional computers use 0 and 1 as the basic units of binary. However, quantum computing can process 0 and 1 simultaneously, and the system can be in a linear superposition state of 0 and 1: |ψ>=α|0>+β|1>, where α and β represent the complex probability amplitude of the system at 0 and 1. Their squared modulus |α| 2 ,|β| 2 represent the probabilities of being 0 and 1 respectively.

[0034] 3. Quantum state: The quantum state of a system can be represented as a linear combination of basis states. For example, for a 1-qubit system, all possible basis states are 0 and 1, while for a 3-qubit system, all possible basis states are 000, 001, 010, 011, 100, 101, 110, 111, a total of 8. Let these basis states be φ i , then the quantum state can be expressed as ∑ i c i φ i , where c i are the linear combination coefficients.

[0035] 4. Quantum circuit: A representation of a quantum universal computer, representing the hardware implementation of a corresponding quantum algorithm or program within the quantum gate model. A quantum circuit acts on a quantum state, generating a new quantum state and completing a quantum computation. If a quantum circuit includes adjustable parameters for controlling quantum gates, it is called a parameterized quantum circuit (PQC) or a variational quantum circuit.

[0036] 5. Quantum entanglement is the process of creating an entangled state between two or more quantum systems through a series of operations. Superconducting quantum circuits, a quantum system based on superconducting materials, can be used to create and manipulate quantum entanglement. High-quality quantum entanglement can be achieved by precisely controlling the interactions between superconducting qubits.

[0037] 6. Quantum circuit depth: This refers to the number of gate layers or depth within a quantum circuit. A quantum circuit is the fundamental unit used to describe quantum computing, consisting of qubits and quantum gates. If the quantum circuit depth is equal to the number of quantum gate layers, it corresponds to the parallel execution time of a quantum algorithm.

[0038] Due to the decoherence property of quantum bits, that is, entanglement decreases with time, in order to ensure the operation effect of quantum circuits, the smaller the quantum circuit depth, the better. Quantum circuit depth is an important indicator to measure the quality of quantum circuits. Since the life of quantum bits is short, if a quantum circuit with a large depth is executed on a quantum device, the circuit will not be completed after the quantum bit life ends, which will greatly affect the operation effect of the quantum circuit. In order to reduce the impact of excessive quantum circuit depth on the operation effect of quantum circuits, the quantum circuit is required to have a circuit depth as small as possible. In the embodiment of the present application, a Dicke state is provided. Preparation method, that is, given the initial n-qubit quantum state |0 n >, design an n-qubit circuit C n , the quantum circuit satisfies

[0039] 7. Qubit connectivity restrictions: In superconducting quantum devices, two-qubit gates can only operate on specific qubit pairs. There are several different types of qubit connectivity restrictions, the most common of which are path restrictions and grid restrictions. Designing quantum circuits for Dicke states under these restrictions is crucial.

[0040] 8. Dicke states: These are an important type of entangled state with widespread applications in quantum networks, quantum game theory, and quantum algorithms. In particular, Dicke states serve as the initial quantum state for quantum algorithms that solve combinatorial problems, such as variational quantum algorithms and adiabatic computing, which are noisy, medium-scale quantum algorithms.

[0041] The Dicke state is an equally weighted superposition of all n quantum states under the Hamming weight k constraint. For example, the (n, k)-Dicke state is defined as follows:

[0042] Here, the Hamming weight hw(x) represents the number of base states 1 in the n-qubit string x, and the binomial coefficient The quantum bits in the n-quantum circuit in the Dicke state are entangled with each other.

[0043] For example,

[0044] 9. Basic symbols: [n] and [n]0 represent the sets of integers {1, 2, …, n} and {0, 1, 2, …, n}, respectively. For a set S, |S| represents the size of the set.

[0045] For any bit string x∈{0,1} n, the Hamming weight hw(x) represents the number of base states 1 in the bit string x. If V represents a set of quantum bits, then the symbol |ψ> V The |V|-qubit quantum state |ψ> is the quantum state of the qubit set V. Symbol 0 k and 1 k Represents a bit string consisting of k 0s and 1s respectively. represents addition over a binary field.

[0046] 10. Dicke state unitary transformation, also known as Dicke state unitary operator: an n-qubit Dicke state unitary transformation satisfy in Indicates a -Dicke state.

[0047] 11. Weight distribution block (WDB), also known as distribution operator: Let S1 and S2 represent sets of k-sized disjoint qubits. For any integer n≥m≥k, a 2k-qubit weight distribution block (S1, S2) satisfies

[0048] Among them if Then the binomial coefficient The weight distribution transformation is a transformation that acts on the quantum bit sets S1 and S2. Its function is to transform the quantum bit set S1 into 1 is allocated to S1 and S2, and each allocation method is assigned a different weight. More specifically, when there is 1, if i 1 and 1 is allocated to S2 and S1 respectively, and the weight of this allocation scheme is equipped

[0049] 12. If the circuit construction uses auxiliary quantum bits, the initial state of the quantum bits is |0> and is restored to |0> after the circuit ends.

[0050] 12.1 Reversible logic gate, also known as Toffoli gate. For any y∈{0,1} n-1 , the n-qubit Toffoli gate T of(y) is defined as follows, for any x∈{0,1} n-1 and a∈{0,1},

[0051] That is, when the control bits x and y are equal, the target bit a is flipped; otherwise, the target bit remains unchanged. If no auxiliary qubits are used, the n-qubit Toffoli gate can be implemented by a quantum circuit with a depth of O(n); if O(n) auxiliary qubits are used, it can be implemented by a quantum circuit with a depth of O(log(n)).

[0052] 12.2 Sum transformation. For any x = x1x2…x n ∈{0,1} n and t∈{0,1}, the sum transformation satisfies

[0053] The sum transformation can be implemented by a quantum circuit with a depth of O(log(n)).

[0054] 12.3 Copy Transformation. For any x∈{0,1} n and an integer p, if |x> is copied p times, then the copy transformation satisfies:

[0055] The copy transformation can be implemented by a circuit with depth O(log(p)).

[0056] 12.4 Controlled Quantum State Preparation. A (n, k)-controlled quantum state preparation is defined as follows:

[0057] |x>|0 k >→|x>|ψ x >, And |ψ x > is any k-qubit quantum state. If N (N≥0) auxiliary qubits are used, any (n,k)-control quantum state can be prepared by a depth of Quantum circuit implementation of .

[0058] 12.5 CNOT circuit. A circuit consisting only of CNOT gates is called a CNOT circuit. Given N ≥ 0 auxiliary qubits, the depth of any n-qubit CNOT circuit can be compressed to

[0059] In an embodiment of the present application, a circuit structure for Dicke state preparation with a circuit depth of O(log(k)log(n / k)+k) is proposed. The embodiment of the present application is mainly divided into two parts: (1) a circuit framework of the Dicke state preparation circuit, which is composed of a weight distribution transformation circuit and a Dicke state unitary transformation circuit; (2) in the circuit framework, some quantum bits are idle. In an embodiment of the present application, idle quantum bits are used as auxiliary quantum bits to compress the weight distribution transformation circuit. In the construction of the Dicke state preparation circuit, idle quantum bits are used as auxiliary bits to construct the weight distribution transformation, thereby obtaining a quantum circuit with a shallower depth.

[0060] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0061] Please refer to FIG1 , which shows a schematic diagram of an implementation environment of a solution provided by an embodiment of the present application. The implementation environment of the solution may include: a terminal device 10 and a server 20 .

[0062] The terminal device 10 may be an electronic device such as a quantum computer, a smartphone, a tablet computer, a laptop computer, a desktop computer, a smart speaker, a smart watch, a smart home appliance, a multimedia player, a PC (Personal Computer), an intelligent robot, an in-vehicle terminal, a wearable device, or the like. The terminal device 10 may be installed with a client for a target application, which may be any application for preparing quantum states.

[0063] The server 20 is used to provide background services for the client of the target application in the terminal device 10. For example, the server 20 can be the background server of the target application. The server 20 can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers. It can also be a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN (Content Delivery Network), and big data and artificial intelligence platforms. The embodiments of the present application are not limited to this.

[0064] The terminal device 10 and the server 20 can communicate with each other via a network 30. The network 30 can be a wired network or a wireless network.

[0065] Exemplarily, the user initializes the initial quantum state of n quantum bits and configures the Hamming weight k in the client in the terminal device 10. Based on these data, the client first constructs an initial Dicke state unitary transformation circuit through recursive decomposition, and performs circuit depth compression on the weight distribution transformation circuit through the idle quantum bits in the initial Dicke state unitary transformation circuit, thereby obtaining the Dicke state unitary transformation circuit, and applying the Dicke state unitary transformation circuit to the initial quantum state to obtain the Dicke state circuit.

[0066] Optionally, the preparation process of the Dicke state circuit may also be completed by the server 20, which is not limited in the embodiment of the present application.

[0067] Below, the technical solution provided by this application will be introduced and explained through method embodiments.

[0068] Please refer to Figure 2, which shows a flow chart of a method for preparing a quantum state provided by an embodiment of the present application. The execution subject of each step of the method can be the terminal device 10 or the server 20 in the implementation environment of the solution shown in Figure 1. For the sake of ease of description, only the execution subject of each step is described as the "client in the terminal device 10". The method can include at least one of the following steps (201-204):

[0069] Step 201: Determine the initial quantum state of n quantum bits, where n is a positive integer.

[0070] The initial quantum state is used to indicate the initial basis state of each of the n quantum bits (such as all 0, or all 1, or any combination of 0 and 1), and the initial entanglement relationship between the n quantum bits (such as no entanglement). The embodiment of the present application does not limit the initial quantum state of the n quantum bits.

[0071] Step 202: Based on n quantum bits and Hamming weight k, construct an initial quantum state unitary transformation circuit through recursive decomposition.

[0072] Among them, the initial quantum state unitary transformation circuit includes a recursively obtained weight distribution transformation operator and a k-qubit unitary transformation operator, wherein the weight distribution transformation operator is used to distribute the Hamming weight k of the first quantum state to multiple quantum bit strings, and the unitary transformation operator is used to make the quantum state of the quantum bit string evolve to the first quantum state. The initial quantum state unitary transformation circuit also includes idle quantum bits, which are quantum bits that are not occupied by the weight distribution transformation operator.

[0073] That is, some operators are recursively obtained in the initial quantum state unitary transformation circuit as weight distribution transformation operators, and some operators are used as unitary transformation operators, among which the quantum bits not occupied by the weight distribution transformation operators are idle quantum bits.

[0074] The weight distribution transformation operator is used to construct a weight distribution circuit, which distributes the Hamming weight of the first quantum state to multiple qubit strings. The unitary transformation operator is used to construct a unitary transformation circuit, which evolves the quantum state of the qubit string to the first quantum state. A qubit string is a sequence of multiple qubits. For example, two qubits can form a qubit string. The possible states of this string include not only the classical bit string "00," "01," "10," and "11," but also any superposition of these states.

[0075] In some embodiments, the value of k is equal to the Hamming weight of a first quantum state, where the first quantum state is the quantum state to which the n qubits are to be evolved, such as a Dicke state. For example, the value of k is equal to the Hamming weight that results in the n qubits being in the Dicke state. Here, k is a positive integer. In some embodiments, the value of the Hamming weight k is pre-set.

[0076] Optionally, the embodiment of the present application adopts the idea of ​​divide and conquer to construct the circuit framework. First, we pass a quantum circuit with a depth of 1 Acting on the initial quantum state |0 n >, then apply Dicke state unitary transformation The Dicke state circuit can be prepared. Represents a tensor product.

[0077] Therefore, in the embodiment of the present application, by constructing the Dicke state unitary transformation The circuit framework is used to realize the preparation of Dicke state.

[0078] In some embodiments, n qubits are divided into qubit sets of size k, and there are a total of n / k sets (assuming n / k is an integer without loss of generality).

[0079] For any The initial quantum state unitary transformation circuit is constructed by the following recursive decomposition. First, the 2k-qubit weight distribution transformation is applied to the initial quantum state. And, the first quantum state unitary transformation of n / 2-qubits in parallel For weight distribution transformation and the first quantum state unitary transformation Perform recursive decomposition until the number of qubits of the first quantum state unitary transformation is k, and obtain the initial quantum state unitary transformation circuit. The initial quantum state unitary transformation circuit is obtained by recursive decomposition, and the specific and unitary transformation characteristics of the full assist distribution transformation are applied to the initial quantum state of n qubits, so that the 2k-qubit weight distribution transformation and the n / 2-qubit first quantum state unitary transformation are applied to the initial quantum state of n qubits. After that, it can be recursively decomposed layer by layer until the number of quantum bits of the unitary transformation is reduced to k, thereby realizing the construction of the first quantum state unitary transformation and weight distribution transformation, and improving the construction efficiency.

[0080] Schematically, the process of recursively decomposing and constructing the initial quantum state unitary transformation circuit is as follows:

[0081] Without loss of generality, we assume that n / 2 is an integer. First, we apply a 2k-qubit weight distribution transformation (Will (S1,S2) is abbreviated as ), and then perform the Dicke state unitary transformation of two n / 2-qubits in parallel Right now

[0082] for Adoption and The same circuit framework, i.e. By recursive decomposition layer by layer, until the number of quantum bits of the first quantum state unitary transformation is reduced to k, that is, until the first quantum state unitary transformation is recursively From the above construction, it can be seen that the number of 2k-qubit weight distribution transformations obtained in each recursion is twice that of the previous one. Therefore, in the final circuit framework, the number of layers of weight distribution transformations is log(n / k).

[0083] Taking the first quantum state as a Dicke state as an example, as shown in Figure 3, it shows a Dicke state unitary matrix circuit framework provided by an exemplary embodiment of the present application. The circuit framework 310 consists of a log(n / k) layer of weight distribution transformation 320 and a single layer of k-qubit Dicke state unitary transformation 330.

[0084] Step 203 , based on the idle quantum bits in the initial quantum state unitary transformation circuit, the circuit depth of the weight distribution transformation operator is compressed to obtain the quantum state unitary transformation circuit.

[0085] The quantum state unitary transformation circuit is used to act on the initial quantum state to obtain a first quantum state circuit.

[0086] In some embodiments, the weight distribution transformation operator constitutes a weight distribution transformation circuit, and the circuit depth of the weight distribution transformation circuit is compressed based on the idle quantum bits.

[0087] Based on the Dicke state unitary matrix circuit framework shown in Figure 3, it can be seen that by simply implementing the weight distribution transformation and the k-qubit Dicke state unitary transformation, a quantum circuit for the n-qubit Dicke state unitary transformation can be obtained. In the absence of auxiliary bits, the weight distribution transformation and Dicke unitary transformation All of them can be implemented by quantum circuits with a depth of O(k). However, as can be seen from the circuit framework shown in Figure 3, when implementing the weight distribution transformation, some quantum states are idle and not used. Therefore, in the embodiment of the present application, unused idle quantum bits are used as auxiliary quantum bits to further compress the circuit of the weight distribution transformation, thereby further compressing the quantum circuit depth of the n-qubit Dicke state unitary transformation.

[0088] In some embodiments, the number of idle qubits in an initial quantum state unitary transformation circuit is determined, and the circuit depth of the weight distribution transformation operator is compressed based on the number of idle qubits to obtain a quantum state unitary transformation circuit. The circuit depth of a quantum circuit is an important concept in quantum computing. It refers to the length of the longest sequence of operations in the quantum circuit, or the maximum number of quantum gate layers in time. This metric reflects the total execution time of a quantum circuit and is one of the key indicators for evaluating the performance of quantum algorithms and quantum hardware capabilities. The circuit depth of a quantum circuit is generally referred to as the logical depth, which refers to the maximum number of steps required to go from input qubits to output qubits in the quantum circuit. Each step corresponds to a time slice, within which multiple quantum gates can be executed.

[0089] Optionally, when the number of idle quantum bits is within a preset number requirement range, the control bit quantum bits are copied and transformed through the idle quantum bits; based on the circuit depth of the control bit quantum bit compression weight distribution transformation operator obtained by the copy, a quantum state unitary transformation circuit is obtained.

[0090] In some embodiments, when the number of auxiliary bits N<4k, no auxiliary qubits are used. Using the circuit implementation of the above weight distribution transformation, a depth of Weight distribution transformation circuit.

[0091] When the number of auxiliary bits is 4k≤N≤k 2When the control bit quantum bit is copied and transformed through the idle quantum bit, the circuit depth compression of the weight distribution transformation is performed based on the copied control bit quantum bit.

[0092] When the number of auxiliary bits N>k 2 When the weight distribution transformation is used only k 2 auxiliary qubits, and the compression method is the same as 4k≤N≤k 2 The same situation.

[0093] The circuit depth compression of the weight distribution transformation is performed based on the number of idle quantum bits. This avoids the problem of low compression efficiency caused by not using idle quantum bits to perform circuit depth compression when the number of idle quantum bits is small. It also avoids the problem of calculation errors caused by some idle quantum bits being out of the application capability when the number of idle quantum bits is large, thereby improving the accuracy of circuit depth compression.

[0094] Step 204: Apply a quantum state unitary transformation circuit to the initial quantum state to obtain a first quantum state circuit, where the first quantum state circuit includes k excited state quantum bits.

[0095] Optionally, a quantum state unitary transformation circuit is used to operate on n qubits, so that the quantum state of the n qubits evolves from an initial quantum state to a first quantum state. For example, using the technical solution provided in an embodiment of the present application, an n-qubit Dicke state unitary transformation circuit is constructed, and then the Dicke state unitary transformation circuit is applied to n qubits, so that the quantum state of the n qubits evolves from the initial quantum state to the Dicke state.

[0096] To sum up, the technical solution provided in the embodiment of the present application first constructs an initial quantum state unitary transformation circuit based on n quantum bits and Hamming weight k through recursive decomposition, and uses the idle quantum bits in the initial quantum state unitary transformation circuit as auxiliary quantum bits. The auxiliary quantum bits improve the operational parallelism of the quantum state preparation operator, and the circuit depth of the weight distribution transformation circuit is compressed, thereby compressing the circuit depth of the quantum state unitary transformation circuit, and on this basis compressing the depth of the first quantum state circuit.

[0097] In some embodiments, when circuit deep compression is performed based on idle quantum bits in an initial quantum state unitary transformation circuit, the circuit transformation of the compression process is as follows.

[0098] For any integer t∈[k]0, Represents the integer t - binary representation of bits, where In the embodiments of this application, Circuit framework. For any

[0099] Among them, if Then define |0 k >.

[0100] The following is a detailed description of the circuit conversion compression process. 2 and N>k 2 The compression method is the same. In this embodiment, the number of idle quantum bits is 4k≤N≤k 2 Taking an example for illustration, as shown in FIG4 , the above step 203 may further include the following contents.

[0101] Step 2031: Encode the unary basis of length k in the weight distribution transformation operator into a length of The binary basis of .

[0102] The above equation (1) is implemented by the following circuit framework.

[0103] Among them, the left side of the equation and |0 k >The corresponding quantum bit sets are denoted as S: = {s k ,s k-1 ,…,s1} and T:={t k ,t k-1 ,…,t1}.

[0104] In some embodiments, the quantum bits in the initial quantum state unitary transformation circuit are flipped by controlling the NOT gate and the reversible logic gate, and after the flip, the unary basis of length k is encoded into a base of length In other words, controlled NOT gates and reversible logic gates are executed and acted on the qubits in the initial quantum state unitary transformation circuit to achieve qubit flipping. Based on the flipped qubits, weights can be distributed to the binary basis through the control bit qubits, improving the efficiency and accuracy of weight distribution.

[0105] Schematically, without using auxiliary qubits, equation (1.1) can be implemented as follows:

[0106] In the above configuration, the quantum bit s k If |1>, use Flipping the qubit t k When j∈[k-1], if the quantum bit s j+1 ,s j If |01> is used Flipping the qubit t j The CNOT and Toffoli gates can be divided into three groups. In each group, all gates act on different qubits, so gates in the same group can be implemented simultaneously. Therefore, equation (1.1) can be implemented by a quantum circuit with a depth of O(1).

[0107] Equation (1.2) can be realized by the following CNOT circuit, that is, for any satisfy:

[0108] In equation (1.2), the circuit in equation (1.1) is replaced by Converted to all 0 state.

[0109] Based on the depth of the CNOT circuit, it can be seen that by using N≥0 auxiliary quantum bits, the depth of the CNOT circuit can be compressed to

[0110] In equation (1.3), replace the unary base |0 in equation (1.2) k Encoded as binary basis And equation (1.3) is implemented by CNOT circuit, so its circuit depth is also

[0111] Step 2032: Based on the number N of idle quantum bits in the initial quantum state unitary transformation circuit, copy control bit qubit.

[0112] For the above equation (1.4), the equation (1.4) is implemented as follows:

[0113] In equation (1.4), the idle qubits are divided into parts, and replicate the register controller in the initial quantum state unitary transformation circuit through the replication transformation copy, will The idle qubits in some parts are used as control qubits.

[0114] By copying the idle quantum bits to the register controller and using them as the copied control quantum bits, the values ​​in the register controller are traversed to obtain different quantum states of the quantum bits, thereby increasing the parallel capability of the control bits in the unitary transformation circuit. Multiple register controllers acting on different quantum bits can act simultaneously, reducing the circuit depth of the weight distribution transformation circuit, thereby compressing the circuit depth of the quantum state unitary transformation circuit.

[0115] Register A consists of The N auxiliary qubits are divided into Part, recorded as register

[0116] The above equation (1.4.1) is a copy transformation, which is to store the controller copy The auxiliary qubit is used to complete the replication of the register controller, and the replicated register controller is used to achieve parallel control, thereby reducing the circuit depth. The circuit depth of the replication transformation is Copy the registered controller via the copy transformation copy, will The idle quantum bits in some parts are used as control quantum bits. Since the circuit depth of the copy transformation itself is low, the conversion of idle quantum bits to control quantum bits can be realized through copy transformation with a lower circuit depth, which improves the utilization rate of idle quantum bits and the parallel capability of control bits.

[0117] In equation (1.4.2), using the circuit Restore the quantum bits t1, t2, …, tN / log(k+1) in register T to |0>. It can be implemented by a circuit with a depth of O(log(k)). Since multiple Toffoli gates act on different quantum bits, they can be implemented in parallel. The circuit depth of is O(log(k)). In a similar way, all qubits in register T can be restored to |0>. Therefore, the circuit depth of equation (1.4.2) is

[0118] Equation (1.4.3) is the inverse of Equation (1.4.1), so the depth is also Therefore, the circuit depth of equation (1.4) is

[0119] The circuit depth of equation (1) is

[0120] Step 2033, in Under the control of the control bit quantum bit, different -Qubit quantum state, weight distribution of binary basis, and re-encoding into unary basis.

[0121] exist Under the control of the control bit quantum bit, different -Qubit quantum states, assigned weights in a binary basis, and re-encoded into a unary basis.

[0122] Optionally, when controlling by controlling the quantum bit, The control bit quantum bit takes different values, generating different - quantum bit quantum state. After the idle quantum bit is copied and transformed to obtain the control bit quantum bit, that is, the above-mentioned storage controller, different quantum states are obtained by controlling the control bit quantum bit to traverse different values. - Quantum state of quantum bits, which improves the parallelism of control bit quantum bit control and improves the efficiency of generating different quantum states.

[0123] Combining the above equation (2), we can see that in equation (2), by controlling middle The value of , generates different The quantum state result is obtained by traversing The value of generates different -quantum state of quantum bits, thereby completing the weight distribution of binary basis.

[0124] Equation (3) is implemented as the inverse circuit of the above equations (1.4), (1.3) and (1.2), realizing the recoding from the binary basis to the unary basis:

[0125] Among them, due to Occupying k idle qubits, that is, using Nk idle qubits in equation (3), the total depth of the circuit is Secondly, using the same circuit, the conversion Any of them and Finally, using a circuit composed of swap gates with a depth of O(1), we can implement Equation (3) by swapping the first k qubits with the last k qubits, and then swapping the second k qubits with the last k qubits. Therefore, the circuit depth of Equation (3) is

[0126] The unary base includes a first unary base and a second unary base, wherein the first unary base and the second unary base are used to implement control bits of a reversible logic gate.

[0127] In step 2034, under the control of the first unary basis and the second unary basis, the operation result of the third unary basis is obtained, and the operation result is encoded into the quantum bit to obtain the encoding result.

[0128] With respect to equation (4), a plurality of reversible logic gates are provided in a first unary basis, a second unary basis, and a third unary basis, wherein the control bits of the reversible logic gates are provided at a first designated qubit position in the first unary basis and a second designated qubit position in the second unary basis, and the target bit of the reversible logic gates is provided at a third designated qubit position in the third unary basis. By controlling the control bits of the plurality of reversible logic gates, a calculation result of the third unary basis is obtained.

[0129] As shown in equation (4), |0 k-i 10 i-1 >corresponding to the unary expression of i, that is, the first unary basis mentioned above, correspond The unary expression of , that is, the second unary base mentioned above, correspond The unary expression of , which is the third unary base mentioned above.

[0130] The first control bit of the reversible logic gate is placed at the position of 1 in the first unary base, the second control bit of the reversible logic gate is placed at the position of 1 in the second unary base, and the target bit of the reversible logic gate is placed at the position of 1 in the third unary base. The value of is 0 to k, and the value of i is 0 to Therefore, by traversing the value of i on the first control bit and traversing the value of i on the second control bit The value of the target bit is generated The result of the operation.

[0131] By using the first designated quantum bit placed with 1 in the first unary basis as the first control bit and the second designated quantum bit placed with 1 in the second unary basis as the second control bit, the value of the third designated quantum bit placed with 1 in the third unary basis is obtained as the target bit, and the operation result of the target bit is obtained, thereby improving the operation efficiency of the target bit of the reversible logic gate. By converting between the binary basis and the unary basis, the first unary basis corresponding to i is obtained. The corresponding second unary base and The corresponding third unary base is thereby controlled by the control of the reversible logic gate to control the first unary base and the second unary base, and the target bit of the reversible logic gate is determined on the basis of the control bit. The calculation results improve operational efficiency.

[0132] In some embodiments, Toffoli gates corresponding to different control bits and target bits can be controlled in parallel. That is, by placing Toffoli gates corresponding to different control bits and target bits in the same Toffoli set, parallel operation of Toffoli gates can be achieved.

[0133] That is, in Equation (1.4), the qubits are relabeled. The first k qubits are labeled as S := {s1, s2, …, s k}. The subsequent k qubits are labeled as T := {t1, t2, …, t k}. The last N qubits are divided into N / k parts of size k. The qubits in the first part are defined as W := {w1, w2, …, w k}. The remaining parts are defined as S j := {s 1,j , s 2,j , …, s k,j}, T j := {t 1,j , t 2,j , …, t k,j}, and W j := {w 1,j , w 2,j , …, w k,j}, where any Then applying the following circuit (4.1) to the qubit sets S, T, and W, Equation (4) can be achieved.

[0134] In the above equation, if (01) is applied to S, T, W, then for any 1 ≤ i ≤ k, the basis |0 k > S |0 k-i 10 i-1 > T |0 k > W is transformed into |0 k > S |0 k-i 10 i-1 > T |0 k-i 1 i-1 > W ; and the other bases of Equation (4) remain unchanged. If (11) is applied to S, T, W, then for any 1 ≤ r < j ≤ k, the basis |0 k-r 1 r-1 > S |0 k-j 10j-1 > T |0 k > W is converted to |0 k-r > S |0 k-j 10 j-1 > T |0 k-(j-r) 1 (j-r)-1 > W ; and the other bases of equation (4) remain unchanged. Therefore, the above circuit (4.1) can realize equation (4). Regrouping the Toffoli gates in (4.1), it can also be expressed as the following equation (4.2).

[0135] in, Figure 5 illustrates the circuit grouping scheme, which represents flipping when the control bits are 0 and 1. As shown in Figure 5, each block 510 represents a Toffoli gate. The first row of blocks 510 represents the control bits of the Toffoli gate, and the second row represents the target bits. Each column of blocks 510 contains the same target bit. Toffoli gates on the same diagonal line act on different qubits (including control bits and target bits). Therefore, Toffoli gates on the diagonal line can be implemented in parallel within the same Toffoli set, and the circuit depth is 1.

[0136] When the Toffoli gate is divided into a set and implemented in parallel, the states on S, T, and W are first copied using a circuit with a depth of O(log(N / k)) by copying the transformation. That is, for any and Complete the following transformation:

[0137] After the transformation is completed, the state of the quantum bit set S, T, W and S τ ,T τ ,W τ The circuit (4.2) contains 3k-3 quantum circuits C′ with a depth of 1 acting on the quantum bit set S, T, W. i (S,T,W), C″ j (S, T, W) and C″′ r (S, T, W). In order to implement these circuits with a depth of 1 in parallel, in the embodiment of the present application, these circuits are divided into Groups, each group contains A circuit of depth 1. For any In the quantum bit set S τ ,Tτ ,W τ The circuit depth of the τth group is 1. The circuit depth of the above process is

[0138] For any i∈[k], if the quantum bit The states are all added to the quantum bit w i On (i.e. sum transformation), the quantum bit w ii The state and the circuit (4.1) act on After w i According to the sum transformation, the process can be done by circuit implementation.

[0139] Using the inverse circuit of the above transformation, all S τ ,T τ ,W τ The quantum state on is restored to |0>. The circuit depth is O(log(N / k))+O(k 2 / N)=O(log(N / k)+k 2 / N).

[0140] The circuit depth of equation (4) is 2(O(log(N / k))+O(k 2 / N))+O(log(N / k))=O(log(N / k)+k 2 / N).

[0141] Step 2035: Generate a quantum state unitary transformation circuit based on the encoding result.

[0142] Optionally, the second unary basis is restored to an all-0 state, the first unary basis is set to 1s starting from the first designated qubit, and the third unary basis is set to 1s starting from the third designated qubit, to obtain a quantum state unitary transformation circuit. After determining the operation result of the third unary basis, that is, obtaining the position of the target bit in the third unary basis, that is, the position of the third designated qubit, the second unary basis is restored to an all-0 state, and the first and third unary bases are set to 1s, thereby improving the preparation efficiency of the quantum state unitary transformation circuit.

[0143] As shown in equation (5), the equation (4) That is, the second unary basis is restored to the all-zero state. When implementing it, the following circuit (5.1) is applied to the quantum bit set S, T, W, and equation (5) can be realized.

[0144] In circuit (5.1), if (01) acts on S, T, W, for any 1≤j≤k, the basis |0k > S |0 k-j 10 j-1 > T |0 k-j 10 j-i > W Can be converted to |0 k > S |0 k > T |0 k-j 10 j-1 > W ; and the other bases remain unchanged.

[0145] If (10) acts on S, T, W, for any 1≤r≤k, the basis |0 k-r 10 r-1 > S |0 k-r 10 r-1 > T |0 k > W Can be converted to |0 k-r 10 r-1 > S |0 k > T |0 k > W ; and the other bases remain unchanged.

[0146] If (11) Acting on S, T, W, for any base Can be converted into And the other bases remain unchanged.

[0147] Therefore, circuit (5.1) can realize equation (5). By regrouping the Toffoli gates in circuit (5.1), it can be expressed as follows

[0148] Figure 6 shows the grouping of the circuit. j ,C″ r , and C″′ i In the circuit, all Toffoli gates act on different qubits, so the depth of these circuits is 1. Therefore, similar to the implementation of circuit (4.2), the circuit depth of circuit (5.2) can be compressed to O(log(N / k)+k) by using auxiliary qubits. 2In the circuit grouping shown in FIG6 , each block 610 represents a Toffoli gate. The first column of each block 610 represents the control bit of the Toffoli gate, and the second column represents the target bit. Each column of blocks has the same target bit. Toffoli gates on the same diagonal have different control bits and target bits, and can be executed in parallel in the same set.

[0149] As shown in equation (6), replace |0 in equation (5) k-i 10 i-1 >Starting from the i-th quantum bit, set it to 1 and get |0 k-i 1 i >, and, replace the equation (5) From The quantum bits are set to 1 to obtain a quantum state unitary transformation circuit.

[0150] Among them, in the process of setting 1, first by acting on the inverse circuit of equations (1.2) and (1.1), the following transformation can be achieved:

[0151] Among them, using Nk auxiliary quantum bits, the circuit depth is Secondly, using the same circuit, the following transformation can be achieved

[0152] Finally, the first k qubits are swapped with the next k qubits using a circuit with a depth of 1 and consisting of swap gates. Therefore, using Nk auxiliary qubits, Equation (6) can be expressed as Quantum circuit implementation of .

[0153] From the circuit depth of equations (1) to (6), it can be seen that when the number of auxiliary quantum bits N satisfies 4k≤N≤k 2 When , the circuit depth of the weight distribution transformation is:

[0154] When the number of auxiliary bits N>k 2 Since only k is used 2 auxiliary qubits. Therefore, the circuit depth is

[0155] In implementing Dicke state unitary transformation When we first set the quantum circuit with depth 1 Acting on the initial quantum state |0 n >, then apply Dicke state unitary transformation The Dicke state can be prepared. The circuit framework consists of log(n / k) layers of weight distribution transformation and one layer of Dicke unitary transformation For any i∈[log(n / k)], the weight distribution transformation of the i-th layer contains 2 i-1 Weight Distribution Transformation The last layer of Dicke unitary transform consists of n / k In the i-th weight distribution transformation, there are n-2 i k qubits are not used, so they can be used as auxiliary qubits to implement the weight distribution transformation in this layer. distribute Auxiliary qubits. The implementation of the weight distribution transformation and From the circuit framework, we can see that The quantum circuit depth is:

[0156] Therefore, the preparation circuit depth of Dicke state is O(log(n / k)log(k)+k).

[0157] To sum up, the technical solution provided in the embodiment of the present application first constructs an initial quantum state unitary transformation circuit based on n quantum bits and Hamming weight k through recursive decomposition, and uses the idle quantum bits in the initial quantum state unitary transformation circuit as auxiliary quantum bits. The auxiliary quantum bits improve the operational parallelism of the quantum state preparation operator, and the circuit depth of the weight distribution transformation circuit is compressed, thereby compressing the circuit depth of the quantum state unitary transformation circuit, and on this basis compressing the depth of the first quantum state circuit.

[0158] The following are device embodiments of the present application, which can be used to implement the method embodiments of the present application. For details not disclosed in the device embodiments of the present application, please refer to the method embodiments of the present application.

[0159] Please refer to Figure 7, which shows a block diagram of a quantum state preparation device provided by one embodiment of the present application. The device 700 may include: an initial quantum state acquisition module 710, a recursive decomposition module 720, a deep compression module 730, and a quantum state preparation module 740;

[0160] An initial quantum state acquisition module 710 is used to determine the initial quantum state of n quantum bits, where n is a positive integer;

[0161] a recursive decomposition module 720 for constructing an initial quantum state unitary transformation circuit by recursive decomposition based on n quantum bits and a Hamming weight k, wherein the initial quantum state unitary transformation circuit includes a recursively obtained weight distribution transformation operator and a k-qubit unitary transformation operator, wherein the weight distribution transformation operator is used to distribute the Hamming weight of a first quantum state to multiple quantum bit strings, and the unitary transformation operator is used to evolve the quantum state of the quantum bit string to the first quantum state. The initial quantum state unitary transformation circuit also includes idle quantum bits not occupied by the weight distribution transformation operator;

[0162] a depth compression module 730 for compressing the circuit depth of the weight distribution transformation operator based on the idle quantum bits in the initial quantum state unitary transformation circuit to obtain a quantum state unitary transformation circuit, wherein the quantum state unitary transformation circuit is used to act on the initial quantum state to obtain a first quantum state circuit;

[0163] The quantum state preparation module 740 is used to apply the quantum state unitary transformation circuit to the initial quantum state to obtain a first quantum state circuit, wherein the first quantum state circuit includes k excited state quantum bits.

[0164] In an optional embodiment, as shown in FIG8 , the depth compression module 730 includes:

[0165] The encoding unit 731 is used to encode the unary basis of length k in the weight distribution transformation operator into a length of The binary basis of

[0166] The copying unit 732 is used to copy the idle quantum bits N in the initial quantum state unitary transformation circuit to obtain control bit qubits;

[0167] The control unit 733 is used to Under the control of the control bit quantum bit, different - a quantum state of a quantum bit, assigning a weight to the binary basis, and re-encoding the result into a unary basis, including a first unary basis and a second unary basis, wherein the first unary basis and the second unary basis are used to implement a control bit of a reversible logic gate; under the control of the first unary basis and the second unary basis, obtaining a calculation result of a third unary basis, and encoding the calculation result into the quantum bit to obtain an encoding result, wherein the third unary basis corresponds to a target bit of the reversible logic gate;

[0168] The generating unit 734 is configured to generate the quantum state unitary transformation circuit based on the encoding result.

[0169] In an optional embodiment, the encoding unit 731 is further configured to flip the quantum bits in the initial quantum state unitary transformation circuit by controlling the NOT gate and the reversible logic gate; after flipping, the unary basis of length k is encoded into a base of length The binary basis of .

[0170] In an optional embodiment, the copy unit 732 is further configured to divide the idle quantum bits into parts, and replicates the register controller in the initial quantum state unitary transformation circuit through a replication transformation copy, will The idle quantum bits of a part are used as the control quantum bits.

[0171] In an optional embodiment, the control unit 733 is further configured to control The control bit quantum bit takes different values, generating different -Qubit quantum state.

[0172] In an optional embodiment, the control unit 733 is further used to set multiple reversible logic gates in the first unary basis, the second unary basis and the third unary basis, wherein the control bits of the reversible logic gates are set at the first designated quantum bit position of the first unary basis and the second designated quantum bit position of the second unary basis, and the target bit of the reversible logic gate is set at the third designated quantum bit position of the third unary basis; by controlling the control bits of the multiple reversible logic gates, the operation results of the third unary basis are obtained.

[0173] In an optional embodiment, the generation unit 734 is further used to restore the second unary basis to an all-0 state; set the first unary basis to 1 starting from the first designated quantum bit, and set the third unary basis to 1 starting from the third designated quantum bit, to obtain the quantum state unitary transformation circuit.

[0174] In an optional embodiment, the recursive decomposition module 720 is further configured to apply a 2k-qubit weight distribution transformation to the initial quantum state. And, the first quantum state unitary transformation of n / 2-qubits in parallel

[0175] The recursive decomposition module 720 is also used to transform the weight distribution And the first quantum state unitary transformation Perform recursive decomposition until the number of quantum bits of the first quantum state unitary transformation is k, and obtain the initial quantum state unitary transformation circuit.

[0176] In an optional embodiment, the deep compression module 730 is further used to determine the number of idle quantum bits in the initial quantum state unitary transformation circuit; and perform circuit deep compression on the weight distribution transformation based on the number of idle quantum bits to obtain the quantum state unitary transformation circuit.

[0177] In an optional embodiment, the deep compression module 730 is further used to perform a copy transformation process on the control bit quantum bits through the idle quantum bits when the number of the idle quantum bits is within a preset number requirement range; and perform circuit deep compression on the weight distribution transformation based on the copied control bit quantum bits to obtain the quantum state unitary transformation circuit.

[0178] To sum up, the technical solution provided in the embodiment of the present application first constructs an initial quantum state unitary transformation circuit based on n quantum bits and Hamming weight k through recursive decomposition, and uses the idle quantum bits in the initial quantum state unitary transformation circuit as auxiliary quantum bits. The auxiliary quantum bits improve the operational parallelism of the quantum state preparation operator, and the circuit depth of the weight distribution transformation circuit is compressed, thereby compressing the circuit depth of the quantum state unitary transformation circuit, and on this basis compressing the depth of the first quantum state circuit.

[0179] Please refer to Figure 9, which shows a block diagram of a computer device provided in one embodiment of the present application. The computer device can be used to implement the quantum state preparation method provided in the above embodiment, which specifically includes the following contents.

[0180] The computer device 900 includes a central processing unit (CPU, central processing unit), GPU (graphics processing unit), and FPGA (field programmable gate array) 901, a system memory 904 including RAM (random-access memory) 902 and ROM (read-only memory) 903, and a system bus 905 connecting the system memory 904 and the central processing unit 901. The computer device 900 also includes a basic input / output system (I / O system) 906 for facilitating information transmission between various components within the server, and a mass storage device 907 for storing an operating system 913, application programs 914, and other program modules 915.

[0181] The basic input / output system 906 includes a display 908 for displaying information and an input device 909 such as a mouse and a keyboard for user input of information. The display 908 and the input device 909 are both connected to the central processing unit 901 via an input / output controller 910 connected to the system bus 905. The basic input / output system 906 may also include an input / output controller 910 for receiving and processing inputs from a plurality of other devices such as a keyboard, a mouse, or an electronic stylus. Similarly, the input / output controller 910 also provides output to a display screen, a printer, or other types of output devices. The system bus 905 is also connected to a network 912 via a network interface unit 911.

[0182] The mass storage device 907 is connected to the central processing unit 901 via a mass storage controller (not shown) connected to the system bus 905. The mass storage device 907 and its associated computer-readable media provide non-volatile storage for the computer device 900. In other words, the mass storage device 907 may include a computer-readable medium (not shown) such as a hard disk or a CD-ROM (Compact Disc Read-Only Memory) drive.

[0183] In some embodiments, a quantum computer is provided, comprising a processor and a memory, wherein the memory stores a computer program, which is loaded and executed by the processor to implement the above-described method for preparing a quantum state. In some embodiments, a computer-readable storage medium is provided, wherein the storage medium stores a computer program, which, when executed by the processor, implements the above-described method for preparing a quantum state.

[0184] In some embodiments, a computer program product is further provided, comprising a computer program stored in a computer-readable storage medium. A processor of a computer device reads the computer program from the computer-readable storage medium and executes the computer program, causing the computer device to perform the above-described method for preparing a quantum state.

[0185] It should be noted that, in the embodiment of the present application, before collecting the relevant data of the user and during the process of collecting the relevant data of the user, a prompt interface, a pop-up window or an output voice prompt information can be displayed. The prompt interface, pop-up window or voice prompt information is used to prompt the user that the relevant data is currently being collected, so that the present application only starts to execute the relevant steps of obtaining the relevant data of the user after obtaining the confirmation operation issued by the user on the prompt interface or pop-up window. Otherwise (that is, when the confirmation operation issued by the user on the prompt interface or pop-up window is not obtained), the relevant steps of obtaining the relevant data of the user are terminated, that is, the relevant data of the user is not obtained. In other words, all user data collected by this application are processed strictly in accordance with the requirements of the laws and regulations of the relevant countries and regions, and the informed consent or separate consent of the personal information subject is obtained with the consent and authorization of the user. Subsequent data use and processing behavior is carried out within the scope of authorization of the laws and regulations and the personal information subject, and the collection, use and processing of relevant user data need to comply with the relevant laws, regulations and standards of the relevant countries and regions. For example, the parameters, quantum circuits, energy, etc. involved in this application are all obtained with full authorization.

Claims

1. A method for preparing a quantum state, performed by a computer device, the method comprising: Determine the initial quantum state of n quantum bits, where n is a positive integer; Based on n quantum bits and a Hamming weight k, an initial quantum state unitary transformation circuit is constructed by recursive decomposition, wherein the initial quantum state unitary transformation circuit includes a recursively obtained weight distribution transformation operator and a k-qubit unitary transformation operator, wherein the weight distribution transformation operator is used to distribute the Hamming weight of a first quantum state to a plurality of quantum bit strings, the unitary transformation operator is used to make the quantum state of the quantum bit string evolve to the first quantum state, and the initial quantum state unitary transformation circuit also includes idle quantum bits not occupied by the weight distribution transformation operator; Based on the idle quantum bits in the initial quantum state unitary transformation circuit, the circuit depth of the weight distribution transformation operator is compressed to obtain a quantum state unitary transformation circuit, wherein the quantum state unitary transformation circuit is used to act on the initial quantum state to obtain a first quantum state circuit; The quantum state unitary transformation circuit acts on the initial quantum state to obtain a first quantum state circuit, wherein the first quantum state circuit includes k excited state quantum bits, where k is a positive integer.

2. The method according to claim 1, wherein: The circuit depth of the weight distribution transformation operator is compressed based on the idle quantum bits in the initial quantum state unitary transformation circuit to obtain the quantum state unitary transformation circuit, including: The unary basis of length k in the weight distribution transformation operator is encoded into a base of length The binary basis of ; Based on the number N of idle quantum bits in the initial quantum state unitary transformation circuit, the copy is obtained control bit qubits; In the Under the control of the control bit quantum bit, different - a quantum bit quantum state, assigning a weight to the binary basis and re-encoding it into a unary basis, including a first unary basis and a second unary basis, wherein the first unary basis and the second unary basis are used to implement a control bit of a reversible logic gate; Under the control of the first unary basis and the second unary basis, obtaining a calculation result of a third unary basis, and encoding the calculation result into a quantum bit to obtain an encoding result, wherein the third unary basis is used to realize a target bit of the reversible logic gate; The quantum state unitary transformation circuit is generated based on the encoding result.

3. The method according to claim 1 or 2, wherein: The unary basis of length k in the weight distribution transformation operator is encoded into a base of length The binary basis of , including: Flipping the quantum bits in the initial quantum state unitary transformation circuit by controlling a NOT gate and a reversible logic gate; After flipping, encode the unary base of length k into a base of length The binary basis of .

4. The method according to any one of claims 1 to 3, wherein: The number of idle quantum bits N in the initial quantum state unitary transformation circuit is copied to obtain Control bit qubits, including: The idle quantum bits are divided into parts, and replicates the register controller in the initial quantum state unitary transformation circuit through a replication transformation copy, will The idle quantum bits in a part are used as the control quantum bits.

5. The method according to any one of claims 1 to 4, wherein: mentioned in Under the control of the control bit quantum bit, different -Qubit quantum states, including: By controlling The control bit quantum bit takes different values ​​to generate different -Qubit quantum state.

6. The method according to any one of claims 1 to 5, wherein: The step of obtaining the operation result of the third unary base under the control of the first unary base and the second unary base includes: A reversible logic gate is set in the first unary basis, the second unary basis and the third unary basis, wherein the control bit of the reversible logic gate is set at the first designated quantum bit of the first unary basis and the second unary basis. A second designated qubit of the basis, a target bit of the reversible logic gate is set at a third designated qubit of the third unary basis; The operation result of the third unary base is obtained by controlling the control bits of the plurality of reversible logic gates.

7. The method according to any one of claims 1 to 6, wherein: The generating the quantum state unitary transformation circuit based on the encoding result comprises: Restoring the second unary basis to an all-0 state; The first unary basis is processed by setting 1 starting from the first designated quantum bit, and the third unary basis is processed by setting 1 starting from the third designated quantum bit, to obtain the quantum state unitary transformation circuit.

8. The method according to any one of claims 1 to 7, wherein: The initial quantum state unitary transformation circuit is constructed by recursive decomposition based on n quantum bits and Hamming weight k, including: A weight distribution transformation of 2k-qubits is applied to the initial quantum state And, the first quantum state unitary transformation of n / 2-qubits in parallel For the weight distribution transformation And the first quantum state unitary transformation Recursive decomposition is performed until the number of quantum bits of the first quantum state unitary transformation is k, thereby obtaining the initial quantum state unitary transformation circuit.

9. The method according to any one of claims 1 to 8, wherein: The circuit depth of the weight distribution transformation operator is compressed based on the idle quantum bits in the initial quantum state unitary transformation circuit to obtain the quantum state unitary transformation circuit, including: Determining the number of idle quantum bits in the initial quantum state unitary transformation circuit; The circuit depth of the weight allocation transformation operator is compressed based on the number of the idle quantum bits to obtain the quantum state unitary transformation circuit.

10. The method according to any one of claims 1 to 9, wherein: The method of compressing the circuit depth of the weight allocation transformation operator based on the number of the idle quantum bits to obtain the quantum state unitary transformation circuit includes: When the number of the idle quantum bits is within a preset number requirement range, the control bit quantum bits are processed by copying and changing the idle quantum bits; The circuit depth of the weight distribution transformation operator is compressed based on the copied control bit quantum bits to obtain the quantum state unitary transformation circuit.

11. A device for preparing a quantum state, the device comprising: An initial quantum state acquisition module is used to determine the initial quantum state of n quantum bits, where n is a positive integer; A recursive decomposition module, for constructing an initial quantum state unitary transformation circuit by recursive decomposition based on n quantum bits and a Hamming weight k, wherein the initial quantum state unitary transformation circuit includes a recursively obtained weight distribution transformation operator and a k-qubit unitary transformation operator, wherein the weight distribution transformation operator is used to distribute the Hamming weight of a first quantum state to a plurality of quantum bit strings, the unitary transformation operator is used to make the quantum state of the quantum bit string evolve to the first quantum state, and the initial quantum state unitary transformation circuit also includes idle quantum bits not occupied by the weight distribution transformation operator; A depth compression module, used to compress the circuit depth of the weight distribution transformation operator based on the idle quantum bits in the initial quantum state unitary transformation circuit to obtain a quantum state unitary transformation circuit, wherein the quantum state unitary transformation circuit is used to act on the initial quantum state to obtain a first quantum state circuit; The quantum state preparation module is used to apply the quantum state unitary transformation circuit to the initial quantum state to obtain a first quantum state circuit, wherein the first quantum state circuit includes k excited state quantum bits.

12. The device according to claim 11, wherein The deep compression module comprises: A coding unit, used to encode the unary basis of length k in the weight distribution transformation operator into a base of length The binary basis of ; A copying unit is used to copy the idle quantum bits N in the initial quantum state unitary transformation circuit to obtain control bit qubits; A control unit for Under the control of the control bit quantum bit, different - qubit quantum states, assigning weights to the binary basis and re-encoding them into a unary basis, which includes A first unary basis and a second unary basis are included, wherein the first unary basis and the second unary basis are used to realize the control bit of the reversible logic gate; under the control of the first unary basis and the second unary basis, a calculation result of a third unary basis is obtained, and the calculation result is encoded into a quantum bit to obtain an encoding result, wherein the third unary basis is used to realize the target bit of the reversible logic gate; A generating unit is used to generate the quantum state unitary transformation circuit based on the encoding result.

13. The device according to claim 11 or 12, wherein: The encoding unit is also used to flip the quantum bits in the initial quantum state unitary transformation circuit by controlling the NOT gate and the reversible logic gate; after flipping, the unary basis with a length of k is encoded into a base with a length of The binary basis of .

14. The device according to any one of claims 11 to 13, wherein: The replication unit is also used to divide the idle quantum bits into parts, and replicates the register controller in the initial quantum state unitary transformation circuit through a replication transformation copy, will The idle quantum bits in a part are used as the control quantum bits.

15. The device according to any one of claims 11 to 14, wherein: The control unit is also used to control The control bit quantum bit takes different values ​​to generate different -Qubit quantum state.

16. The device according to any one of claims 11 to 15, wherein: The control unit is further used to set reversible logic gates in the first unary basis, the second unary basis and the third unary basis, wherein the control bits of the reversible logic gates are set at the first designated quantum bit position of the first unary basis and the second designated quantum bit position of the second unary basis, and the target bits of the reversible logic gates are set at the third designated quantum bit position of the third unary basis; and the operation results of the third unary basis are obtained by controlling the control bits of the multiple reversible logic gates.

17. A quantum computer, comprising a processor and a memory, wherein a computer program is stored in the memory, and the computer program is loaded and executed by the processor to implement the method according to any one of claims 1 to 10.

18. A computer device, comprising a processor and a memory, wherein a computer program is stored in the memory, and the computer program is loaded and executed by the processor to implement the method according to any one of claims 1 to 10.

19. A computer-readable storage medium, wherein a computer program is stored in the computer-readable storage medium, wherein the computer program is loaded and executed by a processor to implement the method according to any one of claims 1 to 10.

20. A computer program product, comprising a computer program, wherein the computer program is stored in a computer-readable storage medium, and a processor reads and executes the computer program from the computer-readable storage medium to implement the method according to any one of claims 1 to 10.

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