Encoding method, decoding method, apparatus, system and chip

Abstract

The present application relates to the technical field of communications. Disclosed are an encoding method, a decoding method, an apparatus, a system and a chip. The encoding method comprises: a first chip combines first signals of n cycles to be transmitted, so as to obtain a second signal, the first signals of the n cycles comprising data information and / or control information, and n being an integer greater than 1; the first chip encodes the second signal, so as to obtain at least one code block; and the first chip transmits the at least one code block via a serial channel, the serial channel being used for connecting an MAC layer and a PHY layer. The second signal comprises the n first signals, such that the number of the first signals comprised in the second signal is high, that is, the present encoding method can convert signals with a lower data bit width into signals with a higher data bit width. Encoding the second signal to obtain at least one code block enables the at least one code block to comprise a high number of the first signals, and therefore compared with modes for transmitting code blocks comprising a plurality of repeated signals, the present encoding method has higher signal transmission efficiency.

Description

Coding method, decoding method, device, system and chip

[0001] This application claims priority to Chinese patent application number 202311764959.8, filed on December 20, 2023, entitled “Encoding method, decoding method, device, system and chip”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to an encoding method, a decoding method, a device, a system and a chip. Background Art

[0003] In the field of communication technology, a signal transmitter may encode a signal to obtain an encoding result, and transmit the encoding result to a signal receiver, which then decodes the received encoding result to recover the signal. Summary of the Invention

[0004] The present application proposes an encoding method, a decoding method, a device, a system and a chip for improving signal transmission efficiency.

[0005] In a first aspect, a coding method is provided, comprising: a first chip combining n cycles of first signals to be transmitted to obtain a second signal, wherein the n cycles of the first signal include at least one of data information or control information, and n is a positive integer greater than 1; the first chip encoding the second signal to obtain at least one code block; and the first chip sending the at least one code block via a serial channel, wherein the serial channel is used to connect a media access control (MAC) layer and a physical layer (PHY).

[0006] In this method, a second signal is obtained by combining n cycles of the first signal. The second signal includes a larger number of the first signals, meaning that the method can convert a first signal with a lower data bit width into a second signal with a higher data bit width. Furthermore, when encoding the second signal to obtain at least one code block, the at least one code block includes a larger number of the first signals, resulting in a more efficient signal transmission method. When the second signal includes multiple types of information, the multiple types of information can be transmitted serially via serial channels, requiring fewer channels for transmission and resulting in lower costs.

[0007] In one possible implementation, a first chip encodes a second signal to obtain at least one code block, including: the first chip encodes the second signal and a third signal to be transmitted to obtain multiple code blocks, wherein the third signal includes management information; and the first chip transmits the at least one code block via a serial channel, including: the first chip transmits the multiple code blocks via a serial channel. If the method also encodes the third signal, the multiple code blocks obtained by encoding can include multiple types of information. A serial channel for transmitting the multiple code blocks can be implemented using a single pin or a group of pins, thereby reducing the number of pins included in the first chip for implementing the serial channel. When at least one of data information or control information is transmitted via a serial channel, and management information is also transmitted via the same serial channel, the cost of transmitting the data, control, and management information is low because the data, control, and management information can be transmitted via the same serial channel.

[0008] In one possible implementation, at least one code block includes a first code block and a second code block, the first code block includes a second signal, and the second code block includes a type indicator, where the type indicator indicates the signal type included in the second signal. That is, the type indicator indicating the signal type may be included in the second code block other than the first code block. A chip that subsequently receives the first and second code blocks can directly obtain the type indicator from the second code block and determine the signal type of the second signal based on the type indicator, resulting in a more efficient acquisition of the signal type of the second signal.

[0009] In one possible implementation, the multiple code blocks include a first code block and a second code block, the first code block includes a second signal, the second code block includes a third signal, and the type of the first code block is used to indicate the signal type included in the second signal. In this implementation, no additional type indicator is required to indicate the signal type included in the second signal, and the overhead of indicating the signal type is reduced.

[0010] In one possible implementation, the multiple code blocks include a first code block and a second code block, the first code block includes a second signal, and the second code block includes a third signal. The first signal is associated with an Ethernet frame, and an Ethernet frame is associated with at least one first code block among the multiple code blocks. The second code block is transmitted before or after the first code block associated with the same Ethernet frame. Therefore, the second code block can be transmitted during an Ethernet interpacket gap (IPG) or when no Ethernet frame is present. By transmitting the second code block instead of an idle code block in at least one of the Ethernet frame gaps or when no Ethernet frame is present, the interface rate used to transmit the code block can be maintained unchanged while the second code block is being transmitted, thereby maintaining the power consumption of the transmitted code block. Furthermore, because the method transmits the second code block instead of an idle code block during an Ethernet frame gap or when no Ethernet frame is being transmitted, and because the second code block includes a type indicator or includes a type indicator and management information, the method achieves high information transmission efficiency.

[0011] In one possible implementation, the multiple code blocks include a first code block and a second code block, the first code block includes a second signal, the second code block includes a third signal, the first signal is associated with an Ethernet frame, at least one first code block among the multiple code blocks is associated with an Ethernet frame, the at least one first code block includes a first code block associated with a preamble of the Ethernet frame, and the second code block is used to replace the first code block associated with the preamble for transmission. Because this method replaces the first code block associated with the preamble for transmission, this implementation can maintain the interface rate used to transmit the code blocks unchanged while transmitting the second code block, thereby maintaining the power consumption of the transmitted code blocks unchanged. Furthermore, when deleting code blocks transmitted between Ethernet frames to compensate for clock differences on the interface, because in this implementation, the second code block is used to replace the first code block associated with the preamble for transmission rather than being transmitted between Ethernet frames, the second code block will not be deleted due to the compensation for clock differences, and the transmission reliability of the second code block is higher.

[0012] In one possible implementation, a first chip transmits at least one code block via a serial channel, including: the first chip negotiates with a chip at the other end of the serial channel about a clock for transmitting the at least one code block; and the first chip transmits the at least one code block via the serial channel according to the negotiated clock. By negotiating the clock used to transmit the code block with the other chip, the frequency of the clock used when transmitting the code block can be adapted to the conditions of the chips at both ends of the serial channel. Consequently, when the code block is transmitted according to the negotiated clock, the chip at the other end of the serial channel can receive the code block according to the negotiated clock, ensuring reliable code block transmission.

[0013] In one possible implementation, the at least one code block includes multiple first code blocks and multiple second code blocks, and the frequency of the clock used for negotiation is determined based on the transmission rate corresponding to the data information in the first signal, the number of first code blocks, the number of second code blocks, and the coding efficiency of the coding scheme. In this case, the frequency of the clock used for negotiation can be adapted to the code blocks to be transmitted, thereby ensuring the reliability of code block transmission according to the negotiated clock.

[0014] In one possible implementation, the first chip is a PHY chip, and the third signal also includes physical layer channel state indication information. Therefore, the third signal includes a relatively rich variety of information. Furthermore, when the physical layer channel state indication information is directly transmitted, the chip receiving the multiple encoded code blocks does not need to perform logical operations on information other than the physical layer channel state indication information to infer the physical layer channel state indication information. This method is applicable to point-to-multipoint scenarios.

[0015] In one possible implementation, the serial channel is a channel between improved serial gigabit media independent interfaces (SGMII). For example, the first chip and the second chip receiving the at least one code block both include interfaces improved based on the SGMII, and the serial channel can be a channel between the SGMIIs.

[0016] In a second aspect, a decoding method is provided, which includes: a second chip receives at least one code block through a serial channel, the at least one code block is obtained by encoding a second signal, the second signal is obtained by merging n cycles of first signals to be transmitted, the n cycles of the first signal include at least one of data information or control information, the serial channel is used to connect the MAC layer and the PHY, and n is a positive integer greater than 1; the second chip decodes the at least one code block to obtain a second signal; the second chip splits the second signal to obtain n signals.

[0017] In this method, the second signal is obtained by combining n cycles of the first signal. The second signal includes a larger number of first signals, which means that the method can convert the second signal with a higher data bit width into the first signal with a lower data bit width. Furthermore, when receiving at least one code block obtained by encoding the second signal, the at least one code block includes a larger number of first signals, and the method has high signal reception efficiency. When the second signal includes multiple types of information, the multiple types of information can be received serially via serial channels, requiring fewer channels to receive the multiple types of information, resulting in lower costs.

[0018] In one possible implementation, the second chip receives at least one code block via a serial channel, including: the second chip receives multiple code blocks via the serial channel, the multiple code blocks being obtained by encoding a second signal and a third signal to be transmitted, the third signal including management information; and the second chip decodes the at least one code block to obtain a second signal, including: the second chip decodes the multiple code blocks to obtain the second signal and the third signal. If the method also receives a code block encoded from the third signal, the method can receive multiple types of information. A serial channel for receiving multiple code blocks can be implemented using a single pin or a group of pins, thereby reducing the number of pins included in the second chip for implementing the serial channel. When at least one of data information or control information is received via a serial channel, and management information is also received via the same serial channel, the cost of receiving data information, control information, and management information is low because the data information, control information, and management information can all be received via the same serial channel.

[0019] In one possible implementation, at least one code block includes a first code block and a second code block, the first code block includes a second signal, and the second code block includes a type indicator, the type indicator being used to indicate the signal type included in the second signal; a second chip decodes the at least one code block to obtain a second signal, including: the second chip obtains the second signal from the first code block; the second chip splits the second signal to obtain n signals, including: the second chip obtains the signal type included in the second signal based on the type indicator included in the second code block; the second chip splits the second signal according to the signal type included in the second signal to obtain n signals. In this implementation, the type indicator indicating the signal type is included in a second code block other than the first code block. The second chip can directly obtain the type indicator from the second code block and obtain the signal type of the second signal based on the type indicator, which is more efficient in obtaining the signal type of the second signal.

[0020] In one possible implementation, the multiple code blocks include a first code block and a second code block, the first code block includes a second signal, the second code block includes a third signal, and the type of the first code block indicates the signal type included in the second signal; the second chip splits the second signal to obtain n signals, including: the second chip obtains the signal type included in the second signal based on the type of the first code block; and the second chip splits the second signal based on the signal type included in the second signal to obtain n signals. In this implementation, no additional type indicator is required to indicate the signal type included in the second signal, and the overhead of indicating the signal type is low.

[0021] In one possible implementation, the multiple code blocks include a first code block and a second code block, the first code block includes a second signal, and the second code block includes a third signal. The first signal is associated with an Ethernet frame, and an Ethernet frame is associated with at least one first code block among the multiple code blocks. The second code block is transmitted before or after the first code block associated with the same Ethernet frame. Therefore, the second code block can be transmitted during an Ethernet frame interval or when no Ethernet frame is present. By transmitting the second code block instead of an idle code block during at least one of an Ethernet frame interval or when no Ethernet frame is present, the interface rate used to transmit the code block can be maintained unchanged while the second code block is being transmitted, thereby maintaining the power consumption of the code block transmission. Furthermore, because the method receives the second code block instead of an idle code block during an Ethernet frame interval or when no Ethernet frame is being transmitted, and because the second code block includes a type indicator or a type indicator and management information, the method achieves high information reception efficiency.

[0022] In one possible implementation, the multiple code blocks include a first code block and a second code block, the first code block includes a second signal, the second code block includes a third signal, the first signal is associated with an Ethernet frame, at least one first code block from the multiple code blocks is associated with an Ethernet frame, the at least one first code block includes a first code block associated with a preamble of the Ethernet frame, and the second code block is used to replace the first code block associated with the preamble for transmission. Because the second code block is used to replace the first code block associated with the preamble for transmission in this implementation, this implementation can maintain the interface rate used to transmit the code blocks unchanged when transmitting the second code block, thereby maintaining the power consumption of the transmitted code blocks unchanged. Furthermore, when deleting code blocks transmitted between Ethernet frames to compensate for clock differences on the interface, because the second code block is used to replace the first code block associated with the preamble for transmission in this implementation, rather than being transmitted between Ethernet frames, the second code block is not deleted due to the compensation for clock differences, resulting in higher transmission reliability for the second code block.

[0023] In one possible implementation, a second chip receives at least one code block via a serial channel, including: the second chip negotiates with a chip at the other end of the serial channel about a clock for transmitting the at least one code block; and the second chip receives the at least one code block via the serial channel according to the negotiated clock. By negotiating with the peer chip about the clock for transmitting the code block, the frequency of the clock used when transmitting the code block can be adapted to the conditions of the chips at both ends of the serial channel. Thus, when the code block is transmitted according to the negotiated clock, the chip at the other end of the serial channel can receive the code block according to the negotiated clock, ensuring reliable code block transmission.

[0024] In one possible implementation, the at least one code block includes multiple first code blocks and multiple second code blocks, and the frequency of the clock used for negotiation is determined based on the transmission rate corresponding to the data information in the first signal, the number of first code blocks, the number of second code blocks, and the coding efficiency of the coding scheme. In this case, the frequency of the clock used for negotiation can be adapted to the code blocks to be transmitted, thereby ensuring the reliability of code block transmission according to the negotiated clock.

[0025] In one possible implementation, the second chip is a MAC chip, and the third signal also includes a physical layer channel state indication signal. Therefore, the third signal includes a relatively rich variety of information. Furthermore, when directly transmitting the physical layer channel state indication information, the second chip does not need to perform logical operations on other information besides the physical layer channel state indication information to infer the physical layer channel state indication information. This method is applicable to point-to-multipoint scenarios.

[0026] In a possible implementation, the serial channel is an improved SGMII channel. That is, the first chip and the second chip both include an interface improved based on the SGMII, and the serial channel can be an SGMII channel.

[0027] In a third aspect, a coding device is provided, which is applied to a first chip, and includes: a merging module, used to merge n periods of first signals to be transmitted to obtain a second signal, where the n periods of first signals include at least one of data information or control information, and n is a positive integer greater than 1; a coding module, used to encode the second signal to obtain at least one code block; and a sending module, used to send at least one code block through a serial channel, where the serial channel is used to connect the MAC layer and the PHY.

[0028] In a possible implementation, the encoding module is configured to encode the second signal and a third signal to be transmitted to obtain multiple code blocks, where the third signal includes management information; and the sending module is configured to send the multiple code blocks through a serial channel.

[0029] In a possible implementation, the at least one code block includes a first code block and a second code block, the first code block includes the second signal, and the second code block includes a type indicator, where the type indicator is used to indicate a signal type included in the second signal.

[0030] In a possible implementation, the multiple code blocks include a first code block and a second code block, the first code block includes the second signal, the second code block includes the third signal, and the type of the first code block is used to indicate the type of signal included in the second signal.

[0031] In one possible implementation, the multiple code blocks include a first code block and a second code block, the first code block includes a second signal, the second code block includes a third signal, the first signal is related to an Ethernet frame, an Ethernet frame is associated with at least one first code block among the multiple code blocks, and the second code block is transmitted before or after the first code block associated with the same Ethernet frame.

[0032] In one possible implementation, the multiple code blocks include a first code block and a second code block, the first code block includes a second signal, the second code block includes a third signal, the first signal is related to an Ethernet frame, an Ethernet frame is associated with at least one first code block among the multiple code blocks, the at least one first code block includes a first code block associated with a preamble of the Ethernet frame, and the second code block is used to replace the first code block associated with the preamble for transmission.

[0033] In a possible implementation, the sending module is configured to negotiate with a chip at the other end of the serial channel a clock for transmitting at least one code block; and send the at least one code block through the serial channel according to the negotiated clock.

[0034] In one possible implementation, at least one code block includes multiple first code blocks and multiple second code blocks, and the frequency of the clock used for negotiation is determined based on the transmission rate corresponding to the data information in the first signal, the number of first code blocks, the number of second code blocks, and the coding efficiency of the coding method.

[0035] In a possible implementation, the first chip is a PHY chip, and the third signal further includes physical layer channel status indication information.

[0036] In a possible implementation, the serial channel is an improved SGMII channel.

[0037] In a fourth aspect, a decoding device is provided, which is applied to a second chip, and the device includes: a receiving module, used to receive at least one code block through a serial channel, the at least one code block is obtained by encoding a second signal, the second signal is obtained by merging n cycles of first signals to be transmitted, the n cycles of first signals include at least one of data information or control information, the serial channel is used to connect the MAC layer and PHY, and n is a positive integer greater than 1; a decoding module, used to decode at least one code block to obtain a second signal; and a splitting module, used to split the second signal to obtain n signals.

[0038] In one possible implementation, a receiving module is used to receive multiple code blocks through a serial channel, where the multiple code blocks are obtained by encoding a second signal and a third signal to be transmitted, where the third signal includes management information; and a decoding module is used to decode the multiple code blocks to obtain the second signal and the third signal.

[0039] In one possible implementation, at least one code block includes a first code block and a second code block, the first code block includes a second signal, and the second code block includes a type indication, where the type indication is used to indicate the signal type included in the second signal; a decoding module is used to obtain the second signal from the first code block; a splitting module is used to obtain the signal type included in the second signal based on the type indication included in the second code block; and the second signal is split according to the signal type included in the second signal to obtain n signals.

[0040] In one possible implementation, the multiple code blocks include a first code block and a second code block, the first code block includes a second signal, the second code block includes a third signal, and the type of the first code block is used to indicate the signal type included in the second signal; the splitting module is used to obtain the signal type included in the second signal according to the type of the first code block; and the second signal is split according to the type included in the second signal to obtain n signals.

[0041] In one possible implementation, the multiple code blocks include a first code block and a second code block, the first code block includes a second signal, the second code block includes a third signal, the first signal is related to an Ethernet frame, an Ethernet frame is associated with at least one first code block among the multiple code blocks, and the second code block is transmitted before or after the first code block associated with the same Ethernet frame.

[0042] In one possible implementation, the multiple code blocks include a first code block and a second code block, the first code block includes a second signal, the second code block includes a third signal, the first signal is related to an Ethernet frame, an Ethernet frame is associated with at least one first code block among the multiple code blocks, the at least one first code block includes a first code block associated with a preamble of the Ethernet frame, and the second code block is used to replace the first code block associated with the preamble for transmission.

[0043] In a possible implementation, the receiving module is configured to negotiate with a chip at the other end of a serial channel a clock for transmitting at least one code block; and receive at least one code block through the serial channel according to the negotiated clock.

[0044] In one possible implementation, at least one code block includes multiple first code blocks and multiple second code blocks, and the frequency of the clock used for negotiation is determined based on the transmission rate corresponding to the data information in the first signal, the number of first code blocks, the number of second code blocks, and the coding efficiency of the coding method.

[0045] In a possible implementation, the second chip is a MAC chip, and the third signal further includes a physical layer channel state indication signal.

[0046] In a possible implementation, the serial channel is an improved SGMII channel.

[0047] In a fifth aspect, a communication system is provided, the communication system comprising a first chip and a second chip, the first chip being used to execute any encoding method in the first aspect, and the second chip being used to execute any decoding method in the second aspect.

[0048] In a sixth aspect, a chip is provided, comprising: a MAC layer circuit, the MAC layer circuit being configured to execute any encoding method in the first aspect or any decoding method in the second aspect.

[0049] In a seventh aspect, another chip is provided, which includes: a PHY circuit, and the PHY circuit is used to execute any encoding method in the first aspect or any decoding method in the second aspect.

[0050] It should be understood that the encoding device and decoding device may be a chip or a communication device. The beneficial effects achieved by the technical solutions of the third to seventh aspects of the present application and the corresponding possible implementations can be referred to the technical effects of the technical solutions of the first to second aspects and the corresponding possible implementations, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] FIG1 is a schematic diagram of an SGMII compatible with a 100 Mbps transmission rate in a related art;

[0052] FIG2 is a schematic diagram of a signal transmitted by MII in a related art;

[0053] FIG3 is a schematic diagram of an implementation environment provided by an embodiment of the present application, taking an MII scenario as an example;

[0054] FIG4 is a flowchart of an encoding method provided in an embodiment of the present application;

[0055] FIG5 is a schematic diagram of transmission management information in a related art;

[0056] FIG6 is a schematic diagram of a sequence to be encoded provided in an embodiment of the present application;

[0057] FIG7 is a schematic diagram of a process of encoding a second signal and a third signal to obtain multiple code blocks according to an embodiment of the present application;

[0058] FIG8 is a schematic diagram of a sequence to be encoded provided in an embodiment of the present application;

[0059] FIG9 is a schematic diagram of a code block sequence obtained by encoding provided by an embodiment of the present application;

[0060] FIG10 is a schematic diagram of the position of a second code block provided in an embodiment of the present application;

[0061] FIG11 is a schematic diagram of the position of another second code block provided in an embodiment of the present application;

[0062] FIG12 is a schematic diagram of the position of another second code block provided in an embodiment of the present application;

[0063] FIG13 is a schematic diagram of a second code block including management information provided by an embodiment of the present application;

[0064] FIG14 is a flowchart of a decoding method provided in an embodiment of the present application;

[0065] FIG15 is a schematic diagram of the architecture of an improved SGMII provided in an embodiment of the present application;

[0066] FIG16 is a schematic structural diagram of an encoding device provided in an embodiment of the present application;

[0067] FIG17 is a schematic structural diagram of a decoding device provided in an embodiment of the present application;

[0068] FIG18 is a schematic diagram of the structure of a computer system provided in an embodiment of the present application;

[0069] FIG19 is a schematic diagram of the structure of another computer system provided in an embodiment of the present application. DETAILED DESCRIPTION

[0070] The terms used in the embodiments of this application are only used to explain the embodiments of this application and are not intended to limit this application. The embodiments of this application are described below in conjunction with the accompanying drawings.

[0071] In the field of communication technology, the MAC chip and the PHY chip can transmit signals through a media independent interface (MII) to achieve network communication. Among them, MII is applicable to transmission scenarios with a rate of 10 megabits per second (Mbps) or 100Mbps. For example, MII is applicable to industrial Internet of Things scenarios. The MII defined by the Institute of Electrical and Electronics Engineers (IEEE) 802.3 standard is a parallel interface. MII includes 18 pins. These 18 pins are used to transmit data information, control information and management information. The specific method of MII pin transmission information can be found in the relevant content of the IEEE 802.3 standard and will not be elaborated here. However, in order to reduce packaging costs and allocate pins to support functions other than network communication, the number of pins included in the chip to support network communication is usually limited, so it is necessary to reduce the number of MII pins used to achieve network communication.

[0072] In a related technology, SGMII is used to implement signal transmission between the MAC chip and the PHY chip, wherein the number of pins of SGMII is less than that of MII. For 1000 baseband (BASE)-twisted pair (T) Ethernet, SGMII supports signal transmission between the MAC chip and the PHY chip in 1000BASE-T Ethernet through a serializer / deserializer (serdes) serial interface. SGMII is also compatible with the speed of 10 / 100BASE-T Ethernet. That is, when compatible with the speed of 10BASE-T Ethernet, SGMII is compatible with the speed of 10Mbps, and when compatible with the speed of 100BASE-T Ethernet, SGMII is compatible with the speed of 100Mbps.

[0073] However, SGMII is actually compatible with 10Mbps or 100Mbps at the rate of Gigabit Ethernet (GE). For example, the native GE rate supported by SGMII is 1000Mbps, and SGMII supports rates of 10Mbps and 100Mbps by replicating bytes 100 times and 10 times, respectively. Figure 1 is a schematic diagram of SGMII compatible with a transmission rate of 100Mbps in the related art. As shown in Figure 1, the data to be transmitted at a transmission rate of 100Mbps includes d0, d1, and d2. For each data that needs to be transmitted at a transmission rate of 100Mbps, each data is replicated 10 times, and then the replicated data is transmitted through SGMII to achieve SGMII compatibility with a rate of 100Mbps. However, when using SGMII to be compatible with lower rates, the replicated data will result in higher transmission costs and power consumption. In addition, since the replicated data is duplicated data, the solution of the related art will result in the transmission of a large amount of duplicate data, and the data transmission efficiency is low.

[0074] Furthermore, since the data bit width of SGMII is different from that of MII, if SGMII is used to directly replace MII, the difference in data bit width will lead to a data bit width mismatch. Figure 2 is a schematic diagram of a signal transmitted by MII in a related art. As shown in Figure 2, the receive data valid (RX_DV) signal indicates that the 4-bit 0101, D1, D2, / F / , and D4 to D7 are valid data, and the receive data error prompt (RX_ER) signal indicates that / F / is erroneous data, and D1, D2, D4 to D7 are all non-erroneous data. Among them, D1, D2, / F / , and D4 to D7 are all 4 bits. For the erroneous data / F / transmitted by MII, if SGMII is used to replace MII, since the data bit width of SGMII is 8 bits, the data transmitted by SGMII to replace the erroneous data / F / will meet the data bit width requirement of 8 bits by squeezing out D2 or D4. That is, the 8-bit data width of SGMII cannot match the 4-bit data width of MII.

[0075] The embodiments of the present application provide a coding method and a decoding method for improving the transmission efficiency of signals. The coding method and decoding method provided in the embodiments of the present application can be applied to a scenario in which a signal is transmitted via MII. When applied to this scenario, the above-mentioned signal is a signal transmitted by MII. In addition, the above-mentioned coding method and decoding method can also be applied to scenarios other than MII. For example, the implementation environment of the coding method and decoding method includes chip 1 and chip 2, and chip 1 and chip 2 are connected via a serial channel. The serial channel is used to connect the MAC layer and PHY. The serial channel is a channel between other interfaces except MII. Both the coding method and the decoding method can be applied to chip 1 or chip 2.

[0076] FIG3 is a schematic diagram of an implementation environment provided by an embodiment of the present application, taking the MII scenario as an example. The encoding method and the decoding method can be applied to the implementation environment shown in FIG3 . Referring to FIG3 , the implementation environment includes a first device 301 and a second device 302. The first device 301 includes a MAC chip 3011 and at least one PHY chip 3012 ( FIG3 takes the first device 301 as an example of including multiple PHY chips 3012). Signals are transmitted between the MAC chip 3011 and each PHY chip 3012 via the MII. The second device 302 includes a MAC chip 30211 and a PHY chip 3022. Signals are transmitted between the MAC chip 30211 and the PHY chip 3022 via the MII. Signals can be transmitted between the PHY chip 3012 and the PHY chip 3022. In some embodiments, the second device 302 includes an MCU 3021 and a PHY chip 3022, and the MCU 3021 includes a MAC chip 30211. In some embodiments, one or more of the MAC chip 3011 , the PHY chip 3012 , the MAC chip 30211 , and the PHY chip 3022 may be located in a separate chip, or in a separate die, or in one or more cores of a multi-core chip.

[0077] The encoding method and decoding method provided in the embodiments of the present application can be applied to signal transmission between the MAC chip 3011 and the PHY chip 3012, and can also be applied to signal transmission between the MAC chip 30211 and the PHY chip 3022. The number of first devices 301, the number of MAC chips 3011, the number of PHY chips 3012, the number of second devices 302, the number of MCUs 3021, the number of MAC chips 30211, and the number of PHY chips 3022 shown in Figure 3 are only examples and are not limited in the embodiments of the present application. The above-mentioned first device 301 can be a switch or a device applied to an Internet of Things terminal, and the second device 302 can be an Internet of Things terminal or a device applied to an Internet of Things terminal, for example, the Internet of Things terminal includes any one of a pressure gauge or a flow meter in the industrial Internet of Things. For example, the above-mentioned first device 301 and the second device 302 can be single pair Ethernet (SPE) devices or advanced physical layer (APL) devices.

[0078] The encoding method provided in the embodiment of the present application can be shown in Figure 4. Next, the method is described in conjunction with the implementation environment shown in Figure 3. The method can be applied to a first chip, which can be the MAC chip or PHY chip shown in Figure 3. As shown in Figure 4, the method includes but is not limited to S401 to S403.

[0079] S401: A first chip combines n cycles of first signals to be transmitted to obtain a second signal, where the n cycles of first signals include at least one of data information or control information, and n is a positive integer greater than 1.

[0080] Exemplarily, the first signal is a signal to be transmitted via the MII. In this case, the data bit width of the first signal is 4 bits. For example, the first signal includes a transmit data error prompt (TX_ER) signal, a transmit enable (TX_EN) signal, and a transmit data (TXD) signal to be transmitted via the MII. The data bit width of the TXD signal is 4 bits, and the TXD signal is represented as TXD<3:0>. The TX_ER signal and the TX_EN signal can identify whether TXD<3:0> is a data signal or a control signal, that is, the TX_ER signal and the TX_EN signal can identify whether the information included in TXD<3:0> is data information or control information.

[0081] In one possible implementation, merging n periods of first signals to obtain a second signal includes: merging the n periods of first signals according to a reference order to obtain the second signal. The reference order can be determined based on experience or actual needs. For example, the reference order can be the order in which the n periods of first signals are acquired, or an order other than the order in which the n periods of first signals are acquired. Thus, the order in which the n periods of first signals are merged is relatively flexible. When the reference order is the order in which the n periods of first signals are acquired, after the second signal is subsequently transmitted to a receiving end, the receiving end can directly obtain the order in which the n periods of first signals are acquired according to the order in which the n periods of first signals are arranged in the second signal, and further obtain at least one of the data information or control information included in the n periods of first signals according to the order in which the n periods of first signals are acquired. In this case, there is no need to adjust the order in which the n periods of first signals are acquired in the second signal to obtain the order in which the n periods of first signals are acquired, and obtaining the order in which the n periods of first signals are acquired is more efficient.

[0082] Illustratively, regardless of the reference order, the data bit width of the second signal is n times the data bit width of the first signal. For example, when the first signal is a signal to be transmitted via MII and n is 2, the second signal is generated by combining two cycles of the first signal, and the data bit width of the second signal is 8 bits. Since the data bit width of SGMII is 8 bits, the second signal can be transmitted via SGMII, and thus this method is compatible with SGMII defined in the IEEE 802.3 standard.

[0083] S402: The first chip encodes the second signal to obtain at least one code block.

[0084] The specific method for encoding the second signal is not limited in this embodiment of the present application. For example, the second signal is encoded according to an 8-bit (B) / 10B method to obtain at least one code block. Thus, at least one code block is a code block encoded in an 8B / 10B method. When at least one code block is encoded in 8B / 10B, the at least one code block can be directly transmitted through the serial channel between SGMIIs. In this embodiment of the present application, the at least one code block can also be obtained using any of 8B / 9B encoding, 64B / 65B encoding, 64B / 66B encoding, or 80B / 81B encoding. Thus, the method for encoding the second and third signals is relatively flexible.

[0085] Exemplarily, the type of the first code block is used to indicate the signal type included in the second signal, so that the signal type included in the second signal can be determined based on the type of the first code block, without the need for an additional type indication to indicate the signal type included in the second signal, and the overhead of indicating the signal type included in the second signal is low. In one possible implementation, the first signal of n periods includes multiple types of information, for example, the first signal of n periods includes data information and control information, or the first signal of n periods includes multiple types of control information. In this case, the second signal is encoded according to the type of information included in the first signal of n periods to obtain at least one code block. That is, when the first signal of n periods includes multiple types of information, the type of the first code block obtained by encoding the second signal can be determined based on the preset correspondence between the information type and the code block type.

[0086] Taking n equal to 2 and using 8B / 10B encoding as an example, the correspondence between information type and code block type can be shown in Table 1. In Table 1, the data bit width of the first signal is 4 bits, so the two first signals included in the second signal are respectively called the first half byte and the second half byte.

[0087] Table 1

[0088] As can be seen from the contents of Table 1, when both nibbles are data information, the two nibbles are encoded into an 8B / 10B encoded data code block. When the first nibble is data information and the second nibble is control information, the two nibbles are encoded into an 8B / 10B encoded control code block, and the type of the control code block is the same as the type of the control information. When the first nibble is control information and the second nibble is data information, the two nibbles are encoded into an 8B / 10B encoded control code block, and the type of the control code block is the same as the type of the control information.

[0089] When two nibbles are respectively control information, if the type of the two control information is the same, the two nibbles are encoded as a control code block of 8B / 10B encoding, and the type of the control code block is the same as the type of the control information. If the types of the two control information are different, the two nibbles can be encoded as a control code block of 8B / 10B encoding, or encoded as two control code blocks of 8B / 10B encoding. The type of control information has priority. When two nibbles are encoded as a control code block of 8B / 10B encoding, the type of the control code block obtained by encoding can be the same as the type with higher priority. When two nibbles are encoded as two control code blocks of 8B / 10B encoding, the type of the two control code blocks is the same as the type of the two control information. Since the code blocks of two nibbles are respectively encoded as two 8B / 10B encodings can cause the number of bits to increase, the increased bit caused by encoding occupies the coding bit width backward. That is, the subsequent signal that needs to be encoded is postponed to avoid missing the signal that needs to be encoded.

[0090] Exemplarily, the encoded second signal is a byte-aligned second signal, so that the second signal can meet the application condition of 8B / 10B encoding, and thus the second signal can be 8B / 10B encoded.

[0091] In one possible implementation, at least one code block includes a first code block and a second code block, the first code block includes a second signal, and the second code block includes a type indicator, where the type indicator is used to indicate the type of signal included in the second signal. In this implementation, the signal type included in the second signal is indicated by a separate code block, thereby ensuring that various types of signals in the second signal are indicated. In this implementation, since the signal type included in the second signal is indicated by the type indicator, the type of the first code block may not be used to indicate the signal type included in the second signal. Exemplarily, a first code block includes a second signal, and the second signal includes n periods of the first signal. The type indicator includes at least one indicator bit, where the at least one indicator bit is used to indicate the types of n*m first signals included in m first code blocks, where m is a positive integer. Thus, when m is greater than or equal to 2, the type indicator included in a second code block can indicate the types of first signals included in multiple first code blocks, making the number of first signals indicated by the type indicator more flexible and diverse.

[0092] In the embodiment of the present application, the manner in which at least one indication bit indicates the types of n*m first signals includes but is not limited to the following manner 1 and manner 2.

[0093] In a first approach, at least one indication bit indicates the types of n*m first signals in a bitmap manner.

[0094] For example, the number of indication bits is n*m, and the n*m ​​indication bits are used to indicate the types of the n*m ​​first signals included in the m first code blocks in a bitmap manner. One indication bit corresponds to one first signal, and the value of the indication bit is used to indicate the type of the first signal corresponding to the indication bit. For example, when the value of the indication bit is the first value, the indication bit is used to indicate that the first signal corresponding to the indication bit is a data signal; when the value of the indication bit is the second value, the indication bit is used to indicate that the second signal corresponding to the indication bit is a control signal. The first value and the second value can be determined based on experience or actual needs, for example, the first value is 0 and the second value is 1, or the first value is 1 and the second value is 0.

[0095] In the second method, at least one indication bit indicates the types of n*m first signals through an overall value.

[0096] For example, one situation of the overall value of at least one indicator bit corresponds to one situation of the type of n*m first signals. Therefore, based on the overall value of at least one indicator bit, the types of n*m first signals can be determined. For example, a chip that subsequently receives multiple code blocks can obtain the correspondence between values ​​and types. After the chip receives multiple code blocks, based on the overall value of at least one indicator bit, it queries the correspondence between values ​​and types to obtain the types of n*m first signals corresponding to the overall value. The embodiment of the present application does not limit the way in which the chip obtains the correspondence between values ​​and types. For example, the chip stores the correspondence between values ​​and types, and thus directly obtains the stored correspondence between values ​​and types. For another example, the chip sends a request instruction to a device that stores the correspondence between values ​​and types. The request instruction is used to request to obtain the correspondence between values ​​and types, and the chip receives the correspondence between values ​​and types sent by the device based on the request instruction. Among them, the device that stores the correspondence can be a chip or a device.

[0097] Combining the above-mentioned method 1 and method 2, it can be seen that in the embodiment of the present application, the method of at least one indicator bit indicating the types of n*m first signals is more flexible and diverse.

[0098] Exemplarily, when the at least one code block obtained by encoding the second signal includes a first code block and a second code block, and the second code block includes a type indication, the encoding method of the first code block corresponds to the type of the first signal of the n periods included in the first code block. For example, when the first signal of the n periods includes at least one data information, the first code block is encoded according to the data type. When the first signals of the n periods all include control information and the control types are the same, the first code block is encoded according to the control type. When the first signals of the n periods all include control information and the control types are different, the first code block is encoded according to the data type.

[0099] In some embodiments, the first chip encodes the second signal to obtain at least one code block, including: the first chip encodes the second signal and a third signal to be transmitted to obtain multiple code blocks, wherein the third signal includes management information. By encoding the second signal and the third signal, the multiple code blocks obtained by encoding can include at least one of data information or control information. The multiple code blocks can also include management information, thereby comprising a richer range of information types. Exemplarily, the management signal includes management data input and output (MDIO) information.

[0100] In the related art, whether it is MII or SGMII, management information is transmitted through an independent channel. Figure 5 is a schematic diagram of transmitting management information in the related art, wherein the switching chip of the switch shown in Figure 5 includes a MAC chip, which is not shown in Figure 5. As shown in Figure 5, the switching chip is connected to multiple PHY chips, and the switching chip is also connected to a complex programmable logic device (CPLD) or a microcontroller unit (MCU). The switching chip establishes channels for transmitting management information with X PHY chips through the CPLD or MCU, where X is a positive integer. That is, the switching chip establishes channels for transmitting management information with X PHY chips through the CPLD or MCU. The management information includes MDIO information. Since the management information is transmitted through an independent channel, the equipment cost for transmitting management information in the related art is relatively high.

[0101] In the method provided in an embodiment of the present application, when at least one of data information or control information is transmitted via a single serial channel, management information can also be transmitted via the same serial channel. Because data information, control information, and management information can be transmitted via the same serial channel, there is no need to transmit data information, control information, and management information separately via multiple channels. This method reduces the cost of transmitting data information, control information, and management information.

[0102] In one possible implementation, when the first chip is a PHY chip, the third signal further includes physical layer channel state indication information. When the third signal includes the physical layer channel state indication information, a chip that subsequently receives a code block encoding the second signal and the third signal can determine the state of the physical layer channel based on the physical layer channel state indication information. Exemplarily, the physical layer channel state indication information includes information included in at least one of a carrier sense (CRS) signal or a collision detection (COL) signal.

[0103] In related technologies, when SGMII is used directly to implement signal transmission between the MAC chip and the PHY chip, the SGMII at the transmitting end does not transmit the COL and CRS signals. The SGMII at the receiving end obtains the COL and CRS signals by performing logical operations on the TX_EN and RX_DV signals. However, in point-to-multipoint scenarios, since real COL and CRS signals, or virtual COL and CRS signals, are required to indicate the status of the physical link, it is necessary to add channels for transmitting the COL and CRS signals to the SGMII, resulting in higher equipment costs for the SGMII.

[0104] Because the method provided in the embodiments of the present application can directly transmit physical layer channel state indication information, without having to perform logical operations on other information other than the physical layer channel state indication information to infer the physical layer channel state indication information, this method is applicable to point-to-multipoint scenarios. The MDIO information, information included in the CRS signal, and information included in the COL signal can all be found in the relevant content of the IEEE 802.3 standard and will not be further described in the embodiments of the present application.

[0105] The embodiment of the present application does not limit the manner in which the second signal and the third signal to be transmitted are encoded. For example, the second signal and the third signal to be transmitted may be encoded using 8B / 10B encoding to obtain multiple code blocks. If the multiple code blocks are all encoded using 8B / 10B, the multiple code blocks obtained by encoding can be directly transmitted via the serial channel between SGMIIs. In the embodiment of the present application, the multiple code blocks may also be obtained using any of 8B / 9B encoding, 64B / 65B encoding, 64B / 66B encoding, or 80B / 81B encoding. This provides a relatively flexible manner in which the second signal and the third signal are encoded.

[0106] In one possible implementation, the multiple code blocks include a first code block and a second code block, the first code block includes a second signal, and the second code block includes a third signal. In this implementation, the second signal and the third signal are encoded in the two code blocks, respectively. In this case, the type of the first code block can be used to indicate the type of signal included in the second signal. The method in which the type of the first code block indicates the type of signal included in the second signal is similar in principle to the method in which the type of the first code block indicates the type of signal included in the second signal described above, and will not be further described here.

[0107] Exemplarily, when the type of the first code block is used to indicate the type of signal included in the second signal, the second code block may only include the third signal, so that the number of bits used by the second code block to include the third signal can be larger. In the case of transmitting the second code block, the transmission efficiency of the third signal is higher. In some embodiments, when the number of first code blocks is multiple, the second code block may be located between the multiple first code blocks, or before the multiple first code blocks, or after the multiple first code blocks. Thus, the position of the second code block is more flexible. When the number of first code blocks and the number of second code blocks are both multiple, the multiple first code blocks and the multiple second code blocks may be arranged periodically. For example, one period includes a first number of first code blocks and a second number of second code blocks. The first number and the second number can be set based on experience or actual needs, and the embodiments of the present application are not limited to this.

[0108] In some embodiments, when the number of bits included in the second code block is equal to or greater than the number of bits of the management information, one second code block can include all the bits of the management information, and thus, all the bits included in the management information can be obtained based on one second code block. When the number of bits included in the second code block is less than the number of bits of the management information, multiple second code blocks include the bits of the management information. In this case, all the bits of the management information can be obtained based on multiple second code blocks. In embodiments of the present application, the relationship between the number of bits included in the second code block and the number of bits of the management information is relatively flexible.

[0109] Exemplarily, when multiple first code blocks and multiple second code blocks are arranged periodically, the second signal and the third signal appear periodically in the coding sequence used for encoding. Figure 6 is a schematic diagram of a sequence to be encoded provided by an embodiment of the present application. As shown in Figure 6, the sequence to be encoded is a coding sequence for 8B / 10B encoding. In the coding sequence, the second signal and the third signal appear periodically, the second signal includes n periods of the first signal, and the third signal includes 8 bits of management information. Thus, in the multiple code blocks obtained based on the sequence to be encoded shown in Figure 6, the first code block and the second code block appear alternately.

[0110] In one possible implementation, when encoding the second signal and the third signal to obtain multiple code blocks, and the multiple code blocks include a first code block and a second code block, the second code block also includes a type indicator, where the type indicator is used to indicate the signal type included in the second signal. That is, the second code block includes the type indicator and the third signal. In this implementation, since the signal type included in the second signal is indicated by the type indicator, the type of the second signal does not need to be indicated by the type of the first code block. The method of using the type indicator to indicate the signal type included in the second signal is similar in principle to the method of using the type indicator to indicate the signal type included in the second signal described above, and will not be further described here.

[0111] FIG7 is a schematic diagram of a process for encoding a second signal and a third signal to obtain multiple code blocks provided by an embodiment of the present application, wherein FIG7 takes 8B / 10B encoding as an example. Referring to FIG7 , the first signal includes a TX_ER signal, a TX_EN signal, and TXD<3:0>. The TX_ER signal and the TX_EN signal can identify whether TXD<3:0> is a data signal or a control signal, that is, the TX_ER signal and the TX_EN signal can identify whether the information included in TXD<3:0> is data information or control information, and the third signal includes MDIO information. In FIG7 , taking n equal to 2 as an example, the first signal of 2 cycles includes the first signal of the a-th cycle and the first signal of the a+1-th cycle, where a is a positive integer. The first signals of the 2 cycles are merged to obtain the second signal, which includes 8 bits, that is, the second signal includes one byte, and the byte includes bits 7 to 0.

[0112] The second signal and the third signal to be encoded are shown in the sequence to be encoded in Figure 7. The sequence to be encoded includes the second signal, a type indicator for indicating the type of signal included in the second signal, and the third signal. Exemplarily, when the second signal includes 8 bits, the sum of the number of bits of the type indicator and the third signal used to encode into a second code block is less than or equal to 8 bits. As shown in Figure 7, the type indicator used to encode into a second code block includes 2 bits, wherein the first bit of the 2 bits is used to indicate the information type of the first 4 bits in the second signal, and the last bit of the 2 bits is used to indicate the information type of the last 4 bits in the second signal. The number of bits of the third signal used to encode into a second code block is 2 bits.

[0113] In the case where the sum of the number of bits of the type indication and the third signal used to encode a second code block is less than 8 bits, the second code block also includes other bits in addition to the bits of the type indication and the third signal. The other bits may be bits of information that needs to be included in the second code block for transmission, and this embodiment of the present application is not limited to this. For example, referring to Figure 7, the 8 bits used to encode a second code block include 2 bits of type indication, 2 bits of management information, and other 4 bits, wherein the positions of the 2 bits of type indication, the 2 bits of management information, and the other 4 bits can be as shown in Figure 7. After obtaining the second signal and the third signal, the second signal and the third signal are encoded. Referring to Figure 7, the second signal and the third signal are encoded to obtain a first code block and a second code block, the first code block includes the second signal, and the second code block includes the type indication and the third signal.

[0114] In some embodiments, when the second signal includes 8 bits, the number of bits used to encode the type indication of a second code block and the third signal is equal to 8 bits. Figure 8 is a schematic diagram of a sequence to be encoded provided by an embodiment of the present application. The third signal includes MDIO information, information included in the CRS signal, and information included in the COL signal. For ease of explanation, the 8 bits used to encode into a second code block are identified as / indication / in Figure 8. The 7th bit of / indication / is used to indicate the information type of the first half byte of the first byte, the 6th bit of / indication / is used to indicate the information type of the second half byte of the first byte, the 5th bit of / indication / is used to indicate the information type of the first half byte of the second byte, and the 4th bit of / indication / is used to indicate the information type of the second half byte of the second byte, wherein the first byte and the second byte are respectively used to encode into a first code block, and the first byte and the second byte are both obtained by merging the first signal of 2 cycles.

[0115] Please continue to refer to Figure 8. The 3rd bit of / indication / is the information included in the CRS signal, the 2nd bit of / indication / is the information included in the COL signal, and the 1st and 0th bits of / indication / are both MDIO signals. Exemplarily, in the case where the second code block includes a type indication, the second code block is adjacent to the first code block of the signal type included in the type indication second signal. For example, the type indication included in the second code block is used to indicate the signal type included in the second signal in at least one first code block. The second code block is adjacent to the at least one first code block, and the second code block can be located after at least one first code block. In the case where the second code block is adjacent to the at least one first code block, the bit used to encode the second code block is adjacent to the bit used to encode the at least one first code block. For example, as shown in Figure 8, the bit used to encode the two first code blocks includes the first byte and the second byte, and the / indication / used to encode the second code block is adjacent to the second byte and is located after the second byte.

[0116] In the sequence to be encoded shown in Figure 8, the 8 bits to be encoded as the first code block can include multiple information types. For example, referring to Figure 8, when both nibbles included in the 8 bits to be encoded as the first code block are data information, the information type included in the 8 bits is represented as / dd / . When the 8 bits to be encoded as the first code block include data information and control information, and the first 4 bits are data information and the last 4 bits are control information, the information type included in the 8 bits is represented as / dk / . When the 8 bits to be encoded as the first code block include data information and control information, and the first 4 bits are control information and the last 4 bits are data information, the information type included in the 8 bits is represented as / kd / . When the 8 bits to be encoded as the first code block include control information, and the control information of the first 4 bits and the control information of the last 4 bits are of the same type, the information type included in the 8 bits is represented as / kk / . When the 8 bits to be encoded as the first code block include control information, and the control information of the first 4 bits and the control information of the last 4 bits are of different types, the information type included in the 8 bits is represented as / k1k2 / . The cases of / kd / , / kk / and / k1k2 / are not shown in FIG. 8 .

[0117] Exemplarily, the control code blocks obtained by encoding the second signal can be used to perform at least one of delimiting or identifying a serial sequence, where the control code blocks refer to code blocks obtained by encoding the second signal including control information, and the serial sequence includes multiple code blocks obtained by encoding the second signal. For example, the serial sequence includes multiple code blocks obtained by encoding only the second signal, or multiple code blocks obtained by encoding the second signal and a third signal. Taking 8B / 10B encoding of the second signal as an example, the control code blocks obtained by encoding the second signal include one or more 8B / 10 encoded control code blocks, where the one or more 8B / 10B encoded control code blocks are used to perform at least one of delimiting or identifying the serial sequence. For example, the one or more 8B / 10B encoded control code blocks include at least one of an / I / code, an / S / code, a / T / code, or an / LI / code. The / I / code is used to indicate an Ethernet frame idle state, the / S / code is used to indicate the start of an Ethernet frame, the / T / code is used to indicate the end of an Ethernet frame, and the / LI / code is used to indicate low power consumption. The / I / and / S / shown in FIG8 are the / I / code and the / S / code, respectively.

[0118] By encoding one or more 8B / 10Bb-encoded control code blocks, the code blocks encoded by the method of the embodiment of the present application can retain the "comma" field in the 8B / 10B encoding defined by the IEEE 802.3 standard. Thus, after the encoded code blocks are sent to the device at the receiving end, the device at the receiving end can more easily identify the boundary of the 8B / 10B encoding. For example, the K28.5 code in the / I / code contains the "comma" field, which is a unique identifier in the 8B / 10B encoding. For another example, the / S / code and the / T / code directly indicate the start and end of the Ethernet frame, respectively, reducing the complexity of judging the start and end of the Ethernet frame.

[0119] Figure 9 is a schematic diagram of a code block sequence obtained by encoding provided by an embodiment of the present application, wherein the code block sequence includes multiple code blocks. As shown in Figure 9, the code block sequence includes code blocks that identify Ethernet frame idle, Ethernet frame start, Ethernet frame data, Ethernet frame end, and Ethernet frame interval. The code block sequence shown in Figure 9 can be a code block sequence associated with an Ethernet frame. The number of code blocks included in the code block sequence shown in Figure 9 is only for illustration and is not used to limit the number of code blocks included in the code block sequence. Exemplarily, the code block that identifies the Ethernet frame idle, the code block that identifies the Ethernet frame start, and the code block that identifies the Ethernet frame end are respectively the same as the code block that identifies the Ethernet frame idle, the code block that identifies the Ethernet frame start, and the code block that identifies the Ethernet frame end obtained by 8B / 10B encoding defined by IEEE 802.3.

[0120] In Figure 9, a square box represents an 8B / 10B-encoded code block. For either the first or second half of a code block, if the first half is derived from data information, it can be identified by / d / ; if the first half is derived from control information, it can be identified by / k / . Referring to Figure 9, if both parts of the code block are derived from data information, the code block can be identified by / dd / ; if the first and second parts of the code block are derived from data information and control information, respectively, the code block can be identified by / dk / .

[0121] In one possible implementation, when the multiple code blocks include a first code block and a second code block, the first code block includes a second signal, the second code block includes a third signal, the first signal is associated with an Ethernet frame, an Ethernet frame is associated with at least one first code block among the multiple code blocks, and the second code block is transmitted before or after the first code block associated with the same Ethernet frame. Because the second code block includes the third signal, and the third signal includes management information, by transmitting the second code block before or after the first code block associated with the same Ethernet frame, the management information can be transmitted when Ethernet frames are not transmitted or when no Ethernet frame is transmitted.

[0122] Because the IEEE 802.3 standard defines idle code blocks as those transmitted during Ethernet frame intervals or when no Ethernet frames are present, by transmitting a second code block instead of an idle code block during at least one of the Ethernet frame intervals or when no Ethernet frames are present, the interface rate used to transmit the code block can be maintained unchanged, thereby maintaining the power consumption of the code block transmission. Furthermore, because this method transmits the second code block instead of an idle code block during Ethernet frame intervals or when no Ethernet frames are present, and the second code block includes a type indicator or includes both a type indicator and management information, this method achieves high information transmission efficiency. For details on the first code block associated with an Ethernet frame, refer to the aforementioned description of the code block including the second signal and will not be further elaborated here.

[0123] FIG10 is a schematic diagram of the position of a second code block provided in an embodiment of the present application. As shown in FIG10 , unlike the idle code blocks transmitted in the Ethernet frame interval, the code blocks transmitted in the Ethernet frame interval are second code blocks including management information. In FIG10 , all code blocks except the second code blocks are code blocks associated with the Ethernet frame. FIG11 is a schematic diagram of the position of another second code block provided in an embodiment of the present application. As shown in FIG11 , unlike the idle code blocks transmitted when there is no Ethernet frame, the second code blocks including management information are transmitted when there is no Ethernet frame. In FIG11 , all code blocks except the second code blocks are idle code blocks.

[0124] In another possible implementation, the multiple code blocks include a first code block and a second code block, the first code block includes a second signal, the second code block includes a third signal, the first signal is associated with an Ethernet frame, an Ethernet frame is associated with at least one first code block from the multiple code blocks, the at least one first code block includes a first code block associated with a preamble of the Ethernet frame, and the second code block is used to replace the first code block associated with the preamble for transmission. Compared to the previous implementation, the second code block including management information is transmitted in the position of the preamble of the Ethernet frame, rather than during Ethernet frame intervals or when no Ethernet frame is present.

[0125] Because this method replaces the first code block associated with the preamble with the second code block for transmission, this implementation method can also maintain the interface rate used to transmit the code block unchanged when transmitting the second code block, thereby maintaining the power consumption of the transmitted code block unchanged. Furthermore, since Ethernet frame intervals may be used to compensate for clock differences between interfaces, code blocks transmitted between Ethernet frame intervals may be deleted when the Ethernet frame interval is used to compensate for clock differences. By replacing the first code block associated with the preamble with the second code block, the deletion of the second code block containing management information when deleting code blocks transmitted between Ethernet frame intervals can be avoided, thereby improving the transmission reliability of the second code block.

[0126] Exemplarily, the management information included in the second code block is the management information of the first Ethernet frame, the first code block associated with the preamble replaced by the second code block is the first code block associated with the preamble of the second Ethernet frame, and the first code block associated with the first Ethernet frame is sent before the first code block associated with the second Ethernet frame. For details about the first code block associated with the Ethernet frame, refer to the content of the code block including the second signal in the previous text and will not be repeated here.

[0127] Figure 12 is a schematic diagram of the position of another second code block provided in an embodiment of the present application. As shown in Figure 12, the format of an Ethernet frame specified in the IEEE 802.3 standard includes a preamble, a start frame delimiter (SFD), data, and a frame check sequence (FCS). The preamble includes 7 bytes and the SFD includes 1 byte. In an embodiment of the present application, the 7-byte preamble and the 1-byte SFD are collectively referred to as the preamble. The Ethernet frame uses a start packet delimiter (SPD) as the starting boundary of the Ethernet frame. The SPD is encoded as an / S / code using 8B / 10B encoding. The / S / code is used to replace the code block encoded by the first byte of the preamble of the Ethernet frame, and the second code block is used to replace the code block encoded by the bytes of the preamble other than the first byte. As shown in Figure 12, the data and FCS of the Ethernet frame can be encoded as the first code block. Exemplarily, the code block transmitted before the Ethernet frame can be an idle code block.

[0128] Exemplarily, when a second code block is transmitted before or after a first code block associated with the same Ethernet frame, or when the second code block is used to replace the first code block associated with the preamble of the Ethernet frame for transmission, the second code block is a control code block or a control code block group whose control type is not clearly defined in the encoding method, so that based on the control code block or control code block group, the code block can be determined to be the second code block, that is, the second code block is used as the starting identifier of multiple second code blocks. Exemplarily, the second code block is a / K / code or a / K / D / code block group whose control type is not clearly defined in 8B / 10B encoding, so based on the / K / code or / K / D / code block group, the code block can be determined to be the second code block including management information.

[0129] In one possible implementation, when there are multiple second code blocks, the multiple second code blocks also include data code blocks, and the data code blocks include management information. For example, the number of data code blocks including management information is four. Thus, when the second code blocks are identified by the / K / code, the number of second code blocks including management information is five; when the second code blocks are identified by the / K / D / code block group, the number of second code blocks including management information is six. When the multiple second code blocks also include data code blocks, the second code block used as a start identifier is located before the data code blocks included in the multiple second code blocks.

[0130] FIG13 is a schematic diagram of a second code block including management information provided by an embodiment of the present application. As shown in FIG13 , when the number of second code blocks is five, the five second code blocks include a / K / code and four data code blocks; when the number of second code blocks is six, the six second code blocks include a / K / D / code block group and four data code blocks. The principles of the five or six second code blocks shown in FIG10 to FIG12 are the same as those of the second code block shown in FIG13 and are not further described.

[0131] Exemplarily, in the absence of Ethernet frame transmission, after sending an idle code block and a second code block to a receiving device, the device can achieve code block alignment using a coding sequence based on the idle code block, and thereby obtain the second code block including management information based on the second code block used as a starting identifier. In the presence of Ethernet frame transmission, after sending a first code block and a second code block to a receiving device, the device can achieve code block alignment using a coding sequence based on the first code block, and thereby obtain the second code block including management information based on the second code block used as a starting identifier.

[0132] S403: The first chip sends at least one code block through a serial channel, where the serial channel is used to connect the MAC layer and the PHY.

[0133] Exemplarily, the serial channel is used to connect the reconciliation sublayer (RS) and the physical coding sublayer (PCS), or the serial channel is used to connect the RS and the physical layer signaling sublayer (PLS). In some embodiments, the serial channel is used to implement data transmission between the MAC sublayer and the PHY, or to implement data transmission between the STA and the PHY. Exemplarily, the serial channel is a channel between improved SGMIIs. For example, the chips on both sides of the serial channel include improved SGMIIs, and the two improved SGMIIs are connected through the serial channel. Among them, the improved SGMII refers to an MII implemented based on the SGMII and applicable to the encoding method and decoding method provided in the embodiments of the present application. The structure of the improved SGMII can be found in the relevant content of Figure 15 below, which will not be explained in detail here.

[0134] In one possible implementation, when multiple code blocks are obtained through encoding, the first chip transmits at least one code block through a serial channel, including: the first chip transmits the multiple code blocks through one serial channel. When the multiple code blocks include a first code block and a second code block, the first code block includes a second signal, and the second code block includes a third signal, by transmitting the multiple code blocks through one serial channel, at least one of data information or control information and management information can be transmitted over the same channel.

[0135] When multiple code blocks are transmitted via a serial channel, a first chip and a second chip that subsequently receives the multiple code blocks only need to be configured with a relatively small number of pins to implement the serial channel, thereby enabling the transmission of at least one of data information or control information and management information. For example, the serial channel is implemented by a single pin or a group of pins. Thus, if the serial channel is implemented by a single pin, the pin is used to transmit the multiple code blocks. If the serial channel is implemented by multiple pins, differential signals transmitted via the multiple pins can be first obtained based on the multiple code blocks, and then the differential signals can be transmitted via the multiple pins, thereby enabling the transmission of the multiple code blocks via a single serial channel.

[0136] Compared to establishing separate channels for transmitting management information and for transmitting data and control information, the method provided in the embodiments of the present application establishes a single channel to transmit data, control, and management information, resulting in lower equipment costs for establishing the channel. Furthermore, since there is no need to transmit data, control, and management information separately through multiple channels, this method reduces the cost of transmitting data, control, and management information.

[0137] In one possible implementation, a first chip transmits at least one code block via a serial channel, including: the first chip negotiates with a chip at the other end of the serial channel about a clock for transmitting the at least one code block; and the first chip transmits the at least one code block via the serial channel according to the negotiated clock. By negotiating the clock used to transmit the code block, the method can adjust the frequency of the transmission clock. Because SGMII uses data replication for byte alignment, the clock frequency used for code block transmission in SGMII is fixed. The clock frequency used in the method provided in the embodiments of the present application is more flexible than that used in SGMII. Furthermore, by negotiating the clock used to transmit the code block with the other end chip, the clock frequency used in code block transmission can be adapted to the conditions of the chips at both ends of the serial channel. Thus, when code blocks are transmitted according to the negotiated clock, the information system at the other end of the serial channel can receive the code blocks according to the negotiated clock, ensuring the reliability of code block transmission.

[0138] Exemplarily, the clock negotiation process provided in the embodiments of the present application is compatible with the auto-negotiation function of the SGMII defined in the IEEE 802.3 standard. For example, a first chip negotiates with a chip at the other end of a serial channel about a clock for transmitting at least one code block, including: the first chip determines the frequency of the clock used for negotiation, and negotiates with the chip at the other end of the serial channel based on the determined frequency; if the negotiation succeeds, the frequency is determined as the frequency of the clock used for transmitting the code block; if the negotiation fails, the first chip adjusts the frequency of the clock used for negotiation, and negotiates with the chip at the other end of the serial channel based on the adjusted frequency until the negotiation succeeds.

[0139] In one possible implementation, the first chip negotiates with the chip at the other end of the serial channel according to the SGMII auto-negotiation format defined by the IEEE 802.3 standard. The frequency of the first clock used for negotiation determined by the first chip can be the main frequency with the highest rate among the multiple main frequency points supported by the first chip, so that when the negotiation is successful, the rate of transmitting code blocks is higher. Of course, the frequency of the first clock used for negotiation can also be other main frequency points among the multiple main frequency points except the main frequency point with the highest rate. Exemplarily, the multiple main frequency points include at least two of a main frequency point with a rate of 10 Mbps, a main frequency point with a rate of 100 Mbps, or a main frequency point with a rate of 1000 Mbps.

[0140] In some embodiments, after successful negotiation, the first chip further determines the interface type of the chip at the other end of the serial channel and transmits code blocks in accordance with the determined interface type's code block transmission method. For example, if successful negotiation is based on a primary frequency point with a rate of 1000 Mbps, and the first chip determines that the interface of the chip at the other end of the serial channel is SGMII, the first chip transmits code blocks in accordance with the SGMII code block transmission method.

[0141] Exemplarily, the first chip periodically negotiates with the chip at the other end of the channel about the clock used to transmit code blocks, thereby avoiding negotiation failures due to inconsistent power-on times of the chips at both ends of the serial channel. For example, if one of the chips at either end is not powered on, negotiations based on multiple main frequencies will fail. However, if both chips are powered on, negotiations based on one or more of the multiple main frequencies will succeed. Therefore, by periodically negotiating the clock, this method can avoid negotiation failures due to inconsistent power-on times and ensure negotiation effectiveness.

[0142] Exemplarily, when at least one code block includes multiple first code blocks and multiple second code blocks, the frequency of the clock used for negotiation is determined based on the transmission rate corresponding to the data information in the first signal, the number of first code blocks, the number of second code blocks, and the coding efficiency of the coding method. In this case, the frequency of the clock used for negotiation can be adapted to the situation of the code block to be transmitted, thereby ensuring the reliability of transmitting the code block according to the clock determined by negotiation. Exemplarily, the frequency R of the clock used for negotiation is obtained based on the following formula 1. R = F*E*(C+D) / C (Formula 1)

[0143] Where F represents the transmission rate corresponding to the data information in the first signal, E represents the coding efficiency of the coding scheme, C represents the number of first code blocks, and D represents the number of second code blocks. When the coding scheme is 8B / 10B, E is equal to 1.25. When multiple first code blocks and multiple second code blocks are arranged periodically, the above (C+D) / C can be obtained based on the code blocks in one period. For example, the (C+D) / C can be obtained by dividing the number of code blocks in one period by the number of first code blocks in that period.

[0144] In the method provided in the embodiment of the present application, a second signal is obtained by merging n cycles of the first signal, and the second signal includes a larger number of first signals, that is, the method can convert the first signal with a lower data bit width into a second signal with a higher data bit width. Thus, when the second signal is encoded to obtain at least one code block and at least one code block is transmitted, the number of first signals included in the at least one code block is larger. Compared with the method of transmitting a code block including multiple repeated signals, this method has a higher efficiency in transmitting signals. When the second signal includes multiple types of information, the multiple types of information can be transmitted serially through the same serial channel, and the number of channels required to transmit the multiple types of information is smaller, resulting in lower costs.

[0145] When the method further encodes a third signal, the multiple code blocks obtained by encoding can include multiple types of information. When a serial channel for transmitting multiple code blocks is implemented via a single pin or a group of pins, the first chip can include a relatively small number of pins for implementing the serial channel. When at least one of data information or control information is transmitted via a serial channel, and management information is also transmitted via the same serial channel, since the data information, control information, and management information can be transmitted via the same serial channel, there is no need to transmit the data information, control information, and management information separately via multiple channels. This method reduces the cost of transmitting the data information, control information, and management information.

[0146] Furthermore, this method can negotiate the clock used to transmit code blocks, allowing for a wide variety of clock frequencies and adapting the clock frequency used to transmit code blocks to the chips at both ends of the serial channel. Thus, when code blocks are transmitted according to the negotiated clock, the information system at the other end of the serial channel can receive the code blocks according to the negotiated clock, ensuring reliable code block transmission. When the negotiated clock frequency is low, this method reduces power consumption when transmitting code blocks.

[0147] The encoding method provided in the embodiment of the present application is described above. This embodiment of the present application also provides a decoding method, which can be shown in Figure 14. This method can be applied to a second chip, which can be the MAC chip or PHY chip shown in Figure 3. As shown in Figure 14, this method includes but is not limited to S1401 to S1403.

[0148] S1401. The second chip receives at least one code block through a serial channel. The at least one code block is obtained by encoding a second signal. The second signal is obtained by merging n cycles of first signals to be transmitted. The n cycles of first signals include at least one of data information or control information. The serial channel is used to connect the MAC layer and the PHY, and n is a positive integer greater than 1.

[0149] Exemplarily, the serial channel is a channel between improved SGMIIs. In one possible implementation, the second chip receives at least one code block via the serial channel, including: the second chip negotiates with the chip at the other end of the serial channel about a clock for transmitting the at least one code block; and the second chip receives the at least one code block via the serial channel according to the negotiated clock. The method by which the second chip negotiates the clock is the same as the principle of the method by which the first chip negotiates the clock in the aforementioned encoding method, and will not be repeated here. Exemplarily, the at least one code block includes multiple first code blocks and multiple second code blocks, and the frequency of the clock used for negotiation is determined based on the transmission rate corresponding to the data information in the first signal, the number of first code blocks, the number of second code blocks, and the coding efficiency of the encoding method. For example, the frequency of the clock used for negotiation is determined according to Formula 1 above.

[0150] In one possible implementation, the second chip receives at least one code block via a serial channel, including: the second chip receives multiple code blocks via the serial channel, the multiple code blocks being obtained by encoding a second signal and a third signal to be transmitted, the third signal including management information. Exemplarily, when the second chip is a MAC chip, the third signal also includes a physical layer channel state indication signal. The code blocks obtained by encoding the second signal and the code blocks obtained by encoding the second signal and the third signal can be found in the relevant description of the encoding method above and are not further described here.

[0151] S1402: The second chip decodes at least one code block to obtain a second signal.

[0152] Exemplarily, when at least one code block includes a first code block and a second code block, and the first code block includes a second signal, and the second code block includes a type indication, and the type indication is used to indicate the type of signal included in the second signal, the second chip decodes the at least one code block to obtain the second signal, including: the second chip obtains the second signal from the first code block.

[0153] Exemplarily, when the second chip receives multiple code blocks, and the multiple code blocks are obtained by encoding the second signal and the third signal, the second chip decodes at least one code block to obtain the second signal, including: the second chip decodes the multiple code blocks to obtain the second signal and the third signal.

[0154] S1403: The second chip splits the second signal to obtain n signals.

[0155] In one possible implementation, when at least one code block includes a second code block and the second code block includes a type indication, the second chip splits the second signal to obtain n signals, including: the second chip obtains the signal type included in the second signal based on the type indication included in the second code block; the second chip splits the second signal according to the signal type included in the second signal to obtain n signals.

[0156] Exemplarily, a first code block includes a second signal, a second signal includes n periods of the first signal, the type indication includes at least one indication bit, the at least one indication bit is used to indicate the type of the n*m ​​first signals included in the m first code blocks, m is a positive integer, and the second chip obtains the signal type included in the second signal based on the type indication included in the second code block, including: the second chip obtains the type of the n*m ​​first signals included in the m first code blocks based on at least one indication bit.

[0157] In some embodiments, the number of indication bits is n*m, and the n*m ​​indication bits are used to indicate the types of n*m first signals included in the m first code blocks in a bitmap manner; the second chip obtains the types of n*m first signals included in the m first code blocks based on at least one indication bit, including: the second chip obtains the type of the first signal corresponding to each indication bit based on the value of each indication bit in the n*m ​​indication bits.

[0158] In other embodiments, the overall value of at least one indicator bit is used to indicate the type of n*m first signals included in the m first code blocks; the second chip obtains the type of n*m first signals included in the m first code blocks based on the at least one indicator bit, including: the second chip obtains the type of each first signal in the n*m ​​first signals based on the overall value of at least one indicator bit.

[0159] Exemplarily, when the signal type included in the second signal is indicated by a type indication, the obtained n signals are n first signals used for merging to obtain the second signal.

[0160] In one possible implementation, when multiple code blocks include a first code block and a second code block, and the first code block includes a second signal, the second code block includes a third signal, and the type of the first code block is used to indicate the signal type included in the second signal, the second chip splits the second signal to obtain n signals, including: the second chip obtains the signal type included in the second signal according to the type of the first code block; the second chip splits the second signal according to the signal type of the second signal to obtain n signals.

[0161] Exemplarily, when the first code block is a data code block, the type of the first code block is used to indicate that the signal type included in the second signal is a data signal. In this case, the obtained n signals are the n first signals used to combine to obtain the second signal.

[0162] Exemplarily, when the first code block is a control code block, the type of the first code block is used to indicate that the type of signal included in the second signal is a control signal, and the type of the control signal is the same as the type of the control code block. In this case, the n signals obtained are n control signals. The type of the n control signals is the same as the type of the control signals in the n first signals used to combine to obtain the second signal.

[0163] In the method provided in the embodiment of the present application, the second signal is obtained by merging n cycles of the first signal, and the second signal includes a larger number of first signals, that is, the method can convert the second signal with a higher data bit width into a first signal with a lower data bit width. In the case of receiving at least one code block obtained by encoding the second signal, the at least one code block includes a larger number of first signals. Compared with the method of receiving a code block including multiple repeated signals, this method has a higher efficiency in receiving signals. In the case where the second signal includes multiple types of information, the multiple types of information can be received serially through the same serial channel, and the number of channels required to receive the multiple types of information is small, and the cost is low.

[0164] When the method also receives a code block obtained by encoding a third signal, the method can receive multiple types of information. When a serial channel for receiving multiple code blocks is implemented via a single pin or a group of pins, the second chip can include fewer pins for implementing the serial channel. When at least one of data information or control information is received via a serial channel, and management information is also received via the same serial channel, since the data information, control information, and management information can be received via the same serial channel, there is no need to receive the data information, control information, and management information separately via multiple channels, resulting in lower costs for receiving the data information, control information, and management information.

[0165] Furthermore, this method can negotiate the clock used to receive code blocks, allowing for a wide variety of clock frequencies and adapting the clock frequency used to receive code blocks to the chips at both ends of the serial channel. The information at the other end of the serial channel can receive code blocks according to the negotiated clock, and the second chip can also receive code blocks according to the negotiated clock, ensuring reliable code block transmission. When the negotiated clock frequency is low, this method reduces power consumption when receiving code blocks.

[0166] FIG15 is a schematic diagram of the architecture of an improved SGMII provided in an embodiment of the present application. As shown in FIG15 , both the MAC chip and the PHY chip include the improved SGMII. As shown in FIG15 , the improved SGMII includes the SGMII, a double-nibble bit width adjustment module, an indication insertion module, a management module, an indication extraction module, a channel status module, and a clock frequency division module. The double-nibble bit width adjustment module is connected to the indication insertion module and the indication extraction module, respectively. The indication insertion module and the indication extraction module are both connected to the management module. The indication insertion module and the indication extraction module are also both connected to the SGMII. The SGMII is also connected to the clock frequency division module. In the MAC chip, the channel status module is connected to the indication extraction module. In the PHY chip, the channel status module is connected to the indication insertion module.

[0167] The SGMII includes an encoding module, a decoding module, a serialization module, a deserialization module, and an auto-negotiation module. The encoding module is connected to the indication insertion module and the serialization module, respectively; the decoding module is connected to the indication extraction module and the deserialization module, respectively; the auto-negotiation module is connected to the encoding module and the decoding module, respectively; and the clock frequency division module is connected to the auto-negotiation module. Exemplarily, the improved SGMII in the MAC chip and the improved SGMII in the PHY chip are connected via a pair of serial channels. As shown in FIG15 , this pair of serial channels includes a serial channel between the serialization module in the MAC chip and the deserialization module in the PHY chip, and also includes a serial channel between the serialization module in the PHY chip and the deserialization module in the MAC chip. The connection between the serialization module and the deserialization module can be referred to as a SerDes connection. By using serial channels to enable signal transmission between the MAC module and the PHY module, signals to be transmitted in parallel via the MII defined by the IEEE 802.3 standard can be transmitted serially via the serial channels.

[0168] Please continue to refer to Figure 15. In the MAC chip, the transmitting side of the improved SGMII includes a TX_ER signal, a TX_EN signal, a TXD signal and a transmit data reference clock (TX_CLK) signal, wherein the TX_ER signal and the TX_EN signal are used to identify the TXD signal as data information or control information. The double half-byte bit width adjustment module merges the half-byte signals of the two cycles of the transmitting side into a byte signal and carries an indication signal of the information type included in the corresponding half-byte signal. The half-byte signal is the first signal in the above method embodiment, and the byte signal is the second signal in the above method embodiment. The indication insertion module receives the byte signal and the indication signal, and the indication insertion module also receives the management signal sent by the management module, and the management signal includes management information. For example, the management information includes the management frame defined by the IEEE 802.3 standard. Exemplarily, the management module receives the MDIO signal and the management data clock (MDC) signal, obtains the management frame based on the MDIO signal and the MDC signal, and sends the management signal to the indication insertion module at a rate suitable for the indication insertion module, and the management signal includes the management frame. The instruction insertion module receives the byte signal, instruction signal, and management signal, and generates a sequence to be encoded. The module then sends the sequence to the encoding module. The encoding module encodes the sequence to be encoded, generating multiple code blocks, which it then sends to the serialization module. The serialization module then transmits the multiple code blocks as a serialized code block stream.

[0169] In the PHY chip, after the improved SGMII receives the serial code block stream sent by the serial channel, the deserialization module deserializes the serial code block stream to obtain multiple code blocks. The decoding module decodes multiple code blocks to obtain a sequence to be encoded. The indication extraction module obtains byte signal, indication signal and management signal from the sequence to be encoded, sends indication signal and byte signal to the double half byte width adjustment module, and sends management signal to the management module. The double half byte width adjustment module splits the byte signal into the half byte signal of two cycles according to the indication signal, outputs the half byte signal of two cycles according to the order of the two half byte signals, and the half byte signal of the output is the received data (RXD) signal of the MII transmission defined by the IEEE 802.3 standard. The management module converts the management signal into the MDIO signal and the MDC signal defined by the IEEE 802.3 standard. Exemplarily, as shown in Figure 15, the PHY chip also receives a receive data reference clock (RX_CLK) signal.

[0170] In the PHY chip, the improved SGMII transmits signals in the same manner as the improved SGMII transmits signals in the MAC chip. In the MAC chip, the improved SGMII receives signals in the same manner as the improved SGMII receive signals in the PHY chip. Continuing with Figure 15, for the improved SGMII in the PHY chip, the channel status indication module sends CRS and COL signals to the indication insertion module at a rate compatible with the indication insertion module. Thus, when the indication insertion module receives the CRS and COL signals, it obtains the sequence to be encoded based on the received byte signal, indication signal, management signal, CRS, and COL signals. For the improved SGMII in the MAC chip, the indication extraction module obtains the CRS and COL signals from the sequence to be encoded and sends them to the channel status module. The channel status module outputs the CRS and COL signals.

[0171] Whether it is the improved SGMII in the MAC chip or the improved SGMII in the PHY chip, the clock division module is used to obtain the frequency of the clock used for negotiation and send the frequency to the auto-negotiation module. The auto-negotiation module is used to negotiate the clock used to transmit the code block.

[0172] The embodiment of the present application also provides an encoding device. Figure 16 is a schematic diagram of the structure of an encoding device provided by an embodiment of the present application. The device is applied to the first chip. Based on the multiple modules shown in Figure 16, the device can perform all or part of the operations in the encoding method shown in Figure 4. It should be understood that the device may include more additional modules than the modules shown or omit some of the modules shown therein, and the embodiment of the present application is not limited to this. As shown in Figure 16, the device includes a merging module 1601, an encoding module 1602, and a sending module 1603.

[0173] Among them, the merging module 1601 is used to merge the first signal of n periods to be transmitted to obtain a second signal, where the first signal of n periods includes at least one of data information or control information, and n is a positive integer greater than 1; the encoding module 1602 is used to encode the second signal to obtain at least one code block; the sending module 1603 is used to send at least one code block through a serial channel, and the serial channel is used to connect the MAC layer and the PHY.

[0174] In a possible implementation, the encoding module 1602 is configured to encode the second signal and the third signal to be transmitted to obtain multiple code blocks, where the third signal includes management information; and the sending module 1603 is configured to send the multiple code blocks through a serial channel.

[0175] In a possible implementation, the at least one code block includes a first code block and a second code block, the first code block includes the second signal, and the second code block includes a type indicator, where the type indicator is used to indicate a signal type included in the second signal.

[0176] In a possible implementation, the multiple code blocks include a first code block and a second code block, the first code block includes the second signal, the second code block includes the third signal, and the type of the first code block is used to indicate the type of signal included in the second signal.

[0177] In one possible implementation, the multiple code blocks include a first code block and a second code block, the first code block includes a second signal, the second code block includes a third signal, the first signal is related to an Ethernet frame, an Ethernet frame is associated with at least one first code block among the multiple code blocks, and the second code block is transmitted before or after the first code block associated with the same Ethernet frame.

[0178] In one possible implementation, the multiple code blocks include a first code block and a second code block, the first code block includes a second signal, the second code block includes a third signal, the first signal is related to an Ethernet frame, an Ethernet frame is associated with at least one first code block among the multiple code blocks, the at least one first code block includes a first code block associated with a preamble of the Ethernet frame, and the second code block is used to replace the first code block associated with the preamble for transmission.

[0179] In a possible implementation, the sending module 1603 is configured to negotiate a clock for transmitting at least one code block with a chip at the other end of the serial channel; and send the at least one code block through the serial channel according to the negotiated clock.

[0180] In one possible implementation, at least one code block includes multiple first code blocks and multiple second code blocks, and the frequency of the clock used for negotiation is determined based on the transmission rate corresponding to the data information in the first signal, the number of first code blocks, the number of second code blocks, and the coding efficiency of the coding method.

[0181] In a possible implementation, the first chip is a PHY chip, and the third signal further includes physical layer channel status indication information.

[0182] In a possible implementation, the serial channel is an improved SGMII channel.

[0183] In the device provided in the embodiment of the present application, a second signal is obtained by merging n cycles of the first signal, and the second signal includes a larger number of first signals, that is, the device can convert the first signal with a lower data bit width into a second signal with a higher data bit width. Thus, when the second signal is encoded to obtain at least one code block and at least one code block is transmitted, the number of first signals included in the at least one code block is larger. Compared with the method of transmitting a code block including multiple repeated signals, the efficiency of signal transmission of the device is higher. When the second signal includes multiple types of information, the multiple types of information can be transmitted serially through the same serial channel, and the number of channels required to transmit the multiple types of information is small, and the cost is low.

[0184] When the device also encodes a third signal, the multiple code blocks obtained by encoding can include multiple types of information. When a serial channel for transmitting multiple code blocks is implemented via a single pin or a group of pins, the device can include a relatively small number of pins for implementing the serial channel. When at least one of data information or control information is transmitted via a serial channel, and management information is also transmitted via the same serial channel, since the data information, control information, and management information can be transmitted via the same serial channel, there is no need to transmit the data information, control information, and management information separately via multiple channels, resulting in lower costs for transmitting the data information, control information, and management information.

[0185] Furthermore, the device can negotiate the clock used to transmit code blocks, allowing for a wide variety of clock frequencies and adapting the clock frequency used to transmit code blocks to the chips at both ends of the serial channel. Thus, when code blocks are transmitted according to the negotiated clock, the information system at the other end of the serial channel can receive the code blocks according to the negotiated clock, ensuring reliable code block transmission. When the negotiated clock frequency is low, the device consumes less power when transmitting code blocks.

[0186] The present application also provides a decoding device. Figure 17 is a schematic diagram of the structure of a decoding device provided by an embodiment of the present application. The device is applied to the second chip. Based on the multiple modules shown in Figure 17, the device can perform all or part of the operations in the decoding method shown in Figure 14. It should be understood that the device may include more additional modules than the modules shown or omit some of the modules shown, and the present application does not limit this. As shown in Figure 17, the device includes a receiving module 1701, a decoding module 1702, and a splitting module 1703.

[0187] Among them, the receiving module 1701 is used to receive at least one code block through a serial channel, the at least one code block is obtained by encoding a second signal, the second signal is obtained by merging n periods of the first signal to be transmitted, the n periods of the first signal include at least one of data information or control information, the serial channel is used to connect the MAC layer and the PHY, and n is a positive integer greater than 1; the decoding module 1702 is used to decode the at least one code block to obtain the second signal; the splitting module 1703 is used to split the second signal to obtain n signals.

[0188] In one possible implementation, the receiving module 1701 is used to receive multiple code blocks through a serial channel, where the multiple code blocks are obtained by encoding a second signal and a third signal to be transmitted, where the third signal includes management information; the decoding module 1702 is used to decode the multiple code blocks to obtain the second signal and the third signal.

[0189] In one possible implementation, at least one code block includes a first code block and a second code block, the first code block includes a second signal, and the second code block includes a type indication, where the type indication is used to indicate the signal type included in the second signal; a decoding module 1702 is used to obtain the second signal from the first code block; a splitting module 1703 is used to obtain the signal type included in the second signal based on the type indication included in the second code block; and the second signal is split according to the signal type included in the second signal to obtain n signals.

[0190] In one possible implementation, the multiple code blocks include a first code block and a second code block, the first code block includes a second signal, the second code block includes a third signal, and the type of the first code block is used to indicate the signal type included in the second signal; the splitting module 1703 is used to obtain the signal type included in the second signal according to the type of the first code block; and split the second signal according to the signal type included in the second signal to obtain n signals.

[0191] In one possible implementation, the multiple code blocks include a first code block and a second code block, the first code block includes a second signal, the second code block includes a third signal, the first signal is related to an Ethernet frame, an Ethernet frame is associated with at least one first code block among the multiple code blocks, and the second code block is transmitted before or after the first code block associated with the same Ethernet frame.

[0192] In one possible implementation, the multiple code blocks include a first code block and a second code block, the first code block includes a second signal, the second code block includes a third signal, the first signal is related to an Ethernet frame, an Ethernet frame is associated with at least one first code block among the multiple code blocks, the at least one first code block includes a first code block associated with a preamble of the Ethernet frame, and the second code block is used to replace the first code block associated with the preamble for transmission.

[0193] In a possible implementation, the receiving module 1701 is configured to negotiate with a chip at the other end of a serial channel about a clock for transmitting at least one code block; and receive at least one code block through the serial channel according to the negotiated clock.

[0194] In one possible implementation, at least one code block includes multiple first code blocks and multiple second code blocks, and the frequency of the clock used for negotiation is determined based on the transmission rate corresponding to the data information in the first signal, the number of first code blocks, the number of second code blocks, and the coding efficiency of the coding method.

[0195] In a possible implementation, the second chip is a MAC chip, and the third signal further includes a physical layer channel state indication signal.

[0196] In a possible implementation, the serial channel is an improved SGMII channel.

[0197] In the device provided in the embodiment of the present application, the second signal is obtained by merging n cycles of the first signal, and the second signal includes a larger number of first signals, that is, the device can convert the second signal with a higher data bit width into a first signal with a lower data bit width. In the case of receiving at least one code block obtained by encoding the second signal, the at least one code block includes a larger number of first signals. Compared with the method of receiving a code block including multiple repeated signals, the efficiency of receiving signals by the device is higher. In the case where the second signal includes multiple information, the multiple information can be received serially through the same serial channel, and the number of channels required to receive the multiple information is small, and the cost is low.

[0198] When the device also receives a code block obtained by encoding a third signal, the method can receive multiple types of information. When a serial channel for receiving multiple code blocks is implemented via a single pin or a group of pins, the device can include fewer pins for implementing the serial channel. When at least one of data information or control information is received via a serial channel, and management information is also received via the same serial channel, since the data information, control information, and management information can be received via the same serial channel, there is no need to receive the data information, control information, and management information separately via multiple channels, resulting in lower costs for receiving the data information, control information, and management information.

[0199] Furthermore, the device can negotiate the clock used to receive code blocks, allowing for a wide variety of frequencies and adapting the clock frequency used to receive code blocks to the chips at both ends of the serial channel. The information at the other end of the serial channel can receive code blocks according to the negotiated clock, and the device can also receive code blocks according to the negotiated clock, ensuring reliable code block transmission. When the negotiated clock frequency is low, the device consumes less power when receiving code blocks.

[0200] It should be understood that the devices provided in Figures 16 and 17 above are only illustrated by the division of the above-mentioned functional modules when implementing their functions. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the devices and method embodiments provided in the above embodiments belong to the same concept, and their specific implementation processes are detailed in the method embodiments, which will not be repeated here. In addition, the device provided in Figures 16 or 17 can be a chip or a communication device, and the device provided is, for example, the computer system described below.

[0201] Referring to FIG. 18 , FIG. 18 is a schematic diagram illustrating the structure of a computer system according to an embodiment of the present application. For example, as shown in FIG. 18 , the computer system is computer system 1800. Computer system 1800 may be a network device, a routing device, or a switching device. Computer system 1800 shown in FIG. 18 is configured to execute the encoding method shown in FIG. 4 or the decoding method shown in FIG. 14 . Computer system 1800 is, for example, a server, and may be implemented using a general bus architecture.

[0202] As shown in FIG. 18 , a computer system 1800 includes at least one processor 1801 , a memory 1803 , and at least one communication interface 1804 .

[0203] The processor 1801 is a central processing unit (CPU), a digital signal processor (DSP), a network processor (NP), a graphics processing unit (GPU), a neural-network processing unit (NPU), a data processing unit (DPU), a microprocessor or one or more integrated circuits for implementing the methods provided in the embodiments of the present application. For example, the processor 1801 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. The PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination of the above three. The processor 1801 can be a combination of various logic blocks, modules and circuits that implement or execute the contents disclosed in conjunction with the embodiments of the present application, or a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, and the like.

[0204] Optionally, computer system 1800 also includes a bus. The bus is used to transmit information between the components of computer system 1800. The bus may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, for example. Buses can be categorized as address buses, data buses, control buses, and the like. For ease of illustration, FIG18 shows only one thick line, but this does not imply that there is only one bus or only one type of bus.

[0205] The memory 1803 is, for example, a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, an optical disc storage (including a compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 1803 is, for example, independent and connected to the processor 1801 via a bus. The memory 1803 can also be integrated with the processor 1801.

[0206] The communication interface 1804 uses any transceiver-like device to communicate with other devices or communication networks. The communication network can be Ethernet, a radio access network (RAN), or a wireless local area network (WLAN). The communication interface 1804 can include a wired communication interface or a wireless communication interface. Specifically, the communication interface 1804 can be an Ethernet interface, a fast Ethernet (FE) interface, a gigabit Ethernet (GE) interface, an asynchronous transfer mode (ATM) interface, a WLAN interface, a cellular network communication interface, or a combination thereof. The Ethernet interface can be an optical interface, an electrical interface, or a combination thereof. In the embodiment of the present application, the communication interface 1804 can be used for the computer system 1800 to communicate with other devices.

[0207] In a specific implementation, as an embodiment, the processor 1801 may include one or more CPUs, such as CPU0 and CPU1 shown in FIG18 . Each of these processors may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. The processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0208] In a specific implementation, as an embodiment, the computer system 1800 may include multiple processors, such as processor 1801 and processor 1805 shown in FIG18 . Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). A processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0209] In a specific implementation, as an embodiment, the computer system 1800 may further include an output device and an input device. The output device communicates with the processor 1801 and can display information in a variety of ways. For example, the output device can be a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device communicates with the processor 1801 and can receive user input in a variety of ways. For example, the input device can be a mouse, a keyboard, a touch screen device, or a sensor device.

[0210] In some embodiments, the memory 1803 is used to store program code 1810, and the processor 1801 can execute the program code 1810 stored in the memory 1803. The program code 1810 may include one or more software modules. Alternatively, the processor 1801 itself can also store program code or instructions.

[0211] In a specific embodiment, the computer system 1800 of the embodiment of the present application may include the first chip and / or the second chip in the above-mentioned various method embodiments, and the first chip and / or the second chip may be implemented by the processor 1801 in the computer system 1800.

[0212] The computer system 1800 may also correspond to the apparatus shown in FIG. 16 and FIG. 17 , and each functional module in the apparatus shown in FIG. 16 or FIG. 17 may be implemented by a circuit in the processor 1800 .

[0213] 4 and the decoding method shown in FIG14 are performed by hardware integrated logic circuits in the processor of the computer system 1800. The steps of the method disclosed in the embodiments of the present application can be directly embodied as being executed by a hardware processor.

[0214] Figure 19 is a schematic diagram of the structure of another computer system provided in an embodiment of the present application, and the computer system is used to execute the encoding method shown in Figure 4 and the decoding method shown in Figure 14. Exemplarily, the computer system is a server, and the server may have relatively large differences due to different configurations or performance. The computer system may include one or more processors 1901, and the one or more processors 1901 are used to implement the first chip and / or the second chip in the method embodiment. As shown in Figure 19, the computer system may also include one or more memories 1902, wherein at least one computer program is stored in one or more memories 1902, and at least one computer program is loaded and executed by one or more processors 1901. Exemplarily, the processor 1901 is a CPU. Of course, the computer system may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output. The computer system may also include other components for implementing device functions, which are not described here.

[0215] An embodiment of the present application further provides a communication device, comprising: a transceiver module for performing operations related to reception and / or transmission in the encoding method shown in FIG4 ; a processing module for performing operations other than operations related to reception and / or transmission in the encoding method shown in FIG4 . An embodiment of the present application further provides another communication device, comprising: a transceiver module for performing operations related to reception and / or transmission in the decoding method shown in FIG14 ; a processing module for performing operations other than operations related to reception and / or transmission in the decoding method shown in FIG14 . Optionally, the communication device may be a chip.

[0216] An embodiment of the present application provides a chip, comprising: a MAC layer circuit, the MAC layer circuit being configured to execute the encoding method shown in FIG4 and / or the decoding method shown in FIG14. An embodiment of the present application also provides another chip, comprising: a PHY circuit, the PHY circuit being configured to execute the encoding method shown in FIG4 and / or the decoding method shown in FIG14.

[0217] An embodiment of the present application also provides a communication system, which includes a first chip and a second chip; the first chip is used to execute the encoding method shown in Figure 4, and the second chip is used to execute the decoding method shown in Figure 14.

[0218] It should be understood that the processor may be a CPU, or other general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc. It is worth noting that the processor may be a processor supporting the Advanced Reduced Instruction Set Machine (ARM) architecture.

[0219] Furthermore, in an optional embodiment, if one or more of the aforementioned computer system, communication device, chip, or communication system further includes memory, the memory may include read-only memory and random access memory, and provide instructions and data to the processor. The memory may also include non-volatile random access memory. For example, the memory may also store device type information.

[0220] The memory may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a ROM, a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a RAM, which is used as an external cache. By way of example but not limitation, many forms of RAM are available. For example, static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0221] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When software is used for implementation, it can be implemented in whole or in part in the form of a computer program or computer program product. The computer program or computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function according to the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, computer, server or data center to another website, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrations. The available medium may be a magnetic medium (eg, a floppy disk, a hard disk, a magnetic tape), an optical medium (eg, a digital versatile disc (DVD)), or a semiconductor medium (eg, a solid state disk (SSD)).

[0222] To clearly illustrate the interchangeability of hardware and software, the above description has generally described the steps and components of each embodiment according to their functions. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0223] The computer program code for realizing the method for the embodiment of the application can be written in one or more programming languages. These computer program codes can be provided to the processor of the storage device of general-purpose computer, special-purpose computer or other programmable annotation content, so that the program code, when being executed by the storage device of computer or other programmable annotation content, causes the function / operation specified in the flow chart and / or block diagram to be implemented. The program code can be executed completely on the computer, partially on the computer, as an independent software package, partially on the computer and partially on a remote computer or completely on a remote computer or server.

[0224] In the context of the embodiments of the present application, computer program code or related data may be carried by any suitable carrier to enable a device, apparatus, or processor to perform the various processes and operations described above. Examples of carriers include signals, computer-readable media, and the like. Examples of signals may include electrical, optical, radio, acoustic, or other forms of propagated signals, such as carrier waves, infrared signals, and the like.

[0225] Those skilled in the art will clearly understand that, for the sake of convenience and brevity of description, the specific working processes of the above-described systems, devices, and modules can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0226] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the modules is merely a logical function division. In actual implementation, there may be other division methods, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or modules, or can be electrical, mechanical or other forms of connection.

[0227] The modules described as separate components may or may not be physically separate, and the components shown as modules may or may not be physical modules, that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules may be selected according to actual needs to achieve the purpose of the embodiments of the present application.

[0228] In addition, the functional modules in the various embodiments of the present application may be integrated into a processing module, or each module may exist physically separately, or two or more modules may be integrated into a single module. The above-mentioned integrated modules may be implemented in the form of hardware or software functional modules.

[0229] In this application, the terms "first", "second", etc. are used to distinguish between identical or similar items with substantially the same role and function. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there a limit on the quantity and execution order. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the various examples, a first chip can be referred to as a second chip, and similarly, a second chip can be referred to as a first chip.

[0230] It should also be understood that in the various embodiments of the present application, the size of the serial number of each process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0231] As used herein, the term "at least one" means one or more, and the term "plurality" means two or more. For example, "plurality of code blocks" means two or more code blocks. The terms "system" and "network" are often used interchangeably herein.

[0232] It should be understood that the terminology used in the description of the various examples herein is for the purpose of describing particular examples only and is not intended to be limiting. As used in the description of the various examples and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0233] It will also be understood that the term “comprise” (also known as “includes,” “including,” “comprises,” and / or “comprising”) when used in this specification specifies the presence of stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0234] It should also be understood that, depending on the context, the phrase “if it is determined that…” or “if [stated condition or event] is detected” may be interpreted to mean “upon determining…” or “in response to determining…” or “upon detecting [stated condition or event]” or “in response to detecting [stated condition or event]”.

[0235] It should be understood that determining B based on A does not mean determining B based solely on A. B can also be determined based on A and / or other information.

[0236] It should also be understood that references throughout this specification to "one embodiment," "an embodiment," or "one possible implementation" mean that specific features, structures, or characteristics associated with that embodiment or implementation are included in at least one embodiment of the present application. Therefore, the appearance of "in one embodiment," "in an embodiment," or "one possible implementation" throughout this specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0237] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the principles of the present application should be included in the scope of protection of the present application.

Claims

1. A coding method, characterized in that: The method comprises: The first chip combines n cycles of first signals to be transmitted to obtain a second signal, wherein the n cycles of first signals include at least one of data information or control information, and n is a positive integer greater than 1; The first chip encodes the second signal to obtain at least one code block; The first chip sends the at least one code block through a serial channel, and the serial channel is used to connect a media access control MAC layer and a physical layer PHY.

2. The method according to claim 1, characterized in that The first chip encodes the second signal to obtain at least one code block, including: The first chip encodes the second signal and a third signal to be transmitted to obtain a plurality of code blocks, wherein the third signal includes management information; The first chip sends the at least one code block through a serial channel, including: The first chip sends the multiple code blocks through a serial channel.

3. The method according to claim 1, characterized in that The at least one code block includes a first code block and a second code block, the first code block includes the second signal, the second code block includes a type indicator, and the type indicator is used to indicate a signal type included in the second signal.

4. The method according to claim 2, characterized in that: The plurality of code blocks include a first code block and a second code block, the first code block includes the second signal, the second code block includes the third signal, and a type of the first code block is used to indicate a signal type included in the second signal.

5. The method according to claim 2, characterized in that: The multiple code blocks include a first code block and a second code block, the first code block includes the second signal, the second code block includes the third signal, the first signal is related to an Ethernet frame, an Ethernet frame is associated with at least one first code block among the multiple code blocks, and the second code block is transmitted before or after the first code block associated with the same Ethernet frame.

6. The method according to claim 2, characterized in that The multiple code blocks include a first code block and a second code block, the first code block includes the second signal, the second code block includes the third signal, the first signal is related to an Ethernet frame, an Ethernet frame is associated with at least one first code block among the multiple code blocks, the at least one first code block includes a first code block associated with a preamble of the Ethernet frame, and the second code block is used to replace the first code block associated with the preamble for transmission.

7. The method according to any one of claims 1 to 6, characterized in that: The first chip sends the at least one code block through a serial channel, including: The first chip negotiates with a chip at the other end of the serial channel a clock for transmitting the at least one code block; The first chip sends the at least one code block through the serial channel according to the negotiated clock.

8. The method according to claim 7, characterized in that The at least one code block includes multiple first code blocks and multiple second code blocks, and the frequency of the clock used for negotiation is determined based on the transmission rate corresponding to the data information in the first signal, the number of the first code blocks, the number of the second code blocks, and the coding efficiency of the coding method.

9. The method according to any one of claims 2, 4-6, characterized in that: The first chip is a PHY chip, and the third signal further includes physical layer channel status indication information.

10. The method according to any one of claims 1 to 9, characterized in that: The serial channel is a channel between improved serial gigabit medium independent interfaces SGMII.

11. A decoding method, characterized in that: The method comprises: The second chip receives at least one code block through a serial channel, the at least one code block is obtained by encoding a second signal, the second signal is obtained by combining n cycles of first signals to be transmitted, the n cycles of first signals include at least one of data information or control information, the serial channel is used to connect a media access control MAC layer and a physical layer PHY, and n is a positive integer greater than 1; The second chip decodes the at least one code block to obtain the second signal; The second chip splits the second signal to obtain n signals.

12. The method according to claim 11, characterized in that The second chip receives at least one code block through a serial channel, including: The second chip receives a plurality of code blocks through the serial channel, the plurality of code blocks being obtained by encoding the second signal and a third signal to be transmitted, the third signal including management information; The second chip decodes the at least one code block to obtain the second signal, including: The second chip decodes the multiple code blocks to obtain the second signal and the third signal.

13. The method according to claim 11, characterized in that The at least one code block includes a first code block and a second code block, the first code block includes the second signal, and the second code block includes a type indicator, where the type indicator is used to indicate a signal type included in the second signal; and the second chip decodes the at least one code block to obtain the second signal, including: The second chip acquires the second signal from the first code block; The second chip splits the second signal to obtain n signals, including: The second chip obtains a signal type included in the second signal based on a type indication included in the second code block; The second chip splits the second signal according to signal types included in the second signal to obtain n signals.

14. The method according to claim 12, characterized in that The multiple code blocks include a first code block and a second code block, the first code block includes the second signal, the second code block includes the third signal, and the type of the first code block is used to indicate the type of signal included in the second signal; the second chip splits the second signal to obtain n signals, including: The second chip obtains, according to the type of the first code block, a signal type included in the second signal; The second chip splits the second signal according to signal types included in the second signal to obtain n signals.

15. The method according to claim 12, characterized in that The multiple code blocks include a first code block and a second code block, the first code block includes the second signal, the second code block includes the third signal, the first signal is related to an Ethernet frame, an Ethernet frame is associated with at least one first code block among the multiple code blocks, and the second code block is transmitted before or after the first code block associated with the same Ethernet frame.

16. The method according to claim 12, characterized in that The multiple code blocks include a first code block and a second code block, the first code block includes the second signal, the second code block includes the third signal, the first signal is related to an Ethernet frame, an Ethernet frame is associated with at least one first code block among the multiple code blocks, the at least one first code block includes a first code block associated with a preamble of the Ethernet frame, and the second code block is used to replace the first code block associated with the preamble for transmission.

17. The method according to any one of claims 11 to 16, characterized in that: The second chip receives at least one code block through a serial channel, including: The second chip negotiates with a chip at the other end of the serial channel a clock for transmitting the at least one code block; The second chip receives the at least one code block through the serial channel according to the negotiated clock.

18. The method according to claim 17, characterized in that The at least one code block includes multiple first code blocks and multiple second code blocks, and the frequency of the clock used for negotiation is determined based on the transmission rate corresponding to the data information in the first signal, the number of the first code blocks, the number of the second code blocks, and the coding efficiency of the coding method.

19. The method according to any one of claims 12, 14-16, characterized in that: The second chip is a MAC chip, and the third signal also includes a physical layer channel status indication signal.

20. The method according to any one of claims 11 to 19, characterized in that: The serial channel is a channel between improved serial gigabit medium independent interfaces SGMII.

21. A coding device, characterized in that: The device is applied to a first chip, and the device includes: a merging module, configured to merge n-period first signals to be transmitted to obtain a second signal, wherein the n-period first signals include at least one of data information or control information, and n is a positive integer greater than 1; an encoding module, configured to encode the second signal to obtain at least one code block; The sending module is used to send the at least one code block through a serial channel, and the serial channel is used to connect the media access control MAC layer and the physical layer PHY.

22. The device according to claim 21, characterized in that The encoding module is used to encode the second signal and the third signal to be transmitted to obtain multiple code blocks, and the third signal includes management information; the sending module is used to send the multiple code blocks through a serial channel.

23. The device according to claim 21, characterized in that The at least one code block includes a first code block and a second code block, the first code block includes the second signal, the second code block includes a type indicator, and the type indicator is used to indicate a signal type included in the second signal.

24. The device according to claim 22, characterized in that The plurality of code blocks include a first code block and a second code block, the first code block includes the second signal, the second code block includes the third signal, and a type of the first code block is used to indicate a signal type included in the second signal.

25. The device according to claim 22, characterized in that The multiple code blocks include a first code block and a second code block, the first code block includes the second signal, the second code block includes the third signal, the first signal is related to an Ethernet frame, an Ethernet frame is associated with at least one first code block among the multiple code blocks, and the second code block is transmitted before or after the first code block associated with the same Ethernet frame.

26. The device according to claim 22, characterized in that The multiple code blocks include a first code block and a second code block, the first code block includes the second signal, the second code block includes the third signal, the first signal is related to an Ethernet frame, an Ethernet frame is associated with at least one first code block among the multiple code blocks, the at least one first code block includes a first code block associated with a preamble of the Ethernet frame, and the second code block is used to replace the first code block associated with the preamble for transmission.

27. The device according to any one of claims 21 to 26, characterized in that The sending module is used to negotiate with the chip at the other end of the serial channel about the clock used to transmit the at least one code block; and send the at least one code block through the serial channel according to the negotiated clock.

28. The device according to claim 27, characterized in that The at least one code block includes multiple first code blocks and multiple second code blocks, and the frequency of the clock used for negotiation is determined based on the transmission rate corresponding to the data information in the first signal, the number of the first code blocks, the number of the second code blocks, and the coding efficiency of the coding method.

29. The device according to any one of claims 22, 24-26, characterized in that: The first chip is a PHY chip, and the third signal further includes physical layer channel status indication information.

30. The device according to any one of claims 21 to 29, characterized in that The serial channel is a channel between improved serial gigabit medium independent interfaces SGMII.

31. A decoding device, characterized in that: The device is applied to a second chip, and the device includes: A receiving module, configured to receive at least one code block through a serial channel, wherein the at least one code block is obtained by encoding a second signal, wherein the second signal is obtained by combining n periods of first signals to be transmitted, wherein the n periods of first signals include at least one of data information or control information, wherein the serial channel is used to connect a media access control MAC layer and a physical layer PHY, and wherein n is a positive integer greater than 1; A decoding module, configured to decode the at least one code block to obtain the second signal; The splitting module is used to split the second signal to obtain n signals.

32. The device according to claim 31, characterized in that The receiving module is used to receive multiple code blocks through the serial channel, and the multiple code blocks are obtained by encoding the second signal and a third signal to be transmitted, and the third signal includes management information; the decoding module is used to decode the multiple code blocks to obtain the second signal and the third signal.

33. The device according to claim 31, characterized in that The at least one code block includes a first code block and a second code block, the first code block includes the second signal, and the second code block includes a type indication, wherein the type indication is used to indicate a signal type included in the second signal; the decoding module is used to obtain the second signal from the first code block; the splitting module is used to obtain the signal type included in the second signal based on the type indication included in the second code block; and the second signal is split according to the signal type included in the second signal to obtain n signals.

34. The device according to claim 32, characterized in that The multiple code blocks include a first code block and a second code block, the first code block includes the second signal, the second code block includes the third signal, and the type of the first code block is used to indicate the signal type included in the second signal; the splitting module is used to obtain the signal type included in the second signal according to the type of the first code block; and split the second signal according to the signal type included in the second signal to obtain n signals.

35. The device according to claim 32, characterized in that The multiple code blocks include a first code block and a second code block, the first code block includes the second signal, the second code block includes the third signal, the first signal is related to an Ethernet frame, an Ethernet frame is associated with at least one first code block among the multiple code blocks, and the second code block is transmitted before or after the first code block associated with the same Ethernet frame.

36. The device according to claim 32, characterized in that The multiple code blocks include a first code block and a second code block, the first code block includes the second signal, the second code block includes the third signal, the first signal is related to an Ethernet frame, an Ethernet frame is associated with at least one first code block among the multiple code blocks, the at least one first code block includes a first code block associated with a preamble of the Ethernet frame, and the second code block is used to replace the first code block associated with the preamble for transmission.

37. The device according to any one of claims 31 to 36, characterized in that The receiving module is used to negotiate with the chip at the other end of the serial channel about the clock used to transmit the at least one code block; and receive the at least one code block through the serial channel according to the negotiated clock.

38. The device according to claim 37, characterized in that The at least one code block includes multiple first code blocks and multiple second code blocks, and the frequency of the clock used for negotiation is determined based on the transmission rate corresponding to the data information in the first signal, the number of the first code blocks, the number of the second code blocks, and the coding efficiency of the coding method.

39. The device according to any one of claims 32, 34-36, characterized in that The second chip is a MAC chip, and the third signal also includes a physical layer channel status indication signal.

40. The device according to any one of claims 31 to 39, characterized in that The serial channel is a channel between improved serial gigabit medium independent interfaces SGMII.

41. A chip, characterized in that: The chip comprises: a media access control MAC layer circuit, wherein the MAC layer circuit is used to execute the encoding method as described in any one of claims 1-10, or the decoding method as described in any one of claims 11-20.

42. A chip, characterized in that: The chip comprises: a physical layer PHY circuit, and the PHY circuit is used to execute the encoding method as described in any one of claims 1-10, or the decoding method as described in any one of claims 11-20.

43. A communication system, characterized in that: The communication system comprises a first chip and a second chip, wherein the first chip is used to execute the encoding method as described in any one of claims 1 to 10, and the second chip is used to execute the decoding method as described in any one of claims 11 to 20.

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