Methods and systems for adjustable-depth circuit for controlled-not gate

Abstract

The invention relates to methods and systems for polylogarithmic-depth controlled-NOT gate implementation in quantum circuits and computers and controlled-NOT gate thereof

Description

Methods and systems for adjustable-depth circuit for controlled-NOT gate implementation in quantum circuits and computers and controlled-NOT gate thereof. Field of the invention

[0001] The present invention relates to the field of quantum computers. In particular, the invention relates to the field of controlled-NOT gate (CnX gate) implementation in quantum circuits and computers. Description of Related Art

[0002] Quantum computing is a rapidly improving technology that employs the laws of quantum mechanics to solve specific problems which are too complex for classical computers.

[0003] In the past three decades, quantum algorithms promising an exponential speedup over their classical counterparts have been designed. The advantages of these algorithms over their classical counterparts stem from the peculiar properties of superposition and entanglement of the quantum bits (qubits). These properties enable to manipulate a vast vector of qubit states using basic operations that act on either one or two qubits. The question of decomposing efficiently any n-qubit operation into a reasonable number of primitive single- and two-qubit operations is one of the major challenges in quantum computing. In this context, multi-controlled operations act as building blocks of many prevalent quantum algorithms such as qubitisation within the quantum singular value transformation, which have immediate repercussions on Hamiltonian simulation, quantum search and quantum phase estimation methods. For this reason, achieving more effective decompositions of multi-controlled operations has the potential to bring about significant enhancements in quantum algorithms, impacting various fields such as quantum chemistry, specifically in estimating ground state energy, physics for the simulation of quantum systems, engineering for solving partial differential equations, quantum machine learning, and finance.

[0004] This non-trivial challenge and the quest for optimal solutions has been an active and ongoing research focus for decades. In 1995, Barenco et al. proposed several linear depth constructions of multi-controlled NOT (MCX) gates (also known as n-Toffoli gates, multi-controlled Toffoli, generalised-Toffoli gates, multicontrolled X or n-controlled NOTgates). All these linear depth constructions used ancilla qubits or relied on an efficient approximation, while the first ancilla-free exact decomposition has a quadratic depth. Years later, exact implementations of controlled-NOT gates with linear depth and quadratic size were proposed. It is only in 2015 that Craig Gidney published a pedagogical blogpost describing an exact linear size decomposition without ancilla qubits. Even though his method was linear, its depth leading coefficient is large compared to that of other methods. Still, this one-of-a-kind method was used in subsequent work. In 2017, a logarithmic-depth controlled-NOT gate using as many zeroed ancilla qubits as control qubits was presented. Such finding motivated the search for a trade-off between the number of ancilla and the circuit depth. Computational approaches have been implemented, suggesting that any zeroed ancilla qubit could be used to reduce the circuit depth of controlled operations. Recently, Orts et al. provided a review of the 2022 state-of- the-art methods for MCX.

[0005] Every controlled-NOT decomposition method aims at optimising certain metrics such as circuit size, circuit depth, or ancilla count. In this context, a precise distinction can be made between borrowed ancilla qubits, qubits whose state is unchanged by an operation, and zeroed ancilla qubits which are initialised to a known state before the computation and disentangled at the end of the computation. Zeroed ancilla qubits are typically more efficient at reducing circuit depth but are also more constraining. Borrowed ancilla qubits are more constraining but have the advantage to be available more often during computations: operations that do not impact the entire system can utilise unaffected wires as borrowed qubits.

[0006] There is still a need for new methods and quantum circuit focusing on circuit depth, the metric associated to quantum algorithmic runtime, and ancilla qubit count, which roughly speaking is correlated to the amount of memory available during the computation. Summary of the invention

[0007] The following sets forth a simplified summary of selected aspects, embodiments and examples of the present invention for the purpose of providing a basic understanding of the invention. However, the summary does not constitute an extensive overview of all the aspects, embodiments and examples of the invention. The sole purpose of the summary is to present selected aspects, embodiments and examples of the invention in a concise form as an introduction to the more detailed description of the aspects, embodiments and examples of the invention that follow the summary.

[0008] The invention relates to a computer-implemented method for implementing a CnX gate (Controlledn-NOT gate) with an overall circuit depth which is polylogarithmic in the number of control qubits, said CnX gate comprising n ≥ 2 control qubits, for example n ≥ 10 control qubits, preferably n ≥ 50 control qubits, more preferably n ≥ 100 control qubits, more preferably n ≥ 500 control qubits and even more preferably n ≥ 1000 control qubits. Preferably, said method providing an adjustable depth circuit using an arbitrary number m ≤ n of ancilla.

[0009] In one aspect, the invention relates to a computer-implemented method for implementing a CnX gate at n control qubits, in a gate-based quantum circuit, said method comprising using a quantum circuit comprising: control registers each comprising control qubits at an initial activation state; one-qubit target register t; said quantum circuit further comprising, or having access to, m zeroed one qubit ancilla, m being smaller than n, preferably m being smaller than n-1; said method comprising: - A step of storing the initial activation state of control registers Riinto a first subset of the m zeroed ancilla a_i; o preferably using a number of multicontrol X gates equal to the number of the zeroed ancilla a_i in the first subset, the number of multicontrol X gates corresponding to the number of control registers Ri; o more preferably using m / 2 multicontrol X gates each controlled by n / (m / 2) qubits; - A step of flipping the one-qubit target when and only when all the first subset ancilla are activated, using a parallelisation method using at least part of the remaining m zeroed ancilla a_i; and - A step of restoring all the qubits which activation state has been modified except the one-qubit target to their initial state.

[0010] The invention aims to overcome the disadvantages of the prior art. In particular, the invention proposes a novel circuit for n control-qubit controlled-NOT gate Cn(X) where for the first time, the overall circuit depth is polylogarithmic in the number of control qubits. In particular, the present invention proposes for the first time a polylogarithmic-depth circuit that can benefit from a further circuit depth reduction by leveraging multiple zeroed ancilla. Furthermore, the polylogarithmic-depth circuit thus benefit from an adjustabledepth circuit using an arbitrary number m ≤ n of ancilla.

[0011] The methods described in the present invention stand out as the only approaches achieving such depth complexities. Such polylogarithmic cost may even be seen as a success in the quest for native arbitrarily controlled single-qubit gates. As such, the present invention has an impact on the internal functioning of the hardware (quantum computer) and can be advantageously combined with specific technical implementation of native controlled single-qubit gates.

[0012] In some implementations, the decomposition can take advantage of a several borrowed or zeroed ancilla qubit, which is made available to each of smaller controlled operations; for example, controlled operations C√n(X). Therefore, a new recursive construction of the controlled-NOT gate appears.

[0013] The invention can find a use with all the method and hardware implicated in CnX gates. For example, the invention can be used in the creation of transformation functions (Oracles) applicable to the majority of quantum algorithms and which exploits quantum properties like superposition and entanglement to process multiple inputs simultaneously. Creating a quantum oracle involves mapping a problem into a quantum circuit. This circuit, when applied to a quantum state, alters it in a way that represents the problem's solution. Using the CnX gates and methods according to the invention, the design of these oracles is simplified, and it harness quantum mechanics' unique properties to offer computational advantages over classical methods and also over quantum methods that are not implementing CnX gates according to the present invention.

[0014] Finally, given that the invention improves the internal functioning of a quantum computer, it makes it possible to improve all the operations that can be executed from a quantum computer and using at least one CnX type gate. For example, the methods according to the invention could be the default decompositions of all solutions for compiling quantum circuits. As such, the invention can be implemented in all commonly used libraries (e.g. Qiskit, Azure, Cirq, MyQLM, etc.).

[0015] The majority of quantum circuit will see their cost (e.g. computational cost) decrease when implementing the present invention.

[0016] According to other optional features of the method according to the invention, it can optionally include one or more of the following characteristics alone or in combination:• the step of storing the initial activation state of control registers into a first subset of the m zeroed ancilla a_i comprises performing in parallel m / 2 multicontrol X gates, each controlled by n / (m / 2) control qubits, to store the values of the control qubits into m / 2 ancilla. • the step of flipping the one-qubit target makes use of sequential operations to combine the results of these parallel computations. • the first subset of the m zeroed ancilla a_i comprises half or more of the m zeroed one qubit ancilla. • the parallelisation method is selected among: • A method comprising decomposing the n-qubit Toffoli gate into two-qubit gates and single-qubit gates; or • A method comprising decomposing the n-qubit Toffoli gate into a reduced Toffoli gate modulo phase shift using one or several Clifford gates and one ancillary qubit • most of the control registers Ricomprises √n control Qubits; preferably all registers except the last register of the second control registers which comprises √n control Qubits or less. • it comprises √n or less control register Ri. • it comprises at least 2 control qubits, for example at least 10 control qubits, preferably at least 50 control qubits, more preferably at least 100 control qubits, more preferably at least 500 control qubits, even more preferably at least 1000 control qubits, for example at least 2000 control qubits. • “n” is a perfect square number. • there is one-qubit target register (t). • it comprises a refactorization of the successive steps to set up an induction, preferably the induction dividing the step of applying a NOT function.

[0017] According to another aspect, the invention can also relate to a CnX gate (Controlledn-NOT gate) with an overall circuit depth which is polylogarithmic in the number of control qubits, said CnX gate comprising n ≥ 2 control qubits, preferably more than 5, 10, 50, 100, 1000 control qubits.

[0018] The invention can also relate to a CnX gate (Controlledn-NOT gate), preferably in a quantum circuit, obtainable according to a method of the invention, preferably obtained according to a method of the invention; preferably said CnX gate (Controlledn-NOT gate) having an overall circuit depth which is polylogarithmic in the number of control qubits,said CnX gate comprising n ≥ 2 control qubits, preferably more than 5, 10, 50, 100, 1000 control qubits.

[0019] The invention can also relate to a CnX gate (Controlledn-NOT gate), preferably in a quantum circuit, said CnX gate comprising at least 100 control qubits and having a circuit depth D which is egal to or lower than 5(log(n)log(12)); with n being the number of control qubits in the CnX gate; said CnX gate having access to at least one borrowed ancilla.

[0020] The invention can also relate to a CnX gate (Controlledn-NOT gate), preferably in a quantum circuit, said CnX gate comprising at least 10 control qubits and having a circuit depth D which is egal to or lower than (2.3 log(n) / ⌊m / 2⌋)log(12)); ) +16⌈log(⌊m / 2⌋)⌉+12, preferably equal to or lower than 27 log(n / ⌊m / 2⌋)3 +16⌈log(⌊m / 2⌋)⌉ - 808; with n being the number of control qubits in the CnX gate; said CnX gate having access to at least and m being the number of zeroed one borrowedqubit ancilla to which said CnX gate have access, m being smaller than n, preferably m being smaller than n-1.

[0021] The invention can also relate to a CnX gate (Controlledn-NOT gate), preferably in a quantum circuit, said CnX gate having a circuit depth D which is egal to or lower than 5⌈log(π / ^)⌉ log(n)log(12); with: ^ being an approximation error; preferably if lower than 10−7; n being the number of control qubits in the CnX gate; said CnX gate comprising less than n ancilla, preferably it does not comprise ancilla qubits ; said CnX gate further being arranged to have access to ancilla qubits which are outside the CnX gate but inside said quantum circuit.

[0022] According to other optional features of the CnX gate according to the invention, it can optionally include one or more of the following characteristics alone or in combination: - said CnNOT gate having access to exactly one borrowed ancilla. - said CnNOT gate comprises at least one borrowed ancilla, preferably exactly one borrowed ancilla. - said CnNOT gate does not comprise ancilla (neither borrowed ancilla nor zeroed ancilla). - said CnNOT gate comprising n ≥ 2 control qubits, preferably more than 10, for example more than 50, more preferably more than 100, even more preferably more than 1000, said CnNOT gate comprising:- a first register R0comprising √n control Qubits; - √n-1 registers Ri, each comprising √n control Qubits; - at least one ancilla, preferably only one ancilla, the ancilla being a zeroed ancilla or a borrowed ancilla; and - a one-qubit target register t. - said CnX gate having a circuit depth D which is egal to or lower than 5⌈log(π / ^)⌉ log(n)log(12); with: ^ being an approximation error; preferably if lower than 10−7; n being the number of control qubits in the CnX gate; said CnX gate comprising less than n ancilla, preferably it does not comprise ancilla qubits ; said CnX gate further being arranged to have access to ancilla qubits which are outside the CnX gate but inside said quantum circuit.

[0023] According to another aspect, the invention can also relate to a quantum gate comprising one or several CnX gate according to anyone of the previous claims.

[0024] The invention can also relate to a unitary quantum gate comprising more than n control qubits and one or several CnX gate according to the invention.

[0025] According to another aspect, the invention can also relate to a quantum circuit comprising one or several CnX gate according to the invention.

[0026] According to another aspect, the invention can also relate to a computer configured to implement a method according to the invention.

[0027] In particular, the invention can relate to a quantum computer configured to implement a method according to the invention.

[0028] Preferably, the invention relates to a quantum computer configured to implement one or several CnX gate according to the invention.

[0029] More preferably, a quantum computer according to the invention can be configured to combine the implementation of one or several CnX gate according to the invention or configured to implement a method according to the invention, wherein it is arranged for a single-step generation of N-body entangling interactions (such as a Toffoli gate) between physical qubits, such as trapped atomic ion.

[0030] In particular, the invention can relate to a conventional computer configured toimplement a simulation of one or several CnX gate according to the invention, preferably it is also configured to implement a method according to the invention.

[0031] The invention can relate to computing means for quantum chemical simulations arranged and specifically configured to implement a method, a CnX gate, quantum gate or a quantum circuit of anyone of the previous claims.

[0032] According to another aspect, the invention can also relate to the use of the method, quantum gate or quantum circuit or a CnX gate of anyone of the invention: - To enhances algorithms like Grover's and Shor's, by reducing their complexity, resource requirements and runtime; - In error corrected algorithms such as fault-tolerant algorithms; - In quantum circuit design to simplify and optimize the design of quantum circuits, leading to more efficient quantum computation (compilation) - In simulation driven by quantum systems such as chemistry and materials science simulation, for example during quantum state preparation (using CnX gates); - In quantum communication, during implementation of quantum communication protocols and quantum keys distribution (using CnX gates); - In machine learning assisted by quantum computing during implementation of the features (using CnX gates), resulting in speeding up training and inference processes; - In quantum random access memory systems and processes by reducing the number of qubits and gate operations required; - In cryptography, with an implementation of the CnX gates into quantum circuits for Quantum Key Distribution QKD ensuring secure key exchange or in Cryptanalysis with implementation of these CnX gates into quantum circuits arranged to search for cryptographic keys in unsorted databases; - In drug discovery, with an implementation of the CnX gates during quantum state preparation: and in particular the initialization of quantum states that represent molecular structures; during the implementation of Ansatz in Quantum Algorithms and for example implementing the ansatz in variational algorithms; during execution of quantum circuit simulating the quantum dynamics of chemical reactions, - In climate modelling: with an implementation of the CnX gates to simulate interactions between these variables, like atmospheric dynamics or oceanic currents.Brief description of the drawings

[0033] The foregoing and other objects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which: FIG.1, FIG.2 and FIG.3 are illustrative diagrams of methods according to the invention. FIG.4 is a quantum circuit for a n controlledusing the zeroed ancilla a, FIG.4A where and Ribeing a register of p qubits for each i ∈ {1, ..., p − 1}; FIG.4B where and Riis a register of at most p qubits for each . r is the remainder of the euclidean division ofFIG.5 is a quantum circuit for a n controlledusing a borrowed ancilla a, where and FIG.5B Ribeing a register of p qubits for each i. FIG.5B. Riis a register of at most p qubits for each . r is the remainder of the euclidean divisionFIG.6 is a quantum circuit for a comprising a refactorisation to set up an induction. FIG.7A is a quantum circuit implementing the invention and controlling arbitrary unitary operation with a zeroed ancilla qubit. In particular, decomposition of n-controlled unitary U in terms of (n-1)-controlled gates and single-control gates. FIG.7B is a quantum circuit implementing the invention for controlling arbitrary special unitary operation W. In particular, controlling arbitrary special unitary operation W. Without loss of generality, W = AXBXC for some matrices A;B;C 2 SU(2) such that ABC = I. FIG.8 is a comparison of circuit depths for methods involving a single or no ancilla. FIG.9 is a comparison of circuit depth of a C100(X) as a function of the number of zeroed for methods of the prior art in comparison of our proposition. FIG.10 is a comparison of circuit depth of a C105(X) as a function of the number ofzeroed for a method of the prior art in comparison of our proposition. FIG.11 is a quantum circuit implementing the invention with two controlled-NOT gates in parallel. FIG.12 is a quantum circuit implementing the invention with n controlled-NOT gates in parallel FIG.13 is a quantum circuit implementing the invention for controlling arbitrary unitary operation without ancilla and to finish. FIG.14 is a quantum circuit implementing the invention said quantum circuit being an adjustable-depth quantum circuit for ^^^^^^^^(^^^^) using an arbitrary number ^^^^ ∈ {2, ... ,^^^^} ofzeroed ancillae. FIG.15 is a schematic representation of an embodiment of a computer configured to implement the invention.

[0034] Several aspects of the present invention are disclosed with reference to flow diagrams and / or block diagrams of methods, devices and computer program products according to embodiments of the invention. On the figures, the flow diagrams and / or block diagrams show the architecture, the functionality and possible implementation of devices or systems or methods and computer program products, according to several embodiments of the invention. For this purpose, each box in the flow diagrams or block diagrams may represent a system, a device, a module or code which comprises several executable instructions for implementing the specified logical function(s). In some implementations, the functions associated with the box may appear in a different order than indicated in the drawings. For example, two boxes successively shown, may be executed substantially simultaneously, or boxes may sometimes be executed in the reverse order, depending on the functionality involved. Each box of flow diagrams or block diagrams and combinations of boxes in flow diagrams or block diagrams may be implemented by special systems that perform the specified functions or actions or perform combinations of special equipment and computer instructions. Detailed description

[0035] Hereinafter, we describe the vocabulary associated with the invention, beforepresenting the drawbacks of the prior art, and then finally showing in greater detail how the invention remedies them.

[0036] Conventional computers operate on binary digits that store or represent information in the form of binary states to perform computational and information processing functions. In contrast, quantum computing devices operate on quantum bits (or qubits) that store or represent information as both binary states and superpositions of binary states. A distinction between a quantum and classical computer is that the quantum computer is probabilistic, thus measurements of algorithmic outputs provide a proper solution within a confidence interval. The computation is then repeated until a satisfactory probable certainty of solution can be achieved. A quantum computation uses a qubit as its essential unit instead of a classical computing bit. The qubit (e.g., quantum binary digit) is the quantum-mechanical analog of the classical bit. Whereas classical bits can employ on only one of two basis states (e.g., 0 or 1), qubits can employ superpositions of those basis states, allowing a number of qubits to theoretically hold exponentially more information than a same number of classical bits. General quantum programs require coordination of quantum and classical parts of a computation. One way to think about general quantum programs is to identify processes and abstractions involved in specifying a quantum algorithm, transforming the algorithm into executable form, running an experiment or simulation, and analyzing the results.

[0037] A “quantum circuit” denotes a sequence of gates that can be implemented on a quantum computing mean to formally realize a unitary operator that acts on a given initial quantum state and produces a final quantum state. Circuits can be parametrized via gate parameters such as one or more angles of a single qubit rotation gate. A “gate” denotes an operation on a quantum system that transforms a quantum state. A quantum computing mean can be either on a hardware exploiting quantum physics phenomena for the generation of physical Qubit or on a classical hardware simulating Qubit.

[0038] By “Hamiltonian” (H) or “molecular Hamiltonian” can mean, within the meaning of the invention, an operator that fully defines a quantum system. The lowest eigenstate of such operators can be called a ground state that can be the target of quantum chemistry calculations. A Hamiltonian, written in a computational basis state, can be different for each molecule. “Energy” denotes an expectation value of a Hamiltonian on a given normalized quantum state. Energy can be minimized when the state is the ground state.

[0039] By “process”, “compute“, “determine”, “display”, “extract”, “compare” or morebroadly “executable operation” can mean, within the meaning of the invention, an action performed by a computing device or a processor unless the context indicates otherwise. In this regard, the operations relate to actions and / or processes of a data processing system, for example a computing system or an electronic computing device, which manipulates and transforms the data represented as physical (electronic) quantities in the memories of the computing system or other devices for storing, transmitting or displaying information. In particular, calculation operations are carried out by the processor of the device, the produced data are entered in a corresponding field in a data memory and this field or these fields can be returned to a user for example through a Human Machine Interface formatting such data. These operations may be based on applications or software.

[0040] The terms or expressions “application”, “software”, “program code”, and “executable code” mean any expression, code or notation, of a set of instructions intended to cause a data processing to perform a particular function directly or indirectly (for example after a conversion operation into another code). Exemplary program codes may include, but are not limited to, a subprogram, a function, an executable application, a source code, an object code, a library and / or any other sequence of instructions designed for being performed on a computing system.

[0041] By “processor” is meant, within the meaning of the invention, at least one hardware circuit configured to perform operations according to instructions contained in a code. The hardware circuit may be an integrated circuit. Examples of a processor include, but are not limited to, a central processing unit, a graphics processor, an application- specific integrated circuit (“ASIC” according to Anglo-Saxon terminology), and a programmable logic circuit. A single processor or several other units may be used to implement the invention.

[0042] By “coupled” is meant, within the meaning of the invention, connected, directly or indirectly, with one or more intermediate elements. Two elements may be coupled mechanically, electrically or linked by a communication channel.

[0043] The expression “human-machine interface”, within the meaning of the invention, corresponds to any element allowing a human being to communicate with a computer, in particular and without that list being exhaustive, a keyboard and means allowing in response to the commands entered on the keyboard to perform displays and optionally to select with the mouse or a touchpad item displayed on the screen. Another embodiment isa touch screen for selecting directly on the screen the elements touched by the finger or an object and optionally with the possibility of displaying a virtual keyboard.

[0044] Controlled operations are fundamental building blocks to quantum algorithms. The controlled-NOT gate operates on two qubits: a control and a target. It flips the state of the target qubit if and only if the control qubit is in the state ∣1^ (activated state). When this is extended to n control qubits, the Cn(X) gate acts only when all control qubits are in the ∣1^ state (activated state). This is similar to the AND gate in classical computing, which outputs a true value only when all its inputs are true. However, the quantum gate is more powerful, allowing for operations on super positioned and entangled states, enabling quantum algorithms to perform complex calculations more efficiently than their classical counterparts.

[0045] The Cn(X) gates are foundational in quantum algorithms. They are crucial for creating entanglement, a quantum mechanical resource that is central to the power of quantum computing. In algorithms like Shor's for factoring and Grover's for database search, the Cn(X) gates can be used to entangle qubits, manipulate probabilities, and exploit the superposition principle. This is analogous to how transistors in classical computers are used to manipulate electrical signals for performing calculations.

[0046] Yet, implementing Cn(X) gates in a physical quantum computer, especially as n increases, poses significant challenges. Each added control qubit increases the complexity and the requirement for more precise quantum coherence and error correction. Indeed, as of now, the most efficient decomposition of n control qubits controlled-NOT gates (Cn(X)) into arbitrary single-qubit and CNOT gates exhibits a linear depth Θ(n).

[0047] This is similar to the challenge in classical computing of miniaturizing transistors to pack more into a chip. Overcoming these challenges in quantum computing is essential for realizing machines capable of solving problems that are currently intractable for classical computers.

[0048] In this context, the inventors developed Cn(X) circuits outperforming previous methods with a superpolynomial advantage by achieving a polylogarithmic depth of Θ(log(n)log2(12)) or preferably less; more preferably Θ(log(n)3) or less.

[0049] Furthermore, hereafter are described Cn(X) gates that can be implemented across several distinct computational resource regimes for example employing zero ancilla, one borrowed ancilla, or also approximating with zero ancilla.

[0050] This implementation of controlled operations with an exponential speedup is expected to have an impact on the field of fault-tolerant quantum computing both on the hardware operation part and on the improvement of the application of quantum computing in a multitude of areas.

[0051] As it will be described in the example, the invention overcome the challenges of depth when decomposition of n control qubits controlled-NOT gates (Cn(X)) faced by the classical methods.

[0052] Hence, according to a first aspect, the invention relates to a computer- implemented method for implementing a CnX gate (Controlledn-NOT gate) with an overall circuit depth which is polylogarithmic in the number of control qubits, said CnX gate comprising n ≥ 2 control qubits.

[0053] To anticipate applications on noisy quantum machines, the inventors developed a method to minimize circuit depth of CnX gates. The advantage of this invention in terms of performance of the computational means becomes stronger and stronger as the number of qubits increases. Hence in a preferred embodiment, the number of control qubits controlled by the CnX gate (n) is at least 10. In a more preferred embodiment, it is at least 50. In a more preferred embodiment, it is at least 100. In a more preferred embodiment, it is at least 500. In a more preferred embodiment, it is at least 1000.

[0054] Hence, a CnX gate in a gate-based quantum circuit according to the invention comprises at least 2 control qubits, for example at least 10 control qubits, preferably at least 50 control qubits, more preferably at least 100 control qubits, more preferably at least 500 control qubits, even more preferably at least 1000 control qubits, for example at least 2000 control qubits.

[0055] Advantageously, the number of control qubits “n” is a perfect square number.

[0056] Preferably, the computer implementing the invention comprises quantum computational means. The computer can be a Hybrid Quantum / classical computing means. Also, the computer implementing the invention, such as the method of the invention can comprise hardware equipment that are physically distant but connected by a communication network. The quantum computational means can be quantum hardware or classical hardware configured to simulate quantum computing.

[0057] The invention can be used when implemented in conventional computer, in quantum computing hardware and in hybrid system combining quantum computing hardware and conventional computer hardware.

[0058] The quantum hardware can for example be selected among quantum computers based on trapped ions, superconducting quantum computers, neutral atoms in optical lattices, quantum dot computer spin-based or spatial-based, Bose-Einstein condensate- based quantum computer, quantum wells computers, nuclear magnetic resonance quantum computer, cavity quantum electrodynamics, optical quantum computer, or diamond-based quantum computer.

[0059] In a method 100 according to the invention, it can comprise using a quantum circuit comprising: control registers Rieach comprising control qubits at an initial activation state; and one-qubit target register t.

[0060] Advantageously, the quantum circuit further comprises, or has access to, m zeroed one qubit ancilla, m being smaller than n, preferably m being smaller than n-1;

[0061] The ancilla qubit can also be outside the CnX gate but within the quantum circuit implementing the gate.

[0062] A CnX gate can comprises √n+1 or less control registers Ri.

[0063] Preferably, most of the control registers Ricomprises √n control Qubits or less; more preferably all registers except the last register of the second control registers comprises √n control Qubits or less. In an embodiment, the second control registers Ri. comprise at most √n+1 control Qubits.

[0064] The method 100 can comprise a step of storing 110 the initial activation state of control registers Riinto a first subset of the m zeroed ancilla a_i. Preferably this step is using a number of multicontrol X gates equal to the number of the zeroed ancilla a_i in the first subset. More preferably, the number of multicontrol X gates corresponds to the number of control registers Ri. More preferably this step is using a using m / 2 multicontrol X gates each controlled by n / (m / 2) qubits.

[0065] The method can comprise a step of flipping 120 the one-qubit target when and only when all the first subset ancilla a_i are activated, using a parallelisation method using at least part of the remaining m zeroed ancilla.

[0066] Advantageously, there is the same number of controls here as zero, so this makes it possible to achieve a polylogarithmic depth. Part (such as half) of the zeroed ancilla can be used in a parallelization method, such as He et al. method. The other part can be used in relation with the same number of control registers.

[0067] The method can comprise a step of restoring 130 all the qubits which activation state has been modified except the one-qubit target to their initial state.

[0068] Preferably, the step of storing 110 the initial activation state of control registers R_i into a first subset of the m zeroed ancilla a_i comprises performing in parallel m / 2 multicontrol X gates. More preferably, further each m / 2 multicontrol X gates are controlled by n / (m / 2) control qubits. This will store the values of the control qubits into m / 2 ancilla.

[0069] Preferably, the step of flipping 120 the one-qubit target makes use of sequential operations to combine the results of these parallel computations.

[0070] Preferably, the first subset of the m zeroed ancilla a_i comprises half or more of the m zeroed one qubit ancilla.

[0071] Preferably, the parallelisation method comprises decomposing the n-qubit Toffoli gate into two-qubit gates and single-qubit gates.

[0072] Preferably, the parallelisation method comprises decomposing the n-qubit Toffoli gate into a reduced Toffoli gate modulo phase shift using one or several Clifford gates. More preferably, the parallelisation method comprises decomposing the n-qubit Toffoli gate into a reduced Toffoli gate modulo phase shift using one or several Clifford gates and one ancillary qubit.

[0073] In another embodiment, as illustrated in the figure, in a method 100 according to the invention, it can comprise using a quantum circuit comprising: a first control register R0comprising control Qubits at an initial activation state; at least one second control register Ri+1at an initial activation state; and one-qubit target register t.

[0074] Advantageously, the quantum circuit can further comprise or have access to at least one ancilla qubit (a).

[0075] The at least one ancilla qubit (a) can be a zeroed ancilla or a borrowed ancilla.

[0076] In particular, the ancilla qubit can be in the CnX gate. The ancilla qubit can also be outside the CnX gate but within the quantum circuit implementing the gate.

[0077] The first control register can comprise a number of control Qubits qithat is at least egal to the number of second control register Ri. In a preferred embodiment, there are always more than b−1 qubits in register R0.

[0078] In some embodiments, the first control register R0can comprise a first subset control register R0acomprising √n - 1 control Qubits numbered i from 0 to √n-2 and a second subset control register R0bcomprising one control Qubit. In particular, during the step of storing 110, it is the activation state of the control Qubits of the control register R0awhich are stored in the at least one ancilla qubit (a).

[0079] A CnX gate can comprises √n or less second control register Ri.

[0080] Preferably, most of the second control registers Ricomprises √n control Qubits; more preferably all registers except the last register of the second control registers comprises √n control Qubits or less. In a preferred embodiment, the second control registers Ri. comprise at most √n+1 control Qubits.

[0081] Preferably, the first control register R0can comprise √n control Qubits, the quantum circuit can comprise √n -1 second control register, and each second control register comprise √n control Qubits.

[0082] As it is understood from the description and the example, a CnX gate can be implemented as such that it does not use all the control Qubits of the first control register or of the second control register.

[0083] In an embodiment, as illustrated in the figures 1 and 2, the computer-implemented method can comprise the following steps: a step of flipping at least one ancilla qubit (a) when the initial activation state of the control qubit (qi) of register R0is an active state; a step of applying 210a, for each second register Ri+1from i=0, a NOT function to each of the control Qubit (qi) of the first control register R0when the initial activation state of all the control qubits of the second register Ri+1is an active state; a step of flipping 230 the one-qubit target register (t) when the initial activation state of the first control qubit (qi) of register R0is an active state, and the initial activation state of thesecond control qubits of register Ri+1is an active state; a step of setting the activation values of the control Qubit (qi) of the first control register R0at their initial activation state.

[0084] A method according to the invention can comprise a step of flipping at least one ancilla qubit (a) when and only when the initial activation state of the control qubits (qi) of first control register R0is an active state. In particular, when and only when the initial activation state of all the control qubits (qi) of register R0are an active state.

[0085] A method according to the invention can comprise a step of applying a NOT function to each of the control Qubit (qi) of the first control register R0when the initial activation state of all the control qubits of the second register Ri+1is an active state.

[0086] This step is preferably applied for each second register Ri+1from i=0 to the last second register Ri+1.

[0087] A method according to the invention can comprise a step of flipping the one-qubit target register (t) when the initial activation state of the first control qubit (qi) of register R0is an active state, and the initial activation state of the second control qubits of register Ri+1is an active state.

[0088] This step can correspond or be substituted by a step of flipping (210b) the at least one one-qubit target register (t) when and only when the at least one ancilla qubit has been flipped and the control Qubits (qi) of the first control register R0corresponding to the second registers have been flipped.

[0089] In some embodiments, the first register R0will comprise control qubit (qi) that are not used in this step (or more in other steps) as there is more control qubit (qi) in the first control Register R0than the number of second control register Ri+1.

[0090] Preferably, the step of flipping the one-qubit target register (t) is done when the at least one ancilla qubit has been flipped and the control Qubits (qi) of the first control register R0corresponding to the second registers have been flipped.

[0091] A method according to the invention can comprise a step of setting the activation values of the control Qubit (qi) of the first control register R0at their initial activation state.

[0092] This step can preferably comprise also setting the activation values of the at least one ancilla qubit (a) at their initial activation state.

[0093] In some embodiments, the at least one ancilla qubit (a) is at least one zeroed ancilla. For example, the at least one zeroed ancilla qubit (a) can be one zeroed ancilla.

[0094] In particular, when the at least one ancilla qubit (a) is at least one zeroed ancilla, the method can further comprise a step of storing (210) the activation state of the control Qubits of the control register R0in the zeroed ancilla.

[0095] Also, the step of flipping can comprise the flipping of the one-qubit target register (t) if the cumulative conditions are met: the ancilla qubit (a) in an active state and the control Qubit (qi) is in an inactive state.

[0096] Preferably, during the step of applying (220) a NOT function, the state of control Qubit (qi) of the first control register is changed from 1 to 0 when all the control qubits of the second control register Ri+1are in an active state.

[0097] The invention can also relate to a method for implementing a CnX gate, comprising n ≥ 2 control qubits, in a gate-based quantum circuit, said CnX gate comprising or having access to at least one borrowed ancilla qubit (a).

[0098] The gate-based quantum circuit can comprise a first control register R0comprising √n control Qubits at an initial activation state; √n-1 control registers Ri, each comprising √n control Qubits; at least one ancilla qubit (a), preferably at least one borrowed ancilla qubit (a), preferably only one borrowed ancilla; and a least one one-qubit target register (t); preferably a one-qubit target register (t).

[0099] As illustrated in the figure 3, a method 300 according to the invention can comprise a step of flipping 320 the at least one ancilla qubit, a step of flipping 340 the least one one-qubit target register t if conditions are met; a step of setting 360 the activation values of the at least one ancilla qubit (a) at their initial activation state; a step of flipping 380 the least one one-qubit target register t if conditions are met; and a step of flipping the least one one-qubit target register t if conditions are met.

[0100] Preferably, the step of flipping the at least one ancilla qubit if the cumulative conditions are met: the control Qubit qiof R0ais in an inactive state, the control qubits of register Ri+1are in an active state, and the control Qubit of R0bis in an active state inverse.

[0101] Preferably, the step of flipping the least one one-qubit target register (t) if the cumulative conditions are met: the at least one ancilla qubit (a) is in an active state, and the control Qubit qiof R0ais in an active state.

[0102] Preferably, the step of setting the activation values of the at least one ancilla qubit (a) at their initial activation state.

[0103] Preferably, the step of flipping the least one one-qubit target register (t) if the cumulative conditions are met: the at least one ancilla qubit (a) is in an active state, and the control Qubit qiof R0ais in an inactive state the control qubits of register Ri+1are in an active state.

[0104] In the borrowed ancilla use, where the registers Riand Ri+1are processed alternately, we can also associate a 'local' ancilla qubit with each operation. We can then display an operation of the same form as the initial CnX, but of reduced size.

[0105] Preferably, in a method according to the invention when the at least one ancilla qubit (a) is an at least one borrowed ancilla, the method can comprise a repetition of the sequence the following steps: -A step of applying, for each second register Ri+1 from i=0, a NOT function to each ofthe control Qubit (qi) of the first control register R0when (and only when) the initial activation state of all the control qubits of the second register Ri+1is an active state; - A step of flipping the least one one-qubit target register (t) when and only when: o the at least one ancilla qubit has been flipped; and o the control Qubits (qi) of the first control register R0corresponding to the second registers have been flipped.

[0106] For some quantum gates, the implementation of a method according to the invention can further reduce the depth.

[0107] It is for example the case for unitary quantum gate, such as Cn(U), having one target qubit.

[0108] In such unitary gate, the invention can advantageously be implemented without ancilla if we consider the operation as a whole. Indeed, in a method according to the invention, one or several ancilla are created from scratch for smaller operations making up the overall gate.

[0109] In particular, the n+1 qubit gate does not use more than n+1 qubits. This is a good alternative to prior art where using a borrowed ancilla where the gate will uses n+2 qubits for example.

[0110] For example, the figure 6 illustrate a quantum circuit for a comprising a refactorisation to set up an induction. The operations which are boxed together denote a set comprised of a control register of size p, a target qubit, and a borrowed ancilla qubit. Such controlled operation has the exact same structure as the larger problem. Moreover,the FIG.11 is a quantum circuit implementing the invention with two controlled-NOT gates in parallel and the FIG.12 is a quantum circuit implementing the invention with n controlled-NOT gates in parallel.

[0111] Preferably, a method according to the invention can comprise a refactorization of the successive steps to set up an induction. Hence, the solution to the implementation of this particular gate depends on solutions to smaller instances of this problem.

[0112] More preferably, the induction can comprise dividing the step of applying a NOT function to each of the control Qubits (qi) of the first control register R0.

[0113] During the step of applying a NOT function to each of the control Qubits qiof the first control register R0, the control Qubits qican be divided into at least two subsets, where the control qubits qiof register R0are used successively as qubits for storing the activation states of control qubits of a first set of second register Ri+1and as borrowed ancilla qubits for use during the storing of activation state of a second set of the second register Ri+1, or vice versa.

[0114] In other words, the invention can relate to a method for implementing an unitary quantum gate, said implementation comprising at least one CnX operation, said CnX operation leaving at least one qubit at rest; said method comprising the implementation of a method for implementing a CnX gate according to the invention wherein the borrowed ancilla is the at least one qubit left at rest.

[0115] In other words, the invention can relate to a method for implementing a unitary quantum gate, said implementation comprising at least one CnX operation, said CnX operation leaving one qubit at rest; said method comprising the implementation of a method for implementing a CnX gate according to the invention wherein the borrowed ancilla is the one qubit left at rest.

[0116] In other words, the invention can relate to a method for implementing a unitaryquantum gate, said implementation comprising at least one CnX operation, said CnXoperation leaving several qubits at rest; said method comprising the implementation of a method for implementing a CnX gate according to the invention wherein the at least one borrowed ancilla is the several qubits left at rest.

[0117] Advantageously, the method for implementing a CnU according to the invention can comprise a step of flipping the activation state of the borrowed ancilla as a function of the activation states of the control qubits of a control register.

[0118] According to another aspect, the invention can also relate to a CnX gate(Controlledn-NOT gate) with an overall circuit depth which is polylogarithmic in the number of control qubits, said CnX gate comprising n ≥ 2 control qubits, preferably more than 5, 10, 50, 100, 1000 control qubits.

[0119] A CnX gate (Controlledn-NOT gate) with an overall circuit depth which is polylogarithmic in the number of control qubits, said CnX gate comprising n ≥ 2 control qubits, preferably more than 5, 10, 50, 100, 500, 1000 control qubits.

[0120] A CnX gate (Controlledn-NOT gate) obtainable according to anyone of the previous method claims, preferably obtained according to anyone of the previous method claims.

[0121] A CnX gate (Controlledn-NOT gate) in a quantum circuit, said CnX gate having a circuit depth D which is egal to or lower than log(n / ⌊m / 2⌋)log(12)+ log(⌊m / 2⌋); said CnX gate comprising less than n ancilla, preferably it does not comprise ancilla qubits ; said CnX gate further being arranged to have access to m zeroed one qubit ancilla, m being smaller than n, preferably m being smaller than n-1.

[0122] A CnX gate (Controlledn-NOT gate), preferably in a quantum circuit, said CnX gate comprising at least 100 control qubits and having a circuit depth D which is egal to or lower than 5(log(n)log(12)); with n being the number of control qubits in the CnX gate; said CnX gate having access to at least one borrowed ancilla.

[0123] A CnX gate (Controlledn-NOT gate), preferably in a quantum circuit, said CnX gate comprising at least 10 control qubits and having a circuit depth D which is equal to or lower than 2.3 log(n / ⌊m / 2⌋)log(12)+16⌈log(⌊m / 2⌋)⌉+12, preferably equal to or lower than 27 log(n / ⌊m / 2⌋)3 +16⌈log(⌊m / 2⌋)⌉ - 808; with n being the number of control qubits in the CnX gate and m being the number of zeroed one qubit ancilla to which said CnX gate have access, m being smaller than n, preferably m being smaller than n-1.

[0124] A CnX gate (Controlledn-NOT gate), preferably in a quantum circuit, according to claim 20 or 21, wherein said CnNOT gate having access to exactly one borrowed ancilla.

[0125] A CnX gate (Controlledn-NOT gate), preferably in a quantum circuit, according to claim 20 or 21, wherein said CnNOT gate comprise at least one borrowed ancilla, preferably exactly one borrowed ancilla.

[0126] A CnX gate (Controlledn-NOT gate) in a quantum circuit according to claim 20 or 21, said CnX gate comprising at least 1000 control qubits and having a circuit depth Dwhich is egal to or lower than 5⌈log(π / ^)⌉ log(n)log(12); with: ^ being an approximation error; preferably if lower than 10−7; n being the number of control qubits in the CnX gate; said CnX gate comprising less than n ancilla, preferably it does not comprise ancilla qubits ; said CnX gate further being arranged to have access to ancilla qubits which are outside the CnX gate but inside said quantum circuit.

[0127] A CnX gate (Controlledn-NOT gate) according to the previous claim, wherein said CnNOT gate does not comprise ancilla (neither borrowed ancilla nor zeroed ancilla).

[0128] A CnX gate (Controlledn-NOT gate), in a quantum circuit, said CnNOT gate comprising n ≥ 2 control qubits, preferably more than 10, for example more than 50, more preferably more than 100, even more preferably more than 1000, said CnNOT gate comprising: a first register R0 comprising √n control Qubits; √n-1 registers Ri, each comprising √n control Qubits; at least one ancilla, preferably only one ancilla, the ancilla being a zeroed ancilla or a borrowed ancilla; and a one-qubit target register.

[0129] According to another aspect, the invention can also relate to a quantum gate comprising one or several CnX gate according to the invention. For example, it can relate to a unitary quantum gate comprising more than n control qubits and one or several CnX gate according to the invention.

[0130] According to another aspect, the invention can also relate to a quantum circuit comprising one or several CnX gate according to the invention.

[0131] For example, the invention can relate to a quantum circuit for quantum chemical simulation. In particular, the quantum circuit can be specifically configured for quantum chemical simulation.

[0132] In particular, the invention relates to a quantum circuit obtainable, preferably obtained, by a method according to the invention. Preferably, the invention relates to a quantum circuit for quantum chemical simulation.

[0133] According to another aspect, the invention can also relate to a computer configured to implement a method according to the invention.

[0134] In particular, it can relate to a quantum computer configured to implement a method according to the invention. Preferably, it can relate to a quantum computer configured to implement one or several CnX gate according to the invention.

[0135] For example, a quantum computer according to the invention can be configured to combine the implementation of one or several CnX gate according to the invention or configured to implement a method according to the invention, wherein it is arranged for a single-step generation of N-body entangling interactions (such as a Toffoli gate) between physical qubits, such as trapped atomic ion.

[0136] In particular, it can relate to a conventional computer configured to implement a simulation of one or several CnX gate according to the invention, preferably it is also configured to implement a method according to the invention.

[0137] Also, it can relate to computing means for quantum chemical simulations arranged and specifically configured to implement a method, a CnX gate, quantum gate or a quantum circuit of anyone of the previous claims.

[0138] In another aspect, as illustrated in the figure 15, the invention relates to quantum computing means 10, for example said quantum computing means 10 being configured for quantum chemical simulations. In particular, the quantum computing means comprise a quantum circuit 11 for quantum chemical simulation obtainable, preferably obtained, by a method according to the invention.

[0139] The invention quantum computing means 10 can be integrated in a computing system 1 as described hereafter. Also, the computer implemented methods according to the invention can be implemented on a computing system.

[0140] The computing system 1 can include one or more classical binary computers coupled to one or more quantum computers. The one or more conventional binary computers can be configured to receive one or more computing tasks via an input port and to output corresponding computational results via an output port.

[0141] The one or more quantum computers can be configured to execute one or more quantum circuits that are generated from the one or more tasks to generate corresponding output results for the one or more classical binary computers to use to generate the corresponding computational results.

[0142] The figure 15 is a schematic block diagram illustrating various hardware components that may be utilized a computing system according to the invention.

[0143] In particular, as illustrated in figure 15, the computing system 1 can comprises: one or more quantum computing mean, one or more memory components 20, one or more communication interfaces 30; one or more processors 40; and / or one or more user interfaces 50.

[0144] The memory component 20 may comprise any computer readable medium known in the art including, for example, a volatile memory, such as a static random access memory (SRAM) and a dynamic random-access memory (DRAM), and / or a non-volatile memory, such as read-only memory, flash memories, hard disks, optical disks and magnetic tapes. The memory component 20 may include a plurality of instructions or modules or applications for performing various functions. Thus, the memory component 20 can implement routines, programs, or matrix-type data structures. Preferably, the memory component 20 may comprise a medium readable by a computing system in the form of a volatile memory, such as a random-access memory (RAM) and / or a cache memory. The memory component 20, like the other modules, can for example be connected with the other components of the computing system 1 via a communication bus and one or more data carrier interfaces.

[0145] Furthermore, the computing system 1 can also comprise a communication interface 30. The communication interface 30 is preferably configured to transmit data on at least one communication network and may implement a wired or wireless communication. The computing system 1 can communicate with other devices or computing systems and in particular with clients thanks to the communication interface 30. A communication interface 30 according to the invention is in particular configured to exchange data with third-party devices or systems.

[0146] A computing system 1 may comprise one or more processors 40. A processor 40 may be operably coupled to the memory component 20 to execute instructions, encoded in programs, for carrying out the presently disclosed techniques, more particularly to perform the method according to the invention.

[0147] The encoded instructions may be stored in any suitable article of manufacture (such as the memory component 20) that includes at least one tangible non-transitory, computer- readable medium that at least collectively stores these instructions or routines. In this manner, the memory component 20 may contain a set of instructions that, when executed by the processor 40, performs the method of the invention.

[0148] The memory component 20 may include any number of databases or similar storage media that can be queried from the processor 40 as needed to perform the method of the invention.

[0149] These different modules or components are separated in Figure 15, but the invention may provide various types of arrangement, for example a single module cumulating all the functions described here. Similarly, these modules or components may be divided into several electronic boards or gathered on a single electronic board. A computing system 1 according to the invention can be incorporated into a computing system and able to communicate with one or several external devices such as a keyboard, a pointer device, a display, or any device allowing a user to interact with the system 1.

[0150] The computing system 1 may also be configured to communicate with or via a human-machine-interface. Thus, in one embodiment of the present invention, the computing system 1 can be coupled to a human interface machine (HMI). The HMI may be used to allow the transmission of parameters to the devices or conversely make available to the user the values of the data measured or calculated by the device.

[0151] In general, the HMI is communicatively coupled to a processor and includes a user output interface and a user input interface. The user output interface may include an audio and display output interface and various indicators such as visual indicators, audible indicators and haptic indicators. The user input interface may include a keyboard, a mouse, or another navigation module such as a touch screen, a touchpad, a stylus input interface, and a microphone for inputting audible signals such as a user speech, data and commands that can be recognized by the processor.

[0152] Preferably, implementing the invention involves manipulating (e.g. initializing, flipping…) quantum states on a specific quantum processor, like an ion-trap, asuperconducting or a photonic qubit system. Advantageously, CnX gates here would beimplemented using the hardware's native gate set, which may involve decomposing them into simpler gates that the hardware can execute.

[0153] As mentioned, the invention can be used on the one hand in improving the proper functioning of any quantum computer and on the other hand in several field of applications using convention, hybrid or quantum computers.

[0154] For example, the invention can be used to initialize a quantum state to represent a molecular system. In particular, it can set up a quantum state, either a ground state or asuperposition, that corresponds to a particular molecular configuration. The integration of CnX gates according to the invention here can control complex superpositions or entanglement patterns needed for accurately representing the molecular state.

[0155] Also, advantageously in a context of molecular analysis, the present invention can be used to apply molecular Hamiltonian's interactions to a prepared quantum state. It's can be used when for analysing chemical properties and / or simulating molecular dynamics. The invention, in particular the CnX gates, in this context might be used to perform conditional operations based on multiple qubit states, accurately reproducing the intricate interactions within a molecule.

[0156] The proposed invention introduces several polylogarithmic depth constructions for controlled-NOT gates, crucial in quantum computing. Utilizing logical qubits, these constructions demonstrate significant efficiency over traditional linear depth methods. The approach of the invention should provide greater scalability and efficiency in quantum computations.

[0157] The application of this invention to physical qubits can be done using several quantum systems such as superconducting qubits systems, trapped ions qubits systems or photonic qubits systems.

[0158] The implementation can for example comprise initializing the qubits in a quantum register. This can involve cooling the superconducting qubits to their ground state, typically using dilution refrigerators that bring the system close to absolute zero temperature. Superconducting quantum computers often use transmon qubits, which are weakly anharmonic oscillators. Coupling multiple transmon qubits using resonant or dispersive interactions can facilitate the control and target operations of the quantum gate or circuit of the present invention. In particular, applying microwave pulses to the control qubits can bring them into the desired state. These pulses should be calibrated in duration, amplitude, and phase to achieve the correct quantum state. The invention can be further implemented by sequentially activating interactions between the control qubits and the target qubit. This can be achieved using a series of controlled-phase gates, which are native to superconducting systems, followed by single-qubit rotations to transform the CZ into CNOT operations. As superconducting qubits are prone to errors due to decoherence and operational inaccuracies, the invention can benefit from implement quantum error correction protocols, such as a surface code, to detect and correct errors during the gate operation. Finally, the implementation should comprise a measure of the state of thequbits. Superconducting qubit measurements typically involve state-dependent frequency shifts, which are detected using resonant circuits.

[0159] The implementation can for example comprise cooling trapped ions to their motional ground state using laser cooling techniques, such as Doppler cooling followed by sideband cooling. Preferably, implementation of the present invention in a trapped ions can use tightly focused laser beams to individually address ions in the trap. This allows for selective manipulation of control and target ions for the quantum gates or quantum circuit according to the invention. The invention can comprise using a combination of single-ion operations and multi-ion entangling operations. Single-ion operations can be achieved through Rabi oscillations induced by laser pulses while multi-ion entangling operations can be implemented using Mølmer-Sørensen gates, which entangle the internal states of the ions via their collective motional modes. Thus, implementing the invention gates and quantum circuit should comprise by sequentially applying controlled operations across the ion chain, with predetermined timing and synchronization of laser pulses. The eventual issues of decoherence and operational error can be addressed using techniques like dynamical decoupling and sympathetic cooling, where auxiliary ions are used for cooling without disturbing the computational qubits. Finally, the invention can comprise a measure of the state of the ions where ions are illuminated with a laser, and the emitted photons are detected, like in a state-dependent fluorescence.

[0160] The implementation can for example comprise a generation of entangled photon pairs using spontaneous parametric down-conversion or other quantum dot-based sources. In such system, the control and target qubits can be encoded into different degrees of freedom of the photons, such as polarization, path, or orbital angular momentum modes. The invention can implement the gates and quantum circuit of the invention using linear optical elements like beam splitters, phase shifters, and wave plates. These elements manipulate the photonic qubits to perform the necessary quantum gates. For example, photons can be entangled using quantum interference effects at beam splitters and other optical elements. Due to the probabilistic nature of optical quantum computing, the invention can preferably use ancilla photons and post-selection techniques to achieve a higher success rate. Finally, the photons can be detected using single-photon detectors, such as avalanche photodiodes. Preferably, the measurement results are then post-processed to account for any non-deterministic operations.

[0161] According to another aspect, the invention can also relate to the use of the otheraspects of the invention, for example method, quantum gate or quantum circuit or a CnX gate

[0162] The invention can be used to enhances algorithms like Grover's and Shor's, by reducing their complexity, resource requirements and runtime.

[0163] The invention can be used in error corrected algorithms such as fault-tolerant algorithms.

[0164] The invention can be used in quantum circuit design to simplify and optimize the design of quantum circuits, leading to more efficient quantum computation (compilation).

[0165] The invention can be used in simulation driven by quantum systems such as chemistry and materials science simulation, for example during quantum state preparation (using CnX gates).

[0166] The invention can be used in quantum communication, during implementation of quantum communication protocols and quantum keys distribution (using CnX gates).

[0167] The invention can be used in machine learning assisted by quantum computing during implementation of the features (using CnX gates), resulting in speeding up training and inference processes.

[0168] The invention can be used in quantum random access memory systems and processes by reducing the number of qubits and gate operations required.

[0169] The invention can be used in cryptography, with an implementation of the CnX gates into quantum circuits for Quantum Key Distribution QKD ensuring secure key exchange or in Cryptanalysis with implementation of these CnX gates into quantum circuits arranged to search for cryptographic keys in unsorted databases.

[0170] The invention can be used in drug discovery, with an implementation of the CnX gates during quantum state preparation: and in particular the initialization of quantum states that represent molecular structures; during the implementation of Ansatz in Quantum Algorithms and for example implementing the ansatz in variational algorithms; during execution of quantum circuit simulating the quantum dynamics of chemical reactions.

[0171] The invention can be used in climate modelling: with an implementation of the CnX gates to simulate interactions between these variables, like atmospheric dynamics oroceanic currents.

[0172] Thus, in another aspect, the invention relates to one or more computer- readable media storing computer-readable instructions that when executed by one or more quantum computing mean and / or one or more processors cause the one or more processors to perform a method according to the invention. Preferably, the computer- readable media is a tangible non-transitory computer-readable media.

[0173] For the purposes of this disclosure, computer-readable media may include any instrumentality or aggregation of instrumentalities that may retain data and / or instructions for a period of time. Computer-readable media may include, for example, without limitation, storage media such as a direct access storage device (e.g. a hard disk drive or floppy disk drive), a sequential access storage device (e.g. a tape disk drive), compact disk, CD-ROM, DVD, RAM, ROM, electrically erasable programmable read-only memory (EEPROM), and / or flash memory; as well as communications media such as wires, optical fibers, microwaves, radio waves, and other electromagnetic and / or optical carriers; and / or any combination of the foregoing.

[0174] In particular, any combination of one or more computer-readable media may be used. In the context of this document, a computer-readable medium may be any tangible medium that may contain, or store, a program for use by or in connection with an instruction execution system, apparatus, or device. A computer-readable medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared or semiconductor system, apparatus or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include: a hard disk, a random-access memory (RAM).

[0175] Computer program code for performing operations for aspects of the present invention may be written in any combination of one or more programming languages, including an object-oriented programming language such as Java, C ++, or similar, the programming language "C" or similar programming languages, a scripting language such as Perl, or similar languages, and / or functional languages such as Meta Language. Program code can run entirely on a user's computer, partly on a user's computer, and partly on a remote computer or entirely on the computer or remote server. In the latter scenario, the remote computer can be connected to a user's computer by any type of network, including a local area network (LAN) or a wide area network (WAN).

[0176] These computer program instructions may be stored on a computer readable medium that can direct a computing device (i.e. computer, server ...), so that the instructions stored in the computer-readable medium produce a computing device configured to implement the invention.

[0177] For example, a computing device may be a personal computer, a network storage device, or any other suitable device and may vary in size, shape, performance, functionality, and price. The computing device may include random access memory (RAM), one or more processing resources such as a central processing unit (CPU) or hardware or software control logic, ROM, and / or other types of non-volatile memory. Additional components of the computing device may include one or more disk drives, one or more network ports for communication with external devices as well as various input and output (I / O) devices, such as a keyboard, a mouse, and a video display. The computing device may also include one or more buses operable to transmit communications between the various hardware components. EXAMPLE

[0178] The invention is further described in detail by reference to the following experimental examples. These examples are provided for purposes of illustration only and are not intended to be limiting unless otherwise specified. Thus, the invention should in no way be construed as being limited to the following examples, but rather, should be construed to encompass any and all variations which become evident as a result of the teaching provided herein.

[0179] Without further description, it is believed that one of ordinary skill in the art can, using the preceding description and the following illustrative examples, make and utilize the quantum circuit and ansatz of the present invention and practice the claimed methods. The following working examples therefore, specifically point out the preferred embodiments of the present invention, and are not to be construed as limiting in any way the remainder of the disclosure. The first one is an exact decomposition whose depth is affine in the depth of a quadratically smaller controlled operation ^^^^√^^^^(^^^^). The global decomposition takes advantage of a single borrowed ancilla qubit, and each of the smaller controlled operations can be associated to a locally borrowed ancilla. As a consequence, a recursive construction of the multi-controlled NOT gate emerges with an overall polylogarithmiccircuit depth in the number of control qubits ^^^^(log(^^^^)3)and a circuit size ^^^^(^^^^log(^^^^)4). Thesecond method approximates a ^^^^^^^^(^^^^) without ancilla qubits up to an error ^^^^ > 0 with acircuit depth ^^^^�log(^^^^)3log(1 / ^^^^)� and a circuit size ^^^^�^^^^log(^^^^)4log(1 / ^^^^)�. It makes use ofthe decomposition of a ^^^^-controlled ^^^^ gate into (^^^^ − 1)-controlled unitaries, generatingborrowed ancilla qubits that facilitate the application of the first method up to an error ^^^^. The last method provides an adjustable-depth quantum circuit which implements exactly a^^^^^^^^(^^^^) for any given number ^^^^ ≤ ^^^^ of zeroed ancilla qubits. The depth decreases with ^^^^from a polylogarithmic-with-^^^^ scaling to a logarithmic one as: To the best of our knowledge, these methods stand out as the only approaches achieving such depth complexities. In particular, they demonstrate an exponential speedup over previous state-of-the-art (or, more formally, a superpolynomial speedup) and readily improves a wide range of quantum algorithms. This section is subdivided into three parts. The first subsection details the logical steps towards achieving Embodiment 1. This includes a detailed study of the single-zeroed-ancilla case, how it can be turned into a borrowed one and where the recursive decomposition can stem from to yield the polylogarithmic-depth controlled-NOT circuit with a single borrowed ancilla. The Embodiment 2 and Embodiment 3 are described respectively in 2.2 and 2.3. Notations This paragraph gathers the most important definitions that will be used throughout the article. Let ^^^^ ≥ 1 and let be the computational basis of an ^^^^-qubit register ^^^^and ^^^^ be a one-qubit register, the so-called target register. The ^^^^^^^^(^^^^) controlled by ^^^^ with target ^^^^ is the gate defined by equation (1):where IRand ITare the identities on register R and T . The symbol X denotes the Pauli matrix X =|0^ ^1|+|1^ ^0|. More generally, a Cn(U) gate will denote a controlled U gate. If the register R is in state |2n− 1^, it will be termed as active. When one wants to emphasise the control and target registers, one will note ^^^^^^^^^^^^. If R′ is a second qubit register, define the (partial) white control, where Xqdenotes an X gate on white control qubit q. The support of a quantum circuit is the set of qubits on which it does not act like the identity. Ancilla qubits are qubits outside the support of U which may be used during the computation. From now, the function log signifies the logarithm in base 2. All circuit sizes and depths are computed in the basis of arbitrary single-qubit and CNOT gates. A. Embodiment 1: Polylogarithmic-depth gate using one borrowed ancilla The decomposition uses a single zeroed ancilla to reduce the global MCX gate to five layers, each exhibiting the depth of a quadratically smaller operation.The ^^^^-control-qubit register ^^^^ = {^^^^0, ... , ^^^^^^^^−1} is first divided into subregisters.The control register ^^^^ can then be written as the disjoint union ^^^^ = ⋃^^^^^^^^=0 ^^^^^^^^ wheresubregister ^^^^0 = {^^^^0, ... , ^^^^2^^^^−1} is a subregister of size 2^^^^ and subregister ^^^^^^^^ is of size atmost ^^^^, for each ^^^^ ∈ {1, ... ,^^^^}.More precisely, let ^^^^ (2+^^^^)^^^^−^^^^ = {^^^^^^^^} 1^^^^=(1+^^^^)^^^^ for each ^^^^ ∈ {1, ... ,^^^^}.Let ^^^^ = |{^^^^ ∈ {1, ... ,^^^^}:^^^^^^^^ ≠ ∅}| be the number of non-empty registers of positive index.Moreover, the first register ^^^^0 is further divided into ^^^^∗0 = {^^^^^^^^}^^^^−1^^^^=0 containing the first ^^^^qubits and ^^^^ ∗0′ = ^^^^0 ∖ ^^^^0.The circuit in Fig.4 illustrates a decomposition of the controlled-NOT operation^^^using a single zeroed ancilla. Note that qubit ^^^^^^^^is positioned between registers ^^^^^^^^and ^^^^^^^^+1. The unitary associated to the circuit is given bywhereThe first operation ^^^^^^^^^^^^0 sets the zeroed ancilla to |1^ if and only if ^^^^0is active. Now, consider the operation ℭ: for ^^^^^^^^^^^^0∗∪^^^^to apply an ^^^^ gate to the target, all the qubits from ^^^^0∗must be in state |0^, and the ancilla ^^^^ must be in state |1^.Now, notice that for each qubit ^^^^ ∗^^^^ ∈ ^^^^0, ^^^^^^^^ is in state |0^ when applying ^^^^^^^^^^^^0∗∪^^^^if and only if it was in the same activation state as ^^^^^^^^+1right before applying ℭ. Therefore, ℭ is a multi-controlled-^^^^ gate conditioned on: • the ancilla ^^^^ being in state|1^ and •for each index ^^^^ ∈ {0, ... , ^^^^ − 1}: ^^^^^^^^ being in the same activation state as ^^^^^^^^+1.By inspection, in the circuit in Fig.4, these conditions are fulfilled if and only if the register ^^^^ of interest is active. Therefore, the target ^^^^ is flipped under exactly the right hypothesis. The operations following the potential flip of qubit ^^^^ leave it unchanged and reset both the qubits from ^^^^0∗and the ancilla to their initial state. The overall operation is the desired ^^^^^^^^^^^^ gate. A more formal proof is given hereafter.______________ DETAILED NOTE 1 - STEP BY STEP STUDY OF THE PROPOSED QUANTUM CIRCUITS Further notations. Before proving the correctness of the method, further notations need to be introduced.The operator ⊕: {0,1}2 → {0,1} is used to denote addition modulo 2, while ⊞:∪∞^^^^=1 {0,1}^^^^ × {0,1}^^^^ →∪∞^^^^=1 {0,1}^^^^ signifies bitwise addition modulo two: (^^^^1, ... , ^^^^^^^^) ⊞It will be practical to denote with the same symbol ^^^^ a set of qubits and the bistring associated with a computational basis state label in the notation. The operations ^^^^ and ^^‾^^ will turn out to be very useful since for any multi-qubit register ^^^^, target qubit register ^^^^ and one of their computational basis states |R,t^:For an ancilla qubit ^^^^, it also holds that.Let ^^^^ > 4 and .Again, write ^^^^ = {^^^^ ^^2^^^^−1^^^^} ^^−1^^^^=0. Let ^^^^ ⊃ ^^^^0 = {^^^^^^^^}^^^^=0be a first subregister of 2^^^^ control qubits,and for each ^^^^ ≥ 1, let ^^^^ ⊃ ^^^^ = {^^^^^^^^ if ^^^^be other subregisters of size at ∗^^^^. Let ^^^^0 = {^^^^^^^^ ∈ ^^^^0:^^^^^^^^+1 ≠ ∅} and ^^^^0′ = 0 0.Finally, let ^^^^ = |^^^^∗0|.The analysis of the construction follows the steps given below. • First, the zeroed-ancilla circuit is proven to be correct. • Second, the borrowed-ancilla circuit is proven to be correct. • Third, it is shown that each of the smaller multi-controlled NOT appearing in the borrowed-ancilla circuit can be achieved with the help of a locally borrowed ancilla. • Fourth, the recursion characterising the circuit depth is solved. Analysis of ^^^^0The single-zeroed-ancilla circuit corresponds to the unitary operationProving that ^^^^0performs the desired operation relies on the following lemma. Lemma 1. It holds that: ^^^^(^^^^0)^^‾^^�^^^^∗0 ⊞�^^^^(^^^^1), ... , ^^^^(^^^^^^^^) = ^^^^(^^^^). (2)It can be noted that ^^^^∗0Proof 1. Assume that ^^^^(^^^^) = 1.Necessarily all the qubits in ^^^^ are in state 1 and for each ^^^^ ∈ {0, ... , ^^^^}, ^^^^^^^^ verifies ^^^^(^^^^^^^^) =1. In particular, for each ^^^^ ∈ {1, ... , ^^^^}, ^^^^^^^^−1 ⊕ ^^^^(^^^^^^^^) = 1 ⊕ 1 = 0.As a consequence, ^^‾^^�^^^^∗0 ⊞�^^^^(^^^^1), ... , ^^^^(^^^^^^^^) = ^^‾^^(^^^^0 ⊕ ^^^^1, ^^^^1 ⊕ ^^^^2, ... , ^^^^^^^^−1 ⊕ ^^^^^^^^) =∏^^^^^^^^=11 = 1.Summarising: ^^^^(^^^^) = 1 ^ ^^^^(^^^^0)^^‾^^�^^^^∗0 ⊞�^^^^(^^^^1), ... , ^^^^(^^^^^^^^) = 1 = ^^^^(^^^^). (3)Now, assume that ^^^^(^^^^) = 0. If ^^^^(^^^^0) = 0,thenare done.Thus, assume that ^^^^(^^^^0) = 1. Since ^^^^(^^^^) = 0, there must exists a qubit ^^^^^^^^ ∈ ^^^^ ∖ ^^^^0 instate |0^.Let ^^^^ ∈ {1, ... , ^^^^} be the register index such that ^^^^^^^^ ∈ ^^^^^^^^.Necessarily, ^^^^�^^^^^^^^� = 0.However, sinceIt follows that:Therefore, in any case, ^^^^(^^^^) = ^^^^(^^^^0)^^‾^^(^^^^∗0 ⊞�^^^^(^^^^1), ... , ^^^^(^^^^^^^^)�.Let us also compute the action of ℭ on an arbitrary computational basis state Lemma 2. The following equation holds for any computational basis stateProof 2.Conclude by noticing that for a single-qubit labelled by ^^^^ in a state of the computationalbasis, ^^^^ = ^^^^(^^^^).Let us verify that for any computational basis state of the formBy linearity, ^^^^0performs the right operation on any superposition of the computational basis with ancilla in state |0^, hence any state with zeroed ancilla. Analysis of ^^^^ Following the same logic, the correctness of single-borrowed-ancilla circuit is proven. This circuit acts as:The evolution of an arbitrary input state is given in equation 10.By linearity, ^^^^ = ^^^^^^^^^^^^ .Each smaller multi-controlled NOT gate has a borrowed ancilla at its disposalLemma 3. The register ^^^^0′ has more qubits than the register ^^^^∗0: |^^^^0′| ≥ |^^^^∗0|.ProofThus,In can ^^^^ subregisters of size ^^^^.In equation, |^^^^∗0| ≤ ^^^^.Finally, |^^^^0′| = |^^^^0|− |^^^^∗0| ≥ 2^^^^ − ^^^^ = ^^^^ ≥ |^^^^∗0|.As a consequence, each of the factors in (11) ^^^^ �^^^^ ^^^^^^^^−1^^^^^^^^^^^^=1 can be executed with the help of a borrowed ancilla in ^^^^0′. Solving the recursion The operation with the highest number of control qubits is controlled by the state of ^^^^0, ofsize |^^^^0| = 2^^^^.It is applied twice. A layer of ^^^^^^^^(^^^^) gates is applied four times, and a layer of ^^^^^^^^+1(^^^^) (or even ^^^^^^^^(^^^^) in some cases) gates is applied twice. The overall depth can be uniformly bounded by the depth of eight successive ^^^^2^^^^(^^^^) gates plus a constant term corresponding to the layers of ^^^^ gates required by the white controls. Let us conclude the analysis by upper bounding the resulting depth.Let ^^^^(^^^^) be the depth of circuit ^^^^^^^^(^^^^). Assume that ^^^^ = 2^^^^+2,by the Master Theorem 1. In terms of ^^^^, the depth of the ^^^^-control gate is ^^^^(log(^^^^)3).______________How the above zeroed ancilla is transformed into a borrowed ancilla This subsection discusses how the above zeroed ancilla is transformed into a borrowed ancilla. The construction is displayed in the circuit in Fig.5, which is formally defined by the unitary operation (4) Notice that ^^^^0and ℭ both leave the control qubits and the ancilla unchanged. As a consequence, one only needs to focus on what happens to the target ^^^^. If the ancilla starts in state |0^, the last ℭ does not affect ^^^^ and ^^^^ overall acts as the desiredgate. It is now sufficient to focus on the case where qubit ^^^^ arrives in state |1^ and to repeat theabove analysis: ^^^^0 flips the target if both ^^^^0 is inactive and for each ^^^^ ∈ {0, ... , ^^^^ − 1}, qubit^^^^^^^^is in the same activation state as ^^^^^^^^+1. Refer to this flip as the first flip.Then, ℭ flips the target if and only if for each ^^^^ ∈ {0, ... , ^^^^ − 1}, qubit ^^^^^^^^ is in the sameactivation state as ^^^^^^^^+1. Refer to this flip as the second flip. Summarising, if ^^^^ is active only the second flip occurs. If ^^^^ is inactive, there are two cases: ^^^^0is either inactive or active. If ^^^^0is inactive, both flip 1 and flip 2 occur, resulting in no flip at all. If ^^^^0is active, the second condition cannot be verified. Therefore, none of the two flips occurs. In any case, the circuit applies the^^^gate and leaves the ancilla unaffected. A more thorough proof has been given in Detailed Note 1.How a qubit can be borrowed to compute each of the smaller MCX operations. It is now possible to use a borrowed ancilla to implement any ^^^^^^^^(^^^^) using smaller ^^^^2^^^^(^^^^), ^^^^^^^^+1and ^^^^^^^^(^^^^)gates. This section details how a qubit can be borrowed tocompute each of the smaller MCX operations. This allows to set up a recursive construction, keeping the number of ancillae to one and achieving the polylogarithmic depth decomposition of ^^^^-MCX.In Fig.5, the block has the same depth as a single controlled-NOT gate with ^^^^ control qubits since it is the product of ^^^^ unitaries with disjoint support. The depth of a controlled operation containing white controls is the same as that of standard controlled-NOT plus that of two additional layers of X gates acting on qubits whose control colour is white. One may want to apply the decomposition from the circuit in Fig.5 to each ^^^^^^^^(^^^^) gate. In order to do so, each block must have a borrowed ancilla qubit at its disposal. There are more available borrowed qubits in the register ^^^^0′ than operations to perform in parallel: |^^^^0′| ≥ |^^^^∗0| (see Supplementary Note 1). Hence, there are sufficiently manyborrowed ancilla qubits to construct the smaller operations recursively. The recursion gives the following equality for the depth ^^^^^^^^ of a ^^^^^^^^(^^^^)gate.^^^^^^^^ = 2^^^^2^^^^ + 4^^^^^^^^ + 2^^^^^^^^+1 + 4, (5)with ^^^^ = ⌊√^^^^⌋ and ^^^^ − 2 ≤ ^^^^ ≤ ^^^^. The asymptotic behavior of the depth can be studied ascircuit depth of ^^^^2^^^^+2(^^^^)gates. Equation^^^^(^^^^) ≤ 8^^^^�^^^^2�+ 4 (6)The Master Theorem, recalled in detailed Note 2, implies that ^^^^(^^^^) ∈ ^^^^(^^^^3).______________ Detailed Note 2 - Master Theorem The Master Theorem 1 is a fundamental theorem for the analysis of dynamical programming algorithms. The master method, based on this theorem, provides asymptoticgrowths for recurrences of the form ^^^^(^^^^) = ^^^^^^^^(^^^^ / ^^^^) + ^^^^(^^^^), where ^^^^ ≥ 1, ^^^^ > 1.Theorem 1. Let ^^^^ ≥ 1 and ^^^^ > 1 be constants, let ^^^^(^^^^) be a function and let ^^^^(^^^^) bedefined on the nonnegative integers by the recurrence ^^^^(^^^^) = ^^^^^^^^(^^^^ / ^^^^) + ^^^^(^^^^),where we interpret ^^^^ / ^^^^ to mean either . Then ^^^^(^^^^)has the following asymptotic bounds: 1. If ^^^^(^^^^) ∈ ^^^^�^^^^log^^^^(^^^^)−^^^^� for some constant ^^^^ > 0, then ^^^^(^^^^) = ^^^^�^^^^log^^^^(^^^^)�.2. If ^^^^(^^^^) = ^^^^�^^^^log^^^^(^^^^)�, then ^^^^(^^^^) = ^^^^�^^^^log^^^^(^^^^)log^^^^�.3. If ^^^^(^^^^) = ^^^^�^^^^log^^^^^^^^+^^^^� for some constant ^^^^ > 0, and if ^^^^^^^^(^^^^ / ^^^^) ≤ ^^^^^^^^(^^^^) for someconstant ^^^^ < 1 and all sufficiently large ^^^^, then ^^^^(^^^^) =______________ In terms of ^^^^, the circuit depth of a ^^^^^^^^(^^^^) gate using one borrowed ancilla qubit is ^^^^^^^^∈^^^^(log(^^^^)3).Now, a lower bound is derived by �≡�^^^^2^^^^�^^^^∈ℕ such that ^^^^(^^^^) ≥8^�^^^(^^^^ / 2) + 4. Similarly, this inequality leads to ^^^^^^^^ ∈ ^^^^(log(^^^^)3).The scaling of the size is computed similarly to the scaling of the depth, i.e. by solving the corresponding recursive equation. Details are given in Detailed Note 3. ______________ Detailed Note 3 - Circuit sizeLet us show that the size ^^^^(^^^^)of a ^^^^^^^^(^^^^)gate is ^^�^^(^^^^).Clearly, ^^^^(^^^^) ∈ ^^^^(^^^^).Let us show that ^^^^(^^^^) ∈ ^^^^(^^^^log(^^^^)4).Let ^^^^ = 2^^^^+2.Then,Define ^̃^^^(^^^^) ≡ ^^^^(^^^^) / ^^^^. Then,As a consequence, ^^^^(^^^^) ∈ ^^^^(^^^^log(^^^^)4) and ^^^^(^^^^) ∈ ^^�^^(^^^^).______________The following proposition gathers these statements. Proposition 1: Hence, according to the invention, a controlled-NOT gate with ^^^^ control qubits is implementable with a circuit of depth ^^^^(log(^^^^)3), size ^^^^(^^^^log(^^^^)4) and using a single borrowed ancilla qubit through the recursive use of circuit in Fig.5. A first application of the invention affects the decomposition of multi-controlled unitary ^^^^^^^^(^^^^)using one zeroed ancilla. The zeroed ancilla allows to decomposed a ^^^^^^^^(^^^^)gateinto two ^^^^^^^^(^^^^) gates and one ^^^^1(^^^^) using the circuit identity in Fig.13. The following gives the complexity to implement a ^^^^^^^^(^^^^) gate. Let ^^^^ be a unitary of size ^^^^ in the basis of single-qubit gates and CNOT gates. A controlled ^^^^ gate with ^^^^ control qubits is implementable with depth ^^^^(^^^^ + log(^^^^)3),size ^^^^(^^^^ + ^^^^log(^^^^)4) and one zeroed ancilla qubit through the circuit in Fig. 13.It is also straight-forward to implement any special unitary single-qubit gate ^^^^ ∈ ^^^^^^^^(2)with polylogarithmic complexity and without ancilla. Let ^^^^ be a special unitary single-qubit gate. A ^^^^^^^^(^^^^) operation can be implemented with a circuit of depth ^^^^(log(^^^^)3)and size ^^^^(^^^^log(^^^^)4)without ancillaqubits. This is illustrated in Fig.7B. B. Embodiment 2: Polylogarithmic-depth and ancilla-free approximate gate This section outlines how to make use of Proposition 1 to control single-qubit unitaries in the absence of ancilla qubits. The first step generates borrowed ancilla qubits bydecomposing a ^^^^-controlled unitary into (^^^^ − 1)-controlled unitaries. More precisely, forany single-qubit unitary ^^^^ whose square root is denoted by ^^^^, one can implement a ^^^^^^^^(^^^^)gate from two ^^^^^^^^−1(^^^^), a ^^^^^^^^−1(^^^^)and two simple two-qubit gates using the circuit identityin Fig.7A. Applying this decomposition ^^^^ times involves implementing the 2^^^^-th root ^^^^^^^^of the original unitary. Performing this recursion ^^^^ times leads to a linear depth quantum circuit .To circumvent this issue, it is possible to neglect the (^^^^ − ^^^^)-controlled ^^^^^^^^ gate,introducing an error exponentially small with ^^^^:Applying the recursion times gives an ^^^^ > 0 error on the implementation ofthe ^^^^^^^^(^^^^) gates. This decomposition leads to 2^^^^ one-controlled-root of ^^^^ and 2^^^^ multi-controlled NOT gates.Each MCX gate is controlled by a number ^^^^ ∈ {1, ... ,^^^^ − 1} of qubits and, therefore, isimplementable using one of the non-affected qubit as a borrowed ancilla through the first method 1 with a polylogarithmic depth. The following proposition summarises the complexity of the method. Proposition 2: According to the present invention, for any single-qubit unitary ^^^^ ∈ ^^^^(2),a controlled-^^^^ gate with ^^^^ control qubits is implementable up to an error ^^^^ > 0 (inspectral norm) with a circuit of depth ^^^^�log(^^^^)3log(1 / ^^^^)�, size ^^^^�^^^^log(^^^^)4log(1 / ^^^^)� without ancilla qubits. The size and depth of the quantum circuits are trivially bounded noticing that the computational cost of ^^^^ ^^^^-MCX, ^^^^ ≤ ^^^^ − 1, is bounded by the computational cost of ^^^^ ^^^^-multi-controlled NOT gates. This approximation proves highly effective for practical applications, as it is not needed toimplement gates with exponentially small phases. The error ^^^^ > 0 can be selected to alignwith the intrinsic hardware error, providing a level of flexibility that exact methods approaches may not offer. A. Embodiment 3: Adjustable-depth methodThis subsection explains how to implement a ^^^^^^^^(^^^^) gate given 2 ≤ ^^^^ ≤ ^^^^ zeroed ancillaqubits. For simplicity, consider an even number of ancillae ^^^^ and a number of control qubits ^^^^ divisible by ^^^^ / 2. The method has three steps: a first one where ^^^^ / 2 controlled- NOT gates, each controlled by ^^^^ / (^^^^ / 2) qubits, are performed in parallel in order to store the activation of the subregisters into ^^^^ / 2 ancillae. A second step where a ^^^^^^^^ / 2(^^^^) controlled by the first ^^^^ / 2 ancillae is implemented on the target qubit using the last ^^^^ / 2 zeroed ancillae. A last one to restore the ancilla qubits in state |0^. The first step makesuse of Proposition 1 to implement each ^^^^^^^^ / (^^^^ / 2)(^^^^) with depth ^^^^�log�^^^^ / (^^^^ / 2)�3� usingone zeroed ancilla of the last ^^^^ / 2 ancillae. The second step uses the logarithmic method from to implement the ^^^^^^^^ / 2(^^^^) with depth ^^^^�log(^^^^ / 2)� using ^^^^ / 2 ancillae. The circuit in Fig.14 represents the three steps of the adjustable-depth method. More generally, one can consider any value of ^^^^ control qubits and ^^^^ ancilla qubits such that 2 ≤ ^^^^ ≤ ^^^^ qubits. Let ^^^^ = {^^^^0, ... ,^^^^^^^^−1} be the register of zeroed ancilla qubits,such that ^^^^ = ^^^^0 ∪ ^^^^1 and let the control register ^^^^ be divided into balancedsubregisters . Let ^^^^ be the operation associated to the first step:Each of the ^^^^^^^^^^^^^^^^^^^^is implemented in parallel of the others using the circuit in Fig.4 with one zeroed ancilla of register ^^^^1. Since all the ^^^^^^^^^^^^^^^^^^^^’s are performed in parallel, the operation ^^^^ has the same depth as the maximum depth of the ^^^^^^^^^^^^^^^^^^^^’s. After applying ^^^^, one can implement ^^^^^^^^^^^^0 using a method uses as many ancillae as control qubits to achieve a logarithmic depth. Therefore, one can implement ^^^^^^^^^^^^0 with depthas a register of zeroed ancilla Finally, one can repeat ^^^^ to fully reset the register ^^^^. The following proposition summarises the complexity of this new method.Proposition 3: According to the invention, let ^^^^ ≥ 2 be the number of control qubits and2 ≤ ^^^^ ≤ ^^^^ be the number of available zeroed ancillae. Then, there exists a decompositionof the ^^^^^^^^(^^^^) into single-qubit gates and CNOT gates with depth complexity:Note that the depth decreases as the number of ancillae ^^^^ increases, providing a method with adjustable depth. This is a valuable asset for aligning with the constraints of the hardware resources. Also, remark that the method that uses as many ancillae as control qubits to achieve a logarithmic depth (ref.22) has been used only for the second part of the algorithm. Using it in the first part would require a number of ancilla qubits proportional to the number of blocks, thus be potentially large. Different combinations of methods did not seem to lead to particular improvements in terms of depth or size. Overall, this decomposition provides a range of logarithmic-depth methods using less than^^^^ ancillae, by considering ^^^^(^^^^) = ^^^^^^^^, with 0 < ^^^^ < 1, improving the decompositionproposed in the scientific paper ref.22. DISCUSSION In non-asymptotic regimes, pre-factors play a crucial role. This section employs graphical comparisons and complexity tables to fairly evaluate the overall effectiveness of current MCX decomposition methods. The circuits are compiled in the basis of single-qubit and CNOT gates for number of control qubits ranging from 102to 107. The obtained depths are numerically fitted, giving useful estimates for each method. Since this section only aims to serve as a ressource estimator, the linear depth decompositions are fitted with a first-order polynomial in the variable ^^^^ and the depth of the decomposition from the method of the invention is fitted with a first-order polynomial in the variable log(^^^^)3. In the case where only one zeroed borrowed ancilla qubit is available, a comparison is made with the one ancilla method from ref.15 as well as Craig Gidney’s ancilla-free method, and illustrated in Fig.8. In practice, the recurrence from Proposition 1 must be initialised. For a number of control qubits ^^^^ less than 30, the ^^^^^^^^(^^^^) gate is implemented using Barenco et al.’s single-borrowed-ancilla method (the small gates can also be optimised via a brute-force approach). From there, the circuits and depths can be computed with a dynamic programming approach. This implementation provides shallower circuit for any number of control qubits. In that case, the asymptotic advantage of a method according to the invention becomes evident early in the process, making the method applicable across various regimes.Next, in the absence of an ancilla qubit but allowing an approximation error ^^^^ > 0, acomparison is conducted against the state-of-the-art method outlined by Silva et al. , as depicted in Fig.8. another method according to the invention 2 yields a shallower circuit than the method as soon as ^^^^ ≳ 105.Finally, with a fixed number of control qubits set at ^^^^ = 100, Fig. 9 illustrates the depthas a function of the number of ancillae. For a single ancilla, the use of circuit in Fig.4 already surpasses the state-of-the-art, and an increase in the number of zeroed ancillae rapidly reduces the overall circuit depth. Another method according to the invention achieves the same depth as the previous best method but with a significantly lower number of ancillae, getting even larger as the number ^^^^ of control qubits increases as depicted in Fig.9 and in Fig.10. Table 1: Circuit depth of zeroed ancillae methods. The depths are numerically fitted in the range from 102to 107control qubits. Table 2: Circuit depth of zeroed ancillae methods. The depths are numerically fitted in the range from 102to 107control qubits.Table 3: Circuit depth of zeroed ancillae methods. The depths are numerically fitted in the range from 102to 107control qubits. This paragraph provides an overview of some standard quantum algorithm oracles where multi-controlled operations act as both building blocks and complexity drivers, and where the improved decomposition reported in this paper readily provides the corresponding speedup. Quantum search, quantum phase estimation, and Hamiltonian simulation provide robust support for the claimed exponential quantum advantage. These algorithms can be seen as particular instances of the quantum singular value transformation (QSVT), which allows the embedding of any Hamiltonian ^^^^ into an invariant subspace of the signal unitary, thereby enabling to compute a broad range of polynomials of ^^^^. The qubitisation is the central technique to the framework of QSVT. When qubitising the Hamiltonian expressed as a linear combination ^^^^ =^^^^^^^^ ^^^^^^^^, witheach ^^^^^^^^decomposable into a maximum of ^^^^ native gates, the process exhibits optimal query complexity for the two following oracles. The PREPARE oracle consists in a quantum state preparation step. Formally, it involves preparing the state |PREPARE^ from a set of coefficients {^^^^^^^^}^^^^^^^^=1such as :The CVO-QRAM algorithm(Ref.32) performs efficiently such task by proceeding ^^^^ layers of ^^^^-controlled operations, where ^^^^ represents the number of control qubits and ^^^^ represents the number of non-zero amplitude in the target state. The resulting circuit exhibits a depth of ^^^^(^^^^^^^^) assuming usual linear decomposition of multi-controlledoperations. The ^^^^^^^^(^^^^) gate decompositions provided in this paper readily improves the scaling to ^^^^(^^^^ log(^^^^)3). The PREPARE operator finds application in a broader context beyond qubitisation, whenever there is a need to transfer classical data into the qubit register. The SELECT oracle consists in a block-diagonal operator and acts as follows:It can be efficiently decomposed as ^^^^ layers of log(^^^^)-controlled-^^^^^^^^operations, yielding a depth in ^^^^(^^^^ log(^^^^)^^^^) with usual linear-depth decomposition ofgates. The decompositions presented in this paper readily reduce the SELECT operation complexityto ^^^^�^^^^ log�log(^^^^)�3^^^^�.Considering an example application in ground-state quantum chemistry, the quantum phase estimation (QPE) stands as the standard fault-tolerant algorithm. The QPE performs a projection on an eigenstate of the Hamiltonian and provides an estimate of the associated eigenenergy. The overall complexity is determined by the preparation of an accurate initial state, and the implementation of the phase estimation circuit. A possible strategy involves using CVO-QRAM to initialise the quantum register to an accurate approximation of the ground state obtained with classical computational chemistry simulations (Ref 33. Then, the phase estimation algorithm calls multiple times a controlled unitary ^^^^. The unitary ^^^^ should be encoded so that its spectrum is related to the spectrum of the molecular Hamiltonian ^^^^. The qubitisation outlined above has become a standard for this task, for example by implementing the quantum walk operator ^^^^ = ^^^^^^^^arccos^^^^ .The polylogarithmic-depth ^^^^^^^^(^^^^)operations presented in this paper directly reduce the depth of two building blocks in QPE, leading to corresponding improvements in the algorithm. The expected costs associated with achieving a quantum advantage in chemistry with QPE require a reconsideration incorporating the previous enhancements. In summary, this invention introduced several methods for decomposing ^^^^^^^^(^^^^)gates into arbitrary single-qubit and CNOT gates. Proposition 1 takes advantage of a single borrowed ancilla qubit to implement a ^^^^^^^^(^^^^)gate with depth complexity ^^^^(log(^^^^)3). Such polylogarithmic complexity significantlyimproves the present state-of-the-art which is set at a depth of ^^^^(^^^^). Proposition 2 aims at the more general task of controlling arbitrary single-qubit unitaries. Introducing an approximation error ^^^^ > 0 and making use of the previous proposition, thetask can be achieved with depth ^^^^(log(1 / ^^^^)log(^^^^)3). With polylogarithmic dependenceon both relevant parameters, this approach emerges as the most efficient in its category. When zeroed ancillae are available, Proposition 3 provides a strategy for enhancing the efficiency of a ^^^^^^^^(^^^^) gate by optimising the utilisation of these ancillae. A glimpse into the potential applications of these enhanced ^^^^^^^^(^^^^)implementations within the QSVT framework is presented.

[0180] While Propositions 1 and 2 offer a superpolynomial speedup in terms of depth, the size is increased by a polylogarithmic factor. The size of the circuit, especially the count of non-Clifford gates (T gates, Toffoli, ...), can dominate the total execution time due to the necessity of preparing magic states through distillation. This process is highly resource- intensive in terms of both runtime and ancilla count, and it does not always allow for efficient parallel execution. Therefore, the larger size resulting from the proposed decompositions could be seen as a drawback compared to methods that scale linearly in size. The key aim of these decompositions is to pioneer a novel approach to circuit design that prioritises minimising depth.It is also important to note that, for a large number ^^^^ of qubits (^^^^ ≥ 105), it is likely that anerror lower than 2−^^^^is experimentally hard to achieve on the parameters of the quantum gates, even in the context of fault-tolerant quantum computing with error correction. Therefore, depending on the wavefunctions that are manipulated in the QPU, it might be preferable to skip a large controlled operation (with more than 105controls). Examples where gates with exponentially small phases are omitted can be seen in the Approximate Quantum Fourier Transform or with Proposition 2. Conversely, removing a multi- controlled NOT gate could significantly impact the algorithm’s outcome, in the case of sparse quantum state preparation for example . Further, the invention can be beneficial for the benefice these enhanced multi-controlled NOT decompositions can offer across various quantum algorithms. The invention can be the subject of numerous variants and applications other than those described above. In particular, unless otherwise indicated, the different structural and functional characteristics of each of the implementations described above should not be considered as combined and / or closely and / or inextricably linked to each other, but on the contrary as simple juxtapositions. In addition, the structural and / or functional characteristics of the various embodiments described above may be the subject in whole or in part of any differentjuxtaposition or any different combination. Ref. [1] P. W. Shor, Polynomial-time algorithms for prime factorization and discrete logarithms on a quantum computer, SIAM Journal on Computing 26, 1484{1509 (1997). [2] A. M. Childs, R. Cleve, E. Deotto, E. Farhi, S. Gutmann, and D. A. Spielman, Exponential algorithmic speedup by a quantum walk, in Proceedings of the thirty-fifth annual ACM symposium on Theory of computing, STOC03 (ACM, 2003). [3] M. A. Nielsen and I. L. Chuang, Quantum Computation and Quantum Information: 10th Anniversary Edition (Cambridge University Press, 2011). [4] M. Maronese, L. Moro, L. Rocutto, and E. Prati, Quantum compiling, in Quantum Computing Environments, edited by S. S. Iyengar, M. Mastriani, and K. L. Kumar (Springer International Publishing, Cham, 2022) pp.39{74. [5] G. H. Low and I. L. Chuang, Hamiltonian simulation by qubitization, Quantum 3, 163 (2019). [6] J. M. Martyn, Z. M. Rossi, A. K. Tan, and I. L. Chuang, Grand unification of quantum algorithms, PRX Quantum 2, 10.1103 / prxquantum.2.040203 (2021). [7] J. Haah, M. B. Hastings, R. Kothari, and G. H. Low, Quantum algorithm for simulating real time evolution of lattice hamiltonians, SIAM Journal on Computing 52, FOCS18 (2021). [8] A. Y. Kitaev, Quantum measurements and the abelian stabilizer problem, Electron. Colloquium Comput. Complex. TR96 (1995). [9] B. Bauer, S. Bravyi, M. Motta, and G. K.- L. Chan, Quantum algorithms for quantum chemistry and quantum materials science, Chemical Reviews 120, 12685 (2020), pMID: 33090772, https: / / doi.org / 10.1021 / acs.chemrev.9b00829.

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Claims

Claims 1. A computer-implemented method (100) for implementing a CnX gate at n control qubits, in a gate-based quantum circuit, said method (100) comprising using a quantum circuit comprising: - control registers Rieach comprising control qubits at an initial activation state; - one-qubit target register t; said quantum circuit further comprising, or having access to, m zeroed one qubit ancilla a_i, m being smaller than n, preferably m being smaller than n-1; said method (100) comprising: - A step of storing (110) the initial activation state of control registers Riinto a first subset of the m zeroed ancilla a_i; - A step of flipping (120) the one-qubit target when and only when all the first subset ancilla are activated, using a parallelisation method using at least part of the remaining m zeroed ancilla a_i; and - A step of restoring (130) all the qubits which activation state has been modified except the one-qubit target to their initial state.

2. The computer-implemented method (100) for implementing a CnX gate at n control qubits according to the previous claim, wherein the step of storing (110) the initial activation state of control registers into a first subset of the m zeroed ancilla a_i comprises performing in parallel m / 2 multicontrol X gates, each controlled by n / (m / 2) control qubits, to store the values of the control qubits into m / 2 ancilla.

3. The computer-implemented method (100) for implementing a CnX gate at n control qubits according to anyone of the previous claims, wherein the step of flipping (120) the one-qubit target makes use of sequential operations to combine the results of these parallel computations.

4. The computer-implemented method (100) for implementing a CnX gate at n control qubits according to anyone of the previous claims, wherein the first subset of the m zeroed ancilla a_i comprises half or more of the m zeroed one qubit ancilla.

5. The computer-implemented method (100) according to anyone of the previous claims, wherein the parallelisation method is selected among:• A method comprising decomposing the n-qubit Toffoli gate into two-qubit gates and single-qubit gates; or • A method comprising decomposing the n-qubit Toffoli gate into a reduced Toffoli gate modulo phase shift using one or several Clifford gates and one ancillary qubit.

6. The computer implemented method (100) for implementing a CnX gate in a gate- based quantum circuit according to anyone of the previous claims, wherein most of the control registers Ricomprises √n control Qubits; preferably all registers except the last register of the second control registers which comprises √n control Qubits or less.

7. The computer implemented method (100) for implementing a CnX gate in a gate- based quantum circuit according to anyone of the previous claims, wherein it comprises √n or less control register Ri.

8. The computer implemented method (100) for implementing a CnX gate according to anyone of the previous claims, wherein it comprises a refactorization of the successive steps to set up an induction, preferably the induction dividing the step of applying a NOT function.

9. A CnX gate (Controlledn-NOT gate) with an overall circuit depth which is polylogarithmic in the number of control qubits, said CnX gate comprising n ≥ 2 control qubits, preferably more than 5, 10, 50, 100, 1000 control qubits.

10. A CnX gate (Controlledn-NOT gate) obtainable according to anyone of the previous method claims 1 to 8, said CnX gate (Controlledn-NOT gate) having an overall circuit depth which is polylogarithmic in the number of control qubits, said CnX gate comprising n ≥ 2 control qubits, preferably more than 5, 10, 50, 100, 1000 control qubits.

11. A CnX gate (Controlledn-NOT gate) in a quantum circuit, said CnX gate comprising at least 10 control qubits and having a circuit depth D which is equal to or lower than 2.3 log(n / ⌊m / 2⌋)log(12)+16⌈log(⌊m / 2⌋)⌉+12; with n being the number of control qubits in the CnX gate and m being the number of zeroed one qubit ancilla to which said CnX gate have access, m being smaller than n, preferably m being smaller than n-1.

12. A quantum gate comprising one or several CnX gate according to anyone of the claims 9 to 11.

13. A unitary quantum gate comprising more than n control qubits and one or several CnX gate according to any one of the claims 9 to 11.

14. A quantum circuit comprising one or several CnX gate according to any one of the claims 9 to 11.

15. A quantum computer, configured to combine the implementation of one or several CnX gate according to any one of the claims 9 to 11, or configured to implement a method according to any one of the claims 1 to 8, wherein it is arranged for a single-step generation of N-body entangling interactions (such as a Toffoli gate) between physical qubits, such as trapped atomic ion.

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