Semiconductor quantum device and quantum computer using same

Abstract

The present invention addresses the problem of performing an accurate qubit operation.　In a preferable aspect of the present invention for achieving the abovementioned purpose, a semiconductor quantum device comprises a transistor having a laminate structure of a semiconductor, an insulator, and a conductor in order to form qubits. At least a portion of the conductor forms a gate electrode of the transistor. At least a portion of the semiconductor forms a channel of the transistor. In a cross-section perpendicular to the channel direction of the transistor, the semiconductor has a protruding section on the gate electrode side thereof and is surrounded by the insulator at the periphery thereof, the protruding section forms the channel, and the width of the protruding section on the side facing the semiconductor is 20 nm or less.

Description

Semiconductor quantum devices and quantum computers using them

[0001] The present invention relates to a semiconductor quantum device structure for hardware used in quantum computers.

[0002] A quantum computer is a computer based on the principles of quantum mechanics. Quantum computers are expected to enable faster information processing than existing computers for certain calculations or applications. Existing computers perform calculations by inputting binary numbers, represented by high and low voltages, into circuits made up of transistors. In contrast, quantum computers use quantum bits, which can simultaneously exist in two states, as their basic information unit. Quantum computers use physical media to physically realize quantum bits, and operations on these physical media are performed by changing their state using electrical pulses or electronic waves. These operations are also called gates or gate operations.

[0003] Known physical media that can serve as quantum bits include atoms, molecules, photons, and electrons. Each physical medium is characterized by its ability to assume discrete energy states. Artificial devices made of superconductors or semiconductors are also known to produce discrete energy states, and these devices can also be used as quantum bit physical media. This invention particularly relates to a quantum computer method that uses semiconductor devices as quantum bit physical media.

[0004] The aforementioned semiconductor device has a structure similar to that of a metal (gate electrode)-insulator-silicon stacked transistor (hereafter referred to as a MOS transistor). Because the insulator functions as a dielectric in this structure, a MOS transistor can be considered a type of capacitor. When a voltage is applied to the metal in this structure, a charging effect occurs, storing electrons in the silicon near the insulator. Numerous experimental evidence from low-temperature physics has shown that MOS transistors miniaturized to the order of tens of nanometers can capture only one electron in a temperature environment below a few Kelvin. This captured electron remains stable even when the voltage applied to the gate electrode fluctuates within a certain range.

[0005] Furthermore, previous research has experimentally shown that when captured electrons are observed from an energy perspective, they have discrete energies, just like atoms. Atoms are one of the physical media that can realize quantum bits, but semiconductor technology can be used to create artificial atoms in the silicon channel of a transistor. Artificial atoms are also called quantum dots.

[0006] The arrangement of artificial atoms can be designed using semiconductor miniaturization technology. While techniques for controlling the arrangement of real atoms are known, the number of atoms that can be arranged in a realistic time frame is limited to a few dozen at most. On the other hand, using semiconductor microfabrication technology, it is possible to arrange artificial atoms in an orderly fashion and even control each one with voltage. Research is being conducted on quantum bit arrays, in which quantum bits using artificial atoms such as electron spin are arranged in two dimensions.

[0007] Patent Document 1 discloses a quantum bit array comprising a semiconductor layer, an insulating layer disposed on the semiconductor layer, and a plurality of first gate electrodes disposed on the insulating layer and trapping electrons of a predetermined spin state in the semiconductor layer by applying a voltage, characterized in that when the spin state of the electrons is to be changed, the quantum bit array has a means for passing a current through at least one of the first gate electrodes in the extension direction of the first gate electrode to form a magnetic field that acts on the electrons.

[0008] Patent Document 2 discloses a technology for realizing quantum bits using electron spin, and describes an example in which calculations in a quantum computer are realized by controlling electron spin realized in a semiconductor integrated circuit (LSI).

[0009] Patent Literature 3 discloses a quantum computing assembly, and related computing devices and methods. For example, in some embodiments, the quantum computing assembly includes a quantum device die for generating a plurality of quantum bits, a control circuit die for controlling the operation of the quantum device die, and a substrate, where the quantum device die and the control circuit die are disposed on the substrate.

[0010] In fact, there have been reports of demonstration experiments in which several MOS transistor structures are arranged to function as a small-scale quantum computer. Because hundreds of millions of MOS transistors have already been successfully integrated into commercial-level semiconductors, the use of MOS transistors as the physical media for quantum bits is also seen as promising from the perspective of quantum bit integration. Furthermore, MOS transistor-based quantum bits are expected to have advantages from the perspective of computation.

[0011] In other words, it is possible to layout the qubits and the peripheral circuits that control them on the same silicon. The integration of qubits and their control circuits is expected to help resolve the problem of the explosion in the number of wires between the qubits and control devices, which is currently one of the factors limiting the number of qubits.

[0012] Japanese Patent Publication No. 2022-130893 Japanese Patent Publication No. 2021-027142 US2019 / 0194016 A1

[0013] According to the inventor's investigations, when forming a quantum bit in a silicon channel, it has been found that multiple quantum bits may be formed on the upper sidewall of the channel, resulting in multiple quantum bits being formed in one transistor.

[0014] Quantum bit operations are based on the premise that they operate on a single quantum bit. If multiple quantum bits are formed in a channel, controlling a single gate will operate on multiple quantum bits, making it impossible to perform accurate quantum bit operations. The objective of this invention is to perform quantum bit operations with high precision.

[0015] A preferred embodiment of the present invention that achieves the above-mentioned object is a semiconductor quantum device that includes a transistor having a stacked structure of a semiconductor, an insulator, and a conductor to form a quantum bit, wherein at least a part of the conductor forms the gate electrode of the transistor, and at least a part of the semiconductor forms the channel of the transistor, and in a cross section perpendicular to the channel direction of the transistor, the semiconductor has a protrusion on the gate electrode side and is surrounded by the insulator, the protrusion forms the channel, and the width of the side of the protrusion facing the semiconductor is 20 nm or less.

[0016] Another preferred embodiment of the present invention that achieves the above object is a quantum computer comprising a memory device, a general arithmetic unit, a control unit, an input unit, an output unit, and a quantum arithmetic unit, wherein the quantum arithmetic unit controlled by the control unit is composed of the semiconductor quantum device described above.

[0017] The present invention can perform quantum bit operations with high precision.

[0018] 1. Three-sided views of a device according to an embodiment. Flow diagram of a device manufacturing. Flow diagram of a device manufacturing. Flow diagram of a device manufacturing. Flow diagram of a device manufacturing. Flow diagram of a device manufacturing. Flow diagram of a device manufacturing. Flow diagram of a device manufacturing. Flow diagram of a device manufacturing. Flow diagram of a device manufacturing. Flow diagram of a device manufacturing. Diagram of a potential map in a silicon cross section. Table diagram showing a potential map and a three-dimensional amplitude map for a channel width of 10 nm. Table diagram showing a potential map and a three-dimensional amplitude map for a channel width of 20 nm. Table diagram showing a potential map and a three-dimensional amplitude map for a channel width of 30 nm. Table diagram showing a potential map and a three-dimensional amplitude map for a channel width of 50 nm. Graphical diagram showing the relationship between channel width and electron energy. Conceptual diagram defining the scale of a device according to an embodiment. Equivalent circuit diagram of a device according to an embodiment. Map diagram of the stable electron number. Table diagram showing various characteristics of a device according to an embodiment. Cross-sectional view of a device according to a third embodiment. Cross-sectional view of a device according to a fourth embodiment. Block diagram of the configuration of a quantum computer according to a fifth embodiment.

[0019] The following describes the embodiments in detail with reference to the drawings. However, the present invention should not be construed as being limited to the description of the embodiments shown below. Those skilled in the art will readily understand that the specific configurations of the present invention can be modified within the scope of the concept and purpose of the present invention.

[0020] In the configuration of the invention shown below, the same parts or parts with similar functions are designated by the same reference numerals in different drawings, and redundant explanations may be omitted. When there are multiple elements with the same or similar functions, they may be explained with different subscripts. However, in some cases, the subscripts may be omitted.

[0021] The terms "first," "second," "third," etc. used in this specification are used to identify components and do not necessarily limit the number, order, or content of the components. Furthermore, numbers used to identify components are used in different contexts, and numbers used in one context do not necessarily indicate the same configuration in another context. Furthermore, a component identified by a certain number does not preclude consideration of the function of a component identified by another number.

[0022] In order to facilitate understanding of the invention, the position, size, shape, range, etc. of each component shown in the drawings etc. may not represent the actual position, size, shape, range, etc. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings etc.

[0023] In order to facilitate understanding of the invention, the position, size, shape, range, etc. of each component shown in the drawings, etc. may not represent the actual position, size, shape, range, etc. Therefore, the present invention is not necessarily limited to the position, size, shape, range, etc. disclosed in the drawings, etc.

[0024] By employing the means described in the following embodiments, it is possible to realize a quantum computer suitable for expanding the number of quantum bits, in which quantum bits and the circuits that control them are integrated on the same silicon.

[0025] An example of a specific device structure includes a silicon layer, a silicon channel provided in the silicon layer, and a gate electrode above the silicon layer that controls quantum bits or interactions between quantum bits, with the silicon channel having a top surface, i.e., a side facing the gate electrode, having a length of 20 nm or less. This configuration makes it possible to form a single quantum dot in the silicon channel with high precision. This makes it easy to trap a single electron used as a quantum bit. Therefore, one quantum dot can be formed with high precision in one transistor.

[0026] 1 shows a top view of the xy plane of a semiconductor device according to an embodiment, and cross-sectional views in the xz and yz directions. The xz cross-sectional view shows the A-A' cross section of the xy top view, and the yz cross-sectional view shows the B-B' cross section of the xy top view. The x, y, and z coordinate axes are shown in the figure, and the origin of the coordinates is indicated by a black circle in the cross-sectional view.

[0027] In the yz cross section of FIG. 1, a fin-shaped silicon channel CH is formed in a silicon substrate 103, and a SiO ２ The figure shows that five gate electrodes 101 are arranged with an insulator 102, such as a silicon substrate 103, sandwiched between them. Here, the fin-type structure refers to a structure in which, as shown in the y-z cross-sectional view of Figure 1, the channel portion made of silicon substrate 103 protrudes from the gate electrode 101 like a fish fin to form a protrusion, and the protrusion is surrounded by the insulator 102. Here, the number of gate electrodes 101 made of, for example, polysilicon is merely an example. Although the gate electrodes 101 are exposed in the top view, they may actually be covered with an insulating layer or wiring layer, not shown.

[0028] In FIG. 1 , a fin-shaped silicon channel CH formed so that the channel extends in the x-direction is disclosed in, for example, Patent Document 2, and quantum dot transistors that hold quantum bits and barrier transistors that form potential barriers can be alternately arranged along the silicon channel. For example, quantum dot control gate electrodes 101g of the quantum dot transistors and interaction control gate electrodes 101b of the barrier transistors are alternately arranged so as to intersect with the silicon channel CH. For specific examples of the device configuration and control of transistors for operating quantum bits, please refer to Patent Document 2, etc., and a detailed description will not be given here.

[0029] 2A to 2H are yz cross-sectional views showing the manufacturing process of the device structure shown in Fig. 1. These processes can basically be carried out by following the current manufacturing techniques for various semiconductor devices.

[0030] In FIG. 2A, first, a silicon substrate 103 is prepared. In FIG. 2B, a resist 201 is applied onto the silicon substrate 103. In FIG. 2C, the resist 201 is covered with a mask 202 and then exposed to light 203. In FIG. 2D, the resist 201 is developed and removed from areas other than the exposed area. In FIG. 2E, the silicon substrate 103 is etched using the resist 201 as a mask to form a fin-shaped shape. In FIG. 2F, the resist 201 is removed. In FIG. 2G, a SiO ２ In FIG. 2H, a gate electrode 101 made of polysilicon or the like is disposed.

[0031] A silicon channel CH is formed in the vicinity of the gate electrode 101 and the silicon substrate 103, forming a transistor. Electrons can be captured in this transistor, and quantum bits can be realized by controlling the electron spin.

[0032] Although the process has been described above using silicon semiconductors as an example, the material does not need to be limited to silicon as long as a transistor that performs similar functions can be formed.

[0033] The above process can produce the device shown in Figure 1. However, when a voltage is applied to the gate electrode 101 of the device produced in this way, undesirable electric field concentration may occur.

[0034] Figure 3 shows a potential map of the approximately square silicon channel CH portion, surrounded by a black line, in the yz cross section of the device. The negative side of the electric field distribution is shown in white and the positive side in black. The gray area outside the channel does not show the electric field distribution. As in Figure 1, the yz coordinate axes are indicated by arrows, and the origin of the coordinates is indicated by a black circle. In this example, the silicon channel CH, shown as an approximately square, has a channel width of approximately 50 nm, and a positive potential is applied to the gate electrode 101, which is approximately 2 nm away from the silicon channel CH in the z direction. As shown in Figure 3, the resulting potential distribution shows that the electric field is concentrated at the corners of the silicon channel CH in the yz cross section. In other words, electrons are easily trapped at corners where the electric field distribution is steep.

[0035] 4A to 4D are diagrams showing the states of electrons forming quantum bits in the silicon channel directly below the quantum dot control gate electrode 101g of a quantum dot transistor. These diagrams show potential maps and three-dimensional amplitude maps of the electron wave function when the channel width is varied from 10 nm (FIG. 4A), 20 nm (FIG. 4B), 30 nm (FIG. 4C), and 50 nm (FIG. 4D) through simulation.

[0036] In the potential map, the channel direction (x direction) is indicated by an arrow, and the potential distribution in the channel direction cross section (xz cross section) is shown on the left, and the channel width direction cross section (yz cross section) is shown on the right. The scale is interpreted in the same way as in Figure 3. The 0 position on the vertical axis (indicated by a thick horizontal line) indicates the top surface position of the channel, and the length in the channel direction (x direction) was set to approximately 40 nm. Specifically, the gate length was fixed at 40 nm, and calculations were performed under conditions where only the channel width was changed.

[0037] In the three-dimensional amplitude map of the electron wave function, the range corresponding to the cross section of the potential map in the channel width direction is shown. The 0 position of the vertical axis (upper left of the map) indicates the position of the top surface of the channel, and the vertical (z direction) is approximately 6 × 10 －８ m (=approximately 60 nm), width (channel width) approximately 4 × 10 －８The range of 100 nm (=approximately 40 nm) is shown.

[0038] In the potential maps, when the channel width is 50 nm (FIG. 4D) and 30 nm (FIG. 4C), the electric field is concentrated at the corners of the channel in the cross section in the channel width direction. On the other hand, when the channel width is 20 nm (FIG. 4B) and 10 nm (FIG. 4A), the electric field is relatively uniform in the upper part of the channel, i.e., on the side facing the gate electrode, in the cross section in the channel width direction.

[0039] In the three-dimensional amplitude map of the electron wave function, when the channel width is 50 nm (FIG. 4D) and 30 nm (FIG. 4C), the region where electrons exist, shown by the gray oval region, is separated into left and right in the channel width direction (the figure shows the electron position on the right side. Although not shown, electrons also exist in a symmetrical position on the left side). On the other hand, when the channel width is 20 nm (FIG. 4B), the electrons are concentrated at the center of the channel in the channel width direction. When the channel width is 10 nm (FIG. 4A), the electrons are further concentrated at the center of the channel.

[0040] Figure 5 shows the relationship between the channel width W and the lowest energy E1 and the next lowest energy E2 of electrons trapped in a transistor, calculated by numerically calculating the electrons trapped in the transistor. Here, the energy reference is E1. When the channel width W is 50 nm, E1 and E2 are almost equal. This indicates that the width of the silicon channel CH is wide enough for electrons, and that different electrons are trapped at each corner. The diagram in the graph shows the yz cross section of the channel, showing the state of electrons e in the silicon channel CH.

[0041] However, when the channel width W is less than 20 nm, a significant difference appears between E1 and E2. This indicates that the width of the silicon channel CH becomes narrow enough for electrons to capture only one electron.

[0042] To use a MOS transistor as a quantum dot transistor, one MOS transistor must constitute one quantum bit. In other words, one MOS transistor needs to capture only one electron. From this perspective, the results of numerical experiments indicate that the width of the silicon channel CH must be limited to 20 nm or less. It is believed that single electron capture is possible if the width of the silicon channel CH is between 0.1 nm and 20 nm, which is the atomic dimension.

[0043] Regarding the width of the silicon channel CH, it is important to control the width of the surface facing the gate electrode, but it is also desirable to narrow the width of portions other than the surface facing the gate electrode.

[0044] As mentioned above, in order to use a MOS transistor as the physical media of a quantum bit, the width of the silicon channel CH must be 20 nm or less on the side facing the gate electrode. Furthermore, when manipulating a quantum bit, the lowest energy E1 (ground state) is Zeeman split to control the state of the electron spin. In this case, the ground state is split by ΔE ｚ = 83 μeV. In order to prevent the transition from energy E1 to E2 as a result of Zeeman splitting, the gap between E1 and E2 is set to ΔE ｚ It is desirable to adopt a channel width W that can be made sufficiently larger. In this sense, the channel width W must be 30 nm or less, and preferably 20 nm or less.

[0045] Next, we will discuss the structural constraints that must be met for MOS transistors to tolerate output voltage variations in integrated circuits. Variations in control voltage in integrated circuits are thought to be caused by atomic-level shape variations and lattice defects that make up the transistors, and in principle, these nano-level variations become more apparent as miniaturization progresses. Therefore, improving the tolerance of artificial atoms to control voltages is technically viable. The tolerance of artificial atoms to voltage fluctuations depends on the device structure. Therefore, it is necessary to appropriately design the device structure to suit the integration described above.

[0046] One example of a specific solution is as follows: A MOS transistor is employed, which is a MOS transistor having a stacked structure of conductors, insulators, and silicon, in which, in a cross section perpendicular to the silicon channel direction of the MOS transistor, the silicon channel has a rectangular shape and is surrounded by an insulator, the silicon channel has a width of 5 nm or less, and the distance between adjacent gate electrodes is 5 nm or less. Considering the difficulty of formation, it is sufficient to reduce the silicon channel width to about 5 nm, and considering a processing variation of plus or minus 10%, a silicon channel width of 5.5 nm or less becomes the design standard.

[0047] 6A shows an xz cross-sectional view of a device similar to that shown in FIG. 1, along with the dimensions of each part of the cross-sectional view. The gate length of the interaction control gate electrode 101b of the barrier transistor is L ｂ , the thickness of the gate electrode is h ｂ The gate length of the quantum dot control gate electrode 101g of the quantum dot transistor is L ｇ The distance between the quantum dot control gate electrode 101g and the silicon substrate 103 (insulator thickness) is h ｇ The gate distance between the interaction control gate electrode 101b of the barrier transistor and the quantum dot control gate electrode 101g of the quantum dot transistor is set to s ｇ Let us consider an equivalent circuit to discuss the resistance of this transistor structure.

[0048] Quantum computers based on MOS transistors have already been demonstrated by several research institutions, but in all of these demonstrations, the voltage applied to the gate electrodes of the MOS transistors must be controlled with sub-millivolt precision in order for them to function as quantum computers.

[0049] However, it has been pointed out that it is difficult to suppress the variation in output voltage in an integrated circuit to 50 mV or less even with careful design. In other words, it is thought to be difficult to suppress the variation in voltage applied to the gate electrode that controls the quantum bit in a silicon quantum bit structure to 50 mV or less.

[0050] Integrating MOS transistors that function as quantum bits and their control circuits is an attractive configuration for creating a practical quantum computer, but actually using this integrated configuration as a quantum computer poses challenges in terms of tolerance to variations in the control voltage.

[0051] Fig. 6B shows an equivalent circuit corresponding to the structure of Fig. 6A. As shown in Fig. 6B, the artificial atom 401 is capacitively coupled to the gate electrode 101, the adjacent artificial atom 401, and the like.

[0052] 7 is a graph showing how the stable number of electrons in the artificial atom is determined with respect to the voltage applied to the quantum dot control gate electrode 101g as a result of the electrostatic capacitive coupling. Ｒ is the voltage applied to the quantum dot control gate electrode 101g (R), and V Ｌ is the voltage applied to the quantum dot control gate electrode 101g(L).

[0053] Each region in the figure shows the number of electrons e trapped in two artificial atoms 401L and 401R. When operating as a quantum computer, the size of each region 701 is related to the resistance to voltage fluctuations. Qualitatively, the larger the size of each region 701, the higher the resistance. The size of the region 701 is determined by the two parameters ΔV ｇ and ΔV ｍ It is characterized by ΔV ｇ and ΔV ｍ are expressed as Equations 1 and 2 using the parameters of the equivalent circuit diagram in FIG. 6B, where e is the elementary charge.

[0054]

[0055]

[0056] As is clear from Equation 1 and Equation 2, ΔV ｇ is ΔV ｍ Also, the parameter ΔV ｇ and ΔV ｍ When increasing C ｇ To make C small, ｍ The structure of the MOS transistor should be designed so that Cｇ In order to reduce ｇ or by increasing the spacing s ｇ On the other hand, it is effective to reduce C ｍ In order to increase the gate length L of the interaction control gate electrode 101b, ｂ It is effective to shorten the

[0057] Assuming that the voltage variation applied to the gate electrode is 50 mV, one design criterion is ΔV ｇ ≧0.9V, ΔV ｍ ≥ 10mV, the preferred design criteria is ΔV ｇ ≧0.9V, ΔV ｍ ≧100 mV.

[0058] Figure 8 shows that in some structures, ΔV ｇ and ΔV ｍ The structures that satisfy the above design criteria and have tolerance to a 50 mV variation in the output voltage of the integrated circuit are the bottom and second-to-bottom cases in the table of FIG. 8, and have a gate insulating film thickness h ｇ is 10 nm or more, and the spacing s between the gate electrodes 101 ｇ The most preferable case is the one at the bottom of the table in FIG. 8, in which the gate length L of the interaction control gate electrode 101b of the barrier transistor is 5 nm or less, and the channel width W of the silicon channel is 5 nm or less. ｂ is 20 nm or less.

[0059] 9 is a yz cross-sectional view of the device of Example 3. As described in Example 2, it is desirable to set the width of the silicon channel CH to 5 nm or less in order to enable one MOS transistor to capture one electron and further to control the electron under variations in the output voltage of the integrated circuit.

[0060] On the other hand, silicon channels with such high aspect ratios are structurally unstable and difficult to manufacture. From the viewpoint of manufacturing yield, a trapezoidal shape such as that shown in Figure 9 is desirable. However, in order to capture only one electron, the width from the surface of the silicon substrate 103 to 5 nm in the z direction (i.e., toward the base of the fin-shaped protrusion) should preferably be 20 nm or less.

[0061] If there is no problem with the difficulty of the process, it is desirable that the width from the surface of the silicon substrate 103 to 10 nm in the z direction be 20 nm or less. It is even more desirable that the width from the surface of the silicon substrate 103 to 20 nm in the z direction be 20 nm or less.

[0062] FIG. 10 is a yz cross-sectional view of the device of Example 4. As described in Example 2, reducing the capacitance between the gate electrode and trapped electrons is important for improving the tolerance of the integrated circuit to variations in output voltage. FIG. 10 shows the cross-sectional structure of the device that reduces capacitance. A feature of this structure is that the cross section of the gate electrode 101 is recessed near the silicon substrate 103. By configuring the gate electrode 101 in this manner, the capacitance between the gate electrode 101 and trapped electrons can be reduced.

[0063] An example of a quantum computer according to this embodiment is shown in Figure 11. While the configuration of Figure 11 is similar to that of a normal computer, it is characterized by the inclusion of a quantum processing unit 1000. The quantum processing unit 1000 implements quantum bits using the semiconductor quantum devices described in Examples 1 to 4, and is a unit dedicated to performing quantum mechanical operations. Other general operations are performed by a general processing unit 2002.

[0064] The above configuration may be configured as an integrated computer, or any part such as the main memory device 2001, general arithmetic unit 2002, control device 2003, auxiliary memory device 2004, input device 2005, and output device 2006 may be configured as another computer connected via a network.

[0065] General calculations are performed in the same manner as in a normal computer. Data is exchanged between the main memory device 2001, which is the storage unit, and the general calculation unit 2002, which is the calculation unit, and calculations are carried out by repeating this process. The control unit 2003 is responsible for directing the entire process. Programs executed by the general calculation unit 2002 are stored in the main memory device 2001, which is the storage unit. If the main memory device 2001 does not have enough storage capacity, the auxiliary memory device 2004, which is also a storage unit, is used. An input device 2005 is used to input data, programs, etc., and an output device 2006 is used to output the results. The input device 2005 includes a manual input device such as a keyboard, as well as an interface for network connection. This interface also serves as an output device.

[0066] Quantum operations are also performed in a similar manner. Data is exchanged between the main memory device 2001, which is the storage unit, and the quantum processing device 1000, which is the processing unit, and the operations are carried out by repeating this process. The control device 2003 directs the entire process. The program executed by the quantum processing device 1000 is stored in the main memory device 2001, which is the storage unit.

[0067] When the quantum operation device 1000 is controlled by the control device 2003, if the voltage variation applied to the gate electrode of the semiconductor quantum device exceeds 50 mV, high-precision operation becomes possible by designing the semiconductor quantum device based on the method described in Example 2.

[0068] The program is converted into code to be used by the quantum processing device 1000 using the general processing device 2002 and stored in the main memory device 2001. If there is insufficient storage capacity, the auxiliary storage device 2004, which is also a storage unit, is used. This encoded program is sent from the main memory device 2001 to the quantum processing device 1000, and the control device 2003 sends a control signal to the quantum processing device 1000 in accordance with the encoded program to execute the operation. The execution results of the quantum processing device 1000 are sent to the main memory device 2001 and are post-processed by the general processing device 2002 as necessary.

[0069] According to the above embodiment, it is possible to realize a quantum computer with low power consumption, which reduces energy consumption, reduces carbon emissions, prevents global warming, and contributes to the realization of a sustainable society.

[0070] CH: silicon channel W: channel width 101: gate electrode 101g: quantum dot control gate electrode 101b: interaction control gate electrode 102: insulator 103: silicon substrate 201: resist 202: mask 203: light 401: artificial atom

Claims

1. A semiconductor quantum device comprising a transistor having a stacked structure of a semiconductor, an insulator, and a conductor for forming a qubit, wherein at least a part of the conductor forms a gate electrode of the transistor, at least a part of the semiconductor forms a channel of the transistor, and in a cross section perpendicular to the channel direction of the transistor, the semiconductor has a protruding portion on the gate electrode side and is surrounded by the insulator therearound, the protruding portion forms the channel, and a width of a side of the protruding portion facing the semiconductor is 20 nm or less. A semiconductor quantum device.

2. The semiconductor quantum device according to claim 1, wherein the width of the side of the protruding portion facing the semiconductor is 0.1 nm or more.

3. The semiconductor quantum device according to claim 1, wherein the width of the side of the protruding portion facing the semiconductor is 10 nm or less.

4. The semiconductor quantum device according to claim 1, wherein the width of the side of the protruding portion facing the semiconductor is 5 nm or less.

5. The semiconductor quantum device according to claim 4, comprising a plurality of the transistors, the plurality of transistors including a quantum dot transistor for holding the qubit and a barrier transistor for controlling the qubit, the quantum dot transistor and the barrier transistor being alternately arranged in the channel direction, and the gate electrode of the quantum dot transistor and the gate electrode of the barrier transistor being separated by the insulator.

6. The thickness h of the insulator directly under the gate electrode of the quantum dot transistor ｇ is 10 nm or more, and the distance s ｇ between the gate electrodes of the quantum dot transistor and the barrier transistor is 5 nm or less. The semiconductor quantum device according to claim 5.

7. The gate length L of the gate electrode of the barrier transistor ｂ is 20 nm or less. The semiconductor quantum device according to claim 6.

8. The semiconductor quantum device according to claim 6, wherein a voltage variation applied to the gate electrode exceeds 50 mV.

9. The semiconductor quantum device according to claim 1, wherein in a range from a surface of the protruding portion facing the semiconductor to 5 nm toward the base of the protruding portion, the width of the protruding portion is 20 nm or less.

10. The semiconductor quantum device according to claim 9, wherein a cross-sectional shape of the protruding portion perpendicular to the channel direction is trapezoidal.

11. The semiconductor quantum device according to claim 9, wherein in a range from a surface of the protruding portion facing the semiconductor to 10 nm toward the base of the protruding portion, the width of the protruding portion is 20 nm or less.

12. The semiconductor quantum device according to claim 9, wherein in a range from a surface of the protruding portion facing the semiconductor to 20 nm toward the base of the protruding portion, the width of the protruding portion is 20 nm or less.

13. The semiconductor quantum device according to claim 1, wherein a gate electrode of the transistor protrudes toward the protruding portion of the semiconductor.

14. A quantum computer comprising a memory device, a general arithmetic device, a control device, an input device, an output device, and a quantum arithmetic device, wherein the quantum arithmetic device controlled by the control device is constituted by the semiconductor quantum device according to claim 1.

15. When controlling the quantum computing device by the control device, the voltage variation applied to the gate electrode exceeds 50 mV, the width of the protruding portion on the side facing the semiconductor is 5 nm or less, a plurality of the transistors are provided, and the plurality of transistors include a quantum dot transistor that holds the quantum bit and a barrier transistor that controls the quantum bit, the quantum dot transistor and the barrier transistor are alternately arranged in the channel direction, the gate electrode of the quantum dot transistor and the gate electrode of the barrier transistor are separated by the insulator, and the thickness h of the insulator directly under the gate electrode of the quantum dot transistor ｇ is 10 nm or more, and the distance s ｇ between the gate electrodes of the quantum dot transistor and the barrier transistor is 5 nm or less. The quantum computer according to claim 14.

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