Scan driving unit, and display device including same

Abstract

The present specification provides a scan driving unit, and a display device including same. The scan driving unit according to an embodiment includes stages sequentially outputting scan signals to scan signal lines in an active period of an N-th (N is a positive integer) frame, wherein at least one of the stages includes an output node control unit for supplying a gate-on voltage to a pull-up node in response to a gate control signal of a display driving unit, and an output node control unit for outputting a scan clock signal input to a scan clock terminal as a scan signal to each connected scan signal line when the gate-on voltage is supplied to the pull-up node. The output node control unit includes at least one thin film transistor including a first active layer and indirectly connected to the pull-up node, and at least one other thin film transistor including a second active layer including a heterogeneous oxide semiconductor material different from the first active layer and directly connected to the pull-up node.

Description

Scan drive unit and display device including the same

[0001] The present invention relates to a scan driving unit and a display device including the same.

[0002] As the information society develops, the demand for display devices for displaying images is increasing in various forms. For example, display devices are being used in various electronic devices such as smartphones, digital cameras, laptop computers, navigation systems, and smart televisions.

[0003] The display device may be a flat panel display device such as a liquid crystal display device, a quantum dot display device, an organic light emitting display device, or the like.

[0004] The display device includes a display panel including data lines, scan signal lines, a plurality of pixels connected to the data lines and the scan signal lines, a scan driver for supplying scan signals to the scan signal lines, and a data driver for supplying data voltages to the data lines.

[0005] The scan driver may be formed in a non-display area of ​​the display panel. The scan driver formed in the display panel includes a plurality of thin film transistors (TFTs) that turn on and off in response to gate control signals. Since the TFTs of the scan driver are maintained in a turned-on or turned-off state for a certain period of time, the operating conditions and other operating characteristics of the TFTs must be maintained constant.

[0006] The problem to be solved by the present invention is to provide a scan driver and a display device including the same that can reduce electrical stress of thin film transistors by improving the composition material of the semiconductor layer of thin film transistors that are subject to stress due to bootstrapping of current or voltage.

[0007] In addition, another problem to be solved by the present invention is to provide a scan driver capable of increasing or controlling electrical characteristics by improving the composition material of a semiconductor layer of at least one thin film transistor directly connected to a pull-up node of scan signal output stages, and a display device including the same.

[0008] The tasks of the present invention are not limited to the tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the description below.

[0009] According to one embodiment of the present invention for solving the above problem, a scan driver includes stages for sequentially outputting scan signals to scan signal wires during an active period of an Nth (N is a positive integer) frame, and at least one of the stages includes an output node control unit for supplying a gate-on voltage to a pull-up node in response to a gate control signal of the display driver, and an output control unit for outputting a scan clock signal input to a scan clock terminal as a scan signal to each connected scan signal wire when the gate-on voltage is supplied to the pull-up node.

[0010] The output node control unit includes at least one thin film transistor including a first active layer and indirectly connected to the pull-up node, and at least another thin film transistor including a second active layer including a hetero-oxide semiconductor material different from the first active layer and directly connected to the pull-up node.

[0011] According to one embodiment of the present invention for solving the above problem, a display device includes a plurality of pixels arranged in a display area of ​​a display panel, a touch sensing unit mounted on a front surface of the display panel or formed integrally with the display panel, a touch driving unit that detects a touch using a plurality of touch electrodes arranged in the touch sensing unit, a display driving unit that controls data voltages supplied to the plurality of pixels and image display timing of the pixels, and a scan driving unit that sequentially drives scan signal lines connected to the plurality of pixels in response to a gate control signal from the display driving unit.

[0012] The above scan driving unit includes stages for sequentially outputting scan signals to scan signal wires during an active period of an Nth (N is a positive integer) frame, and at least one of the stages includes an output node control unit for supplying a gate-on voltage to a pull-up node in response to a gate control signal of the display driving unit, and an output control unit for outputting a scan clock signal input to a scan clock terminal as a scan signal to each connected scan signal wire when the gate-on voltage is supplied to the pull-up node.

[0013] The output node control unit includes at least one thin film transistor including a first active layer and indirectly connected to the pull-up node, and at least another thin film transistor including a second active layer including a different oxide semiconductor material from the first active layer and directly connected to the pull-up node.

[0014] According to the scan driver and the display device including the same according to the embodiments, the electrical stress of the thin film transistors can be reduced and the reliability can be increased by improving the composition material of the semiconductor layer of the thin film transistors that are stressed due to bootstrapping of current or voltage, etc.

[0015] In addition, according to the scan driving unit and the display device including the same according to the embodiments, the composition material of the semiconductor layer of at least one thin film transistor directly connected to the pull-up node of the scan signal output stages can be improved to increase or stabilize electrical characteristics such as high-speed driving, suppression of operating range fluctuations, and threshold voltage fluctuations.

[0016] The effects according to the embodiments are not limited to those exemplified above, and more diverse effects are included in this specification.

[0017] FIG. 1 is a perspective view showing a display device according to one embodiment.

[0018] Fig. 2 is a cross-sectional view showing a display device according to one embodiment.

[0019] Fig. 3 is a plan view showing a display unit of a display device according to one embodiment.

[0020] FIG. 4 is a block diagram showing a display panel and a display driver according to one embodiment.

[0021] FIG. 5 is an exemplary drawing showing a scan driving unit according to one embodiment of the present invention.

[0022] FIG. 6 is a circuit diagram of the first embodiment specifically showing the nth stage of the scan driving unit illustrated in FIG. 5.

[0023] Figure 7 is a waveform diagram showing changes in the voltage magnitude of sensing control signals, scan clock signals, and pull-up nodes during the active period of the Nth frame period.

[0024] Fig. 8 is a circuit diagram of a second embodiment specifically showing the nth stage of the scan driving unit illustrated in Fig. 5.

[0025] Fig. 9 is a cross-sectional view showing the cross-sectional structure of the first and sixth transistors of the scan driver illustrated in Fig. 8.

[0026] FIG. 10 is a drawing of another embodiment showing the nth stage illustrated in FIG. 8.

[0027] Fig. 11 is a cross-sectional view showing the cross-sectional structure of the fourth and sixth transistors of the scan driver illustrated in Fig. 10.

[0028] FIG. 12 and FIG. 13 are perspective views showing application examples of a display device according to one embodiment of the present invention.

[0029] FIG. 14 and FIG. 15 are perspective views showing application examples of a display device according to another embodiment of the present invention.

[0030] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0031] When elements or layers are referred to as being "on" another element or layer, this includes both cases where the other element or layer is directly on top of the other element or layer or intervening therebetween. Like reference numerals refer to like elements throughout the specification. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments are illustrative and therefore the present invention is not limited to the matters illustrated.

[0032] Although terms like "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it should be understood that a "first" component referred to below may also be a "second" component within the technical scope of the present invention.

[0033] The individual features of the various embodiments of the present invention can be partially or wholly combined or combined with each other, and various technical linkages and operations are possible, and each embodiment can be implemented independently of each other or implemented together in a related relationship.

[0034] Specific embodiments are described below with reference to the attached drawings.

[0035] FIG. 1 is a perspective view showing a display device according to one embodiment.

[0036] Referring to FIG. 1, the display device (10) can be applied to portable electronic devices such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, an ultra mobile PC (UMPC), etc. For example, the display device (10) can be applied as a display unit of a television, a laptop, a monitor, a billboard, or the Internet of Things (IOT). As another example, the display device (10) can be applied to a wearable device such as a smart watch, a watch phone, a glasses-type display, and a head mounted display (HMD).

[0037] The display device (10) may have a planar shape similar to a rectangle. For example, the display device (10) may have a planar shape similar to a rectangle having a short side in a first direction (DR1) and a long side in a second direction (DR2). The corner where the short side in the first direction (DR1) and the long side in the second direction (DR2) meet may be formed to be rounded to have a predetermined curvature or formed at a right angle. The planar shape of the display device (10) is not limited to a rectangle, and may be formed to be similar to other polygons, circles, or ovals.

[0038] The display device (10) may include a display panel (100), a display driver (200), a circuit board (300), a touch driver (400), and a power supply (500).

[0039] The display panel (100) may include a main area (MA) and a sub area (SBA).

[0040] The main area (MA) may include a display area (DA) having pixels for displaying an image, and a non-display area (NDA) arranged around the display area (DA). The display area (DA) may emit light from a plurality of light-emitting areas or a plurality of aperture areas. For example, the display panel (100) may include a pixel circuit including switching elements, a pixel definition film defining a light-emitting area or an aperture area, and a self-light emitting element.

[0041] For example, the self-luminous element may include, but is not limited to, at least one of an organic light emitting diode (OLED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED.

[0042] The non-display area (NDA) may be an area outside the display area (DA). The non-display area (NDA) may be defined as an edge area of ​​the main area (MA) of the display panel (100). The non-display area (NDA) may include a gate driver (not shown) that supplies gate signals to gate lines, and fan-out lines (not shown) that connect the display driver (200) and the display area (DA).

[0043] The sub-area (SBA) may extend from one side of the main area (MA). The sub-area (SBA) may include a flexible material capable of bending, folding, rolling, etc. For example, when the sub-area (SBA) is bent, the sub-area (SBA) may overlap the main area (MA) in the thickness direction (e.g., the third direction (DR3)). The sub-area (SBA) may include a display driver (200) and a pad portion connected to a circuit board (300). Optionally, the sub-area (SBA) may be omitted, and the display driver (200) and the pad portion may be disposed in a non-display area (NDA).

[0044] The display driver (200) can output signals and voltages for driving the display panel (100). The display driver (200) can supply data voltages to data lines (DL). The display driver (200) can supply a power voltage to a power line and supply a gate control signal to a scan driver (or gate driver). The display driver (200) can be formed as an integrated circuit (IC) and mounted on the display panel (100) using a COG (Chip on Glass) method, a COP (Chip on Plastic) method, or an ultrasonic bonding method. For example, the display driver (200) can be placed in the sub-area (SBA) and can overlap the main area (MA) in the thickness direction (third direction (DR3)) by bending the sub-area (SBA). As another example, the display driver (200) can be mounted on a circuit board (300).

[0045] The circuit board (300) may be attached to the pad portion of the display panel (100) using an anisotropic conductive film (ACF). Lead lines of the circuit board (300) may be electrically connected to the pad portion of the display panel (100). The circuit board (300) may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0046] The touch driver (400) may be mounted on the circuit board (300). The touch driver (400) may be electrically connected to the touch sensing unit of the display panel (100). The touch driver (400) may supply a touch driving signal to a plurality of touch electrodes of the touch sensing unit and sense a change in electrostatic capacity between the plurality of touch electrodes. For example, the touch driving signal may be a pulse signal having a predetermined frequency. The touch driver (400) may calculate whether an input has occurred and the input coordinates based on the change in electrostatic capacity between the plurality of touch electrodes. The touch driver (400) may be formed as an integrated circuit (IC).

[0047] The power supply unit (500) can be arranged on the circuit board (300) and supply power voltage to the display driver unit (200) and the display panel (100). The power supply unit (500) can generate a first driving voltage and supply it to a first driving voltage line (VDL), generate an initialization voltage and supply it to the initialization voltage line, and generate a common voltage and supply it to a common electrode common to light-emitting elements of a plurality of pixels (PX). For example, the first driving voltage can be a high-potential voltage for driving the light-emitting elements, and the common voltage and the second driving voltage can be low-potential voltages for driving the light-emitting elements.

[0048] Fig. 2 is a cross-sectional view showing a display device according to one embodiment.

[0049] Referring to FIG. 2, the display panel (100) may include a display unit (DU), a touch sensing unit (TSU), and a color filter layer (CFL). The display unit (DU) may include a substrate (SUB), a thin film transistor layer (TFTL), a light emitting element layer (ETML), and an encapsulation layer (TFEL).

[0050] The substrate (SUB) may be a base substrate or a base member. The substrate (SUB) may be a flexible substrate capable of bending, folding, rolling, etc. For example, the substrate (SUB) may include a polymer resin such as polyimide (PI), but is not limited thereto. In another example, the substrate (SUB) may include a glass material or a metal material.

[0051] A thin film transistor layer (TFTL) may be disposed on a substrate (SUB). The thin film transistor layer (TFTL) may include a plurality of thin film transistors constituting a pixel circuit of pixels (PX). The thin film transistor layer (TFTL) may further include gate lines (GL), data lines (DL), power lines, gate control lines (GLS1, GLS2), fan out lines (FL) connecting the display driver (200) and the data lines (DL), and lead lines connecting the display driver (200) and the pad portion. Each of the thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when the scan driver (610, for example, a gate driver) is formed on one side of the non-display area (NDA) of the display panel (100), the scan driver may include thin film transistors.

[0052] A thin film transistor layer (TFTL) can be arranged in a display area (DA), a non-display area (NDA), and a sub-area (SBA). Thin film transistors, gate lines, data lines (DL), and power lines of each pixel of the thin film transistor layer (TFTL) can be arranged in the display area (DA). Gate control lines (GLS1, GLS2) and fan out lines (FL) of the thin film transistor layer (TFTL) can be arranged in the non-display area (NDA). Lead lines of the thin film transistor layer (TFTL) can be arranged in the sub-area (SBA).

[0053] The light emitting element layer (EMTL) may be disposed on the thin film transistor layer (TFTL). The light emitting element layer (EMTL) may include a plurality of light emitting elements that emit light, in which a pixel electrode, a light emitting layer, and a common electrode are sequentially laminated, and a pixel definition film that defines pixels. The plurality of light emitting elements of the light emitting element layer (ETML) may be disposed in the display area (DA).

[0054] The light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transporting layer, an organic light-emitting layer, and an electron transporting layer. When the pixel electrode receives a predetermined voltage through a thin film transistor of a thin film transistor layer (TFTL) and the common electrode receives a cathode voltage, holes and electrons may move to the organic light-emitting layer through the hole transporting layer and the electron transporting layer, respectively, and may combine with each other in the organic light-emitting layer to emit light. For example, the pixel electrode may be an anode electrode and the common electrode may be a cathode electrode, but is not limited thereto.

[0055] For another example, the plurality of light-emitting elements may include quantum dot light-emitting diodes including quantum dot light-emitting layers, inorganic light-emitting diodes including inorganic semiconductors, or micro-light-emitting diodes.

[0056] The encapsulation layer (TFEL) can cover the top and side surfaces of the light-emitting element layer (EMTL) and protect the light-emitting element layer (EMTL). The encapsulation layer (TFEL) can include at least one inorganic film and at least one organic film for encapsulating the light-emitting element layer (EMTL).

[0057] The touch sensing unit (TSU) may be disposed on the encapsulation layer (TFEL). The touch sensing unit (TSU) may include a plurality of touch electrodes for detecting a user's touch using a capacitive method, and touch lines connecting the plurality of touch electrodes and the touch driver (400). For example, the touch sensing unit (TSU) may sense a user's touch using a mutual capacitance method or a self-capacitance method.

[0058] For another example, the touch sensing unit (TSU) may be placed on a separate substrate placed on the display unit (DU). In this case, the substrate supporting the touch sensing unit (TSU) may be a base member encapsulating the display unit (DU).

[0059] A plurality of touch electrodes of a touch sensing unit (TSU) may be arranged in a touch sensor area overlapping a display area (DA). Touch lines of the touch sensing unit (TSU) may be arranged in a touch peripheral area overlapping a non-display area (NDA).

[0060] A color filter layer (CFL) may be disposed on the touch sensing unit (TSU). The color filter layer (CFL) may include a plurality of color filters corresponding to each of a plurality of light-emitting regions. Each of the color filters may selectively transmit light of a specific wavelength and block or absorb light of a different wavelength. The color filter layer (CFL) may absorb a portion of light entering from the outside of the display device (10) to reduce light reflected by external light. Therefore, the color filter layer (CFL) may prevent color distortion due to reflection of external light.

[0061] Since the color filter layer (CFL) is directly disposed on the touch sensing unit (TSU), the display device (10) may not require a separate substrate for the color filter layer (CFL). Accordingly, the thickness of the display device (10) can be relatively reduced.

[0062] The sub-area (SBA) of the display panel (100) may extend from one side of the main area (MA). The sub-area (SBA) may include a flexible material capable of bending, folding, rolling, etc. For example, when the sub-area (SBA) is bent, the sub-area (SBA) may overlap the main area (MA) in the thickness direction (third direction (DR3)). The sub-area (SBA) may include a pad portion electrically connected to the display driver (200) and the circuit board (300).

[0063] Fig. 3 is a plan view showing a display unit of a display device according to one embodiment. Fig. 4 is a block diagram showing a display panel and a display driver according to one embodiment.

[0064] Referring to FIGS. 3 and 4, the display panel (100) may include a display area (DA) and a non-display area (NDA).

[0065] The display area (DA) may include a plurality of pixels (PX), a plurality of first driving voltage lines (VDL) connected to the plurality of pixels (PX), a plurality of gate lines (GL) of a plurality of second driving voltage lines, a plurality of emission control lines (EML), and a plurality of data lines (DL).

[0066] Each of the plurality of pixels (PX) may be connected to a gate line (GL), a data line (DL), a light emission control line (EML), a first driving voltage line (VDL), and a second driving voltage line. Each of the plurality of pixels (PX) may include at least one transistor, a light emitting element, and a capacitor.

[0067] Each of the gate lines (GL) may extend in a first direction (DR1) and may be spaced apart from each other in a second direction (DR2) intersecting the first direction (DR1). The gate lines (GL) may be arranged along the second direction (DR2). The gate lines (GL) may sequentially supply gate signals to a plurality of pixels (PX).

[0068] Each of the emission control lines (EML) can extend in a first direction (DR1) and be spaced apart from each other in a second direction (DR2). The emission control lines (EML) can be arranged along the second direction (DR2). The emission control lines (EML) can sequentially supply emission control signals to a plurality of pixels (PX).

[0069] The data lines (DL) can extend in a second direction (DR2) and be spaced apart from each other in a first direction (DR1). The data lines (DL) can be arranged along the first direction (DR1). The data lines (DL) can supply data voltages to a plurality of pixels (PX). The data voltages can determine the brightness of each of the plurality of pixels (PX).

[0070] Each of the first driving voltage lines (VDL) may extend in the second direction (DR2) and may be spaced apart from each other in the first direction (DR1). The first driving voltage lines (VDL) may be arranged along the first direction (DR1). The first driving voltage lines (VDL) may supply a first driving voltage to a plurality of pixels (PX). The first driving voltage may be a high-potential voltage for driving light-emitting elements of the pixels (PX).

[0071] A non-display area (NDA) may surround a display area (DA). The non-display area (NDA) may include a scan driver (610), a light emission control driver (620), fan out lines (FL), a first gate control line (GSL1), and a second gate control line (GSL2).

[0072] Fan out lines (FL) can extend from the display driver (200) to the display area (DA). The fan out lines (FL) can supply data voltages received from the display driver (200) to a plurality of data lines (DL).

[0073] The first gate control line (GSL1) can extend from the display driver (200) to the scan driver (610). The first gate control line (GSL1) can supply a gate control signal (GCS) received from the display driver (200) to the scan driver (610).

[0074] The second gate control line (GSL2) can extend from the display driver (200) to the light emission control driver (620). The second gate control line (GSL2) can supply the light emission control signal (ECS) received from the display driver (200) to the light emission control driver (620).

[0075] The sub-area (SBA) may extend from one side of the non-display area (NDA). The sub-area (SBA) may include a display driver (200) and a pad portion (DP). The pad portion (DP) may be positioned closer to one edge of the sub-area (SBA) than the display driver (200). The pad portion (DP) may be electrically connected to a circuit board (300) via an anisotropic conductive film (ACF).

[0076] The display driving unit (200) may include a timing control unit (210) and a data driving unit (220).

[0077] The timing control unit (210) can receive digital video data (DATA) and timing signals from the circuit board (300). The timing control unit (210) can generate a data control signal (DCS) based on the timing signals to control the operation timing of the data driver (220), generate a gate control signal (GCS) to control the operation timing of the scan driver (610), and generate an emission control signal (ECS) to control the operation timing of the emission control driver (620). The timing control unit (210) can supply the gate control signal (GCS) to the scan driver (610) through a first gate control line (GSL1). The timing control unit (210) can supply the emission control signal (ECS) to the emission control driver (620) through a second gate control line (GSL2). The timing control unit (210) can supply digital video data (DATA) and a data control signal (DCS) to the data driving unit (220).

[0078] The data driver (220) can convert digital video data (DATA) into analog data voltages and supply them to data lines (DL) through fan out lines (FL). The gate signals of the scan driver (610) can select pixels (PX) to which data voltages are supplied, and the selected pixels (PX) can receive the data voltages through the data lines (DL).

[0079] The power supply unit (500) is arranged on the circuit board (300) and can supply power voltage to the display driver unit (200) and the display panel (100). The power supply unit (500) can generate a first driving voltage and supply it to a first driving voltage line (VDL), generate an initialization voltage and supply it to an initialization voltage line (VIL), and generate a common voltage and supply it to a common electrode common to light-emitting elements of a plurality of pixels (PX).

[0080] The scan driver (610) may be positioned on one outer side of the display area (DA) or on one side of the non-display area (NDA), and the light emission control driver (620) may be positioned on the other outer side of the display area (DA) or on the other side of the non-display area (NDA), but is not limited thereto. For another example, the scan driver (610) and the light emission control driver (620) may be positioned on either one side or the other side of the non-display area (NDA).

[0081] The scan driver (610) may include a plurality of transistors that generate gate signals based on a gate control signal (GCS). The light emission control driver (620) may include a plurality of transistors that generate light emission control signals based on a light emission control signal (ECS). For example, the transistors of the scan driver (610) and the transistors of the light emission control driver (620) may be formed on the same layer as the transistors of each of the pixels (PX). The scan driver (610) may supply gate signals to the gate lines (GL), and the light emission control driver (620) may supply light emission control signals to the light emission control lines (EML).

[0082] FIG. 5 is an exemplary drawing showing a scan driving unit according to one embodiment of the present invention.

[0083] Referring to FIG. 5, a scan driver (610) according to one embodiment includes a plurality of stages, i.e., n-th stages (STn), that are cascadedly connected to each other. Here, n is a positive integer.

[0084] For convenience of explanation, in Fig. 5, only the n-2 to n+2 stages (STn-2 to STn+2) are illustrated based on the n-th stage (STn).

[0085] In the following description, a "preceding stage" refers to a stage located before a reference n-th stage (STn). A "successive stage" refers to a stage located after a reference n-th stage (STn). For example, the stages preceding the n-th stage (STn) refer to the n-1-th stage (STn-1), and the stages subsequent to the n-th stage (STn) refer to the n+1-th stage (STn+1).

[0086] On one side of the n-2 to n+2 stages (STn-2 to STn+2), scan clock wires to which a plurality of scan clock signals (CLK1, CLK2) whose phases are sequentially delayed or sequentially alternated are respectively applied, and sensing control wires to which a start signal (ST), a line select signal (ES), and a reset signal are respectively applied can be respectively arranged.

[0087] Scan clock signals (CLK1, CLK2), line selection signal (ES), start signal (ST), and reset signals may be gate control signals (GCS) generated from the display driver (200) and transmitted through the first gate control lines (GSL1). In Fig. 5, two scan clock lines, two sensing control lines, and two power lines are exemplified as the first gate control lines (GSL1), but the number of scan clock lines and sensing control lines is not limited thereto.

[0088] The scan driver (610) includes n-2 to n+2 stages (STn-2 to STn+2) respectively connected to the first gate control lines (GSL1). Among the n-th stages (STn), the n-2nd stage (STn-2) outputs an n-2nd scan signal (SCn-2) to the n-2nd scan signal wire (SCLn-2), and the n-1st stage (STn-1) outputs an n-1st scan signal (SCn-1) to the n-1st scan signal wire (SCLn-1). Therefore, the nth stage (STn) can output the nth scan signal (SCn) to the nth scan signal wire (SCLn). Next, the n+1-th stage (STn+1) outputs the n+1-th scan signal (SCn+1) to the n+1-th scan signal wire (SCLn+1), and the n+2-th stage (STn+2) outputs the n+2-th scan signal (SCn+2) to the n+2-th scan signal wire (SCLn+2).

[0089] Each of the n-2 to n+2 stages (STn-2 to STn+2) includes a front-end carry terminal (CPI), a rear-end carry terminal (CNI), a first scan clock terminal (SCI1), a second scan clock terminal (SCI2), a first power supply terminal (SSI1), a second power supply terminal (SSI2), a sensing signal terminal (RSI), and a scan output terminal (SCO).

[0090] When the n-2 stage (STn-2) is the first stage, a start signal (ST) can be input to the preceding carry terminal (CPI) of the n-2 stage (STn-2) through a start signal wiring. Each stage connected in a cascaded manner after the first stage, excluding the first stage, can have its preceding carry terminal (CPI) connected to the scan output terminal (SCO) of the stage located immediately preceding it. For example, as shown in Fig. 5, the preceding carry terminal (CPI) of the n-th stage (STn) can be connected to the scan output terminal (SCO) of the n-1 stage (STn-1).

[0091] The rear carry terminal (CNI) of each of the n-2 to n+2 stages (STn-2 to STn+2) can be connected to the scan output terminal (SCO) of any of the rear stages. For example, as shown in Fig. 5, the rear carry terminal (CNI) of the n-th stage (STn) can be connected to the scan output terminal (SCO) of the n+1-th stage (STn+1) so as to receive the scan signal (SCn+1) of the n+1-th stage (STn+1) as the rear carry signal.

[0092] The scan output terminals (SCO) of each of the n-2 to n+2 stages (STn-2 to STn+2) are sequentially connected to the scan signal lines (SCL), which are the corresponding gate lines (GL). Therefore, the scan signal lines (SCLs) can be connected one-to-one to the scan output terminals (SCOs) of each of the stages (STn-2 to STn+2). For example, the n-1 scan signal line (SCLn-1) is connected to the scan output terminal (SCO) of the n-th stage (STn-1), and the n-th scan signal line (SCLn) is connected to the scan output terminal (SCO) of the n-th stage (STn). In addition, the n+1 scan signal line (SCLn+1) can be connected to the scan output terminal (SCO) of the n+1 stage (STn+1).

[0093] The sensing signal terminal (RSI) of each of the n-2 to n+2 stages (STn-2 to STn+2) receives a line selection signal (ES) through a sensing control wire to which the line selection signal (ES) is applied.

[0094] Each of the n-2 to n+2 stages (STn-2 to STn+2) sequentially or alternately receives two scan clock signals, i.e., scan clock signals (CLK1, CLK2), whose phases are sequentially alternated or delayed, through the first scan clock terminal (SCI1) and the second scan clock terminal (SCI2).

[0095] For example, each of the n-2 to n+2 stages (STn-2 to STn+2) can receive a first scan clock signal (CLK1) through a first scan clock terminal (SCI1), and can receive a second scan clock signal (CLK2) whose phase is sequentially alternated or delayed with the first scan clock signal (CLK1) through a second scan clock terminal (SCI2).

[0096] The n-2 to n+2 stages (STn-2 to STn+2) sequentially output scan signals (SCn-2 to SCn+2) to respective scan signal wires (SCLn-2 to SCLn+2) that are connected one-to-one through their respective scan output terminals (SCO). For example, in at least one frame period, the n-2 stage (STn-2) outputs the n-2 scan signal (SCn-2) to the n-2 scan signal wire (SCLn-2) connected to the scan output terminal (SCO). Next, the n-1 stage (STn-1) outputs the n-1 scan signal (SCn-1) to the n-1 scan signal wire (SCLn-1) connected to the scan output terminal (SCO). Therefore, the n-th stage (STn) outputs the n-th scan signal (SCn) to the n-th scan signal wire (SCLn) connected to the scan output terminal (SCO). Next, the n+1-th stage (STn+1) can output the n+1-th scan signal (SCn+1) through the n+1-th scan signal wire (SCLn+1) connected to the scan output terminal (SCO), and the n+2-th stage (STn+2) can output the n+2-th scan signal (SCn+2) through the n+2-th scan signal wire (SCLn+2) connected to the scan output terminal (SCO).

[0097] In general, the scan driving unit (610) may be configured with stages (ST1 to STn) that sequentially output the first to nth scan signals (SC1 to SCn) for each active period during each frame period. The detailed structure of the scan driving unit (610) has been described with reference to FIG. 5.

[0098] The structure of the light emitting control driving unit (620) that sequentially generates and outputs light emitting signals in response to the light emitting control signal (ECS) received from the display driving unit (200) can also be formed as an n-2 to n+2 stage (STn-2 to STn+2), i.e., an n-th stage (STn) structure. Accordingly, the detailed structural description of the light emitting control driving unit (620) will be replaced with the description of the scan driving unit (610).

[0099] Fig. 6 is a circuit diagram of the first embodiment specifically showing the nth stage of the scan driving unit illustrated in Fig. 5. In particular, Fig. 6 shows the nth stage (STn) among the n-2nd to n+2nd stages (STn-2 to STn+2) as an example.

[0100] The nth stage (STn) includes an output node control unit (SCC) and an output control unit (OUC). In addition, the nth stage (STn) further includes a first power supply terminal (SSI1) to which a gate-on voltage (VGH) is supplied, and a second power supply terminal (SSI2) to which a gate-off voltage (VGL) is supplied.

[0101] The nth stage (STn) may operate by receiving a start signal (ST) as an input to a carry terminal (CPI), but when it is cascadedly connected to the previous n-1th stage (STn-1), it may operate by receiving the n-1th scan signal (SCn-1) of the n-1th stage (STn-1) as a carry signal. Hereinafter, an example will be described in which the nth stage (STn) is one of the nth stages (STn) cascadedly connected to the previous n-1th stage (STn-1).

[0102] The output node control unit (SCC) of the nth stage (STn) enables the output control unit (OUC) by supplying a voltage of the gate-on voltage (VGH) level to the pull-up node (Q) during the active period of each frame period, and while the pull-up node (Q) is maintained at the gate-on voltage (VGH) level, the gate-off voltage (VGL) of the second power supply terminal (SSI2) is applied to the pull-down node (QB).

[0103] Specifically, the output node control unit (SCC) supplies a gate-on voltage (VGH) to the pull-up node (Q) in response to a line select signal (ES) input during an active period or a carry signal of the preceding stage, i.e., the n-1th scan signal (SCn-1) of the n-1th stage (STn-1). Here, the line select signal (ES) or the carry signal of the preceding stage may be the magnitude of the gate-on voltage. The pull-up node (Q) of the output node control unit (SCC) is enabled depending on the magnitude of the gate-on voltage (VGH) when the gate-on voltage (VGH) is applied. The output node control unit (SCC) causes a gate-off voltage (VGL) to be applied to the pull-down node (QB) during a period in which the gate-on voltage (VGH) is supplied to the pull-up node (Q).

[0104] When the pull-up node (Q) of the output node control unit (SCC) is enabled, the output control unit (OUC) outputs the n-th scan signal (SCn) to the n-th scan signal wire (SCLn) connected to the scan output terminal (SCO) in response to one of the scan clock signals (CLK2) among the scan clock signals (CLK1, CLK2).

[0105] After the nth scan signal (SCn) is output, the output node control unit (SCC) supplies a gate-off voltage (VGL) to the pull-up node (Q) in response to either the scan clock signal (CLK1) of the scan clock signals (CLK1, CLK2) or the n+1th scan signal (SCn+1) of the n+1th stage (STn+1). The pull-up node (Q) is disabled by the gate-off voltage (VGL).

[0106] The output node control unit (SCC) enables the pull-down node (QB) to the gate-on voltage (VGH) in response to one of the scan clock signals (CLK1, CLK2) while the pull-up node (Q) is disabled.

[0107] When the pull-down node (QB) of the output node control unit (SCC) is enabled, the output control unit (OUC) electrically connects the n-th scan signal wire (SCLn) to the second power supply terminal (SSI2) to which the gate-off voltage (VGL) is applied.

[0108] The n-2 to n+2 stages (STn-2 to STn+2) sequentially and repeatedly output the n-th scan signal (SCn) to each scan signal wire (SCLn) and maintain each scan signal wire (SCLn) at the gate-off voltage (VGL).

[0109] The output node control unit (SCC) of the nth stage (STn) includes first to seventh transistors (T1 to T7) and at least one first capacitor (C1), and one of the first electrode and the second electrode of each of the first to seventh transistors (T1 to T7) may be a source electrode and the other may be a drain electrode.

[0110] The gate electrode of the first transistor (T1) may be connected to a pull-up node (Q), the first electrode of the first transistor (T1) may be connected to a second scan clock terminal (SCI2), and the second electrode may be connected to a pre-carry terminal (CPI) and the first electrode of the second transistor (T2). When the pull-up node (Q) is enabled by a gate-on voltage (VGH), the first transistor (T1) may be turned on to supply the second scan clock signal (CLK2) to a first capacitor (C1) and a second transistor (T2) connected in parallel.

[0111] The gate electrode of the second transistor (T2) is connected to the pull-down node (QB), and the first electrode is connected to the second electrode and the pre-carry terminal (CPI) of the first transistor (T1). In addition, the second electrode of the second transistor (T2) is connected to the second power supply terminal (SSI2). The second transistor (T2) is turned on when the pull-down node (QB) is enabled by the gate-on voltage (VGH) and supplies the gate-off voltage (VGL) to the first transistor (T1).

[0112] The gate electrode of the third transistor (T3) is connected to the pull-up node (Q), and the first electrode is connected to the first scan clock terminal (SCI1). In addition, the second electrode of the third transistor (T3) is connected to the pull-down node (QB). When the pull-up node (Q) is enabled by the gate-on voltage (VGH), the third transistor (T3) is turned on to supply the first scan clock signal (CLK1) to the pull-down node (QB).

[0113] The gate electrode of the fourth transistor (T4) is connected to the sensing signal terminal (RSI) or the preceding carry terminal (CPI), and the first electrode is connected to the first power supply terminal (SSI1). In addition, the second electrode of the fourth transistor (T4) is connected to the pull-up node (Q). The fourth transistor (T4) is turned on in response to the line select signal (ES) or the preceding carry signal of the sensing signal terminal (RSI) and supplies the gate-on voltage (VGH) to the pull-up node (Q). Accordingly, the fourth transistor (T4) can enable the pull-up node (Q) with the gate-on voltage (VGH) in response to the line select signal (ES) or the preceding carry signal of the sensing signal terminal (RSI).

[0114] The gate electrode of the fifth transistor (T5) is connected to the first scan clock terminal (SCI1), and the first electrode is connected to the first power supply terminal (SSI1). In addition, the second electrode of the fifth transistor (T5) is connected to the pull-down node (QB). The fifth transistor (T5) is turned on in response to the first scan clock signal (CLK1) and supplies the gate-on voltage (VGH) to the pull-down node (QB). Accordingly, the fifth transistor (T5) can enable the pull-down node (QB) with the size of the gate-on voltage (VGH) in response to the first scan clock signal (CLK1).

[0115] The gate electrode of the sixth transistor (T6) is connected to the second scan clock terminal (SCI2), and the first electrode is connected to the pull-up node (Q). In addition, the second electrode of the sixth transistor (T6) is connected to the second electrode of the first transistor (T1) or the first electrode of the seventh transistor (T7). The sixth transistor (T6) electrically connects the pull-up node (Q) to the second electrode of the first transistor (T1) or the first electrode of the seventh transistor (T7) in response to the second scan clock signal (CLK2). The sixth transistor (T6) can function as a diode between the pull-up node (Q) and the first capacitor (C1).

[0116] The gate electrode of the seventh transistor (T1) is connected to the pull-down node (QB), and the first electrode is connected to the second electrode of the sixth transistor (T6). In addition, the second electrode of the seventh transistor (T7) is connected to the second electrode of the first transistor (T1) and the first capacitor (C1). When the pull-down node (QB) is enabled, the seventh transistor (T7) is turned on to electrically connect the second electrode of the sixth transistor (T6), the first capacitor (C1), and the second electrode of the first transistor (T1). The seventh transistor (T1) acts as a diode to maintain the sixth transistor (T6) and the first transistor (T1) in a turn-off state during the enable period of the pull-down node (QB).

[0117] The output control circuit (OUC) includes a pull-up transistor (DT) and a pull-down transistor (VT).

[0118] A first electrode of a pull-up transistor (DT) is connected to a second scan clock terminal (SCI2), a gate electrode is connected to a pull-up node (Q), and a second electrode is connected to a scan output terminal (SCO). The pull-up transistor (D7) is turned on by a gate-on voltage (VGH) of the pull-up node (Q) and outputs one scan clock signal, for example, a second scan clock signal (CLK2), input to the second scan clock terminal (SCI2) to the scan output terminal (SCO). As a result, an n-th scan signal (SCn) having a gate-on voltage can be supplied to the n-th scan signal line (SCLn).

[0119] A first electrode of a pull-down transistor (VT) is connected to a scan output terminal (SCO), a gate electrode is connected to a pull-down node (QB), and a second electrode is connected to a second power supply terminal (SSI2). The pull-down transistor (VT) is turned on by a gate-on voltage (VGH) of the pull-down node (QB) and applies a gate-off voltage (VGL) input to the second power supply terminal (SSI2) to the scan output terminal (SCO). As a result, an n-th scan signal line (SCLn) connected to the scan output terminal (SCO) can be maintained at the gate-off voltage (VGL) during a turn-on period of the pull-down transistor (VT). Here, a second capacitor (2C) can be formed between the second electrode and the gate electrode of the pull-down transistor (VT).

[0120] Figure 7 is a waveform diagram showing changes in the voltage magnitude of sensing control signals, scan clock signals, and pull-up nodes during the active period of the Nth frame period.

[0121] Referring to FIG. 7, the line select signal (ES), the start signal (ST), the first and second scan clock signals (CLK1, CLK2), etc. are signals generated with the gate-on voltage (VGH) level for one horizontal period (1H). The line select signal (ES) may be generated for one horizontal period (1H) so that the gate-on voltage (VGH) can be supplied to the pull-up node (Q) of each stage (STn-2 to STn+2) during the active period. Even if the line select signal (ES) is not generated and supplied separately, it may be replaced with the start signal (ST) or a carry signal from a previous stage (i.e., a previous carry signal).

[0122] The first and second scan clock signals (CLK1, CLK2) are clock signals whose phases are sequentially delayed or repeatedly alternated. Each of the first and second scan clock signals (CLK1, CLK2) can be generated with a gate-on voltage (VGH) magnitude for at least one horizontal period (1H) and can be repeatedly generated with a gate-off voltage (VGL) magnitude for at least one horizontal period (1H). Here, the generation cycle, pulse width, and amplitude of the first and second scan clock signals (CLK1, CLK2) are not limited to FIG. 7 and can be variously changed.

[0123] The gate-on voltage (VGH) may be a gate high voltage that can turn on the transistors of the n-2 to n+2 stages (STn-2 to STn+2) of the scan driver (610) and the transistors of the sub-pixels (PX). The gate-off voltage (VGH) may be a gate low voltage (VGL) that can turn off the transistors of the n-2 to n+2 stages (STn-2 to STn+2) of the scan driver (610) and the transistors of the sub-pixels (PX).

[0124] Referring to FIGS. 6 and 7, the operation of the nth stage (STn) during one frame period is briefly described as follows.

[0125] First, the fourth transistor (T4) is turned on in response to the line select signal (ES) or start signal (ST) of the sensing signal terminal (RSI) and supplies the gate-on voltage (VGH) to the pull-up node (Q). Accordingly, the pull-up node (Q) is enabled.

[0126] Next, the first transistor (T1) is turned on when the pull-up node (Q) is enabled by the gate-on voltage (VGH), thereby charging the first capacitor (C1). Then, the pull-up transistor (D7) is turned on by the gate-on voltage (VGH) of the pull-up node (Q), thereby outputting the second scan clock signal (CLK2) input to the second scan clock terminal (SCI2) to the scan output terminal (SCO). As a result, the pull-up node (Q) is bootstrapped, and the n-th scan signal (SCn) of the gate-on voltage is supplied to the n-th scan signal line (SCLn).

[0127] Thereafter, the fifth transistor (T5) is turned on in response to the first scan clock signal (CLK1) and enables the pull-down node (QB) with the gate-on voltage (VGH). The pull-down transistor (VT) is turned on by the gate-on voltage (VGH) of the pull-down node (QB) and applies the gate-off voltage (VGL) input to the second power supply terminal (SSI2) to the scan output terminal (SCO). As a result, the n-th scan signal line (SCLn) connected to the scan output terminal (SCO) can be maintained at the gate-off voltage (VGL) during the turn-on period of the pull-down transistor (VT).

[0128] Fig. 8 is a circuit diagram of a second embodiment specifically showing the nth stage of the scan driving unit illustrated in Fig. 5.

[0129] Referring to FIG. 8, the output node control unit (SCC) of the nth stage (STn) may further include an eighth transistor (T8) that disables the pull-up node (Q) with a gate-off voltage (VGL) in response to a rear-end carry signal from the next stage (STn+1).

[0130] The gate electrode of the eighth transistor (T8) is connected to the subsequent carry terminal (CNI), and the first electrode is connected to the previous carry terminal (CPI) or the second power supply terminal (SSI2). In addition, the second electrode of the eighth transistor (T8) is connected to the pull-up node (Q). Accordingly, the eighth transistor (T8) can supply a gate-off voltage (VGL) to the pull-up node (Q) in response to a subsequent carry signal from the next stage (STn+1).

[0131] As described above, the output node control unit (SCC) of each of the entire stages, i.e., the n-2 to n+2-th stages (STn-2 to STn+2), may be configured to include first to seventh transistors (T1 to T7) or first to eighth transistors (T1 to T8). At least one transistor among the first to eighth transistors (T1 to T8) of each stage (STn) arranged in this way, for example, the first transistor (T1), the third transistor (T3), and the fourth transistor (T4), enables the pull-up node (Q) with a gate-on voltage (VGH), and while the pull-up node (Q) is enabled, the bootstrapped voltage is applied to one electrode while being bootstrapped to a voltage higher than the gate-on voltage (VGH) by one scan clock signal (CLK2). Accordingly, the first, third, and fourth transistors (T1, T3, T4), etc. are subjected to high potential and high voltage stress, and the current and voltage characteristics of the semiconductor layer (or active layer), such as the threshold voltage characteristics of the semiconductor layer, may vary due to the influence of the high potential and high voltage stress. If the current and voltage characteristics of the first, third, and fourth transistors (T1, T3, T4), etc. vary, the voltage and current output characteristics of the first, third, and fourth transistors (T1, T3, T4), etc. may deteriorate, resulting in a decrease in the output of each stage (STn-2 to STn+2) or a decrease in reliability.

[0132] Accordingly, the semiconductor layer (or active layer) of at least one transistor (T1 to T8) among the first to eighth transistors (T1 to T8) of each stage (STn) can be composed of a different oxide semiconductor material from the semiconductor layer (or active layer) of at least one other transistor (T1 to T8).

[0133] For example, among the first to eighth transistors (T1 to T8) of each stage (STn), a semiconductor layer (or active layer) for at least one transistor (T1 to T8) that is directly connected to the pull-up node (Q) and receives high potential and high voltage stress may be formed by including a heterogeneous oxide semiconductor material, unlike the semiconductor layer (or active layer) of at least one other transistor (T1 to T8) that is not directly connected to the pull-up node (Q).

[0134] In particular, the semiconductor layers (or active layers) of the first, third, and fourth transistors (T1, T3, and T4) directly connected to the pull-up node (Q) among the first to eighth transistors (T1 to T8) of each stage (STn) are formed of heterogeneous oxide semiconductor materials having a large current range, thereby increasing the current amount and current transfer speed of the first, third, and fourth transistors (T1, T3, and T4).

[0135] Fig. 9 is a cross-sectional view showing the cross-sectional structure of the first and sixth transistors of the scan driver illustrated in Fig. 8.

[0136] Referring to FIGS. 8 and 9, among the plurality of transistors (T1 to T8) included in each stage (STn), at least one transistor indirectly connected to the pull-up node (Q), for example, the second, fifth to seventh transistors (T2, T5 T6, T7), includes a first active layer (ACT1) including an oxide semiconductor.

[0137] In contrast, among the plurality of transistors (T1 to T8) included in each stage (STn), at least one transistor directly connected to the pull-up node (Q), for example, the first, third, fourth, and eighth transistors (T1, T3, T4, T8), includes a second active layer (ACT2) including a hetero-oxide semiconductor different from the oxide semiconductor of the first active layer (ACT1).

[0138] Specifically, a barrier film (BR) is formed on a substrate (SUB) on which each stage (STn) is formed, and a thin film transistor layer (TFTL) including a plurality of transistors (T1 to T8) for each stage (STn) is formed on the barrier film (BR).

[0139] The substrate (SUB) may be a rigid substrate or a flexible substrate capable of bending, folding, rolling, etc. The substrate (SUB) may be made of an insulating material such as glass, quartz, or polymer resin. Examples of polymeric materials include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene napthalate (PEN), polyethylene terepthalate (PET), polyphenylene sulfide (PPS), polyallylate, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT), cellulose acetate propionate (CAP), or combinations thereof. Alternatively, the first substrate (SUB) may include a metallic material.

[0140] A barrier film (BR) is disposed on the substrate (SUB), and the barrier film (BR) may be a film for protecting a thin film transistor layer (TFTL) from moisture penetrating through the substrate (SUB) which is vulnerable to moisture permeation. The barrier film (BR) may be formed of a plurality of inorganic films alternately laminated. For example, the barrier film (BR) may be formed as a multi-film in which one or more inorganic films of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately laminated.

[0141] A thin film transistor layer (TFTL) including multiple transistors (T1 to T8) for each stage (STn) is formed on the barrier film (BR).

[0142] A thin film transistor layer (TFTL) of at least one transistor indirectly connected to a pull-up node (Q), for example, a sixth transistor (T6), includes a first gate electrode (GEb1), an interlayer insulating film (BF), a first active layer (ACT1), first and second gate insulating films (GTI1, GTI2), and a second gate electrode (GE6).

[0143] An interlayer insulating film (BF) is formed to cover the barrier film (BR) including the first gate electrode (GEb1).

[0144] A first active layer (ACT1) is formed to cover a first gate electrode (GEb1) with an interlayer insulating film (BF) therebetween, thereby forming a sixth channel region (CH6). A first electrode (E61) and a second electrode (E62) may be defined on one side and the other side of the first active layer (ACT1), respectively.

[0145] The first gate insulating film (GTI1) is formed to overlap the first gate electrode (GEb1) with the first active layer (ACT1) interposed therebetween, and the second gate insulating film (GTI2) is formed to overlap the first gate electrode (GEb1) with the first gate insulating film (GTI1) interposed therebetween.

[0146] The second gate electrode (GE6) is formed to overlap the first gate electrode (GEb1) with the first and second gate insulating films (GTI1, GTI2) interposed therebetween.

[0147] The interlayer insulating film (BF) may include an inorganic film, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. Meanwhile, the interlayer insulating film (BF) may include a plurality of inorganic films.

[0148] The first active layer (ACT1) may include polycrystalline silicon, single-crystal silicon, low-temperature polycrystalline silicon, amorphous silicon, or an oxide semiconductor material. When the first active layer (ACT1) includes an oxide semiconductor material, the first active layer (ACT1) may include indium-gallium-zinc oxide (IGZO).

[0149] When the first active layer (ACT1) includes polycrystalline silicon or an oxide semiconductor material, the source region and the drain region in the first active layer (ACT2) may be conductive regions doped with ions to have conductivity.

[0150] The first gate insulating film (GTI1) may include at least one of tetraethoxysilane (TetraEthylOrthoSilicate, TEOS), silicon nitride (SiNx), and silicon oxide (SiO2). For example, the first gate insulating film (GTI1) may have a double film structure in which a silicon nitride film having a thickness of 40 nm and a tetraethoxysilane film having a thickness of 80 nm are sequentially laminated. The second gate insulating film (GTI2) may include the same material and structure as the first gate insulating film (GTI1) described above.

[0151] Meanwhile, among the plurality of transistors (T1 to T8) included in each stage (STn), at least one transistor directly connected to the pull-up node (Q), for example, the first, third, fourth, and eighth transistors (T1, T3, T4, T8), includes a second active layer (ACT2) including a hetero-oxide semiconductor different from the oxide semiconductor of the first active layer (ACT1).

[0152] For example, the thin film transistor layer (TFTL) of the first transistor (T1) directly connected to the pull-up node (Q) includes a first gate electrode (GEb1), an interlayer insulating film (BF), a second active layer (ACT2), first and second gate insulating films (GTI1, GTI2), and a second gate electrode (GE6).

[0153] An interlayer insulating film (BF) is formed by covering the barrier film (BR) including the first gate electrode (GEb1).

[0154] A second active layer (ACT2) is formed to cover the first gate electrode (GEb1) with an interlayer insulating film (BF) therebetween, thereby forming a first channel region (CH1). A first electrode (E61) and a second electrode (E62) may be defined on one side and the other side of the second active layer (ACT2), respectively.

[0155] The first gate insulating film (GTI1) is formed to overlap the first gate electrode (GEb1) with the second active layer (ACT2) interposed therebetween, and the second gate insulating film (GTI2) is formed to overlap the first gate electrode (GEb1) with the first gate insulating film (GTI1) interposed therebetween.

[0156] The second gate electrode (GE6) is formed to overlap the first gate electrode (GEb1) with the first and second gate insulating films (GTI1, GTI2) interposed therebetween.

[0157] The second active layer (ACT2) may include a different hetero oxide semiconductor material from the first active layer (ACT1). For example, when the above-described first active layer (ACT1) is an oxide semiconductor including indium-gallium-zinc-oxide (IGZO), the second active layer (ACT2) may be an oxide semiconductor including indium-gallium-zinc-tin oxide (IGZTO). When the second active layer (ACT2) includes a hetero oxide semiconductor material, the source region and the drain region in the second active layer (ACT2) may be conductive regions that are doped with ions to have conductivity.

[0158] Meanwhile, since the first active layer (ACT1) and the second active layer (ACT2) are semiconductor layers of different materials, the first active layer (ACT1) and the second active layer (ACT2) can be formed on the substrate through different processes.

[0159] The second, fifth, and seventh transistors (T2, T5, T6, and T7), which are transistors requiring high-speed switching speed, may include a first active layer (ACT1) of indium-gallium-zinc-oxide (IGZO).

[0160] However, each of the first, third, fourth, and eighth transistors (T1, T3, T4, and T8) that require a wide current transfer range and high reliability may include a second active layer (ACT2) of indium-gallium-zinc-tin oxide (IGZTO). In other words, each of the first, third, fourth, and eighth transistors (T1, T3, T4, and T8) that are directly connected to the pull-up node (Q) and require high reliability may include heterogeneous oxide semiconductor materials. Accordingly, both high reliability and high speed of each stage (STn) can be satisfied.

[0161] Fig. 10 is a diagram of another embodiment showing the nth stage illustrated in Fig. 8. And, Fig. 11 is a cross-sectional view showing the cross-sectional structure of the fourth and sixth transistors of the scan driver illustrated in Fig. 10.

[0162] Referring to FIGS. 10 and 11, among the plurality of transistors (T1 to T8) included in each stage (STn), the fourth transistor (T4) directly connected to the pull-up node (Q) may include a second active layer (ACT2) including a hetero-oxide semiconductor different from the oxide semiconductor of the first active layer (ACT1).

[0163] On the other hand, among the plurality of transistors (T1 to T8) included in each stage (STn), the second, fifth to seventh transistors (T2, T5 T6, T7) indirectly connected to the pull-up node (Q) may include a first active layer (ACT1) including an oxide semiconductor.

[0164] The thin film transistor layer (TFTL) of the fourth transistor (T4) directly connected to the pull-up node (Q) may include a first gate electrode (GEb1), an interlayer insulating film (BF), a second active layer (ACT2) forming a fourth channel region (CH4), first and second gate insulating films (GTI1, GTI2), and a second gate electrode (GE6).

[0165] An interlayer insulating film (BF) is formed to cover a barrier film (BR) including a first gate electrode (GEb1), and a second active layer (ACT2) is formed to cover the first gate electrode (GEb1) with the interlayer insulating film (BF) therebetween, thereby forming a fourth channel region (CH4). The first electrode (E41) and the second electrode (E42) may be defined (or formed) on one side and the other side of the fourth channel region CH4 (or the second active layer ACT2), respectively.

[0166] The first gate insulating film (GTI1) is formed to overlap the first gate electrode (GEb1) with the second active layer (ACT2) interposed therebetween, and the second gate insulating film (GTI2) is formed to overlap the first gate electrode (GEb1) with the first gate insulating film (GTI1) interposed therebetween.

[0167] The second gate electrode (GE6) is formed to overlap the first gate electrode (GEb1) with the first and second gate insulating films (GTI1, GTI2) interposed therebetween, and a first electrode (E61) and a second electrode (E62) can be defined on one side and the other side of the second active layer (ACT2), respectively.

[0168] The second active layer (ACT2) of the fourth transistor (T4) includes a hetero-oxide semiconductor material different from the first active layer (ACT1). The second active layer (ACT2) may be an oxide semiconductor including indium-gallium-zinc-tin oxide (IGZTO).

[0169] Meanwhile, among the plurality of transistors (T1 to T8) included in each stage (STn), the third and fourth transistors (T3, T4) directly connected to the pull-up node (Q) may be formed to include a second active layer (ACT2) including a hetero-oxide semiconductor, and the first transistor (T1) directly connected to the pull-up node (Q) may be formed to include a first active layer (ACT1) including an oxide semiconductor.

[0170] On the other hand, among the plurality of transistors (T1 to T8) included in each stage (STn), the first transistor (T1) directly connected to the pull-up node (Q) may be formed to include a second active layer (ACT2) including a hetero-oxide semiconductor, and the third and fourth transistors (T3, T4) directly connected to the pull-up node (Q) may be formed to include a first active layer (ACT1) including an oxide semiconductor.

[0171] Meanwhile, the pull-down transistor (VT) of the output control unit (OUC) may include a first active layer (ACT1) including an oxide semiconductor. Alternatively, the pull-up transistor (DT) of the output control unit (OUC) directly connected to the pull-up node (Q) may be formed by including a second active layer (ACT2) including a heterogeneous oxide semiconductor material different from the first active layer (ACT1) of the pull-down transistor (VT).

[0172] FIG. 12 and FIG. 13 are perspective views showing application examples of a display device according to one embodiment of the present invention.

[0173] FIG. 12 and FIG. 13 illustrate examples in which the display device (10) is applied as a foldable display device that folds in the first direction (X-axis direction). The display device (10) can maintain both a folded state and an unfolded state. The display device (10) can be folded in an in-folding manner in which the front surface is disposed on the inside. When the display device (10) is bent or folded in an in-folding manner, the front surfaces of the display devices (10) can be arranged to face each other. Alternatively, the display device (10) can be folded in an out-folding manner in which the front surface is disposed on the outside. When the display device (10) is bent or folded in an out-folding manner, the back surfaces of the display devices (10) can be arranged to face each other.

[0174] The first non-folding area (NFA1) may be arranged on one side of the folding area (FDA), for example, on the right side. The second non-folding area (NFA2) may be arranged on the other side of the folding area (FDA), for example, on the left side. A touch sensing unit (TSU) according to an embodiment of the present disclosure may be formed and arranged on each of the first non-folding area (NFA1) and the second non-folding area (NFA2).

[0175] The first folding line (FOL1) and the second folding line (FOL2) extend in the second direction (Y-axis direction), and the display device (10) can be folded in the first direction (X-axis direction). As a result, the length of the display device (10) in the first direction (X-axis direction) can be reduced by approximately half, so that the user can conveniently carry the display device (10).

[0176] Meanwhile, the extension direction of the first folding line (FOL1) and the extension direction of the second folding line (FOL2) are not limited to the second direction (Y-axis direction). For example, the first folding line (FOL1) and the second folding line (FOL2) extend in the first direction (X-axis direction), and the display device (10) can be folded in the second direction (Y-axis direction). In this case, the length of the display device (10) in the second direction (Y-axis direction) can be reduced by approximately half. Alternatively, the first folding line (FOL1) and the second folding line (FOL2) can extend in a diagonal direction of the display device (10) between the first direction (X-axis direction) and the second direction (Y-axis direction). In this case, the display device (10) can be folded in a triangular shape.

[0177] When the first folding line (FOL1) and the second folding line (FOL2) extend in the second direction (Y-axis direction), the length of the folding area (FDA) in the first direction (X-axis direction) may be shorter than the length of the second direction (Y-axis direction). In addition, the length of the first direction (X-axis direction) of the first non-folding area (NFA1) may be longer than the length of the folding area (FDA) in the first direction (X-axis direction). The length of the first direction (X-axis direction) of the second non-folding area (NFA2) may be longer than the length of the folding area (FDA) in the first direction (X-axis direction).

[0178] The first display area (DA1) may be arranged on the front side of the display device (10). The first display area (DA1) may overlap the folding area (FDA), the first non-folding area (NFA1), and the second non-folding area (NFA2). Therefore, when the display device (10) is unfolded, an image may be displayed in the front direction in the folding area (FDA), the first non-folding area (NFA1), and the second non-folding area (NFA2) of the display device (10).

[0179] The second display area (DA2) may be arranged on the back surface of the display device (10). The second display area (DA2) may overlap the second non-folding area (NFA2). Therefore, when the display device (10) is folded, an image may be displayed in the front direction in the second non-folding area (NFA2) of the display device (10).

[0180] In FIGS. 12 and 13, the through hole (TH) in which the camera (SDA) is formed is exemplified as being positioned in the first non-folding area (NFA1), but this is not limited thereto. The through hole (TH) or the camera (SDA) may be positioned in the second non-folding area (NFA2) or the folding area (FDA).

[0181] FIG. 14 and FIG. 15 are perspective views showing application examples of a display device according to another embodiment of the present invention.

[0182] FIG. 14 and FIG. 15 illustrate examples in which the display device (10) is applied as a foldable display device that folds in the second direction (Y-axis direction). The display device (10) can maintain both a folded state and an unfolded state. The display device (10) can be folded in an in-folding manner in which the front surface is positioned on the inside. When the display device (10) is bent or folded in an in-folding manner, the front surfaces of the display devices (10) can be positioned to face each other. Alternatively, the display device (10) can be folded in an out-folding manner in which the front surface is positioned on the outside. When the display device (10) is bent or folded in an out-folding manner, the back surfaces of the display devices (10) can be positioned to face each other.

[0183] The display device (10) may include a folding area (FDA), a first non-folding area (NFA1), and a second non-folding area (NFA2). The folding area (FDA) may be an area where the display device (10) is folded, and the first non-folding area (NFA1) and the second non-folding area (NFA2) may be areas where the display device (10) is not folded. The first non-folding area (NFA1) may be arranged on one side of the folding area (FDA), for example, on the lower side. The second non-folding area (NFA2) may be arranged on the other side of the folding area (FDA), for example, on the upper side.

[0184] A touch sensing unit (TSU) according to an embodiment of the present specification may be formed and placed on the first non-folding area (NFA1) and the second non-folding area (NFA2), respectively.

[0185] On the other hand, the folding area (FDA) may be an area bent at a predetermined curvature at the first folding line (FOL1) and the second folding line (FOL2). Therefore, the first folding line (FOL1) may be a boundary between the folding area (FDA) and the first non-folding area (NFA1), and the second folding line (FOL2) may be a boundary between the folding area (FDA) and the second non-folding area (NFA2).

[0186] The first folding line (FOL1) and the second folding line (FOL2) extend in the first direction (X-axis direction) as shown in FIGS. 14 and 15, and the display device (10) can be folded in the second direction (Y-axis direction). As a result, the length of the display device (10) in the second direction (Y-axis direction) can be reduced by approximately half, so that the user can conveniently carry the display device (10).

[0187] Meanwhile, the extension direction of the first folding line (FOL1) and the extension direction of the second folding line (FOL2) are not limited to the first direction (X-axis direction). For example, the first folding line (FOL1) and the second folding line (FOL2) extend in the second direction (Y-axis direction), and the display device (10) can be folded in the first direction (X-axis direction). In this case, the length of the display device (10) in the first direction (X-axis direction) can be reduced by approximately half. Alternatively, the first folding line (FOL1) and the second folding line (FOL2) can extend in a diagonal direction of the display device (10) between the first direction (X-axis direction) and the second direction (Y-axis direction). In this case, the display device (10) can be folded in a triangular shape.

[0188] When the first folding line (FOL1) and the second folding line (FOL2) extend in the first direction (X-axis direction) as shown in FIGS. 14 and 15, the length of the folding area (FDA) in the second direction (Y-axis direction) may be shorter than the length of the first direction (X-axis direction). In addition, the length of the first non-folding area (NFA1) in the second direction (Y-axis direction) may be longer than the length of the folding area (FDA) in the second direction (Y-axis direction). The length of the second non-folding area (NFA2) in the second direction (Y-axis direction) may be longer than the length of the folding area (FDA) in the second direction (Y-axis direction).

[0189] The first display area (DA1) may be arranged on the front side of the display device (10). The first display area (DA1) may overlap the folding area (FDA), the first non-folding area (NFA1), and the second non-folding area (NFA2). Therefore, when the display device (10) is unfolded, an image may be displayed in the front direction in the folding area (FDA), the first non-folding area (NFA1), and the second non-folding area (NFA2) of the display device (10).

[0190] The second display area (DA2) may be arranged on the back surface of the display device (10). The second display area (DA2) may overlap the second non-folding area (NFA2). Therefore, when the display device (10) is folded, an image may be displayed in the front direction in the second non-folding area (NFA2) of the display device (10).

[0191] In FIGS. 14 and 15, the through hole (TH) in which the camera (SDA) and the like are placed is exemplified as being placed in the second non-folding area (NFA2), but this is not limited thereto. The through hole (TH) may be placed in the first non-folding area (NFA1) or the folding area (FDA).

[0192] Although embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without altering the technical spirit or essential characteristics of the present invention. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

Claims

1. Equipped with stages that sequentially output scan signals to scan signal wires during the active period of the Nth (N is a positive integer) frame, At least one of the above stages, An output node control unit that supplies a gate-on voltage to a pull-up node in response to a gate control signal of a display driver unit; and When the gate-on voltage is supplied to the pull-up node, the output control unit includes a scan clock signal input to the scan clock terminal and outputs the scan signal to each connected scan signal wire as a scan signal. The above output node control unit At least one thin film transistor comprising a first active layer and indirectly connected to the pull-up node; and A scan driver comprising a second active layer including a hetero oxide semiconductor material different from the first active layer and at least one other thin film transistor directly connected to the pull-up node.

2. In paragraph 1, The above output node control unit A first transistor which is turned on when the pull-up node is enabled by the gate-on voltage and supplies one scan clock signal to a first capacitor connected in parallel; A second transistor which is turned on when the pull-down node is enabled by the gate-on voltage and supplies the gate-off voltage to the first transistor; A third transistor which is turned on when the pull-up node is enabled by the gate-on voltage and supplies another scan clock signal to the pull-down node; A fourth transistor that is turned on in response to a line select signal or a pre-carry signal of a sensing signal terminal and supplies the gate-on voltage to the pull-up node; A fifth transistor turned on in response to said other scan clock signal to supply said gate-on voltage to said pull-down node; A sixth transistor electrically connecting the pull-up node with another transistor or the first capacitor in response to one of the scan clock signals; and A scan driver including a seventh transistor that is turned on when the pull-down node is enabled to electrically connect the sixth transistor, the first capacitor, and the first transistor.

3. In paragraph 2, The above output control unit A pull-up transistor that is turned on by the gate-on voltage of the pull-up node and outputs one of the scan clock signals input to the scan clock terminal to the scan output terminal and the scan signal wiring; and A scan driver including a pull-down transistor that is turned on by the gate-on voltage of the pull-down node and applies the gate-off voltage to the scan output terminal and the scan signal wiring.

4. In paragraph 3, The above pull-down transistor includes the first active layer including an oxide semiconductor, The pull-up transistor is a scan driver including the second active layer including a hetero oxide semiconductor different from the oxide semiconductor of the first active layer.

5. In paragraph 2, The above output node control unit A scan driver further comprising an eighth transistor for disabling the pull-up node with the gate-off voltage or one of the scan clock signals in response to a rear-end carry signal from the next stage.

6. In paragraph 5, Among the first to eighth transistors included in the output node control unit, at least one of the second, fifth to seventh transistors indirectly connected to the pull-up node includes the first active layer including an oxide semiconductor, A scan driver including the second active layer, wherein at least one of the first, third, fourth, and eighth transistors directly connected to the pull-up node among the first to eighth transistors included in the output node control unit includes a hetero oxide semiconductor different from the oxide semiconductor of the first active layer.

7. In paragraph 2, The gate electrode of the first transistor is connected to the pull-up node, the first electrode is connected to the second scan clock terminal, and the second electrode is connected to the previous carry terminal and the first electrode of the second transistor. The gate electrode of the second transistor is connected to the pull-down node, the first electrode is connected to the second electrode of the first transistor and the previous carry terminal, and the second electrode of the second transistor is connected to the gate-off voltage supply terminal. The gate electrode of the third transistor is connected to the pull-up node, the first electrode is connected to the first scan clock terminal, and the second electrode of the third transistor is connected to the pull-down node. The gate electrode of the fourth transistor is connected to the sensing signal terminal or the preceding carry terminal, the first electrode is connected to the gate-on voltage supply terminal, and the second electrode is connected to the pull-up node. The gate electrode of the fifth transistor is connected to the first scan clock terminal, the first electrode is connected to the gate-on voltage supply terminal, and the second electrode is connected to the pull-down node. The gate electrode of the sixth transistor is connected to the second scan clock terminal, the first electrode is connected to the pull-up node, and the second electrode is connected to the second electrode of the first transistor or the first electrode of the seventh transistor. A scan driver in which the gate electrode of the seventh transistor is connected to the pull-down node, the first electrode is connected to the second electrode of the sixth transistor, and the second electrode is connected to the second electrode of the first transistor and the first capacitor.

8. In paragraph 7, The above output control unit A pull-up transistor having a first electrode connected to the second scan clock terminal, a gate electrode connected to the pull-up node, and a second electrode connected to the scan output terminal; and A scan driver including a pull-down transistor, the first electrode of which is connected to the scan output terminal, the gate electrode of which is connected to the pull-down node, and the second electrode of which is connected to the gate-off voltage supply terminal.

9. In paragraph 8, The above pull-down transistor includes the first active layer including an oxide semiconductor, The pull-up transistor is a scan driver including the second active layer including a hetero oxide semiconductor different from the oxide semiconductor of the first active layer.

10. In paragraph 7, The above output node control unit A scan driver further comprising an eighth transistor, wherein the gate electrode is connected to the rear carry terminal, the first electrode is connected to the front carry terminal or the gate-off voltage supply terminal, and the second electrode is connected to the pull-up node.

11. In Article 10, Among the first to eighth transistors included in the output node control unit, at least one of the second, fifth to seventh transistors indirectly connected to the pull-up node includes the first active layer including an oxide semiconductor, A scan driver including the second active layer, wherein at least one of the first, third, fourth, and eighth transistors directly connected to the pull-up node among the first to eighth transistors included in the output node control unit includes a hetero oxide semiconductor different from the oxide semiconductor of the first active layer.

12. In paragraph 7, The first active layer comprises indium-gallium-zinc-oxide, The second active layer is a scan driver including indium-gallium-zinc-tin oxide.

13. A plurality of pixels arranged in a display area of ​​a display panel; and A touch sensing unit mounted on the front side of the display panel or formed integrally with the display panel; A touch driving unit that detects a touch using a plurality of touch electrodes arranged in the above touch sensing unit; A display driving unit that controls the data voltages supplied to the plurality of pixels and the image display timing of the pixels; and Including a scan driver that sequentially drives scan signal wires connected to the plurality of pixels in response to a gate control signal from the display driver, The above scan drive unit It has stages that sequentially output scan signals to scan signal wires during the active period of the Nth (N is a positive integer) frame, At least one of the above stages, An output node control unit that supplies a gate-on voltage to a pull-up node in response to a gate control signal of a display driver unit; and When the gate-on voltage is supplied to the pull-up node, the output control unit includes a scan clock signal input to the scan clock terminal and outputs the scan signal to each connected scan signal wire as a scan signal. The above output node control unit At least one thin film transistor including a first active layer and indirectly connected to the pull-up node; and A display device comprising a second active layer including a heterogeneous oxide semiconductor material different from the first active layer and at least one other thin film transistor directly connected to the pull-up node.

14. In paragraph 13, The above output node control unit A first transistor which is turned on when the pull-up node is enabled by the gate-on voltage and supplies one scan clock signal to a first capacitor connected in parallel; A second transistor which is turned on when the pull-down node is enabled by the gate-on voltage and supplies the gate-off voltage to the first transistor; A third transistor which is turned on when the pull-up node is enabled by the gate-on voltage and supplies another scan clock signal to the pull-down node; A fourth transistor that is turned on in response to a line select signal or a pre-carry signal of a sensing signal terminal and supplies the gate-on voltage to the pull-up node; A fifth transistor turned on in response to said other scan clock signal to supply said gate-on voltage to said pull-down node; A sixth transistor electrically connecting the pull-up node with another transistor or the first capacitor in response to one of the scan clock signals; and A display device including a seventh transistor that is turned on when the pull-down node is enabled to electrically connect the sixth transistor, the first capacitor, and the first transistor.

15. In paragraph 14, The above output control unit A pull-up transistor that is turned on by the gate-on voltage of the pull-up node and outputs one of the scan clock signals input to the scan clock terminal to the scan output terminal and the scan signal wiring; and A display device including a pull-down transistor that is turned on by the gate-on voltage of the pull-down node and applies the gate-off voltage to the scan output terminal and the scan signal wiring.

16. In paragraph 14, The above output node control unit A display device further comprising an eighth transistor for disabling the pull-up node with the gate-off voltage or one of the scan clock signals in response to a subsequent carry signal from the next stage.

17. In paragraph 14, The gate electrode of the first transistor is connected to the pull-up node, the first electrode is connected to the second scan clock terminal, and the second electrode is connected to the previous carry terminal and the first electrode of the second transistor. The gate electrode of the second transistor is connected to the pull-down node, the first electrode is connected to the second electrode of the first transistor and the previous carry terminal, and the second electrode of the second transistor is connected to the gate-off voltage supply terminal. The gate electrode of the third transistor is connected to the pull-up node, the first electrode is connected to the first scan clock terminal, and the second electrode of the third transistor is connected to the pull-down node. The gate electrode of the fourth transistor is connected to the sensing signal terminal or the preceding carry terminal, the first electrode is connected to the gate-on voltage supply terminal, and the second electrode is connected to the pull-up node. The gate electrode of the fifth transistor is connected to the first scan clock terminal, the first electrode is connected to the gate-on voltage supply terminal, and the second electrode is connected to the pull-down node. The gate electrode of the sixth transistor is connected to the second scan clock terminal, the first electrode is connected to the pull-up node, and the second electrode is connected to the second electrode of the first transistor or the first electrode of the seventh transistor. A display device wherein the gate electrode of the seventh transistor is connected to the pull-down node, the first electrode is connected to the second electrode of the sixth transistor, and the second electrode is connected to the second electrode of the first transistor and the first capacitor.

18. In paragraph 17, The above output control unit A pull-up transistor having a first electrode connected to the second scan clock terminal, a gate electrode connected to the pull-up node, and a second electrode connected to the scan output terminal; and A display device including a pull-down transistor, wherein a first electrode is connected to the scan output terminal, a gate electrode is connected to the pull-down node, and a second electrode is connected to a gate-off voltage supply terminal.

19. In paragraph 17, The above output node control unit A display device further comprising an eighth transistor, wherein a gate electrode is connected to a rear carry terminal, a first electrode is connected to a front carry terminal or a gate-off voltage supply terminal, and a second electrode is connected to the pull-up node.

20. In paragraph 19, Among the first to eighth transistors included in the output node control unit, at least one of the second, fifth to seventh transistors indirectly connected to the pull-up node includes the first active layer including an oxide semiconductor, A display device including the second active layer, wherein at least one of the first, third, fourth, and eighth transistors directly connected to the pull-up node among the first to eighth transistors included in the output node control unit includes a hetero oxide semiconductor different from the oxide semiconductor of the first active layer.

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