Topological devices with an asymmetric junction design

Abstract

Topological devices with asymmetric junction(s) are described. An example topological device (100) includes a superconducting wire (112) comprising a first segment (114) and a second segment (116), where the first segment (114) is configurable to be in a trivial phase and the second segment (116) is configurable to be in a topological phase. The topological device further includes an asymmetric junction (182), at an interface of the first segment (114) and the second segment (116). The asymmetric junction (182) is operable to couple a Majorana zero mode, MZM, in the second segment (116) to a quantum dot (172) or a transport lead (153) such that the asymmetric junction (182) increases strength of a coupling between the MZM and the quantum dot (172) or the transport lead (153) while reducing strength of a coupling between any states formed in the first segment (114) of the superconducting wire (112) and the quantum dot (172) or the transport lead (153).

Description

TITLETOPOLOGICAL DEVICES WITH AN ASYMMETRIC JUNCTION DESIGNBACKGROUND

[0001] In certain applications, topological devices can be used to enable measurement-based Majorana zero mode (MZM) qubits. Such MZM qubits require the ability to tune portions of a topological device into the topological phase and open or close tunnel junctions. Conventional junctions used for coupling can cause coupling to unwanted states located in outside segments or trivial segments of the topological device. Such topological devices can be improved by using a better junction design as described in the present disclosure.SUMMARY

[0002] In one example, the present disclosure relates to a topological device including a superconducting wire comprising a first segment and a second segment, where the first segment is configurable to be in a trivial phase and the second segment is configurable to be in a topological phase. The topological device may further include an asymmetric junction, at an interface of the first segment and the second segment, operable to couple a Majorana zero mode (MZM) in the second segment to a quantum dot or a transport lead such that the asymmetric junction increases strength of a coupling between the MZM and the quantum dot or the transport lead while reducing strength of a coupling between any states formed in the first segment of the superconducting wire and the quantum dot or the transport lead.

[0003] In another example, the present disclosure relates to a topological device including a superconducting wire having a first segment, a second segment, and a third segment where each of the first segment and the third segment is configurable to be in a trivial phase, and the second segment is configurable to be in a topological phase. The topological device may further include a first asymmetric junction, at an interface of the first segment and the second segment, operable to couple a first Majorana zero mode (MZM) in the second segment to a first quantum dot or a first transport lead such that the first asymmetric junction increases strength of a coupling between the first MZM and the first quantum dot or the first transport lead while reducing strength of a coupling between any states formed in the first segment of the superconducting wire and the first quantum dot or the first transport lead.

[0004] The topological device may further include a second asymmetric junction, at an interface of the second segment and the third segment, operable to couple a second MZM in the second segment to a second quantum dot or a second transport lead such that the second asymmetric junction increases strength of a coupling between the second MZM and the second quantum dot or the second transport lead while reducing strength of a coupling between any states formed in the third segment of the superconducting wire and the second quantum dot or the second transport lead.

[0005] In yet another example, the present disclosure relates to a topological device including a superconducting wire having a first segment, a second segment, and a third segment, where each of the first segment and the third segment is configurable to be in a trivial phase, and the second segment is configurable to be in a topological phase. The topological device may furtherinclude a first asymmetric junction, at an interface of the first segment and the second segment, operable to couple a first Majorana zero mode (MZM) in the second segment to a first quantum dot or a first transport lead. The topological device may further include a second asymmetric junction, at an interface of the second segment and the third segment, operable to couple a second MZM in the second segment to a second quantum dot or a second transport lead.

[0006] The topological device may further include a first side-plunger gate operable to tune the first segment of the superconducting wire into the trivial phase. The topological device may further include a middle-plunger gate operable to tune the second segment of the superconducting wire into the topological phase. The topological device may further include a second sideplunger gate operable to tune the third segment of the superconducting wire into the trivial phase, where the first side-plunger gate comprises a first portion facing the middle-plunger gate and a second portion angling away from the middleplunger gate at a first predetermined angle, and where the second side-plunger gate comprises a third portion facing the middle-plunger gate and a fourth portion angling away from the middle-plunger gate at the first predetermined angle.

[0007] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

[0009] FIG. 1 shows a top view of a topological device in accordance with one example;

[0010] FIG. 2 shows an expanded view of a portion of the topological device of FIG. 1 ;

[0011] FIG. 3 shows an expanded view of a portion of the topological device of FIG. 1 ;

[0012] FIG. 4 shows a graph that compares the local conductance plot of a device with a conventional junction with the local conductance plot of a device with an asymmetric junction;

[0013] FIG. 5 shows a graph comparing the quantum dot (QD)-Majorana zero mode (MZM) coupling for a conventional junction with the QD-MZM coupling for an asymmetric junction; and

[0014] FIG. 6 shows an expanded view of an alternative structure for an asymmetric junction for the topological device of FIG. 1 .DETAILED DESCRIPTION

[0015] Examples described in this disclosure relate to asymmetric junction design for selective coupling to a topological segment in topological devices. Topological devices can be used to enable quantum computers. Such quantumcomputers require reliable reproduction of a stable topological phase of matter that supports non-Abelian quasiparticles or defects and processes quantum information through protected operations, such as braiding.

[0016] Certain topological devices can be used to support two phases — one trivial and the other topological. As used herein, the terms topological and trivial refer to the phase of the superconductor sections (e.g., nanowire sections) that are tuned using electrostatic gates to form topological or trivial superconducting sections. Topological devices allow one to measure a topological phase transition in a 2-dimensional electron gas (2DEG) nanowire device with a single or multiple occupied sub-bands and normal-superconducting (NS) junctions for probing the device from the sides. As an example, the wire is defined by the combination of a narrow superconducting strip and one or more layers of gate electrodes. These gate electrodes deplete the surrounding 2DEG, confining the strip in a channel under the superconductor and controlling the chemical potential in the nanowire. The superconducting strip (partly) screens the electric fields from the gate electrodes defining a wire. At the same time, the superconducting strip induces superconductivity via the proximity effect. Another set of gates can be used to open and close the junction and optionally control the chemical potential in the attached quantum dots. The device can then be used, among other things, to create a Majorana zero mode-based quantum computer with qubits.

[0017] Majorana zero mode (MZM) qubits require rapidly configuring couplings between different pairs of MZMs for qubit operations and measurement. As used herein, the term qubit refers to any quantum system that can be in a superposition of two quantum states, 0 and 1 . As an example ofdevices that can be used with such a quantum system, topological devices formed from a single superconducting wire patterned on a two-dimensional electron gas (2DEG) are described. Different segments of the wire can be tuned using electrostatic gates to form trivial or topological superconducting sections, with Majorana zero modes at their interface. These gates can also be used to control the density in the 2DEG to deplete certain sections and define semiconducting regions that can form tunnel junctions. Each qubit may store information in either four or six Majorana zero modes (MZMs) and can be measured in any Pauli basis.

[0018] As explained earlier, in certain applications, topological devices can be used to enable measurement-based Majorana zero mode (MZM) qubits. Such MZM qubits require the ability to tune portions of a topological device into the topological phase and open or close tunnel junctions. Conventional junctions used for coupling can cause coupling to unwanted states located in outside segments or trivial segments of the topological device. Such topological devices can be improved by using better junction design as described in the present disclosure. As an example, the side-junctions can be improved by having an asymmetric coupling to the left side of the junction in relation to the right side of the junction.

[0019] In the topological superconducting phase of a nanowire, the low-energy physics is characterized by two real fermionic operators y1and y2. These operators are localized at the left and right ends of the topological section, respectively, and satisfy the relationship {y^y = 26ij. The wire has two nearly- degenerate ground states with opposite fermion parities iy^y2= ±1- The splittingenergy between these states is EM~ Arexp (- in the limit where L » s. Here, E represents the coherence length, and ATis the topological gap. This behavior holds also in the presence of disorder, although the coherence length E is renormalized. The expected improvements from the asymmetric design of the junction described herein include: (1) better coupling of MZMs to quantum dots, and (2) effective increase of the topological region. The better coupling of the MZMs to quantum dots may result in a better signal-to-noise (SNR) ratio. The effective increase in the topological region may result in a smaller MZM splitting energy (e.g., EM~ Arexp (-In addition, the asymmetric junction design also ensures that the MZM is formed closer to the asymmetric junction.

[0020] FIG. 1 shows a top view of a topological device 100 in accordance with one example. The top view is shown in shades of gray with transparent layering to describe the various aspects of topological device 100. Topological device 100 includes a superconducting wire 112 formed on a two-dimensional electron gas (2DEG) 110. Superconducting wire 112 may be formed as a single nanowire. As an example, superconducting wire 112 may be formed as a semiconductor wire (e.g., indium arsenide (InAs)) coated by a superconductor (e.g., aluminum (Al)).

[0021] With continued reference to FIG. 1 , topological device 100 further includes a middle-plunger gate 122, a side-plunger gate 124, another sideplunger gate 126, several cutter gates 132, 134, 136, 138, 140, and 142, a helper gate 152, and another helper gate 154. As part of topological device 100, in one example, middle-plunger gate 122, side-plunger gate 124, side-plunger gate 126, helper gate 152, and helper gate 154 may be formed as part of a first gate layerassociated with topological device 100. In addition, cutter gates 132, 134, 136, 138, 140, and 142 may be formed as part of a second gate layer, different from the first gate layer, associated with topological device 100.

[0022] Sections of superconducting wire 112 can be configured into the topological phase or the trivial phase. As an example, superconducting wire sections 114 and 118 may be configured into the trivial phase. Superconducting wire section 116 may be configured into the topological phase. In one example, the terms topological and trivial refer to the phase of the superconductor sections that are tuned using electrostatic gates to form topological or trivial superconducting sections. Topological device 100 further includes regions of the 2DEG 172, 174, and 176, in which quantum dots could be formed. The quantum dot formed in region 172 may be controlled, in part, using quantum dot gate 162 (overlayed in FIG. 1). The quantum dot formed in region 174 may be controlled, in part, using quantum dot gate 164 (overlayed in FIG. 1). The quantum dot formed in region 176 may be controlled, in part, using quantum dot gate 166 (overlayed in FIG. 1).

[0023] Some of the gates can be used to deplete the 2DEG. Once the 2DEG has been depleted, the plunger gates may be operated at even more negative voltages to tune the electrochemical potential, and therefore, the density underneath the wire. In one example, middle-plunger gate 122 may be used to control the charge density in the middle section (e.g., section 116, which is under middle plunger gate 122) of superconducting wire 112, side-plunger gate 124 may be used to control the density in the left section (e.g., section 114) of superconducting wire 112, and side-plunger gate 126 may be used to control the density in the right section (e.g., section 118) of superconducting wire 112.Middle-plunger gate 122 may also be used to tune the density of the wire to the topological regime.

[0024] Still referring to FIG. 1 , cutter gate 132 and cutter gate 136 may be used to open and close the two asymmetric junctions (e g., asymmetric junction 182 and asymmetric junction 184) formed in superconducting wire 112.Asymmetric junction 182 may be formed near a first end of superconducting wire 112 and the other asymmetric junction 184 may be formed near a second end, opposite to the first end, of superconducting wire 112. As used herein, the term “near” is used to identify the relative locations of the two junctions with respect to the opposite ends of the superconducting wire. As such, the specific location of the two junctions is determined by the location of the gates since the gates control the conductivity of the various regions of the 2DEG underlying the superconducting wire. As an example, the first asymmetric junction (e.g., asymmetric junction 182) may be formed in a region between middle-plunger gate 122 and side-plunger gate 124 and the second asymmetric junction (e.g., asymmetric junction 184) may be formed in a region between middle-plunger gate 122 and side-plunger gate 126. In addition, these junctions may be connected via conducting paths (e.g., semiconducting regions) in the 2DEG to other Ohmic contacts. Helper gates 152 and 154 may be used to increase the electron density in the junctions and leads, the latter of which may be connected to measurement circuits. As an example, helper gates 152 and 154 may also help define conducting paths by accumulating carrier density in the 2DEG underneath them and keeping such areas conductive. Transport leads 153 and 155 may be formed underneath helper gates 152 and 154, respectively, when the gates are in the accumulation mode.

[0025] The plunger gates, the cutter gates, the quantum dot gates, and the helper gates described herein may be supplied voltages via voltage waveforms generated by a control system (not shown) associated with the topological device 100 of FIG. 1 . Such a control system may include oscillators, switches, finite state machines, and a memory. As an example, the memory may be implemented as one or more multi-bit registers for allowing pulse-patterns to be stored.

[0026] Topological device 100 may be operated such that Majorana zero modes (MZMs) are formed at the ends of section 116 of superconducting wire 112. In sum, electrostatic gates around the superconductor can be used to define an adjacent semiconducting region consisting of junctions, quantum dots, and transport leads, with all other parts of the 2DEG fully depleted. There are junctions between the MZMs and neighboring semiconductors (QDs or transport leads) and junctions between two semiconductors (QDs and transport leads).

[0027] The various gates described above may be formed in different layers of topological device 100. In one example, the 2DEG underlying the gates may be manufactured by forming a series of layers of semiconductors on a substrate (e.g., using any of indium phosphide (InP) substrate, indium arsenide (InAs), indium antimonide (InSb), mercury cadmium telluride (HgCdTe), gallium arsenide (GaAs), gallium antimonide (GaSb), silicon (Si) or any appropriate combination of materials selected from groups II, III, IV, V, or VI of the periodic table, any ternary compounds of three different atoms of materials selected from groups II, III, IV, V, or VI of the periodic table, or any quarternary compounds of four different atoms of materials selected from groups II, III, IV, V, or VI of the periodic table). As an example, the 2DEG may further include a buffer layer (e.g., an indium aluminumarsenide (InAIAs) layer) formed over the substrate. The 2DEG may further include a quantum well layer (e.g., an indium arsenide (InAs) layer) formed over the buffer layer, and a barrier layer formed over the quantum well layer. Each of these layers may be formed using molecular-beam epitaxy (MBE). As an example, the MBE related process may be performed in an MBE system that allows the deposition of the appropriate materials in a vacuum.

[0028] Topologically active areas may be defined by depositing a metal layer (e.g., aluminum (Al)). A portion 150 of topological device 100 delineated by the dotted box is further described with respect to FIG. 2. Although FIG. 1 shows topological device 100 as including a certain number of components arranged and coupled in a certain way, topological device 100 may include fewer or additional components arranged and coupled differently. As an example, although FIG. 1 shows a certain configuration of gates and asymmetric junctions for topological device 100 of FIG. 1 , other configurations may also be used to implement the functionality of an asymmetric junction for the topological device 100 of FIG. 1.

[0029] FIG. 2 shows an expanded view 200 of the portion 150 of topological device 100 of FIG. 1 . Unless labeled otherwise, the expanded view 200 of the portion 150 uses the same reference numerals as used for FIG. 1 to identify the same, or portions of the same, structures of topological device 100 of FIG. 1 . Some such structures, or portions thereof, are not described again with respect to FIG. 2. Applying appropriate voltages to the various gates allows one to tune the junctions between MZMs and neighboring semiconductors (QDs or transport leads) as well as the junctions between QDs and transport leads. FIG. 2 shows a region 210 in which an MZM may be formed as part of the topological segment(e.g. , part of section 116 of superconducting wire 112 of FIG. 1). In addition, FIG. 2 shows a region 220 in which a quantum dot may be formed.

[0030] The junction is formed at the boundaries between the side-plunger gate and the middle-plunger gate. In addition, the cutter gate is also supplied a voltage to vary the transparency of the asymmetric junction. The asymmetric design of the junction for coupling the MZM and the quantum dot increases the MZM to the junction coupling while reducing coupling to the unwanted states that may be formed in the trivial segment (e.g., a part of section 114 of superconducting wire 112 of FIG. 1).

[0031] In this example, the asymmetric design of the junction is accomplished by having two portions of the side-plunger gate, such that the portion A and the portion B meet at a point identified as the KNEE in FIG. 2. Portion A of the sideplunger gate runs parallel to the mid-plunger gate. Portion B of the side-plunger gate is angled away from the mid-plunger gate as shown in FIG. 2. The sideplunger angle (0s) can be anywhere in a range of 20° to 60°. In another example, the side-plunger angle (0s) has a range of 30° to 45°. In the example shown in FIG. 2, the side-plunger angle (0s) is 45°. The expected improvements from the asymmetric design of the junction illustrated in FIG. 2 include: (1) better coupling of MZMs to quantum dots, and (2) effective increase of the topological region.The better coupling of the MZMs to quantum dots may result in a better signal-to- noise (SNR) ratio. The effective increase in the topological region may result in a smaller MZM splitting energy. In addition, the asymmetric junction design also ensures that the MZM is formed closer to the asymmetric junction.

[0032] With continued reference to FIG. 2, in terms of the design choices, the quantum dot width is affected by several design parameters, including: (1) thegap (W) between the side-plunger gate and the middle-plunger gate with respect to portion A of the side-plunger gate, (2) the mid-plunger angle, and (3) the length (L) of the cutter gate . With these design choices, the quantum dot width is equal to W + L tan(Qs). The length (L) of the cutter gate is selected such that the junction can be opened and closed using the cutter gate (e.g., cutter gate 132 of FIG. 1 ). At the same time, the length (L) of the cutter gate cannot be too large since that could make the region of the junction more disordered than otherwise. While view 200 shows portions of topological device 100 of FIG. 1 with gates and regions located on the left side of the device, similar gates and regions are formed on the right side of the device. Moreover, the asymmetric junction formed on the right side of the device is operable in an analogous manner as described with respect to the asymmetric junction formed on the left side of the device.

[0033] FIG. 3 shows a view 300 of a portion of the topological device 100 of FIG. 1 . View 300 shows portions of the gates and other structures described earlier with respect to FIG. 1 . View 300 shows a portion 302 of the side-plunger gate 124 of FIG. 1 and a portion 304 of the middle-plunger gate 122 of FIG. 1. Moreover, view 300 shows a topological segment 316 of superconducting wire 112 of FIG. 1 and a trivial segment 314 of the superconducting wire 112 of FIG. 1 . In addition, view 300 shows a portion 322 of the cutter gate 132 of FIG. 1 . View 300 further shows a portion 324 of another cutter gate. View 300 further shows depletion regions 344 and 346. View 300 further shows the region 310 in which an MZM may be formed and a region 320 in which a quantum dot may be formed.

[0034] The asymmetric junction allows a stronger coupling between the MZM formed in region 310 and the quantum dot formed in region 320. The asymmetricjunction results in a stronger coupling to the MZM formed in region 310 while reducing coupling to unwanted states formed in trivial segments (e.g., trivial segment 314 of FIG. 3). While view 300 shows portions of topological device 100 of FIG. 1 with gates and regions located on the left side of the device, similar gates and regions are formed on the right side of the device. Moreover, the asymmetric junction formed on the right side of the device is operable in an analogous manner as described with respect to the asymmetric junction formed on the left side of the device.

[0035] FIG. 4 shows a graph 400 that compares the local conductance plot 410 (open regime) of a device with a conventional junction with the local conductance plot 420 (open regime) of a device with an asymmetric junction. The horizontal axis of graph 400 corresponds to bias (measured in peV units) and the vertical axis of graph 400 corresponds to local conductance (GLL) (measured in units of e2 / h, where e is the electronic charge and h is Planck’s constant). As shown in FIG. 4, advantageously the zero bias peak conductance (related to the coupling of the junction) is wider for the device with the asymmetric junction than the zero bias peak conductance for the device with the conventional junction (422 vs. 412 in FIG. 4) indicating a stronger coupling of the MZM to a quantum dot or a transport lead for the improved topological device.

[0036] FIG. 5 shows a graph comparing the quantum dot (QD)-Majorana zero mode (MZM) coupling 510 for a conventional junction with the QD-MZM coupling 520 for an asymmetric junction. The horizontal axis of graph 500 corresponds to the local differential conductance (G) at a high-bias above the superconducting gap and measured in units of e2 / h. The vertical axis of graph 500 corresponds to the strength of the coupling t / wz / w (measured in peV units). As shown in FIG. 5,advantageously QD-MZM coupling 520 shows higher strength of the coupling (f / wz / w) for the asymmetric junction relative to the strength of the coupling (twz / w) for the conventional junction.

[0037] FIG. 6 shows an expanded view 600 of an alternative structure for the portion 150 of the topological device 100 of FIG. 1. Unless labeled otherwise, the expanded view 600 of the portion 150 uses the same reference numerals as used for FIG. 1 to identify the same, or portions of the same, structures of topological device 100 of FIG. 1 . The alternative structure for portion 150 of FIG.1 shown in expanded view can be used in place of the asymmetric junction structure shown as part of the topological device 100 of FIG. 1 . Applying appropriate voltages to the various gates allows one to tune the junctions between MZMs and neighboring semiconductors (QDs or transport leads) as well as the junctions between QDs and transport leads. FIG. 6 shows a region 610 in which an MZM may be formed as part of the topological segment (e.g., part of section 116 of superconducting wire 1 12 of FIG. 1 ). In addition, FIG. 6 shows a region 620 in which a quantum dot may be formed.

[0038] As noted before, the junction is formed at the boundaries between the side-plunger gate and the middle-plunger gate. In addition, the cutter gate is also supplied a voltage to vary the transparency of the asymmetric junction. The splitgate geometry with the plunger-cutter pairs further ensures the tuning of density for the various gate-defined sections of the superconducting wire. The asymmetric design of the junction for coupling the MZM and the quantum dot increases the MZM to the junction coupling while reducing coupling to the unwanted states that may be formed in the trivial segment (e.g., a part of section

[0039] In this example, the asymmetric design of the junction is accomplished by having two portions of the side-plunger gate, such that the portion A and the portion B meet at a point identified as the KNEE-1 in FIG. 6. Portion A of the side-plunger gate runs parallel to the mid-plunger gate. Portion B of the sideplunger gate is angled away from the mid-plunger gate as shown in FIG. 6. The side-plunger angle (0s) can be anywhere in a range of 20° to 60°. In another example, the side-plunger angle (0s) has a range of 30° to 45°. In addition, the asymmetric design of the junction is accomplished by having two portions of the mid-plunger gate, such that the portion C and the portion D meet at a point identified as the KNEE-2 in FIG. 6. Portion C of the mid-plunger gate runs parallel to the side-plunger gate. Portion D of the mid-plunger gate is angled away from the side-plunger gate as shown in FIG. 6. The mid-plunger angle (0M) can be anywhere in a range of 0° to 60°. In another example, the mid-plunger angle (0M) has a range of 30° to 45°. In the example shown in FIG. 6, the asymmetry of the junction design is achieved by having different values (greater than zero) for the side-plunger angle (0s) and the mid-plunger angle (0M). AS an example, as shown in FIG. 6 the side-plunger angle (0s) is 45° but the midplunger angle (0M) can be any angle that is smaller in value (e.g., the mid-plunger angle could be 30°) than the value for the side-plunger angle (0s).

[0040] The expected improvements from the asymmetric design of the junction illustrated in FIG. 6 include: (1) better coupling of MZMs to quantum dots, and (2) effective increase of the topological region. The effective increase in the topological region may result in a smaller MZM splitting energy. The better coupling of the MZMs to quantum dots may result in a better signal-to-noise(SNR) ratio. In addition, the asymmetric junction design also ensures that the MZM is formed closer to the asymmetric junction.

[0041] With continued reference to FIG. 6, in terms of the design choices, the quantum dot width is affected by several design parameters, including: (1) the gap (W) between the side-plunger gate and the middle-plunger gate with respect to portion A of the side-plunger gate, (2) the mid-plunger angle (0M), and (3) the length (L) of the cutter gate. With these design choices, the quantum dot width is equal to W + L(tan(0s) + tan(0M)). The length (L) of the cutter gate is selected such that the junction can be opened and closed using the cutter gate (e.g., cutter gate 132 of FIG. 1). At the same time, the length (L) of the cutter gate cannot be too large since that could make the region of the junction more disordered than otherwise. While view 600 shows portions of topological device 100 of FIG. 1 with gates and regions located on the left side of the device, similar gates and regions are formed on the right side of the device. Moreover, the asymmetric junction formed on the right side of the device is operable in an analogous manner as described with respect to the asymmetric junction formed on the left side of the device.

[0042] Although FIGs. 1-6 focus on the asymmetric junction design, other design parameters associated with the device (e.g., topological device 100 of FIG. 1) can also be optimized in conjunction with the asymmetric junction design. As explained earlier, the design of the topological device includes several different structures, including several types of gates, that are formed in one or more layers. Thus, in order to operate the topological device with a superconducting wire, formed on a 2DEG, several gates may be used, including a middle-plunger gate, a side-plunger gate, another side-plunger gate, a cuttergate, and another cutter gate, a helper gate, and another helper gate. Examples of design parameters include parameters such as plunger separation, plunger setback, plunger taper, helper setback, and helper taper. Plunger separation relates to the amount of separation between two plunger gates. In a topological device that has gates formed in only one layer, the plunger gates need to be set back from the cutter gates. Plunger setback relates to the separation between the plunger gates and the cutter gates, assuming these two gates were formed in the same layer. For a topological device that has the plunger gates formed in a different layer from the cutter gates, the plunger setback can effectively be zero. Helper setback relates to the amount of separation between the superconducting wire and the helper gate. Helper taper relates to the angle of taper of the helper gates. Each of these design parameters can be selected to optimize the performance of the topological device.

[0043] In conclusion, the present disclosure relates to a topological device including a superconducting wire comprising a first segment and a second segment, where the first segment is configurable to be in a trivial phase and the second segment is configurable to be in a topological phase. The topological device may further include an asymmetric junction, at an interface of the first segment and the second segment, operable to couple a Majorana zero mode (MZM) in the second segment to a quantum dot or a transport lead such that the asymmetric junction increases strength of a coupling between the MZM and the quantum dot or the transport lead while reducing strength of a coupling between any states formed in the first segment of the superconducting wire and the quantum dot or the transport lead.

[0044] The quantum dot may be formed in a semiconducting region tunable using an electrostatic gate. The topological device may further comprise a sideplunger gate operable to tune the first segment of the superconducting wire into the trivial phase. The topological device may further comprise a middle-plunger gate operable to tune the second segment of the superconducting wire into the topological phase.

[0045] The side-plunger gate may comprise a first portion facing the middleplunger gate and a second portion angling away from the middle-plunger gate at a predetermined angle. In one example, the predetermined angle may be in a range from 20° to 60°. In another example, the predetermined angle may be 45°. The superconducting wire may be patterned on a two-dimensional electron gas (2DEG).

[0046] In another example, the present disclosure relates to a topological device including a superconducting wire having a first segment, a second segment, and a third segment where each of the first segment and the third segment is configurable to be in a trivial phase, and the second segment is configurable to be in a topological phase. The topological device may further include a first asymmetric junction, at an interface of the first segment and the second segment, operable to couple a first Majorana zero mode (MZM) in the second segment to a first quantum dot or a first transport lead such that the first asymmetric junction increases strength of a coupling between the first MZM and the first quantum dot or the first transport lead while reducing strength of a coupling between any states formed in the first segment of the superconducting wire and the first quantum dot or the first transport lead.

[0047] The topological device may further include a second asymmetric junction, at an interface of the second segment and the third segment, operable to couple a second MZM in the second segment to a second quantum dot or a second transport lead such that the second asymmetric junction increases strength of a coupling between the second MZM and the second quantum dot or the second transport lead while reducing strength of a coupling between any states formed in the third segment of the superconducting wire and the second quantum dot or the second transport lead.

[0048] The first quantum dot may be formed in a first semiconducting region tunable using a first electrostatic gate, and the second quantum dot may be formed in a second semiconducting region tunable using a second electrostatic gate. The topological device may further comprise: (1) a first side-plunger gate operable to tune the first segment of the superconducting wire into the trivial phase, (2) a middle-plunger gate operable to tune the second segment of the superconducting wire into the topological phase, and (3) a second side-plunger gate operable to tune the third segment of the superconducting wire into the trivial phase.

[0049] The first side-plunger gate may comprise a first portion facing the middle-plunger gate and a second portion angling away from the middle-plunger gate at a predetermined angle. The second side-plunger gate may comprise a third portion facing the middle-plunger gate and a fourth portion angling away from the middle-plunger gate at the predetermined angle. In one example, the predetermined angle may be in a range from 20° to 60°. In another example, the predetermined angle may be 45°.

[0050] In yet another example, the present disclosure relates to a topological device including a superconducting wire having a first segment, a second segment, and a third segment, where each of the first segment and the third segment is configurable to be in a trivial phase, and the second segment is configurable to be in a topological phase. The topological device may further include a first asymmetric junction, at an interface of the first segment and the second segment, operable to couple a first Majorana zero mode (MZM) in the second segment to a first quantum dot or a first transport lead. The topological device may further include a second asymmetric junction, at an interface of the second segment and the third segment, operable to couple a second MZM in the second segment to a second quantum dot or a second transport lead.

[0051] The topological device may further include a first side-plunger gate operable to tune the first segment of the superconducting wire into the trivial phase. The topological device may further include a middle-plunger gate operable to tune the second segment of the superconducting wire into the topological phase. The topological device may further include a second sideplunger gate operable to tune the third segment of the superconducting wire into the trivial phase, where the first side-plunger gate comprises a first portion facing the middle-plunger gate and a second portion angling away from the middleplunger gate at a first predetermined angle, and where the second side-plunger gate comprises a third portion facing the middle-plunger gate and a fourth portion angling away from the middle-plunger gate at the first predetermined angle.

[0052] The middle-plunger gate may comprise a fifth portion facing the first side-plunger gate and a sixth portion angling away from the first side-plunger gate at a second predetermined angle, different from the first predeterminedangle. The middle-plunger gate may comprise a seventh portion facing the second side-plunger gate and an eighth portion angling away from the second side-plunger gate at the second predetermined angle, different from the first predetermined angle. In one example, the predetermined angle may be in a range from 20° to 60°. In addition, the second predetermined angle may be smaller than the first predetermined angle.

[0053] It is to be understood that the systems, devices, methods, and components described herein are merely examples. In an abstract, but still definite sense, any arrangement of components to achieve the same functionality is effectively "associated" such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as "associated with" each other such that the desired functionality is achieved, irrespective of architectures or inter-medial components. Likewise, any two components so associated can also be viewed as being "operably connected," or "coupled," to each other to achieve the desired functionality.Merely because a component, which may be an apparatus, a structure, a device, a system, or any other implementation of a functionality, is described herein as being coupled to another component does not mean that the components are necessarily separate components. As an example, a component A described as being coupled to another component B may be a sub-component of the component B, the component B may be a sub-component of the component A, or components A and B may be a combined sub-component of another component C.

[0054] Furthermore, those skilled in the art will recognize that boundaries between the functionality of the above described operations are merelyillustrative. The functionality of multiple operations may be combined into a single operation, and / or the functionality of a single operation may be distributed in additional operations. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments.

[0055] Although the disclosure provides specific examples, various modifications and changes can be made without departing from the scope of the disclosure as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present disclosure. Any benefits, advantages, or solutions to problems that are described herein with regard to a specific example are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.

[0056] Furthermore, the terms "a" or "an," as used herein, are defined as one or more than one. Also, the use of introductory phrases such as "at least one" and "one or more" in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an." The same holds true for the use of definite articles.

[0057] Unless stated otherwise, terms such as "first" and "second" are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.

Claims

WHAT IS CLAIMED:1 . A topological device (100) comprising: a superconducting wire (112) comprising a first segment (114) and a second segment (116), wherein the first segment (114) is configurable to be in a trivial phase and the second segment (116) is configurable to be in a topological phase; and an asymmetric junction (182), at an interface of the first segment (114) and the second segment (116), operable to couple a Majorana zero mode (MZM) in the second segment (116) to a quantum dot (172) or a transport lead such that the asymmetric junction (182) increases strength of a coupling between the MZM and the quantum dot (172) or the transport lead while reducing strength of a coupling between any states formed in the first segment (114) of the superconducting wire (112) and the quantum dot (172) or the transport lead.

2. The topological device of claim 1 , wherein the quantum dot is formed in a semiconducting region tunable using an electrostatic gate.

3. The topological device of claim 1 , further comprising a side-plunger gate operable to tune the first segment of the superconducting wire into the trivial phase.

4. The topological device of claim 1 , further comprising a middle-plunger gate operable to tune the second segment of the superconducting wire into the topological phase.

5. The topological device of claim 3, wherein the side-plunger gate comprises a first portion facing the middle-plunger gate and a second portion angling away from the middle-plunger gate at a predetermined angle.

6. The topological device of claim 5, wherein the predetermined angle is in a range from 20° to 60°.

7. The topological device of claim 5, wherein the predetermined angle is 45°.

8. The topological device of claim 1 , wherein the superconducting wire is patterned on a two-dimensional electron gas (2DEG).

9. A topological device (100) comprising: a superconducting wire (112) having a first segment (114), a second segment (116), and a third segment (118) wherein each of the first segment (114) and the third segment (118) is configurable to be in a trivial phase, and the second segment (116) is configurable to be in a topological phase; a first asymmetric junction (182), at an interface of the first segment (1 14) and the second segment (116), operable to couple a first Majorana zero mode (MZM) in the second segment to a first quantum dot (172) or a first transport lead such that the first asymmetric junction (182) increases strength of a coupling between the first MZM and the first quantum dot (172) or the first transport lead while reducing strength of a coupling between any states formed in the first segment (114) of the superconducting wire (112) and the first quantum dot (172) or the first transport lead; and a second asymmetric junction (184), at an interface of the second segment (116) and the third segment (118), operable to couple a secondMZM in the second segment (116) to a second quantum dot (176) or a second transport lead such that the second asymmetric junction (184) increases strength of a coupling between the second MZM and the second quantum dot (176) or the second transport lead while reducing strength of a coupling between any states formed in the third segment (118) of the superconducting wire (112) and the second quantum dot (176) or the second transport lead.

10. The topological device of claim 9, wherein the first quantum dot is formed in a first semiconducting region tunable using a first electrostatic gate, and wherein the second quantum dot is formed in a second semiconducting region tunable using a second electrostatic gate.11 . The topological device of claim 9, further comprising: (1 ) a first sideplunger gate operable to tune the first segment of the superconducting wire into the trivial phase, (2) a middle-plunger gate operable to tune the second segment of the superconducting wire into the topological phase, and (3) a second side-plunger gate operable to tune the third segment of the superconducting wire into the trivial phase.

12. The topological device of claim 1 1 , wherein the first side-plunger gate comprises a first portion facing the middle-plunger gate and a second portion angling away from the middle-plunger gate at a predetermined angle.

13. The topological device of claim 12, wherein the second side-plunger gate comprises a third portion facing the middle-plunger gate and a fourth portion angling away from the middle-plunger gate at the predetermined angle.

14. The topological device of claim 13, wherein the predetermined angle is in a range from 20° to 60°.

15. The topological device of claim 14, wherein the predetermined angle is 45°.

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