Solar cell and preparation method therefor

Abstract

The present application relates to a solar cell and a preparation method therefor. The preparation method for a solar cell of the present application comprises: preparing a first doped silicon material layer (4), a first intrinsic silicon material layer (5) and a first protective layer (6), which are sequentially stacked on a surface of a substrate; forming a groove in the first protective layer (6) by means of a laser; etching away the first doped silicon material layer (4) at the groove; and performing annealing to convert the first doped silicon material layer (4) and the first intrinsic silicon material layer (5) into a first doped polycrystalline silicon layer (10).

Description

Solar cell and preparation method thereof

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on December 28, 2023, with application number 202311869248.7 and invention name “Solar Cell and Its Preparation Method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of photovoltaic technology, and in particular to a solar cell and a method for preparing the same. Background Art

[0003] During the solar cell fabrication process, patterning of the doped layer is typically achieved through laser grooving followed by wet etching. During the traditional laser grooving process, the laser's action on the doped polysilicon layer causes a localized increase in the doping concentration at the contact area. This high doping concentration in the doped polysilicon region makes wet etching of the doped polysilicon more difficult, impacting the subsequent wet etching process and resulting in poor etching results. Summary of the Invention

[0004] Based on this, it is necessary to provide a solar cell and a method for preparing the same. The method for preparing the solar cell in this application can reduce the formation of local high-doped regions during the laser grooving process, reduce the impact on subsequent wet etching, and thus obtain doped polysilicon with better etching effect.

[0005] In a first aspect, the present application provides a method for preparing a solar cell, comprising:

[0006] A first doped silicon material layer, a first intrinsic silicon material layer, and a first protective layer are sequentially stacked on the surface of the substrate;

[0007] forming a groove on the first protective layer by laser, wherein the groove only penetrates the first protective layer, or the groove penetrates the first protective layer and partially penetrates the first intrinsic silicon material layer;

[0008] removing the first doped silicon material layer at the groove by wet etching;

[0009] Annealing converts the first doped silicon material layer and the first intrinsic silicon material layer into a first doped polysilicon layer.

[0010] In some embodiments, the annealing temperature is 850°C to 950°C.

[0011] In some embodiments, the doping concentration of the first doped polysilicon layer is 8×10 19 cm -3 ~1×10 20 cm-3 .

[0012] In some embodiments, the thickness of the first doped silicon material layer is 50 nm to 100 nm.

[0013] In some embodiments, the thickness of the first intrinsic silicon material layer is 100 nm to 500 nm.

[0014] In some embodiments, forming a first doped silicon material layer, a first intrinsic silicon material layer, and a first protective layer stacked sequentially on a surface of a substrate includes:

[0015] A second intrinsic silicon material layer, a first doped silicon material layer, a first intrinsic silicon material layer and a first protective layer are prepared on the surface of the substrate and are stacked in sequence.

[0016] In some embodiments, forming a second intrinsic silicon material layer on the surface of the substrate includes:

[0017] A first tunneling oxide layer is formed on the surface of the substrate, and the second intrinsic silicon material layer is formed on the surface of the first tunneling oxide layer.

[0018] In some embodiments, the thickness of the first tunnel oxide layer is 1 nm to 3 nm.

[0019] In some embodiments, the second intrinsic silicon material layer has a thickness of 50 nm to 100 nm.

[0020] In some embodiments, the doping element of the first doped silicon material layer includes boron.

[0021] In some embodiments, after removing the first doped silicon material layer in the groove by wet etching, the method further includes:

[0022] preparing a second doped silicon material layer at the bottom of the groove, wherein the first doped silicon material layer and the second doped silicon material layer are spaced apart;

[0023] The doping type of the first doped silicon material layer is opposite to the doping type of the second doped silicon material layer.

[0024] In some embodiments, removing the first doped silicon material layer at the groove by wet etching includes: making the groove partially penetrate the substrate;

[0025] Along the depth direction of the groove, a surface of the second doped silicon material layer away from the bottom of the groove is lower than a surface of the first doped silicon material layer facing the substrate.

[0026] In some embodiments, making the groove partially penetrate the substrate includes: making the height difference between the bottom of the groove and the surface of the substrate where the first doped silicon material layer is provided be 2 μm to 4 μm.

[0027] In some embodiments, preparing the second doped silicon material layer at the bottom of the groove includes: preparing a second tunneling oxide layer and a second doped silicon material layer stacked in sequence at the bottom of the groove.

[0028] In some embodiments, the thickness of the second tunnel oxide layer is 1 nm to 3 nm.

[0029] In some embodiments, the thickness of the second doped silicon material layer is 100 nm to 500 nm.

[0030] In a second aspect, the present application provides a solar cell prepared by any of the above-mentioned methods for preparing a solar cell.

[0031] In the above-mentioned solar cell manufacturing method, a first intrinsic silicon material layer is prepared on the surface of the first doped silicon material layer away from the substrate. The first intrinsic silicon material layer serves as a laser buffer layer. During the subsequent laser grooving of the first protective layer, by controlling the grooves to only penetrate the first protective layer, or by ensuring that the grooves penetrate the first protective layer and partially penetrate the first intrinsic silicon material layer, the laser can be prevented from contacting the doped silicon material layer, thereby reducing the formation of localized highly doped regions during the laser grooving process and thereby reducing the impact on subsequent wet etching. Simultaneously, through annealing, the first doped silicon material layer and the first intrinsic silicon material layer can be converted into a first doped polysilicon layer, thereby obtaining a doped polysilicon layer with relatively good etching performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] FIG1 is a schematic structural diagram of a first tunneling oxide layer, a second intrinsic silicon material layer, a first doped silicon material layer, a first intrinsic silicon material layer, and a first protective layer stacked sequentially on a surface of a substrate according to an embodiment of the present application;

[0033] FIG2 is a schematic diagram of a structure in which a groove is formed by laser on the basis of the structure shown in FIG1 ;

[0034] FIG3 is a schematic diagram of a structure in which the first intrinsic silicon material layer, the first doped silicon material layer, the second intrinsic silicon material layer and the first tunnel oxide layer are etched away at the groove based on the structure shown in FIG2 , so that the groove partially penetrates the substrate;

[0035] FIG4 is a schematic structural diagram of preparing a second tunneling oxide layer, a second doped silicon material layer and a second protective layer based on the structure shown in FIG3 ;

[0036] 5 is a schematic structural diagram showing that annealing is performed on the basis of the structure shown in FIG. 4 so that the third intrinsic amorphous silicon layer, the first doped silicon material layer and the first intrinsic silicon material layer are converted into a first doped polysilicon layer, and the second doped silicon material layer is converted into a second doped silicon material layer;

[0037] FIG6 is a schematic structural diagram of a velvet surface obtained by performing a velvet treatment on the structure shown in FIG5 ;

[0038] FIG7 is a schematic structural diagram of preparing a first passivation layer, a first anti-reflection layer, a second passivation layer, and a second anti-reflection layer based on the structure shown in FIG6 ;

[0039] FIG8 is a schematic diagram showing a structure of preparing a first electrode and a second electrode based on the structure shown in FIG7 .

[0040] Explanation of the accompanying symbols: 1. substrate; 2. first tunneling oxide layer; 3. second intrinsic silicon material layer; 4. first doped silicon material layer; 5. first intrinsic silicon material layer; 6. first protective layer; 7. second tunneling oxide layer; 8. second doped silicon material layer; 9. second protective layer; 10. first doped polysilicon layer; 11. second doped polysilicon layer; 12. first passivation layer; 13. first anti-reflection layer; 14. second passivation layer; 15. second anti-reflection layer; 16. first electrode; 17. second electrode. DETAILED DESCRIPTION

[0041] To make the above-mentioned objects, features, and advantages of the present application more clearly understood, the specific embodiments of the present application are described in detail below. The following description sets forth many specific details to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways than those described herein, and those skilled in the art can make similar modifications without violating the scope of the present application. Therefore, the present application is not limited to the specific embodiments disclosed below.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0043] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0044] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of such features. In the description of this application, "plurality" means at least two, for example, two, three, etc., unless otherwise specifically defined.

[0045] In this application, unless otherwise specified or limited, the terms "installed," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they can refer to fixed connection, detachable connection, or integration; mechanical connection or electrical connection; direct connection or indirect connection through an intermediate medium; internal communication between two elements or interaction between two elements, unless otherwise specified. Those skilled in the art will understand the specific meanings of the above terms in this application based on specific circumstances.

[0046] 1 to 5 , an embodiment of the present application provides a method for preparing a solar cell, comprising:

[0047] S110: preparing a first doped silicon material layer 4, a first intrinsic silicon material layer 5 and a first protective layer 6 stacked in sequence on a surface of a substrate 1;

[0048] S120: forming a groove on the first protective layer 6 by laser, wherein the groove only penetrates the first protective layer 6, or the groove penetrates the first protective layer 6 and partially penetrates the first intrinsic silicon material layer 5;

[0049] S130: removing the first doped silicon material layer 4 in the groove by wet etching;

[0050] S140 : Annealing to transform the first doped silicon material layer 4 and the first intrinsic silicon material layer 5 into a first doped polysilicon layer 10 .

[0051] In the above-mentioned method for preparing solar cells, a first intrinsic silicon material layer 5 is prepared on the surface of the first doped silicon material layer 4 away from the substrate 1. The first intrinsic silicon material layer 5 serves as a laser buffer layer. In the subsequent process of grooving the first protective layer by laser, by controlling the groove to only penetrate the first protective layer 6, or the groove to penetrate the first protective layer 6 and partially penetrate the first intrinsic silicon material layer 5, the laser can be prevented from contacting the doped silicon material layer, thereby reducing the formation of local high-doped areas during the laser grooving process, thereby reducing the impact on subsequent wet etching. At the same time, the first doped silicon material layer 4 and the first intrinsic silicon material layer 5 can be converted into a first doped polysilicon layer 10 through annealing, thereby obtaining a doped polysilicon layer with a relatively good etching effect. The first protective layer 6 can serve as a protective layer for subsequent etching or texturing of the sample to protect the underlying film layer.

[0052] In some embodiments, the material of the first protection layer 6 includes silicon oxide.

[0053] In some embodiments, the annealing temperature is 850° C. to 950° C. Within this annealing temperature range, the dopant atoms in the first doped silicon material layer 4 can diffuse, so that the first doped silicon material layer 4 and the first intrinsic silicon material layer 5 are transformed into an integrated first doped polysilicon layer 10. Optionally, the annealing temperature is 850° C., 860° C., 870° C., 880° C., 890° C., 900° C., 910° C., 920° C., 930° C., 940° C., or 950° C. Alternatively, the annealing temperature can be within a range between any two of the above temperatures.

[0054] In some embodiments, the doping concentration of the first doped polysilicon layer 10 is 8×10 19 cm -3 ~1×10 20 cm -3 The first doped polysilicon layer 10 with a higher doping concentration can be obtained by the above preparation method. Optionally, the doping concentration of the first doped polysilicon layer 10 is 8×10 19 cm -3 , 8.1×10 19 cm -3 , 8.2×10 19 cm -3 , 8.3×10 19 cm -3 , 8.4×10 19 cm -3 , 8.5×10 19 cm -3 , 8.6×10 19 cm -3 , 8.7×10 19 cm -3, 8.8×10 19 cm -3 , 8.9×10 19 cm -3 , 9×10 19 cm -3 , 9.1×10 19 cm -3 , 9.2×10 19 cm -3 , 9.3×10 19 cm -3 , 9.4×10 19 cm -3 , 9.5×10 19 cm -3 , 9.6×10 19 cm -3 , 9.7×10 19 cm -3 , 9.8×10 19 cm -3 , 9.9×10 19 cm -3 or 1×10 20 cm -3 Alternatively, the doping concentration of the first doped polysilicon layer 10 may also be within a range between any two of the above doping concentrations.

[0055] It should be noted that the doping concentration of doped polysilicon obtained by conventional solar cell preparation methods is generally 4×10 19 cm -3 ~7×10 19 cm -3 On the basis of controlling the laser not to contact the first doped silicon material layer 4 , the first doped silicon material layer 4 can be doped with a higher concentration, thereby realizing a first doped polysilicon layer 10 with a higher doping concentration.

[0056] In some embodiments, the thickness of the first doped silicon material layer 4 is 50 nm to 100 nm. Alternatively, the thickness of the first doped silicon material layer 4 is 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, or 100 nm. Alternatively, the thickness of the first doped silicon material layer 4 may be within a range between any two of the aforementioned thicknesses.

[0057] In some embodiments, the thickness of the first intrinsic silicon material layer 5 is 100 nm to 500 nm. Within the thickness range of the first intrinsic silicon material layer 5, the first doped silicon material layer 4 and the first intrinsic silicon material layer 5 can be converted into a first doped polysilicon layer 10 with a higher doping concentration through annealing. Optionally, the thickness of the first intrinsic silicon material layer 5 is 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, or 500 nm. Alternatively, the thickness of the first intrinsic silicon material layer 5 can also be within a range between any two of the above thicknesses.

[0058] As shown in Figure 1, in some embodiments, preparing a first doped silicon material layer 4, a first intrinsic silicon material layer 5 and a first protective layer 6 stacked in sequence on the surface of a substrate 1 includes: preparing a second intrinsic silicon material layer 3, a first doped silicon material layer 4, a first intrinsic silicon material layer 5 and a first protective layer 6 stacked in sequence on the surface of the substrate 1.

[0059] The second intrinsic silicon material layer 3 can serve as a buffer layer between the first tunneling oxide layer 2 and the first doped silicon material layer 4, thereby reducing the risk of penetration of the first tunneling oxide layer 2. Furthermore, the deposition rate of the intrinsic amorphous silicon layer is greater than that of the doped layer, and this preparation method can increase the deposition rate of the entire film layer.

[0060] In some embodiments, the first doped silicon material layer 4 is a first doped single crystal silicon layer. It is understood that annealing can transform the first doped single crystal silicon layer and the first intrinsic silicon material layer 5 into the first doped polysilicon layer 10 .

[0061] 1 , in some embodiments, preparing a second intrinsic silicon material layer 3 on the surface of a substrate 1 includes: preparing a first tunneling oxide layer 2 on the surface of the substrate 1 , and preparing a second intrinsic silicon material layer 3 on the surface of the first tunneling oxide layer 2 .

[0062] In some embodiments, the thickness of the first tunnel oxide layer 2 is 1 nm to 3 nm. Optionally, the thickness of the first tunnel oxide layer 2 is 1 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm, 2 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm, 2.6 nm, 2.7 nm, 2.8 nm, 2.9 nm, or 3 nm. Alternatively, the thickness of the first tunnel oxide layer 2 may be within a range between any two of the above thicknesses.

[0063] In some embodiments, the second intrinsic silicon material layer 3 has a thickness of 50 nm to 100 nm. Alternatively, the second intrinsic silicon material layer 3 has a thickness of 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, or 100 nm. Alternatively, the thickness of the second intrinsic silicon material layer 3 may be within a range between any two of the aforementioned thicknesses.

[0064] In some embodiments, the doping element of the first doped silicon material layer 4 includes boron.

[0065] In some embodiments, a borosilicate glass layer is further provided on the surface of the first doped silicon material layer 4 away from the substrate 1 .

[0066] 4 , in some embodiments, after wet etching to remove the first doped silicon material layer 4 at the groove, the method further includes: forming a second doped silicon material layer 8 at the bottom of the groove, wherein the first doped silicon material layer 4 and the second doped silicon material layer 8 are spaced apart. The doping type of the first doped silicon material layer 4 and the doping type of the second doped silicon material layer 8 are opposite.

[0067] It can be understood that the interval arrangement of the first doped silicon material layer 4 and the second doped silicon material layer 8 can be achieved by staggering the first doped silicon material layer 4 and the second doped silicon material layer 8 in the depth direction of the groove, or the first doped silicon material layer 4 and the second doped silicon material layer 8 can be set at the same height and achieved through the gap between the first doped silicon material layer 4 and the second doped silicon material layer 8.

[0068] In some embodiments, the doping element of the second doped silicon material layer 8 includes phosphorus.

[0069] As shown in FIG3 , in some embodiments, wet etching to remove the first doped silicon material layer 4 at the groove includes: causing the groove to partially penetrate the substrate 1. Along the depth direction of the groove, a surface of the second doped silicon material layer 8 away from the groove bottom is lower than a surface of the first doped silicon material layer 4 facing the substrate 1. Through the above arrangement method, the first doped silicon material layer 4 and the second doped silicon material layer 8 can be spaced apart by staggering the height difference along the depth direction of the groove.

[0070] In some embodiments, forming a groove partially through the substrate 1 includes: ensuring that the height difference between the bottom of the groove and the surface of the substrate 1 provided with the first doped silicon material layer 4 is 2 μm to 4 μm. Within the height difference between the bottom of the groove and the surface of the substrate 1 provided with the first doped silicon material layer 4, a second doped silicon material layer 8 of appropriate thickness can be deposited on the bottom of the groove, and the second doped silicon material layer 8 does not contact the first doped silicon material layer 4. Optionally, the height difference between the bottom of the groove and the surface of the substrate 1 provided with the first doped silicon material layer 4 is 2 μm, 2.1 μm, 2.2 μm, 2.3 μm, 2.4 μm, 2.5 μm, 2.6 μm, 2.7 μm, 2.8 μm, 2.9 μm, 3.0 μm, 3.1 μm, 3.2 μm, 3.3 μm, 3.4 μm, 3.5 μm, 3.6 μm, 3.7 μm, 3.8 μm, 3.9 μm, or 4 μm. Alternatively, the height difference between the bottom of the groove and the surface of the substrate 1 provided with the first doped silicon material layer 4 may also be within the range between any two of the above height differences.

[0071] As shown in Figure 4, in some embodiments, forming a second doped silicon material layer 8 at the bottom of the groove includes forming a second tunneling oxide layer 7 and a second doped silicon material layer 8 stacked sequentially at the bottom of the groove. It should be noted that no intrinsic silicon material layer is provided between the second tunneling oxide layer 7 and the second doped silicon material layer 8. This is because, generally speaking, the load in the P region is greater than that in the N region. Therefore, a second intrinsic silicon material layer 3 is required in the P region, i.e., between the first tunneling oxide layer 2 and the first doped silicon material layer 4, to provide diffusion protection for the first tunneling oxide layer 2. The load in the N region is less, meaning that an intrinsic silicon material layer is not required between the second tunneling oxide layer 7 and the second doped silicon material layer 8 for diffusion protection. Furthermore, the provision of the second intrinsic silicon material layer 3 increases the thickness of the first doped polysilicon layer 10. The required thickness of the second doped polysilicon layer 11 is smaller than that of the first doped polysilicon layer 10. Therefore, an intrinsic silicon material layer is not required between the second tunneling oxide layer 7 and the second doped silicon material layer 8.

[0072] In some embodiments, the second doped silicon material layer 8 has a thickness of 100 nm to 500 nm. Alternatively, the second doped silicon material layer 8 has a thickness of 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, or 500 nm. Alternatively, the thickness of the second doped silicon material layer 8 may be within a range between any two of the aforementioned thicknesses.

[0073] In some embodiments, the second tunnel oxide layer 7 has a thickness of 1 nm to 3 nm. Optionally, the second tunnel oxide layer 7 has a thickness of 1 nm, 1.1 nm, 1.2 nm, 1.3 nm, 1.4 nm, 1.5 nm, 1.6 nm, 1.7 nm, 1.8 nm, 1.9 nm, 2 nm, 2.1 nm, 2.2 nm, 2.3 nm, 2.4 nm, 2.5 nm, 2.6 nm, 2.7 nm, 2.8 nm, 2.9 nm, or 3 nm. Alternatively, the thickness of the second tunnel oxide layer 7 may be within a range between any two of the aforementioned thicknesses.

[0074] In some embodiments, the material of the first tunnel oxide layer 2 includes silicon oxide.

[0075] In some embodiments, the substrate 1 includes an N-type silicon wafer.

[0076] In some embodiments, before preparing the first tunneling oxide layer 2 , the first doped silicon material layer 4 and the first intrinsic silicon material layer 5 stacked in sequence on the surface of the substrate 1 , the process further includes: removing damage and cleaning the silicon wafer with alkaline solution.

[0077] In some embodiments, removing the first doped silicon material layer 4 in the groove by wet etching includes: removing the first doped silicon material layer 4 in the groove by wet alkaline etching.

[0078] 4 , in some embodiments, preparing the second doped silicon material layer 8 at the bottom of the groove includes: preparing a second tunneling oxide layer 7 , a second doped silicon material layer 8 , and a second protective layer 9 stacked sequentially at the bottom of the groove.

[0079] A second protective layer 9 is prepared on the surface of the second doped silicon material layer 8. The second protective layer 9 can serve as a protective layer for subsequent etching or texturing of the sample to protect the underlying film layer.

[0080] It can be understood that the second doped silicon material layer 8 can be a doped polysilicon layer prepared directly by high-temperature diffusion, or a doped single crystal silicon layer can be prepared first, and annealing is performed so that the first doped silicon material layer 4 and the first intrinsic silicon material layer 5 are converted into the first doped polysilicon layer 10, while the doped single crystal silicon layer is also converted into the second doped polysilicon layer 11.

[0081] 6 , in some embodiments, after annealing, the process further includes texturing the surface of the substrate 1 opposite to the surface on which the first doped silicon material layer 4 is provided. The textured surface obtained by the texturing process can enhance the light trapping effect of the surface.

[0082] 7 , in some embodiments, the texturing process further includes: removing the first protective layer 6 and / or the second protective layer 9 ; and preparing a first passivation layer 12 and a first anti-reflection layer 13 stacked in sequence on the surfaces of the first doped polysilicon layer 10 and the second protective layer 9 .

[0083] In some embodiments, the method of removing the first protective layer 6 includes removing the first protective layer 6 by cleaning with hydrofluoric acid.

[0084] In some embodiments, the method of removing the second protective layer 9 includes removing the second protective layer 9 by cleaning with hydrofluoric acid.

[0085] In some embodiments, the material of the first passivation layer 12 includes aluminum oxide.

[0086] In some embodiments, the material of the first anti-reflection layer 13 includes silicon nitride.

[0087] In some embodiments, after the texturing treatment, the method further includes: preparing a second passivation layer 14 and a second anti-reflection layer 15 stacked in sequence on the texturing surface.

[0088] In some embodiments, the material of the second passivation layer 14 includes aluminum oxide.

[0089] In some embodiments, the material of the second anti-reflection layer 15 includes silicon nitride.

[0090] 8 , in some embodiments, the method for preparing a solar cell further includes: preparing a first electrode 16 on the surface of the first anti-reflection layer 13 covering the portion of the first doped polysilicon layer 10 , wherein the first electrode 16 is in contact with the first doped polysilicon layer 10 .

[0091] In some embodiments, the method for preparing a solar cell further includes: forming a second electrode 17 on the surface of the second anti-reflection layer 15 covering the portion of the second doped polysilicon layer 11 , wherein the second electrode 17 is in contact with the second doped polysilicon layer 11 .

[0092] In some embodiments, the preparation methods of the first tunneling oxide layer 2, the second intrinsic silicon material layer 3, the first doped silicon material layer 4, the first intrinsic silicon material layer 5, the first protective layer 6, the second tunneling oxide layer 7, the second doped silicon material layer 8, the second protective layer 9, the first doped polysilicon layer 10, the second doped polysilicon layer 11, the first passivation layer 12, the first anti-reflection layer 13, the second passivation layer 14 and the second anti-reflection layer 15 are each independently selected from low-pressure chemical vapor deposition and plasma-enhanced chemical vapor deposition.

[0093] Referring again to Figures 1 to 8, in some embodiments, a method for preparing a solar cell includes:

[0094] S210: preparing a first tunneling oxide layer 2, a second intrinsic silicon material layer 3, a first doped silicon material layer 4, a first intrinsic silicon material layer 5 and a first protective layer 6 stacked in sequence on a surface of a substrate 1;

[0095] S220: forming a groove on the first protective layer 6 by laser, wherein the groove penetrates the first protective layer 6 and partially penetrates the first intrinsic silicon material layer 5;

[0096] S230: etching and removing the first doped silicon material layer 4, the second intrinsic silicon material layer 3 and the first tunnel oxide layer 2 at the groove, so that the groove partially penetrates the substrate 1;

[0097] S240: A second tunneling oxide layer 7, a second doped silicon material layer 8, and a second protective layer 9 are sequentially stacked at the bottom of the groove, wherein, along the depth direction of the groove, a surface of the second doped silicon material layer 8 away from the bottom of the groove is lower than a surface of the first doped silicon material layer 4 facing the substrate 1;

[0098] S250 : Annealing so that the second intrinsic silicon material layer 3 , the first doped silicon material layer 4 and the first intrinsic silicon material layer 5 are transformed into the first doped polysilicon layer 10 , and the second doped silicon material layer 8 is transformed into the second doped polysilicon layer 11 ;

[0099] S260: performing a texturing process on a surface of the substrate 1 opposite to the surface on which the first doped silicon material layer 4 is provided, to obtain a textured surface;

[0100] S270: removing the first protective layer 6 and the second protective layer 9, and forming a first passivation layer 12 and a first anti-reflection layer 13 stacked in sequence on the surfaces of the first doped polysilicon layer 10 and the second doped polysilicon layer 11;

[0101] S280: preparing a second passivation layer 14 and a second anti-reflection layer 15 stacked in sequence on the suede surface;

[0102] S290: A first electrode 16 is prepared on the surface of the first anti-reflection layer 13 covering the portion of the first doped polysilicon layer 10, and the first electrode 16 is in contact with the first doped polysilicon layer 10. A second electrode 17 is prepared on the surface of the second anti-reflection layer 15 covering the portion of the second doped polysilicon layer 11, and the second electrode 17 is in contact with the second doped polysilicon layer 11.

[0103] Yet another embodiment of the present application provides a solar cell, which is prepared by any of the above-mentioned methods for preparing a solar cell.

[0104] The following are specific embodiments

[0105] Example 1

[0106] Preparation method of solar cells:

[0107] (1) An N-type silicon wafer is selected as substrate 1, and a sodium hydroxide solution is used to remove damage and clean the silicon wafer.

[0108] (2) on the front surface of the substrate 1, a first tunneling oxide layer 2 with a thickness of 1.5 nm, a second intrinsic silicon material layer 3 with a thickness of 50 nm, a first boron-doped doped silicon material layer 4 with a thickness of 100 nm, a first intrinsic silicon material layer 5 with a thickness of 200 nm, and a first protective layer 6 with a thickness of 20 nm are prepared in sequence;

[0109] (3) forming a groove on the first protective layer 6 by laser grooving, wherein the groove penetrates the first protective layer 6 and partially penetrates the first intrinsic silicon material layer 5;

[0110] (4) using wet alkaline etching to remove the first doped silicon material layer 4, the second intrinsic silicon material layer 3, and the first tunneling oxide layer 2 at the groove, so that the groove partially penetrates the substrate 1, and the distance between the bottom of the groove and the front surface of the substrate 1 is 3 μm;

[0111] (5) a second tunneling oxide layer 7 having a thickness of 3 nm, a second phosphorus-doped silicon material layer 8 having a thickness of 150 nm, and a second protective layer 9 having a thickness of 20 nm are sequentially stacked at the bottom of the groove;

[0112] (6) Annealing is performed to transform the second intrinsic silicon material layer 3, the first doped silicon material layer 4, and the first intrinsic silicon material layer 5 into the first doped polysilicon layer 10, and the second doped silicon material layer 8 into the second doped polysilicon layer 11. The annealing temperature is 920°C, and the doping concentration of the first doped polysilicon layer 10 is 8×10 19 cm -3 ;

[0113] (7) The back side of the substrate 1 is subjected to chain acid etching and groove texturing to obtain a velvet surface;

[0114] (8) removing the first protective layer 6 and the second protective layer 9 by hydrofluoric acid cleaning, and preparing a first aluminum oxide passivation layer 12 and a first silicon nitride anti-reflection layer 13 stacked in sequence on the surfaces of the first doped polysilicon layer 10 and the second doped polysilicon layer 11;

[0115] (9) preparing a second aluminum oxide passivation layer 14 and a second silicon nitride anti-reflection layer 15 stacked in sequence on the velvet surface;

[0116] (10) A first electrode 16 is formed on the surface of the portion of the first anti-reflection layer 13 covering the first doped polysilicon layer 10, and the first electrode 16 is in contact with the first doped polysilicon layer 10. A second electrode 17 is formed on the surface of the portion of the second anti-reflection layer 15 covering the second doped polysilicon layer 11, and the second electrode 17 is in contact with the second doped polysilicon layer 11.

[0117] Example 2

[0118] The preparation method of the solar cell in this embodiment is basically the same as that in Example 1, with the only difference being that in step (5), instead of preparing the phosphorus-doped second doped silicon material layer 8, a third intrinsic amorphous silicon layer is prepared and converted into a second doped polycrystalline silicon layer 11 by phosphorus diffusion at 920°C.

[0119] Example 3

[0120] The preparation method of the solar cell in this embodiment is basically the same as that in Example 1, except that in step (2), the thickness of the first tunneling oxide layer 2 is 2 nm, the thickness of the second intrinsic silicon material layer 3 is 100 nm, and the annealing temperature in step (6) is 950°C.

[0121] Example 4

[0122] The preparation method of the solar cell in this embodiment is basically the same as that in Example 1, with the only difference being that the thickness of the first intrinsic silicon material layer 5 in step (2) is 200 nm.

[0123] Example 5

[0124] The preparation method of the solar cell in this embodiment is basically the same as that in embodiment 1, except that the doping concentration of the first doped polysilicon layer 10 obtained in step (6) is controlled to be 9×10 19 cm -3 .

[0125] Example 6

[0126] The method for preparing the solar cell in this embodiment is substantially the same as that in embodiment 1, with the only difference being that the second intrinsic silicon material layer 3 is not prepared in step (2).

[0127] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0128] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art could make several modifications and improvements without departing from the spirit of the present application, all of which fall within the scope of protection of the present application. Therefore, the scope of protection of the patent in this application shall be based on the appended claims, and the specification and drawings may be used to interpret the claims.

Claims

1. A method for preparing a solar cell, comprising: Preparing a first doped silicon material layer, a first intrinsic silicon material layer, and a first protective layer that are sequentially stacked on the surface of a substrate; Forming a groove on the first protective layer by laser, where the groove only penetrates the first protective layer, or the groove penetrates the first protective layer and partially penetrates the first intrinsic silicon material layer; Wet etching to remove the first doped silicon material layer at the groove; Annealing to convert the first doped silicon material layer and the first intrinsic silicon material layer into a first doped polysilicon layer.

2. The method for preparing a solar cell according to claim 1, wherein, The annealing temperature is 850°C to 950°C.

3. The method for preparing a solar cell according to any one of claims 1 to 2, wherein, The doping concentration of the first doped polysilicon layer is 8×10 19 cm -3 ~1×10 20 cm -3 .

4. The manufacturing method of the solar cell according to any one of claims 1 to 3, wherein, The thickness of the first doped silicon material layer is 50 nm to 100 nm.

5. The manufacturing method of a solar cell according to any one of claims 1 to 4, wherein, The thickness of the first intrinsic silicon material layer is 100 nm to 500 nm.

6. The manufacturing method of the solar cell according to any one of claims 1 to 5, wherein, Preparing a first doped silicon material layer, a first intrinsic silicon material layer, and a first protective layer that are sequentially stacked on the surface of a substrate includes: Preparing a second intrinsic silicon material layer, a first doped silicon material layer, a first intrinsic silicon material layer, and a first protective layer that are sequentially stacked on the surface of the substrate.

7. The manufacturing method of the solar cell according to claim 6, wherein, Preparing a second intrinsic silicon material layer on the surface of the substrate includes: Preparing a first tunneling oxide layer on the surface of the substrate, and preparing the second intrinsic silicon material layer on the surface of the first tunneling oxide layer.

8. The manufacturing method of the solar cell according to claim 7, wherein, The thickness of the first tunneling oxide layer is 1 nm to 3 nm.

9. The method for preparing a solar cell according to any one of claims 7 to 8, wherein, The thickness of the second intrinsic silicon material layer is 50 nm to 100 nm.

10. The manufacturing method of a solar cell according to any one of claims 1 to 9, wherein, The doping element of the first doped silicon material layer includes boron element.

11. The method for preparing a solar cell according to any one of claims 1 to 10, wherein, After wet etching to remove the first doped silicon material layer at the groove, it further includes: Preparing a second doped silicon material layer at the bottom of the groove, and the first doped silicon material layer and the second doped silicon material layer are spaced apart; The doping type of the first doped silicon material layer is opposite to the doping type of the second doped silicon material layer.

12. The manufacturing method of the solar cell according to claim 11, wherein, Wet etching to remove the first doped silicon material layer at the groove includes: making the groove partially penetrate the substrate; Along the depth direction of the groove, the surface of the second doped silicon material layer away from the bottom of the groove is lower than the surface of the first doped silicon material layer facing the substrate.

13. The method for preparing a solar cell according to claim 12, wherein, Making the groove partially penetrate the substrate includes: making the height difference between the bottom of the groove and the surface of the substrate provided with the first doped silicon material layer be 2 μm to 4 μm.

14. The method for preparing a solar cell according to any one of claims 11 to 13, wherein, Preparing a second doped silicon material layer at the bottom of the groove includes: preparing a second tunneling oxide layer and a second doped silicon material layer that are sequentially stacked at the bottom of the groove.

15. The manufacturing method of a solar cell according to claim 14, wherein, The thickness of the second tunneling oxide layer is 1 nm to 3 nm.

16. The method for preparing a solar cell according to any one of claims 14 to 15, wherein, The thickness of the second doped silicon material layer is 100 nm to 500 nm.

17. A solar cell prepared by the method for preparing a solar cell according to any one of claims 1 to 16.

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