Coding method and apparatus, and decoding method and apparatus

Abstract

A coding method and apparatus, and a decoding method and apparatus, which are applied to support IEEE 802.11ax next-generation Wi-Fi protocols (e.g., 802.11be, Wi-Fi 7 or EHT), or IEEE 802.11be next-generation Wi-Fi protocols (e.g., 802.11bn, Wi-Fi 8 or UHR) or Wi-Fi AI or millimeter wave (MMW) or ultra wide band (UWB) or sensing, etc. After acquiring an information bit sequence, a first communication apparatus performs LDPC coding on the information bit sequence on the basis of a check matrix, so as to obtain a coded sequence, and outputs the sequence, wherein the length of the sequence is N1, N1 is n times 1944, and n is an integer greater than or equal to 2; and Z of the check matrix may be equal to 81. After obtaining information to be decoded, a second communication apparatus performs LDPC decoding in view of the check matrix, so as to obtain the information bit sequence. The method can improve the decoding performance.

Description

Encoding methods, decoding methods and apparatus

[0001] This application claims priority to Chinese Patent Application No. 202311805346.4, filed with the China National Intellectual Property Administration on December 25, 2023, entitled "Encoding Method, Decoding Method and Apparatus", the entire contents of which are incorporated herein by reference. This application also claims priority to Chinese Patent Application No. 202410787720.0, filed with the China National Intellectual Property Administration on June 17, 2024, entitled "Encoding Method, Decoding Method and Apparatus", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, and in particular to an encoding method, a decoding method, and an apparatus. Background Technology

[0003] The Institute of Electrical and Electronics Engineers (IEEE) 802.11n / ac / ax / be and other wireless local area network (WLAN) transmission standards primarily focus on improving user experience in high-bandwidth scenarios (such as 60 GHz), including increasing average user throughput and energy efficiency of battery-powered devices. High-bandwidth scenarios require high-speed and reliable transmission of data, video, and other services on limited frequency and power resources, thus necessitating highly reliable and efficient channel coding and decoding schemes.

[0004] In the field of channel coding, concatenated codes (such as Turbo codes) and low-density parity-check (LDPC) codes are currently the two most mature and widely used channel coding methods, both of which have performance close to the Shannon limit. Compared with concatenated codes, LDPC codes have the following advantages: good error performance without the need for a deep interleaver; better frame error rate performance; significantly reduced error levels; decoding is not grid-based; supports parallel decoding; and has low decoding latency. Therefore, LDPC codes have become the standard channel coding scheme for low-frequency short-range WLAN communication systems such as IEEE 802.11n / ac / ax.

[0005] How to further improve the decoding performance of LDPC codes is an urgent problem to be solved. Summary of the Invention

[0006] This application provides an encoding method, a decoding method, and an apparatus that can support LDPC codes with longer code lengths and improve decoding performance.

[0007] In a first aspect, embodiments of this application provide an encoding method applied to a first communication device, the first communication device including a Wi-Fi device, or a chip or functional module disposed in the Wi-Fi device, the method comprising:

[0008] Obtain the information bit sequence; perform low-density parity-check (LDPC) encoding on the information bit sequence based on the parity-check matrix to obtain the encoded sequence, the length of the encoded sequence is N1, where N1 is n times 1944, n is an integer greater than or equal to 2, and the expansion factor Z of the parity-check matrix is ​​81; output the encoded sequence.

[0009] In this embodiment, the parity check matrix can be applied to information bit sequences that are n times the code length of 1944, where n is an integer greater than or equal to 2. This improves the transmission reliability of the system and enhances decoding performance. Generally, the longer the applicable code length, the better the reliability of the parity check matrix and the better the decoding performance.

[0010] Secondly, embodiments of this application provide a decoding method, the method being applied to a second communication device, the second communication device including a Wi-Fi device, or a chip or functional module disposed within the Wi-Fi device, the method comprising:

[0011] Obtain the information to be decoded, the length of which is N1, where N1 is n times 1944, and n is an integer greater than or equal to 2; perform low-density parity-check (LDPC) decoding on the information to be decoded based on the parity-check matrix to obtain the information bit sequence, where the expansion factor of the parity-check matrix is ​​Z = 81.

[0012] In conjunction with the first or second aspect, in one possible implementation, the parity check matrix is ​​obtained by diagonally expanding or anti-diagonally expanding the element in the x-th row and y-th column of the matrix prototype of the basic parity check matrix. The code length N0 corresponding to the basic parity check matrix is ​​less than or equal to 1944, the code rate corresponding to the basic parity check matrix is ​​the same as the code rate corresponding to the parity check matrix, the element in the x-th row and j-th column is greater than or equal to 0, and x and y are both positive integers.

[0013] In conjunction with the first or second aspect, in one possible implementation, the parity check matrix is ​​obtained by diagonally or anti-diagonally expanding the element in the x-th row and y-th column of the matrix prototype of the basic parity check matrix. This includes: the matrix prototype of the parity check matrix is ​​determined based on the matrix prototype of the basic parity check matrix and the expanded indicator matrix; the size of the expanded indicator matrix is ​​the same as the size of the matrix prototype of the basic parity check matrix; and the element in the x-th row and y-th column of the expanded indicator matrix is ​​used to indicate: the square matrix at the corresponding position in the matrix prototype of the parity check matrix is ​​obtained by diagonally or anti-diagonally expanding the element in the x-th row and y-th column of the matrix prototype of the basic parity check matrix.

[0014] In conjunction with the first or second aspect, in one possible implementation, the first and second columns of the matrix corresponding to the check bit in the matrix prototype of the basic check matrix are obtained by extending the first and last elements of the first column of the matrix corresponding to the check bit in the matrix prototype of the basic check matrix diagonally or by extending them diagonally against the check bit.

[0015] Typically, the first column of the matrix corresponding to the parity bit in the matrix prototype of the basic parity check matrix has a "1-0-1" structure, meaning that the first and last rows of the first column are both 1, and the remaining rows are all 0. Therefore, in this embodiment, the first element (e.g., 1) and the last element (e.g., 1) of the first column of the matrix corresponding to the parity bit in the matrix prototype of the basic parity check matrix can be expanded in the same way. By using the same expansion method, the elements at the corresponding positions in the first and second columns of the matrix corresponding to the parity bit in the matrix prototype of the parity check matrix can be obtained, thereby maintaining a similar structure in the matrix corresponding to the parity bit (e.g., the first or second element in the first column is 1, and the last or second-to-last element in the first column is 1), which can guarantee the fast and efficient encoding algorithm of LDPC codes.

[0016] In conjunction with the first or second aspect, in one possible implementation, the elements in the matrix prototype of the parity check matrix, excluding the first and second columns, of the matrix corresponding to the parity bits are obtained by diagonally expanding all 0 elements (excluding the first column) of the matrix corresponding to the parity bits in the matrix prototype of the basic parity check matrix.

[0017] In this embodiment, the expansion method of all elements in the matrix corresponding to the parity bit in the matrix prototype of the basic parity check matrix, except for the first column, is diagonal expansion. The parity check matrix obtained by the above expansion method can not only ensure fast and efficient encoding, but also reduce the implementation complexity because the expansion method is the same.

[0018] For example, the prototype of the basic parity-check matrix corresponds to a code length of 1944 bits. By using LDPC codes with different code rates (1944 bits) from the WLAN system as the basic matrix, parity-check matrices with code lengths of 3888 bits for the corresponding code rates are obtained. This allows for maximum reuse of the original WLAN LDPC code encoding and decoding architecture, minimizing modifications to the LDPC encoding and decoding modules for the new long LDPC codes and reducing implementation complexity.

[0019] In conjunction with the first or second aspect, in one possible implementation, the matrix corresponding to the information bit in the matrix prototype of the parity check matrix is ​​obtained by performing a diagonal expansion or an anti-diagonal expansion on the element in the x-th row and y-th column of the matrix corresponding to the information bit in the matrix prototype of the basic parity check matrix.

[0020] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, when the code rate R of the information bit sequence is 1 / 2, the matrix prototype of the parity check matrix is ​​as follows:

[0021] Where -1 represents a Z*Z all-zero matrix, 0 represents a Z*Z identity matrix, and elements greater than 0 represent the cyclic shift matrix CPM of the Z*Z identity matrix.

[0022] The "1" in matrix 1 or "2" in matrix 2 shown in the embodiments of this application are used to distinguish different matrices and facilitate subsequent reference.

[0023] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, the extended indicator matrix corresponding to matrix 1 is:

[0024] Where -1 indicates that the element at the corresponding position in the matrix prototype of the parity check matrix is ​​obtained by expanding element j1 in the matrix prototype of the basic parity check matrix into a 2*2 matrix of all zeros; 0 indicates that the element at the corresponding position in the matrix prototype of the parity check matrix is ​​obtained by expanding element j2 in the matrix prototype of the basic parity check matrix diagonally; and 1 indicates that the element at the corresponding position in the matrix prototype of the parity check matrix is ​​obtained by expanding element j3 in the matrix prototype of the basic parity check matrix anti-diagonally. The explanation of each element in the matrix prototype also applies to matrices 2 to 14 shown below, and will not be repeated below.

[0025] [Revised according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, when the code rate R of the information bit sequence is 1 / 2, the matrix prototype of the parity check matrix is ​​as follows: Matrix 2:

[0026] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, the extended indicator matrix corresponding to matrix 2 is:

[0027] [Revised according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, when the code rate R of the information bit sequence is 1 / 2, the matrix prototype of the parity check matrix is ​​as follows: Matrix 3:

[0028] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, the extended indicator matrix corresponding to matrix 3 is:

[0029] [Revised according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, when the code rate R of the information bit sequence is 2 / 3, the matrix prototype of the parity check matrix is ​​as follows: Matrix 4:

[0030] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, the extended indicator matrix corresponding to matrix 4 is:

[0031] [Revised according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, when the code rate R of the information bit sequence is 2 / 3, the matrix prototype of the parity check matrix is ​​as follows: Matrix 5:

[0032] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, the extended indicator matrix corresponding to matrix 5 is:

[0033] [Revised according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, when the code rate R of the information bit sequence is 2 / 3, the matrix prototype of the parity check matrix is ​​as follows: Matrix 6:

[0034] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, the extended indicator matrix corresponding to matrix 6 is:

[0035] [Revised according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, when the code rate R of the information bit sequence is 3 / 4, the matrix prototype of the parity check matrix is ​​as follows: Matrix 7:

[0036] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, the extended indicator matrix corresponding to matrix 7 is:

[0037] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, when the code rate R of the information bit sequence is 3 / 4, the matrix prototype of the parity check matrix is ​​as follows: Matrix 8:

[0038] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, the extended indicator matrix corresponding to matrix 8 is:

[0039] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, when the code rate R of the information bit sequence is 3 / 4, the matrix prototype of the parity check matrix is ​​as follows: Matrix 9:

[0040] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, the extended indicator matrix corresponding to matrix 9 is:

[0041] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, when the code rate R of the information bit sequence is 3 / 4, the matrix prototype of the parity check matrix is ​​as follows: Matrix 10:

[0042] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, the extended indicator matrix corresponding to matrix 10 is:

[0043] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, when the code rate R of the information bit sequence is 5 / 6, the matrix prototype of the parity check matrix is ​​as follows: Matrix 11:

[0044] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, the extended indicator matrix corresponding to matrix 11 is:

[0045] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, when the code rate R of the information bit sequence is 5 / 6, the matrix prototype of the parity check matrix is ​​as follows: Matrix 12:

[0046] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, the extended indicator matrix corresponding to matrix 12 is:

[0047] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, when the code rate R of the information bit sequence is 5 / 6, the matrix prototype of the parity check matrix is ​​as follows: Matrix 13:

[0048] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, the extended indicator matrix corresponding to matrix 13 is:

[0049] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, when the code rate R of the information bit sequence is 5 / 6, the matrix prototype of the parity check matrix is ​​as follows: Matrix 14:

[0050] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, the extended indicator matrix corresponding to matrix 14 is:

[0051] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, when the code rate R of the information bit sequence is 1 / 2, the matrix prototype of the parity check matrix is ​​as follows: Matrix 15:

[0052] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, the extended indicator matrix corresponding to matrix 15 is:

[0053] [Revised according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, when the code rate R of the information bit sequence is 1 / 2, the matrix prototype of the parity check matrix is ​​as follows: Matrix 16:

[0054] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, the extended indicator matrix corresponding to matrix 16 is:

[0055] [Revised according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, when the code rate R of the information bit sequence is 2 / 3, the matrix prototype of the parity check matrix is ​​as follows: Matrix 17:

[0056] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, the extended indicator matrix corresponding to matrix 17 is:

[0057] [Revised according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, when the code rate R of the information bit sequence is 2 / 3, the matrix prototype of the parity check matrix is ​​as follows: Matrix 18:

[0058] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, the extended indicator matrix corresponding to matrix 18 is:

[0059] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, when the code rate R of the information bit sequence is 3 / 4, the matrix prototype of the parity check matrix is ​​as follows: Matrix 19:

[0060] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, the extended indicator matrix corresponding to matrix 19 is:

[0061] [Revised according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, when the code rate R of the information bit sequence is 3 / 4, the matrix prototype of the parity check matrix is ​​as follows:

[0062] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, the extended indicator matrix corresponding to matrix 20 is:

[0063] [Revised according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, when the code rate R of the information bit sequence is 5 / 6, the matrix prototype of the parity check matrix is ​​as follows: Matrix 21:

[0064] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, the extended indicator matrix corresponding to matrix 21 is:

[0065] [Revised according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, when the code rate R of the information bit sequence is 5 / 6, the matrix prototype of the parity check matrix is ​​as follows: Matrix 22:

[0066] [Amended according to Rule 26, 10.02.2025] In conjunction with the first or second aspect, in one possible implementation, the extended indicator matrix corresponding to matrix 22 is:

[0067] Thirdly, embodiments of this application provide a first communication device for executing the method in the first aspect or any possible implementation. The first communication device includes a module for executing the method in the first aspect or any possible implementation.

[0068] Fourthly, embodiments of this application provide a second communication device for executing the method in the second aspect or any possible implementation. The second communication device includes a module for executing the method in the second aspect or any possible implementation.

[0069] Fifthly, embodiments of this application provide a first communication device, which includes a processor for executing the method described in the first aspect or any possible implementation thereof. The processor executes a program stored in a memory, and when the program is executed, the method described in the first aspect or any possible implementation thereof is executed.

[0070] In one possible implementation, the memory is located outside the aforementioned first communication device.

[0071] In one possible implementation, the memory is located within the aforementioned first communication device.

[0072] In this embodiment, the processor and memory can also be integrated into a single device, that is, the processor and memory can be integrated together. For example, the first communication device can be a chip.

[0073] In one possible implementation, the first communication device further includes a transceiver for receiving or sending information.

[0074] Sixthly, embodiments of this application provide a second communication device, which includes a processor for executing the methods described in the second aspect or any possible implementation thereof. The processor executes a program stored in a memory, and when the program is executed, the methods described in the second aspect or any possible implementation thereof are executed.

[0075] In one possible implementation, the memory is located outside the aforementioned second communication device.

[0076] In one possible implementation, the memory is located within the aforementioned second communication device.

[0077] In this embodiment, the processor and memory can also be integrated into a single device, i.e., the processor and memory can be integrated together. For example, the second communication device can be a chip.

[0078] In one possible implementation, the second communication device further includes a transceiver for receiving or sending information.

[0079] In a seventh aspect, embodiments of this application provide a first communication device, the first communication device including a logic circuit and an interface, the logic circuit and the interface being coupled; the interface is used for inputting and / or outputting information, and the logic circuit is used for performing the method as described in the first aspect or any possible implementation.

[0080] Eighthly, embodiments of this application provide a second communication device, the second communication device including logic circuitry and an interface, the logic circuitry and the interface being coupled; the interface being used for inputting and / or outputting information, and the logic circuitry being used for performing the method described in the second aspect or any possible implementation thereof.

[0081] Ninthly, embodiments of this application provide a computer-readable storage medium for storing a computer program that, when run on a computer, causes the methods shown in any of the first to second aspects or any possible implementation thereof to be executed.

[0082] In a tenth aspect, embodiments of this application provide a computer program product that, when run on a computer, causes the methods shown in any of the first to second aspects or any possible implementations described above to be executed.

[0083] In one aspect, embodiments of this application provide a computer program that, when run on a computer, executes the methods shown in any of the first to second aspects or any possible implementations described above.

[0084] In a twelfth aspect, embodiments of this application provide a communication system comprising a first communication device and / or a second communication device, wherein the first communication device is configured to perform the method shown in the first aspect or any possible implementation thereof, and the second communication device is configured to perform the method shown in the second aspect or any possible implementation thereof. Attached Figure Description

[0085] Figure 1a is a schematic diagram of a matrix prototype of a reference verification matrix provided in an embodiment of this application;

[0086] Figure 1b is a schematic diagram of a CPM provided in an embodiment of this application;

[0087] Figure 2a is a schematic diagram of the architecture of a communication system provided in an embodiment of this application;

[0088] Figure 2b is a schematic diagram of the architecture of a communication system provided in an embodiment of this application;

[0089] Figure 2c is a schematic diagram of the architecture of a communication system provided in an embodiment of this application;

[0090] Figure 3 is a flowchart illustrating an encoding and decoding method provided in an embodiment of this application;

[0091] Figure 4a is a schematic diagram of a matrix prototype of a verification matrix provided in an embodiment of this application;

[0092] Figure 4b is a schematic diagram of the extended indicator matrix corresponding to Figure 4a provided in an embodiment of this application;

[0093] Figure 5a is a schematic diagram of a matrix prototype of a verification matrix provided in an embodiment of this application;

[0094] Figure 5b is a schematic diagram of the extended indicator matrix corresponding to Figure 5a provided in an embodiment of this application;

[0095] Figure 6a is a schematic diagram of a matrix prototype of a verification matrix provided in an embodiment of this application;

[0096] Figure 6b is a schematic diagram of the extended indicator matrix corresponding to Figure 6a provided in an embodiment of this application;

[0097] Figure 7a is a schematic diagram of a matrix prototype of a verification matrix provided in an embodiment of this application;

[0098] Figure 7b is a schematic diagram of the extended indicator matrix corresponding to Figure 7a provided in an embodiment of this application;

[0099] Figure 8a is a schematic diagram of a matrix prototype of a verification matrix provided in an embodiment of this application;

[0100] Figure 8b is a schematic diagram of the extended indicator matrix corresponding to Figure 8a provided in an embodiment of this application;

[0101] Figure 9a is a schematic diagram of a matrix prototype of a verification matrix provided in an embodiment of this application;

[0102] Figure 9b is a schematic diagram of the extended indicator matrix corresponding to Figure 9a provided in an embodiment of this application;

[0103] Figure 10a is a schematic diagram of a matrix prototype of a verification matrix provided in an embodiment of this application;

[0104] Figure 10b is a schematic diagram of the extended indicator matrix corresponding to Figure 10a provided in an embodiment of this application;

[0105] Figure 11a is a schematic diagram of a matrix prototype of a verification matrix provided in an embodiment of this application;

[0106] Figure 11b is a schematic diagram of the extended indicator matrix corresponding to Figure 11a provided in an embodiment of this application;

[0107] Figure 12a is a schematic diagram of a matrix prototype of a verification matrix provided in an embodiment of this application;

[0108] Figure 12b is a schematic diagram of the extended indicator matrix corresponding to Figure 12a provided in an embodiment of this application;

[0109] Figure 13a is a schematic diagram of a matrix prototype of a verification matrix provided in an embodiment of this application;

[0110] Figure 13b is a schematic diagram of the extended indicator matrix corresponding to Figure 13a provided in an embodiment of this application;

[0111] Figure 13c is a schematic diagram of the extended indicator matrix corresponding to Figure 13a provided in an embodiment of this application;

[0112] Figure 14a is a schematic diagram of a matrix prototype of a verification matrix provided in an embodiment of this application;

[0113] Figure 14b is a schematic diagram of the extended indicator matrix corresponding to Figure 14a provided in an embodiment of this application;

[0114] Figure 15a is a schematic diagram of a matrix prototype of a verification matrix provided in an embodiment of this application;

[0115] Figure 15b is a schematic diagram of the extended indicator matrix corresponding to Figure 15a provided in an embodiment of this application;

[0116] Figure 16a is a schematic diagram of a matrix prototype of a verification matrix provided in an embodiment of this application;

[0117] Figure 16b is a schematic diagram of the extended indicator matrix corresponding to Figure 16a provided in an embodiment of this application;

[0118] Figure 17a is a schematic diagram of a matrix prototype of a verification matrix provided in an embodiment of this application;

[0119] Figure 17b is a schematic diagram of the extended indicator matrix corresponding to Figure 17a provided in an embodiment of this application;

[0120] Figure 18 is a partial schematic diagram of a shortening operation in LDPC encoding provided in an embodiment of this application;

[0121] Figure 19a is a schematic diagram of element i after diagonal expansion according to an embodiment of this application;

[0122] Figure 19b is a schematic diagram of element i after anti-angle expansion according to an embodiment of this application;

[0123] Figure 20a is a schematic diagram of two options, positive diagonal extension and negative diagonal extension, provided in the embodiments of this application;

[0124] Figure 20b is a schematic diagram of a tree-shaped expansion provided in an embodiment of this application;

[0125] Figure 21a is a schematic diagram of a simulation result provided in an embodiment of this application;

[0126] Figure 21b is a schematic diagram of a simulation result provided in an embodiment of this application;

[0127] Figure 21c is a schematic diagram of a simulation result provided in an embodiment of this application;

[0128] Figure 21d is a schematic diagram of a simulation result provided in an embodiment of this application;

[0129] Figure 22 is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0130] Figure 23 is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0131] Figure 24 is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0132] Figure 25 is a schematic diagram of the matrix prototype grouping design of the basic parity check matrix provided in an embodiment of this application;

[0133] Figures 26a and 26b are schematic diagrams of the extended indicator matrix provided in the embodiments of this application;

[0134] Figure 27a is a schematic diagram of a matrix prototype of a verification matrix provided in an embodiment of this application;

[0135] Figure 27b is a schematic diagram of the extended indicator matrix corresponding to Figure 27a provided in an embodiment of this application;

[0136] Figure 28a is a schematic diagram of a matrix prototype of a verification matrix provided in an embodiment of this application;

[0137] Figure 28b is a schematic diagram of the extended indicator matrix corresponding to Figure 28a provided in an embodiment of this application;

[0138] Figure 29a is a schematic diagram of a matrix prototype of a verification matrix provided in an embodiment of this application;

[0139] Figure 29b is a schematic diagram of the extended indicator matrix corresponding to Figure 29a provided in an embodiment of this application;

[0140] Figure 30a is a schematic diagram of a matrix prototype of a verification matrix provided in an embodiment of this application;

[0141] Figure 30b is a schematic diagram of the extended indicator matrix corresponding to Figure 30a provided in an embodiment of this application;

[0142] Figure 31a is a schematic diagram of a matrix prototype of a verification matrix provided in an embodiment of this application;

[0143] Figure 31b is a schematic diagram of the extended indicator matrix corresponding to Figure 31a provided in an embodiment of this application;

[0144] Figure 32a is a schematic diagram of a matrix prototype of a verification matrix provided in an embodiment of this application;

[0145] Figure 32b is a schematic diagram of the extended indicator matrix corresponding to Figure 32a provided in an embodiment of this application;

[0146] Figure 33a is a schematic diagram of a matrix prototype of a verification matrix provided in an embodiment of this application;

[0147] Figure 33b is a schematic diagram of the extended indicator matrix corresponding to Figure 33a provided in an embodiment of this application;

[0148] Figure 34a is a schematic diagram of a matrix prototype of a verification matrix provided in an embodiment of this application;

[0149] Figure 34b is a schematic diagram of the extended indicator matrix corresponding to Figure 34a provided in an embodiment of this application;

[0150] Figure 35a is a schematic diagram of a matrix prototype of a verification matrix provided in an embodiment of this application;

[0151] Figure 35b is a schematic diagram of the extended indicator matrix corresponding to Figure 35a provided in an embodiment of this application;

[0152] Figure 36a is a schematic diagram of a matrix prototype of a verification matrix provided in an embodiment of this application;

[0153] Figure 36b is a schematic diagram of the extended indicator matrix corresponding to Figure 36a provided in an embodiment of this application;

[0154] Figure 37a is a schematic diagram of a matrix prototype of a verification matrix provided in an embodiment of this application;

[0155] Figure 37b is a schematic diagram of the extended indicator matrix corresponding to Figure 31a provided in an embodiment of this application. Detailed Implementation

[0156] To facilitate understanding of the technical solution of this application, the application will be further described below with reference to the accompanying drawings.

[0157] The terms "first" and "second," etc., used in the specification, claims, and drawings of this application are used only to distinguish different objects and not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0158] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0159] In this application, "at least one (item)" refers to one or more, "more than one" refers to two or more, "at least two (items)" refers to two or three or more, and "and / or" is used to describe the relationship between related objects, indicating that there can be three relationships. For example, "A and / or B" can mean: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. "Or" indicates that there can be two relationships, such as only A exists and only B exists; when A and B are not mutually exclusive, it can also mean that there are three relationships, such as only A exists, only B exists, and both A and B exist simultaneously. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items. For example, at least one (item) of a, b, or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c".

[0160] The LDPC codes used in standards such as IEEE 802.11ac / ax are quasi-cyclic (QC) LDPC (QC-LDPC) codes. QC-LDPC codes are a widely used type of structured LDPC codes. Due to the unique structure of their parity-check matrix, they can be encoded using simple feedback shift registers, which can effectively solve the encoding complexity problem of LDPC codes.

[0161] Currently, the standard adopts 12 LDPC code parity-check matrices, with three code lengths N: N=648, N=1296, or N=1944. Each code length supports four different coding rates: 1 / 2, 2 / 3, 3 / 4, and 5 / 6. The matrix prototypes of the parity-check matrices are different for each code length and code rate. However, the parity bit portion (the matrix corresponding to the parity bits, or parity square matrix, shown below) of the 12 parity-check matrices with different code lengths and codes has the same structure. For example, the code rate can be determined by the modulation and coding scheme (MCS) adaptively selected by the transmission system based on the link. Therefore, communication devices in a wireless local area network (WLAN) can select one of the 12 parity-check matrices based on the given code length and code rate. The aforementioned identical structure can be understood as the parity bit portion in the matrix prototypes of different parity-check matrices in Figure 1a having all elements in the first row and first column being 1, and all elements in the last row and first column being 1. In the first matrix of Figure 1a, the first column of the parity bit portion is the 13th column of the original parity matrix, and the last column of the parity bit portion is the 24th column of the original parity matrix. In the second matrix of Figure 1a, the first column of the parity bit portion is the 17th column of the original parity matrix, and the last column of the parity bit portion is the 24th column of the original parity matrix. In the third matrix of Figure 1a, the first column of the parity bit portion is the 19th column of the original parity matrix, and the last column of the parity bit portion is the 24th column of the original parity matrix. In the second matrix of Figure 1a, the first column of the parity bit portion is the 21st column of the original parity matrix, and the last column of the parity bit portion is the 24th column of the original parity matrix.

[0162] Figure 1a shows the matrix prototypes of the LDPC code parity-check matrix at different code rates with a code length N = 1944. In Figure 1a, "-" represents a Z*Z all-zero matrix, "0" represents a Z*Z identity matrix, and the non-zero elements represent the circulant permutation matrix (CPM) of the Z*Z identity matrix. For example, if CPM is represented by P... iIn this context, 'i' represents the cyclic shift value, the number of bits in the identity matrix cyclically shifted to the right, the CPM coefficient, or an element greater than or equal to 0 in the matrix prototype of the parity check matrix. The specific name of 'i' is not limited in this embodiment. 'i' is a non-negative integer, such as 0 ≤ i ≤ Z-1. When i = 0, the CPM can be understood as a Z*Z identity matrix, or a CPM with a cyclic shift value of 0. For example, in Figure 1a, Z = N / 24. The aforementioned "24" can be the same as the number of columns in the matrix prototype of the parity check matrix in the IEEE 802.11ac / ax standard. For IEEE 801.11ac / ax, regardless of whether the code length N = 648, N = 1296, or N = 1944, the number of columns in the matrix prototype of the parity check matrix is ​​always 24.

[0163] For example, taking element "1" (i.e., i = 1) in Figure 1a as an example, element 1 can be expanded into a CPM of 81*81 (1944 / 24 = 81). This CPM can be obtained by cyclically shifting the identity matrix one bit to the right, as shown below:

[0164] For example, taking a 4*4 CPM as an example, Figure 1b shows the CPM when i=0, i=1, i=2, and i=3, respectively. The CPM shown in Figure 1b is only an example. The CPM of other Z*Z identity matrices in this application embodiment can be obtained by referring to the principle shown in Figure 1a or Figure 1b to obtain the final P. i This will not be elaborated upon further below.

[0165] Because LDPC codes can improve the transmission reliability of wireless transmission systems, they have been widely used in WLAN standards. To further improve the data transmission reliability of Wi-Fi systems, current or next-generation standards may consider longer LDPC code lengths, thereby providing stronger error control performance for the encoding module and improving the decoding performance of the decoding module.

[0166] In view of this, embodiments of this application provide an encoding method, a decoding method, and an apparatus. This method relates to a novel LDPC code that can support longer code lengths. The parity check matrix provided in this application is applicable to longer code lengths, such as a code length that is n times 1944 bits, where n is an integer greater than or equal to 2. Furthermore, the parity check matrix can improve decoding performance. For example, based on existing WLAN LDPC long codes (e.g., code length of 1944 bits), the LDPC code (or long LDPC code) (e.g., code length of 3888 bits) provided in this application can achieve superior performance. Further, the new long LDPC code provided in this application can reuse the encoding and decoding architecture of existing WLAN LDPC codes as much as possible, requiring minimal modifications to existing LDPC encoding and decoding modules, thus reducing the implementation complexity of LDPC encoding and decoding.

[0167] In this application embodiment, the matrices shown below can be referred to as prototypes of the parity-matrices, or matrix prototypes of the parity-matrices, or matrix prototypes for codeword block length N, or parent matrix, etc. The specific names of the matrices involved in this application embodiment are not limited. Generally speaking, the matrix including elements 0 and 1 after expansion based on Z and the cyclic shift value i is called the parity-matrices. Therefore, the matrices shown below can also be referred to as matrices before CPM expansion, etc. The matrices shown in Examples 1 to 14 below can be called matrix prototypes of the parity-matrices, and the matrices expanded based on the elements in the matrices shown in Examples 1 to 14 can be called parity-matrices. For the specific expansion method, please refer to the relevant descriptions of Figures 1a and 1b above. The specific content of the expanded parity-matrices will not be listed one by one in this application embodiment.

[0168] The code length in this application embodiment can also be called the codeword block length, etc. The specific name for the code length is not limited in this application embodiment. Z in this application embodiment can be called the subblock size, expansion factor, or lift factor, etc. The specific name for Z is not limited in this application embodiment. For ease of description, Z will be referred to as the expansion factor in the following explanation.

[0169] In this embodiment, Z = N / 48. However, as standards evolve, the method for calculating Z may change, and this embodiment does not limit this. For ease of understanding, different letter parameters are used to represent different meanings in this embodiment, such as N representing code length, Z representing the spread factor, R representing the code rate, K representing the number of information bits, and E representing the number of parity bits. However, the letter parameters shown in this embodiment are merely examples and should not be construed as limiting the embodiments of this application.

[0170] The following describes the communication system involved in the embodiments of this application.

[0171] The technical solutions provided in this application can be applied to wireless local area network (WLAN) systems, such as Wi-Fi. The methods provided in this application can also be applied to the IEEE 802.11 series of protocols, such as the 802.11be protocol, the 802.11bn protocol, or next-generation protocols of the 802.11bn protocol, or protocols supporting ambient power (AMP), etc., and will not be listed exhaustively. The technical solutions provided in this application can also be applied to wireless personal area networks (WPANs) based on millimeter wave (MMW) and ultra-wideband (UWB) technologies. The methods provided in this application can also be applied to the IEEE 802.15 series of protocols, such as the 802.15.4a protocol, the 802.15.4z protocol, or the 802.15.4ab protocol, or a future generation of UWB WPAN protocols, etc., and will not be listed exhaustively. The technical solutions provided in this application can also be applied to the following communication systems, such as Internet of Things (IoT) systems, vehicle-to-everything (V2X, where X can represent anything), device-to-device (D2D), narrowband Internet of Things (NB-IoT) systems, long-term evolution (LTE) systems, 5th-generation (5G) communication systems, and new communication systems emerging in future communication development. For example, V2X can include vehicle-to-vehicle (V2V), vehicle-to-infrastructure (V2I), vehicle-to-pedestrian (V2P), or vehicle-to-network (V2N) communication.

[0172] WLAN systems can provide high-speed, low-latency transmission. As WLAN application scenarios continue to evolve, WLAN systems will be applied to more scenarios or industries, such as the Internet of Things industry, the Internet of Vehicles industry, the banking industry, enterprise offices, stadiums and exhibition halls, concert halls, hotel rooms, dormitories, hospital wards, classrooms, shopping malls, squares, streets, production workshops and warehouses, etc. Of course, devices that support WLAN communication or sensing (such as access points or sites) can be sensor nodes in smart cities (such as smart water meters, smart electricity meters, and smart air monitoring nodes), smart devices in smart homes (such as smart cameras, projectors, displays, televisions, speakers, refrigerators, and washing machines), nodes in the Internet of Things (IoT), entertainment terminals (such as wearable devices for augmented reality (AR) and virtual reality (VR), smart devices in smart offices (such as printers, projectors, loudspeakers, and speakers), vehicle-to-everything (V2X) devices, infrastructure in daily life scenarios (such as vending machines, self-service navigation kiosks in supermarkets, self-service checkout machines, and self-service ordering machines), and equipment in large sports and music venues.

[0173] Although this application primarily uses WLAN as an example, especially networks applied to the IEEE 802.11 series of standards, it can also support Wi-Fi 8, also known as Ultra High Reliability (UHR) or Ultra High Reliability and Throughput (UHRT), etc., which will not be listed here. The various aspects involved in this application can be extended to other networks employing various standards or protocols. For example, Bluetooth, High Performance Radio LAN (HIPERLAN) (a wireless standard similar to IEEE 802.11), and Wide Area Network (WAN) or other networks now known or to be developed in the future.

[0174] In one possible implementation, the method provided in this application embodiment can be implemented by a communication device in a communication system. For example, the communication device can be an access point (AP) or a station (STA).

[0175] An Access Point (AP) is a device with wireless communication capabilities that supports communication, sensing, or power transmission using WLAN protocols. It has the function of communicating or sensing with other devices in a WLAN network (such as non-access point stations (non-AP STAs) or other access points), and can also have the function of communicating, sensing, or transmitting power with other devices. Alternatively, an access point acts as a bridge connecting wired and wireless networks, primarily connecting various wireless network clients together and then connecting the wireless network to an Ethernet network. In a WLAN system, an access point can be called an Access Point Station (AP STA). This wireless communication device can be a complete device or a chip, processing system, or functional module installed within a complete device. Devices with these chips, processing systems, or functional modules can implement the methods and functions of the embodiments in this application under the control of the chips, processing systems, or functional modules. The AP in the embodiments of this application is a device that provides services to non-AP STAs and can support 802.11 series protocols or subsequent protocols. For example, an access point can be an access point for a terminal (such as a mobile phone) to enter a wired (or wireless) network, mainly deployed in homes, buildings, and parks, with a typical coverage radius of tens to hundreds of meters. Of course, it can also be deployed outdoors. Another example is that an AP can be a communication entity such as a communication server, router, switch, or bridge; APs can include various forms of macro base stations, micro base stations, and repeater stations. Of course, an AP can also be a chip, processing system, or module within the above-mentioned devices, thereby implementing the methods and functions of the embodiments of this application.

[0176] A Station-Style (STA) is a device with wireless communication capabilities that supports communication, sensing, or power transmission using the WLAN protocol. It has the ability to communicate, sense, or transmit power with other non-AP STAs or access points in a WLAN network. In a WLAN system, a station can be called a non-access point station (non-AP STA). For example, an STA is any user communication device that allows a user to communicate with an AP (Access Point) or sense or transmit power, and thus communicate with the WLAN. This wireless communication device can be a complete device, or it can be a chip, processing system, or functional module installed in a complete device. Devices with these chips, processing systems, or functional modules can implement the methods and functions of the embodiments of this application under the control of the chips, processing systems, or functional modules. For example, an STA can be a wireless communication chip, a wireless sensor, or a wireless communication terminal, and can also be referred to as a user. Furthermore, an STA can be a mobile phone supporting Wi-Fi communication, a tablet computer supporting Wi-Fi communication, a set-top box supporting Wi-Fi communication, a smart TV supporting Wi-Fi communication, a smart wearable device supporting Wi-Fi communication, an in-vehicle communication device supporting Wi-Fi communication, and a computer supporting Wi-Fi communication. Of course, STA can also be a chip, processing system, or module in the various types of devices described above, thereby implementing the methods and functions of the embodiments of this application.

[0177] For example, the communication systems to which the methods provided in this application can be applied may include access points and stations. For instance, this application can be applied to scenarios of communication or sensing between APs and STAs, between APs, or between STAs in a WLAN, and this application does not limit this. Optionally, an AP can communicate or sense with a single STA, or an AP can communicate or sense with multiple STAs simultaneously. Specifically, communication or sensing between an AP and multiple STAs can be further divided into downlink transmission where the AP simultaneously sends signals to multiple STAs, and uplink transmission where multiple STAs send signals to the AP. The communication protocols between APs and STAs, between APs, and between STAs can support WLAN communication protocols, which may include IEEE 802.11 series protocols, such as the 802.11bn protocol, and of course, protocols after 802.11bn.

[0178] Figure 2a is a schematic diagram of the architecture of a communication system provided in an embodiment of this application. The communication system may include one or more APs and one or more STAs. Figure 2a shows two access points, such as AP1 and AP2, and three stations, such as STA1, STA2, and STA3. As an example, the method provided in this embodiment can be applied to data communication or sensing between an AP and one or more STAs, such as the communication between AP1 and STA1 shown in Figure 2a, the communication between AP and STA shown in Figure 2b, the communication, sensing, or power transmission between AP1 and STA1 and STA2 shown in Figure 2a, and the communication, sensing, or power transmission between AP and STA1, STA2, and STA3 shown in Figure 2c. As another example, the method provided in this embodiment can be applied to communication between APs, such as the communication or sensing between AP1 and AP2 shown in Figure 2a. As yet another example, the method provided in this embodiment can be applied to communication or sensing between STAs, such as the communication or sensing between STA2 and STA3 shown in Figure 2a.

[0179] Figures 2a-2c use STA (Mobile Phone) and AP (Router) as examples and do not imply limitation on the types of APs and STAs in the embodiments of this application. Furthermore, the number of APs and STAs shown in Figures 2a-2c is merely an example; in actual implementations, the number of APs or STAs may be more or less, and this application does not limit this.

[0180] From the perspectives of transmitting and receiving signals, the first communication device described below can be understood as a communication device that transmits signals, and the second communication device can be understood as a communication device that receives signals. Alternatively, the first communication device can also be called a transmitting end, and the second communication device can also be called a receiving end. In the embodiments of this application, the signal can be an encoded sequence, or a signal obtained by processing the encoded sequence.

[0181] From the perspective of different devices, as an example, the first communication device and the second communication device can be Wi-Fi chips, functional modules, or processing systems installed in different Wi-Fi devices. As another example, the first communication device can be an access point (AP), and the second communication device can be a non-AP STA. As yet another example, both the first and second communication devices can be non-AP STAs or both can be APs. As yet another example, the first communication device can be a non-AP STA, and the second communication device can be an AP. As yet another example, at least one of the first and second communication devices can be a multi-link device (MLD), etc., which will not be listed in detail in this application. Exemplarily, a multi-link device (MLD) refers to a device that simultaneously has multiple sites (such as APs or non-AP STAs), each operating on different frequency bands or channels. A multi-link device includes multiple affiliated sites, which can be physical sites or logical sites, and each site can operate on a link, a frequency band, or a channel, etc. The aforementioned affiliated sites can be APs or non-AP STAs. Multilink devices (such as non-AP MLDs or AP MLDs) can be communication devices with wireless communication capabilities. This communication device can be a complete unit, or it can be a chip, processing system, or module installed within a complete unit. Devices with these chips, processing systems, or modules installed can implement the methods and functions of the embodiments of this application under the control of these chips, processing systems, or modules. Multilink devices can implement wireless communication by conforming to the 802.11 series of protocols, thereby enabling communication with other devices. Other devices shown herein may or may not be multilink devices. The operating frequency bands of multilink devices may include, but are not limited to, sub-1GHz, 2.4GHz, 5GHz, 6GHz, etc., and will not be listed here.

[0182] This application describes the method provided by the first communication device and the second communication device from both sides. However, during the transmission of signals, the first communication device and the second communication device can also forward the signals through other devices, such as forwarding the signals between the first communication device and the second communication device through a forwarding device. This application does not limit other devices besides the first communication device and the second communication device.

[0183] The following describes the methods involved in the embodiments of this application.

[0184] Figure 3 is a flowchart illustrating an encoding and decoding method provided in an embodiment of this application. Descriptions of the first and second communication devices, etc., can be found above and will not be detailed here. As shown in Figure 3, the method includes:

[0185] 301. The first communication device acquires the information bit sequence.

[0186] This information bit sequence can be a bit sequence containing information. For example, the length of the information bit sequence is N², or the number of bits in the information bit sequence is N². N² is a positive integer. These N² bits can include K information bits, also called K data bits or K payload bits. K is a positive integer. N² can be an integer greater than or equal to K. For example, when N² is greater than K, the information bit sequence can also include (N²-K) zeros. For a related explanation of the "0" shown here, please refer to the description of the shortening operation in Figure 18 below; it will not be detailed here.

[0187] The value of N2 mentioned above can be related to the code length and code rate. If the length of the encoded sequence in step 302 below is N1, then N2 = N1 * R, where R is the encoding code rate of the information bit sequence. Here, N1 can also be called the code length corresponding to the parity check matrix. N1 can also be understood as the original code length of a single LDPC codeword, and N2 can be understood as the original information bits of a single LDPC codeword.

[0188] In one possible implementation, the method shown in Figure 3 may also include:

[0189] The first communication device acquires the code length N1.

[0190] As an example, N1 can be m times 1296, where m is an integer greater than or equal to 2. For example, N1 = 1296 * 2 = 2592. Another example is N1 = 1296 * 3 = 3888, etc., and so on.

[0191] As another example, N1 can be n times 1944, where n is an integer greater than or equal to 2. For example, N1 = 1944 * 2 = 3888, or N1 = 1944 * 3 = 5832, etc., which will not be listed here.

[0192] In one possible implementation, the method shown in Figure 3 may also include:

[0193] The first communication device acquires the code rate R.

[0194] In a WLAN system, different code lengths and code rates can correspond to different parity check matrices. Therefore, the code rate R can be obtained before the first communication device performs LDPC encoding. After obtaining the code rate R, the first communication device can select the parity check matrix based on the code rate R and the code length N1. The code rate R can be determined based on the link adaptive selection MCS. For example, the code rate R can be determined based on the current channel information. The specific method for determining the code rate R is not limited in the embodiments of this application. As an example, the MCS can be issued by the AP. As another example, the MCS can be determined by the first communication device, etc. For example, the first communication device sends the MCS to the second communication device, and the second communication device receives the MCS and obtains the code rate R based on the MCS. Or, the second communication device sends the MCS to the first communication device, and the first communication device receives the MCS and obtains the code rate R based on the MCS. The specific interaction process of the MCS is not limited in the embodiments of this application.

[0195] For example, R can be any of the following: 1 / 2, 2 / 3, 3 / 4, 5 / 6. Of course, as standards evolve, R may take other values, and this application embodiment does not limit this.

[0196] This application does not limit the order in which the first communication device acquires the code length and code rate. After the first communication device acquires the code length and code rate, it can determine the matrix prototype of the corresponding parity check matrix based on the code length and code rate. Similarly, the order in which the first communication device acquires the information bit sequence and code length (or code rate) is also not limited.

[0197] 302. The first communication device performs LDPC encoding on the information bit sequence based on the parity check matrix to obtain the encoded sequence. The length of the encoded sequence is N1, such that N1 is n times 1944, where n is an integer greater than or equal to 2.

[0198] The encoded sequence can include K information bits and E parity bits. Alternatively, the encoded sequence can consist of an information bit sequence and a parity bit sequence, where the length of the information bit sequence can be N² and the length of the parity bit sequence can be E. N₁ = N² + E. The value of E depends on N₁ and R. For example, if N₁ = 3888 and R = 1 / 2, then E = 1944. If N₁ = 3888 and R = 2 / 3, then E = 3888 * 1 / 3 = 1296. If N₁ = 3888 and R = 3 / 4, then E = 3888 * 1 / 4 = 972. If N₁ = 3888 and R = 5 / 6, then E = 3888 * 1 / 6 = 648.

[0199] The following describes the matrix prototype of the verification matrix involved in the embodiments of this application.

[0200] In the matrix prototype of the parity check matrix shown below, "-1" represents a Z*Z all-zero matrix, "0" represents a Z*Z identity matrix, and non-zero elements represent the CPM of the Z*Z identity matrix. Of course, "-1" in the matrix prototype can also be replaced with "-", and this application does not impose any restrictions. For explanations of the various parameters and CPM, please refer to the above text; they will not be detailed here. The "1" in Example 1, "2" in Example 2, or "3" in Example 3 below are used to distinguish different examples and for ease of subsequent reference.

[0201] As an example 1, the prototype of the parity check matrix can be shown in Figure 4a. An explanation of Figure 4b can be found below, and will not be detailed here.

[0202] As another example 2, the prototype of the check matrix can be shown in Figure 5a. An explanation of Figure 5b can be found below, and will not be detailed here.

[0203] As another example 3, the prototype of the check matrix can be shown in Figure 6a. An explanation of Figure 6b can be found below, and will not be detailed here.

[0204] The R corresponding to the matrix prototype of the parity check matrix shown in Examples 1 to 3 above can be equal to 1 / 2. Similarly, the R corresponding to the parity check matrix is ​​also equal to 1 / 2. For example, the N1 corresponding to the matrix prototype of the parity check matrix shown in Examples 1 to 3 above can be equal to 3888. And the first communication device performs LDPC encoding using the parity check matrix corresponding to the matrix prototype shown in Examples 1 to 3, obtaining an encoded sequence with a length of 3888 bits.

[0205] Each non-negative integer (e.g., element i) in the matrix prototype of the parity-check matrices shown in Examples 1-3 can be expanded into a CPM of a Z*Z identity matrix. Element i in Examples 1-3 can be expanded into a CPM, such as by circularly shifting the identity matrix i positions to the right. For example, element 0 in Examples 1-3 can be expanded into an 81*81 identity matrix, and elements i greater than 0 (e.g., i > 0) can be circularly shifted i positions to the right of the identity matrix to obtain an 81*81 CPM. For instance, element "57" in the matrix prototype can be expanded into an 81*81 identity matrix CPM, obtained by circularly shifting the 81*81 identity matrix 57 positions to the right.

[0206] In the embodiments of this application, the matrix prototypes shown in Examples 1 to 3 include 24 rows and 48 columns. Therefore, the parity check matrix expanded based on the expansion factor Z can include 24*81 rows and 48*81 columns (i.e., 1944 rows and 3888 columns). For instructions on how to expand the matrix prototype into a parity check matrix, please refer to the description in Figure 1a or Figure 1b, or relevant standards or protocols, etc., which will not be detailed here. The explanation regarding the expansion factor Z also applies to Examples 4 to 14 below, and will not be repeated here.

[0207] For ease of description, the first X columns of the parity check matrix prototype will be referred to as the matrix corresponding to the information bits, or the information bit portion of the LDPC codeword, or the information bit portion of the matrix prototype, etc., and the last Y columns of the parity check matrix prototype will be referred to as the matrix corresponding to the parity bits, or the parity check matrix, or the parity bit portion of the LDPC codeword, or the parity bit portion of the matrix prototype, etc. X and Y are both positive integers. For example, X = 48 * R, Y = 48 * (1 - R). For the matrix prototypes shown in Examples 1 to 3, X = 24, Y = 24.

[0208] As an example, K = 3888 * 1 / 2 = 1944, meaning that when the information bit sequence includes 1944 information bits, the encoded sequence can include 1944 information bits and 1944 parity bits.

[0209] As another example, when K is less than 1944, meaning the information bit sequence contains less than 1944 information bits, the encoded sequence can include K information bits and 1944 parity bits. Although the encoded sequence includes K information bits and 1944 parity bits, its length is N1. As shown in Figure 18 below, since the number of information bits is less than 1944, the first communication device can obtain the information bit sequence by filling in a certain number of 0s before performing LDPC encoding, and then delete these 0s after completing the LDPC encoding. For example, the number of 0s can be equal to 1944-K. For related explanations of the shortening operation, please refer to Figure 18, which will not be detailed here.

[0210] As another example, when the number of information bits to be transmitted obtained by the first communication device before acquiring the information bit sequence is greater than 1944, the first communication device can perform codeword processing on the information bits before performing LDPC encoding. For example, after codeword processing, multiple codewords (or blocks or segments, etc.) can be obtained, and the number of information bits carried by each codeword can be less than or equal to 1944. Specific descriptions of codeword processing can be found in relevant standards or protocols, and this application does not limit this aspect. Of course, after the first communication device performs codeword processing, it can also combine it with shortening operations, etc. The combination of the above-mentioned shortening operations and codeword processing will not be detailed here.

[0211] The explanations regarding different values ​​of K also apply to Examples 4 to 14 below, and will not be repeated here.

[0212] As an example 4, the prototype of the parity check matrix can be shown in Figure 7a. An explanation of Figure 7b can be found below, and will not be detailed here.

[0213] As another example 5, the prototype of the check matrix can be shown in Figure 8a. A description of Figure 8b can be found below, and will not be detailed here.

[0214] As another example 6, the prototype of the check matrix can be shown in Figure 9a. An explanation of Figure 9b can be found below, and will not be detailed here.

[0215] The R corresponding to the matrix prototype of the parity check matrix shown in Examples 4 to 6 above can be equal to 2 / 3. Similarly, the R corresponding to the parity check matrix is ​​also equal to 2 / 3. For example, the N1 corresponding to the matrix prototype of the parity check matrix shown in Examples 4 to 6 above can be equal to 3888. And the first communication device performs LDPC encoding using the parity check matrix corresponding to the matrix prototype shown in Examples 4 to 6, obtaining an encoded sequence with a length of 3888 bits.

[0216] For Examples 4 to 6, X = 48 * 2 / 3 = 32, Y = 48 * 1 / 3 = 16. For further explanation of X and Y, please refer to Examples 1 to 3 above; they will not be elaborated upon here.

[0217] For explanations of the expansion factor, CPM, and K, please refer to Examples 1 to 3 above; they will not be elaborated upon here.

[0218] As an example 7, the prototype of the parity check matrix can be shown in Figure 10a. An explanation of Figure 10b can be found below, and will not be detailed here.

[0219] As another example 8, the prototype of the parity check matrix can be shown in Figure 11a. A description of Figure 11b can be found below, and will not be detailed here.

[0220] As another example 9, the prototype of the check matrix can be shown in Figure 12a. An explanation of Figure 12b can be found below, and will not be detailed here.

[0221] As another example 10, the prototype of the parity check matrix can be shown in Figure 13a. A description of Figure 13b can be found below, and will not be detailed here.

[0222] The R corresponding to the matrix prototype of the parity check matrix shown in Examples 7 to 10 above can be equal to 3 / 4. Similarly, the R corresponding to the parity check matrix is ​​also equal to 3 / 4. For example, the N1 corresponding to the matrix prototype of the parity check matrix shown in Examples 7 to 10 above can be equal to 3888. And the N1 corresponding to the parity check matrix is ​​also equal to 3888. The first communication device performs LDPC encoding using the parity check matrix corresponding to the matrix prototype shown in Examples 7 to 10, and the length of the encoded sequence is 3888 bits.

[0223] For Examples 7 to 10, X = 48 * 3 / 4 = 36, Y = 48 * 1 / 4 = 12. For further explanation of X and Y, please refer to Examples 1 to 3 above; they will not be elaborated upon here.

[0224] For explanations of the expansion factor, CPM, and K, please refer to Examples 1 to 3 above; they will not be elaborated upon here.

[0225] As an example 11, the prototype of the parity check matrix can be shown in Figure 14a. A description of Figure 14b can be found below, and will not be detailed here.

[0226] As another example 12, the prototype of the parity check matrix can be shown in Figure 15a. A description of Figure 15b can be found below, and will not be detailed here.

[0227] As another example 13, the prototype of the parity check matrix can be shown in Figure 16a. A description of Figure 16b can be found below, and will not be detailed here.

[0228] As another example 14, the prototype of the parity check matrix can be shown in Figure 17a. A description of Figure 17b can be found below, and will not be detailed here.

[0229] The R corresponding to the matrix prototype of the parity check matrix shown in Examples 11 to 14 above can be equal to 5 / 6. Similarly, the R corresponding to the parity check matrix is ​​also equal to 5 / 6. For example, the N1 corresponding to the matrix prototype of the parity check matrix shown in Examples 11 to 14 above can be equal to 3888. And the N1 corresponding to the parity check matrix is ​​also equal to 3888. The first communication device performs LDPC encoding using the parity check matrix corresponding to the matrix prototype shown in Examples 7 to 10, and the length of the encoded sequence is 3888 bits.

[0230] For Examples 11 to 14, X = 48 * 5 / 6 = 40, Y = 48 * 1 / 6 = 8. For further explanation of X and Y, please refer to Examples 1 to 3 above; they will not be elaborated upon here.

[0231] For explanations of the expansion factor, CPM, and K, please refer to Examples 1 to 3 above; they will not be elaborated upon here.

[0232] The matrix prototypes of the check matrices shown in Examples 1 to 14 above are merely examples. Other matrix prototypes of the check matrices shown in the embodiments of this application can also be obtained by the determination method described below, which will not be listed here.

[0233] 303. The first communication device outputs the encoded sequence.

[0234] For example, the first communication device can perform LDPC encoding using an encoding module (such as an LDPC encoding module) to obtain the encoded sequence, and output the encoded sequence from the encoding module. A description of the length of the encoded sequence can be found in steps 301 or 302 above, and will not be detailed here.

[0235] In one possible implementation, the first communication device may perform a shortening operation after outputting the encoded sequence. An example is given below.

[0236] Typically, the encoded information bit sequence needs to be placed into an integer number of orthogonal frequency division multiplexing (OFDM) symbols, and the encoded sequence also needs to be placed into an exact integer number of LDPC codewords. Therefore, before the first communication device performs LDPC encoding, it needs to determine the minimum number of OFDM symbols N required for this transmission. SYM Then based on N SYM Calculate the total number of coded bits N that can be stored in all OFDM symbols, based on the current coding and modulation scheme (such as the modulation order indicated by the MCS). TCB =N CBPS *N SYM , where N CBPS The number of encoded bits that can be stored for each OFDM symbol. Next, the first communication device can calculate the LDPC code length (i.e., the code length shown in the embodiments of this application) and the required number of codewords N based on the above results. CWFor example, when there are not enough information bits (as shown in Examples 1 to 3 below, where K is less than 1944) to fill the information bit portion of the LDPC codeword, the first communication device can perform a shortening operation before performing LDPC encoding (also known as generating parity bits). The shortening operation refers to filling the information bits with a certain number of 0s before generating the parity bits through LDPC encoding, and then deleting these 0s after encoding the parity bits. Figure 18 is a partial schematic diagram of a shortening operation in LDPC encoding provided by an embodiment of this application. As shown in Figure 18, step 1801 indicates that the first communication device can obtain the payload bits to be encoded (as shown in the embodiments of this application, K information bits). Step 1802 indicates that the first communication device can calculate the LDPC code length and the number of codewords. Figure 18 exemplarily shows three LDPC codewords. The length (i.e., code length) of each LDPC codeword can be equal to the code length. Step 1803 indicates that the first communication device can perform a shortening operation on the information bits. Figure 18 shows a codeword containing load bits and shortening zero bits. Step 1804 indicates that the first communication device can generate parity bits using the load bits and shortening bits. Figure 18 shows a codeword containing load bits, shortening zero bits, and parity bits. Step 1805 indicates that the first communication device discards these shortening zero bits. Figure 18 shows a codeword containing data bits and parity bits. The above descriptions regarding shortening operations are merely examples. Further explanations regarding shortening operations can be found in relevant standards or protocols, and this application does not limit the scope of the embodiments.

[0237] 304. The first communication device sends a signal corresponding to the encoded sequence, and the second communication device receives the signal.

[0238] The signal corresponding to the encoded sequence mentioned above refers to the processed signal that the encoded sequence can be further processed after being output from the encoding module, and then transmitted by the first communication device through the channel.

[0239] For example, the first communication device can perform rate matching on the encoded sequence, and the rate matching method may include puncturing, repetition, and shortening. For instance, the first communication device can puncture the parity bits in the encoded sequence to obtain a higher code rate or a shorter code length. For example, the first communication device can also perform at least one of the following processes on the encoded sequence: stream parsing, constellation mapping, LDPC subcarrier mapping, stream cyclic shifting, space-frequency mapping, inverse discrete fourier transform (IDFT), insertion of cyclic prefix, and windowing. For example, after receiving a signal transmitted through the channel, the second communication device can perform corresponding processing on the signal. For example, before obtaining the information to be decoded, the second communication device can perform at least one of the following processes: removing the cyclic prefix, performing a discrete fourier transform (DFT), space-frequency demapping, deinterleaving, and constellation deconstellation.

[0240] For other processing of the encoded sequence by the first communication device, and the corresponding processing of the second communication device before obtaining the information to be decoded, relevant standards or protocols can be referenced, but the embodiments of this application do not limit this.

[0241] 305. The second communication device performs LDPC decoding on the information to be decoded based on the parity check matrix to obtain the information bit sequence.

[0242] The length of the information to be decoded can be N1. The information to be decoded may include bits or real numbers, etc. This application embodiment does not limit the specific content included in the information to be decoded. For example, before obtaining the information to be decoded, the second communication device may supplement shortening bits, such as by combining the code length and K to supplement shortening bits, or it may supplement punch bits, etc. This application embodiment does not limit this.

[0243] For example, the decoding methods that the second communication device may employ include, but are not limited to, hard-decision decoding, soft-decision decoding, or hybrid decoding methods. The specific decoding process will not be detailed in the embodiments of this application.

[0244] For example, the second communication device can also use a method similar to Figure 18 to determine the code length N1, etc. For the relevant explanation of how the second communication device obtains the code length N1 and code rate R, please refer to the description of the first communication device above, which will not be detailed here. For the methods of the first communication device to obtain N1 and R, and the methods of the second communication device to obtain N1 and R, please refer to relevant standards or protocols, etc., and this application embodiment does not limit them.

[0245] In this embodiment, steps 302-303 can be implemented by an encoding module, and step 305 can be implemented by a decoding module. In a specific implementation, the method shown in FIG3 can also be divided into an encoding method or a decoding method. For example, the encoding method may include steps 302-303, or steps 301-303, and the first communication device may include an encoding module. For example, the decoding method may include step 305, and the second communication device may include a decoding module. Optionally, in addition to the encoding module, the first communication device may also include an acquisition module, which can be used to acquire code length and code rate, etc. Optionally, the first communication device may also include a shortening module or a segmentation module, etc. Optionally, in addition to the decoding module, the second communication device may also include an acquisition module, which can be used to acquire information to be decoded.

[0246] In this embodiment, the parity check matrix can be applied to information bit sequences that are n times the code length of 1944, where n is an integer greater than or equal to 2, thereby improving the transmission reliability of the system and enhancing decoding performance.

[0247] The following describes the method for determining the verification matrix involved in the embodiments of this application.

[0248] The method for determining the parity check matrix shown in this application embodiment is merely an example. In specific implementations, the determination method described below can be defined by a standard. Alternatively, in specific implementations, the communicating parties may not execute the determination method described below. For example, the communicating parties may save the matrix prototype of the parity check matrix, or save the extended indicator matrix (or accompanying extended indicator matrix, etc.). The matrix prototypes of the 14 parity check matrices shown above can be obtained through the determination method described below. Although the matrix prototypes of 14 parity check matrices are shown above as an example, the matrix prototypes of other parity check matrices determined according to the determination method shown in this application embodiment also fall within the protection scope of this application embodiment.

[0249] The determination method described below uses a base parity check matrix with a code length N0 = 1944 as an example. As shown in step 301 above, N1 can also be m times 1296. That is, according to the determination method described below, parity check matrices with a code length greater than 1944 can also be determined based on the parity check matrix corresponding to a code length of 1296. According to the determination method described below, parity check matrices with a code length greater than 1944 determined using the parity check matrix corresponding to a code length of 1296 as the base parity check matrix also fall within the protection scope of this application embodiment. The following uses the matrix prototype of the base parity check matrix as shown in Figure 1a as an example to illustrate the method for determining the matrix prototype of the parity check matrix shown in the embodiment of this application. Of course, the name of the base parity check matrix shown in the embodiment of this application is only an example. For example, the base parity check matrix can also be called a reference parity check matrix, a baseline parity check matrix, or a primary parity check matrix, etc.

[0250] To reuse the existing WLAN LDPC code encoding and decoding architecture as much as possible, this application extends the existing 1944-bit LDPC codes at different code rates in the WLAN system as the base matrix, thereby obtaining LDPC code parity-check matrices with a code length of 3888 bits for the corresponding code rates. In the original 1944-bit parity-check matrix prototypes (shown in Figure 1a), the CPM size of each element is 81. The CPM size of each element in the 3888-bit LDPC code parity-check matrix prototype shown in this application embodiment is also 81. However, the size of the parity-check matrix prototype shown in this application embodiment is twice the size of the base parity-check matrix prototype. This is explained in detail below.

[0251] Explanation of the basic parity check matrix:

[0252] The code length of the basic parity-check matrix is ​​N0 = 1944, and the code rates include: 1 / 2, 2 / 3, 3 / 4, and 5 / 6. The expansion factor of the basic parity-check matrix is ​​Z = 1944 / 24 = 81.

[0253] When R = 1 / 2, the prototype of the basic parity-check matrix is ​​a 12*24 matrix, meaning it consists of 12 rows and 24 columns. The expanded basic parity-check matrix based on this prototype can contain 972 rows and 1944 columns. X = 12, Y = 12.

[0254] When R = 2 / 3, the prototype of the basic parity-check matrix is ​​an 8*24 matrix, meaning it consists of 8 rows and 24 columns. The expanded basic parity-check matrix based on this prototype can contain 648 rows and 1944 columns. X = 16, Y = 8.

[0255] When R = 3 / 4, the prototype of the basic parity-check matrix is ​​a 6*24 matrix, meaning it consists of 6 rows and 24 columns. The expanded basic parity-check matrix based on this prototype can contain 648 rows and 1944 columns. X = 18, Y = 6.

[0256] When R = 5 / 6, the prototype of the basic parity-check matrix is ​​a 4*24 matrix, meaning it consists of 4 rows and 24 columns. The expanded basic parity-check matrix based on this prototype can contain 324 rows and 1944 columns. X = 20, Y = 4.

[0257] Explanation of the parity check matrix:

[0258] The code length of the parity-check matrix is ​​N1 = 3888, and the code rates include 1 / 2, 2 / 3, 3 / 4, and 5 / 6. The expansion factor of the parity-check matrix is ​​Z = 3888 / 48 = 81.

[0259] When R = 1 / 2, the prototype of the parity-check matrix is ​​a 24*48 matrix, meaning it consists of 24 rows and 48 columns. The expanded parity-check matrix based on this prototype consists of 1944 rows and 3888 columns. X = 24, Y = 24.

[0260] When R = 2 / 3, the prototype of the parity-check matrix is ​​a 16*48 matrix, meaning it consists of 16 rows and 48 columns. The expanded parity-check matrix based on this prototype consists of 1296 rows and 3888 columns. X = 32, Y = 16.

[0261] When R = 3 / 4, the prototype of the parity-check matrix is ​​a 12*48 matrix, meaning it consists of 12 rows and 48 columns. The expanded parity-check matrix based on this prototype consists of 972 rows and 3888 columns. X = 36, Y = 12.

[0262] When R = 5 / 6, the prototype of the parity-check matrix is ​​an 8*48 matrix, meaning it consists of 8 rows and 48 columns. The expanded parity-check matrix based on this prototype consists of 648 rows and 3888 columns. X = 40, Y = 8.

[0263] In this embodiment, the parity check matrix can be obtained by diagonally or anti-diagonally expanding the element in the x-th row and y-th column of the prototype of the basic parity check matrix. The code length N0 corresponding to the basic parity check matrix is ​​less than or equal to 1944 bits, and the code rate corresponding to the basic parity check matrix is ​​the same as the code rate corresponding to the parity check matrix. The element in the x-th row and y-th column is greater than or equal to 0. By diagonally or anti-diagonally expanding each item in the basic parity check matrix to obtain the parity check matrix, the various modules in the 1944-bit LDPC encoding and decoding architecture can be effectively reused. The following is a detailed description.

[0264] For example, if the element in the x-th row and y-th column of the basic parity-check matrix prototype is i, then expanding i diagonally yields the matrix shown in Figure 19a, and expanding i against the diagonal yields the matrix shown in Figure 19b. i can be an integer greater than or equal to 0. As another example, if the element in the x-th row and j-th column of the basic parity-check matrix prototype is "-1" or "-", the corresponding element in the parity-check matrix can also be "-1" or "-". Therefore, the element i in the basic parity-check matrix prototype can be expanded diagonally or against the diagonal. For example, each element can be expanded into a 2*2 square matrix. The non-negative elements in the square matrix can represent the CPM of a Z*Z identity matrix (e.g., 0 in the square matrix can represent a Z*Z identity matrix, and elements greater than 0 can represent the CPM of a Z*Z identity matrix). The blank areas in Figures 19a and 19b do not show "-1" (or "-"). "-1" in the square matrix can represent a Z*Z all-zero square matrix.

[0265] Taking (d)R = 5 / 6 in Figure 1a as an example, the Z of the basic parity-check matrix is ​​81, and the matrix prototype size of the basic parity-check matrix is ​​4 rows and 24 columns. After expanding element i in the basic parity-check matrix diagonally or anti-diagonally, the Z of the parity-check matrix remains equal to 81, that is, the expansion factor of the basic parity-check matrix remains unchanged. For example, when element i is expanded to a 2*2 square matrix, the matrix prototype size of the parity-check matrix is ​​8 rows and 48 columns, and the code rate of the parity-check matrix remains equal to 5 / 6. Therefore, the code length can be equal to 1944*2 = 3888. Of course, the expansion of element i in the matrix prototype of the basic parity-check matrix shown in this embodiment is only an example. Element i can also be expanded to a 3*3 square matrix, or even a 4*4 square matrix, etc., which will not be listed here. In this case, the code length of the expanded parity-check matrix can be longer. For example, when element i in the matrix prototype of the basic parity-check matrix is ​​expanded to a 3*3 square matrix, the corresponding code length of the parity-check matrix can be 24*3*81 = 5382. For example, when element i in the prototype of the basic parity check matrix is ​​expanded to a 4x4 square matrix, the code length corresponding to the parity check matrix can be 24*4*81 = 7776. These will not be listed individually here.

[0266] In this embodiment, element i in the matrix prototype of the basic parity check matrix can be expanded diagonally or anti-diagonally. This does not mean that every element in the matrix prototype of the basic parity check matrix is ​​expanded diagonally or anti-diagonally. Instead, diagonal expansion is performed on the first part of the matrix prototype of the basic parity check matrix that is greater than or equal to 0, and anti-diagonal expansion is performed on the second part of the matrix prototype of the basic parity check matrix that is greater than or equal to 0. The matrix corresponding to the information bits in the matrix prototype of the parity check matrix is ​​obtained by expanding the x-th row and y-th column element of the matrix corresponding to the information bits in the basic parity check matrix prototype diagonally or anti-diagonally. That is, expanding the first part of the information bit portion of the matrix prototype of the basic parity check matrix diagonally and anti-diagonally expanding the second part of the information bit portion diagonally yields the information bit portion of the matrix prototype of the parity check matrix.

[0267] Furthermore, the first and second columns of the matrix corresponding to the parity bits in the matrix prototype of the parity check matrix are obtained by either diagonally expanding the first element or anti-diagonally expanding the last element of the first column of the matrix corresponding to the parity bits in the matrix prototype of the basic parity check matrix. In other words, by diagonally expanding or anti-diagonally expanding the first element (e.g., element 1) or the last element (e.g., element 1) of the first column of the parity bit portion in the matrix prototype of the basic parity check matrix, the first and second columns of the parity bit portion in the matrix prototype of the parity check matrix can be obtained. That is, the first and last elements of the first column in the last Y columns of the matrix prototype of the basic parity check matrix are expanded in the same way.

[0268] If the elements in the first row of the first column and the last row of the first column in the matrix prototype of the basic check matrix are both extended diagonally (or extended anti-diagonally), then the elements in the first row of the first column, the second row of the first column, the first row of the second column, the second row of the second column, the last row of the first column, the second row of the first column, and the second row of the second column in the matrix prototype of the second column are obtained. For example, the elements in the first row of the first column and the last row of the first column in the extended indicator matrix are the same. Taking Figure 13b as an example, Y = 6, that is, the element in the first row of the first column of the last 6 columns of the extended indicator matrix is ​​0, and the element in the last row of the first column is also 0, as shown in Figure 13c. Similarly, in Figure 14b, the element in the first row of the first column of the extended indicator matrix is ​​1, and the element in the last row of the first column is also 1. And so on, without going into detail here.

[0269] For example, the element 0 in the first column of the parity bit part of the matrix prototype of the basic parity check matrix can be expanded diagonally or diagonally to obtain the element at the corresponding position in the matrix prototype of the parity check matrix.

[0270] Typically, in the prototype of the basic parity check matrix, the first column of the parity bit portion has a "1-0-1" structure, meaning that the first and last rows of this column are both 1, and the remaining rows are all 0. Therefore, to maintain the fast and efficient coding algorithm of the original WLAN LDPC, the embodiments of this application maintain a similar structure for the parity bit portion, such as having the first and last row elements of the last Y column in the extended indicator matrix both be 0 or both be 1. This ensures the fast and efficient coding algorithm of the LDPC code.

[0271] Furthermore, the elements in the matrix prototype of the parity check matrix, excluding columns 1 and 2, corresponding to the parity bits, are obtained by diagonally expanding all 0 elements (excluding column 1) in the matrix prototype of the parity check matrix corresponding to the parity bits. In the matrix prototype of the parity check matrix, all elements in the parity bit portion (excluding column 1) except for "-1" (or "-") (such as 0) can be diagonally expanded. As shown in Figure 1a, diagonally expanding the 0 elements in the parity bit portion of the matrix prototype, and diagonally expanding (or anti-diagonally expanding) all 1 elements in column 1 of this parity bit portion, yields the parity bit portion of the matrix prototype of the parity check matrix.

[0272] In other words, the first and second columns of the parity bit portion in the matrix prototype of the parity check matrix can be obtained by extending the first and last elements of the first column of the parity bit portion in the matrix prototype of the basic parity check matrix diagonally or by extending them against the diagonal. Similarly, the remaining columns of the parity bit portion in the matrix prototype of the parity check matrix can be obtained by extending all 0 elements in the parity bit portion of the matrix prototype of the basic parity check matrix diagonally, except for the first column. Therefore, as an example, the extension methods of the elements in the parity bit portion of the matrix prototype of the basic parity check matrix may all be the same. As shown in Figure 4a, the parity bit portion of the matrix prototype of the parity check matrix can be obtained by extending all elements of the parity bit portion of the matrix prototype of the basic parity check matrix diagonally. As another example, the extension methods of the elements in the parity bit portion of the matrix prototype of the basic parity check matrix may not be entirely the same. As shown in Figure 8b, the parity bit portion in the matrix prototype of the parity check matrix can be obtained by diagonally expanding the first and last elements of the first column of the parity bit portion in the matrix prototype of the basic parity check matrix, and by diagonally expanding all 0 elements in the parity bit portion except for the first and last elements of the first column. These will not be listed individually here.

[0273] The matrix prototype of the parity check matrix shown above can be obtained by extending the elements of the matrix prototype of the basic parity check matrix accordingly. The extension methods of each element shown above can also be represented by an extended indicator matrix. For example, the matrix prototype of the parity check matrix can be determined based on the matrix prototype of the basic parity check matrix and the extended indicator matrix. Alternatively, the relationship between the matrix prototype of the basic parity check matrix and the matrix prototype of the parity check matrix can be represented by the extended indicator matrix.

[0274] The size of this extended indicator matrix is ​​the same as the size of the matrix prototype of the base parity check matrix. For example, the element in the x-th row and y-th column of this extended indicator matrix indicates that the square matrix at the corresponding position in the matrix prototype of the parity check matrix is ​​obtained by performing a diagonal expansion or an anti-diagonal expansion on the element in the x-th row and y-th column of the base parity check matrix. Alternatively, the element in the x-th row and y-th column of this extended indicator matrix can indicate that performing the following operations on the x-th row and j-th column of the matrix prototype of the base parity check matrix results in the element at the corresponding position in the matrix prototype of the parity check matrix: diagonal expansion, anti-diagonal expansion, or remaining unchanged.

[0275] For example, if the element in the x-th row and j-th column of the extended indicator matrix is ​​element j, then element j can be equal to 0, 1, or "-1" (or can be replaced with "-"). Here, j=0 indicates that the element at the corresponding position in the matrix prototype of the parity check matrix is ​​obtained by diagonally expanding the element in the x-th row and j-th column of the matrix prototype of the basic parity check matrix. j=1 indicates that the element at the corresponding position in the matrix prototype of the parity check matrix is ​​obtained by anti-diagonally expanding the element in the x-th row and j-th column of the matrix prototype of the basic parity check matrix. j=-1 indicates that the element in the x-th row and j-th column of the matrix prototype of the basic parity check matrix (i.e., "-1" or "-") is expanded into a 2*2 all-zero matrix, or j=-1 indicates that the element at the corresponding position in the matrix prototype of the parity check matrix remains the same as the element in the x-th row and j-th column of the matrix prototype of the basic parity check matrix (i.e., "-1") (or can be interpreted as no expansion, or as remaining unchanged). The relationship between the value of j and its meaning shown here is only an example. In specific implementations, other values ​​can also be used to represent the above meaning, which will not be listed here.

[0276] For a bitrate R = 1 / 2, the following explanation is provided:

[0277] As an example, the matrix prototype of the check matrix shown in Figure 4a can be determined based on the extended indicator matrix shown in Figure 4b and the matrix (a) shown in Figure 1a (i.e., R = 1 / 2).

[0278] For example, in the matrix (a) shown in Figure 1a, the element in the first row and first column is 57, and in the extended index matrix shown in Figure 4b, the element in the first row and first column is 1. This means that the elements in the first row and first column, the first row and second column, the second row and first column, and the second row and second column of the matrix prototype of the check matrix are obtained by anti-diagonal expansion based on the element 57. That is, the element in the first row and first column of the matrix prototype of the check matrix is ​​"-1", the element in the first row and second column is 57, the element in the second row and first column is 57, and the element in the second row and second column is "-1".

[0279] For example, if the element in the first row and second column of the matrix (a) shown in Figure 1a is "-1", then the element in the first row and second column of the extended indicator matrix shown in Figure 4b is also "-1". Therefore, the elements in the first row and third column, the first row and fourth column, the second row and third column, and the second row and fourth column of the matrix prototype of the check matrix remain unchanged, that is, they are still "-1".

[0280] For example, in matrix (a) shown in Figure 1a, the element in the 3rd row and 1st column is 30, and in the extended index matrix shown in Figure 4b, the element in the 3rd row and 1st column is 0. This means that the elements in the 5th row and 1st column, 5th row and 2nd column, 6th row and 1st column, and 6th row and 2nd column of the original matrix of the check matrix are obtained by diagonally expanding the element 30. That is, the elements in the 5th row and 1st column of the original matrix of the check matrix are 30, the elements in the 5th row and 2nd column are "-1", the elements in the 6th row and 1st column are "-1", and the elements in the 6th row and 2nd column are 30.

[0281] The descriptions of other elements in the matrix prototype of the basic parity check matrix, other elements in the extended indicator matrix, and elements in the matrix prototype of the parity check matrix will not be listed here.

[0282] As another example, the matrix prototype of the check matrix shown in Figure 5a can be determined based on the extended indicator matrix shown in Figure 5b and the matrix (a) shown in Figure 1a (i.e., R = 1 / 2).

[0283] As another example, the matrix prototype of the check matrix shown in Figure 6a can be determined based on the extended indicator matrix shown in Figure 6b and the matrix (a) shown in Figure 1a (i.e., R = 1 / 2).

[0284] For a bitrate R = 2 / 3, the following explanation is provided:

[0285] As an example, the matrix prototype of the check matrix shown in Figure 7a can be determined based on the extended indicator matrix shown in Figure 7b and the matrix (b) shown in Figure 1a (i.e., R = 2 / 3).

[0286] As another example, the matrix prototype of the check matrix shown in Figure 8a can be determined based on the extended indicator matrix shown in Figure 8b and the matrix (b) shown in Figure 1a (i.e., R = 2 / 3).

[0287] As another example, the matrix prototype of the check matrix shown in Figure 9a can be determined based on the extended indicator matrix shown in Figure 9b and the matrix (b) shown in Figure 1a (i.e., R = 2 / 3).

[0288] For a bitrate R = 3 / 4, the following explanation is provided:

[0289] As an example, the matrix prototype of the check matrix shown in Figure 10a can be determined based on the extended indicator matrix shown in Figure 10b and the matrix (c) shown in Figure 1a (i.e., R = 3 / 4).

[0290] As another example, the matrix prototype of the check matrix shown in Figure 11a can be determined based on the extended indicator matrix shown in Figure 11b and the matrix (c) shown in Figure 1a (i.e., R = 3 / 4).

[0291] As another example, the matrix prototype of the check matrix shown in Figure 12a can be determined based on the extended indicator matrix shown in Figure 12b and the matrix (c) shown in Figure 1a (i.e., R = 3 / 4).

[0292] As another example, the matrix prototype of the check matrix shown in Figure 13a can be determined based on the extended indicator matrix shown in Figure 13b and the matrix (c) shown in Figure 1a (i.e., R = 3 / 4).

[0293] For a bitrate R = 5 / 6, the following explanation is provided:

[0294] As an example, the matrix prototype of the check matrix shown in Figure 14a can be determined based on the extended indicator matrix shown in Figure 14b and the matrix (d) shown in Figure 1a (i.e., R = 5 / 6).

[0295] As another example, the matrix prototype of the check matrix shown in Figure 15a can be determined based on the extended indicator matrix shown in Figure 15b and the matrix (d) shown in Figure 1a (i.e., R = 5 / 6).

[0296] As another example, the matrix prototype of the check matrix shown in Figure 16a can be determined based on the extended indicator matrix shown in Figure 16b and the matrix (d) shown in Figure 1a (i.e., R = 5 / 6).

[0297] As another example, the matrix prototype of the check matrix shown in Figure 17a can be determined based on the extended indicator matrix shown in Figure 17b and the matrix (d) shown in Figure 1a (i.e., R = 5 / 6).

[0298] As an example, the communicating parties (such as the first and second communication devices) store the elements of the matrix prototype of the parity check matrix. For instance, by storing the elements of the matrix prototype, when the code length is 3888 bits, the communicating parties can directly obtain the parity check matrix based on their respective stored elements and expansion factors. Similarly, by storing the elements of the matrix prototype, when the code length is 1944 bits, the communicating parties can obtain the basic parity check matrix based on the aforementioned expansion method. In other words, by storing the elements (or CPM coefficients or cyclic shift values, etc.) of the matrix prototype of the parity check matrix, the communicating parties can obtain LDPC codes of two code lengths, saving storage space. As another example, the communicating parties can also store the basic parity check matrix and the extended indicator matrix. For instance, when the code length is 3888 bits, the communicating parties can obtain the matrix prototype of the parity check matrix based on the matrix prototype of the basic parity check matrix and the extended indicator matrix.

[0299] The above describes how each element in the prototype of the basic parity check matrix is ​​extended in matrix form. However, the matrix form shown is only an example. In specific implementations, other variations of the extension indicator matrix can be made. For example, a bitmap can be used to indicate the extension of each element in the prototype of the basic parity check matrix, and the length of the bitmap can be equal to the number of elements greater than or equal to 0 in the prototype of the basic parity check matrix. Another example is using a table to indicate the extension of each element in the prototype of the basic parity check matrix, etc., which will not be listed here.

[0300] The prototype (or parity check matrix) of the parity check matrix obtained by the above determination method is within the protection scope of the embodiments of this application. Furthermore, combining the above method with a tree structure can effectively filter out parity check matrices with better decoding performance, further improving the decoding performance of the parity check matrix.

[0301] Each element in the prototype of the basic parity-check matrix can be expanded using either diagonal expansion or anti-diagonal expansion, choosing one of these two expansion methods: diagonal (Opt A) or anti-diagonal (Opt B). The small squares in Figure 20a represent element values ​​in the prototype of the basic parity-check matrix. Option A (Opt A) represents the square matrix after diagonally expanding the element value, and option B (Opt B) represents the square matrix after anti-diagonally expanding the element value.

[0302] The specific selection of OptA or OptB for the above element values ​​can be achieved by expanding the candidate nodes numerically, choosing the deeper expansion method. A schematic diagram of the tree expansion is shown in Figure 20b, where circles represent variable nodes and squares represent check nodes. The deeper the expanded tree, the fewer short cycles the resulting matrix contains; short cycles negatively impact decoding performance. Expanding each variable node using a tree, the depth of each Opt A or Opt B item in the corresponding matrix may differ, resulting in different cycle structures in the overall check matrix's corresponding factor graph (tanner graph). Therefore, this embodiment comprehensively considers the local and overall cycle structure of the matrix, designing all non-zero elements based on tree expansion to ensure that the factor graph corresponding to the check matrix has a good cycle structure.

[0303] By combining the determination method and tree structure shown above, the verification matrix provided in this application embodiment can effectively ensure that the original WLAN LDPC code's fast and efficient encoding method is maintained, thereby improving decoding performance.

[0304] The following describes the simulation results of the verification matrix provided in the embodiments of this application.

[0305] The performance comparison between the above-mentioned parity-check matrix and the basic parity-check matrix is ​​given below. In Figures 21a-21d, the horizontal axis represents the signal-to-noise ratio (SNR) in dB, and the vertical axis represents the block error rate (BLER). The decoding method used is a soft-decision decoding method, such as the brief propagation (BP) algorithm, with 8 decoding iterations. Numbers 1-4 in Figures 21a-21d are used to distinguish different curves and should not be construed as limiting the embodiments of this application.

[0306] Figure 21a shows a performance comparison between a parity-check matrix with a code length of 3888 and a basic parity-check matrix with a code length of 1944. R = 1 / 2.

[0307] Figure 21b shows a performance comparison between a parity-check matrix with a code length of 3888 and a basic parity-check matrix with a code length of 1944. R = 2 / 3.

[0308] Figure 21c shows a performance comparison between a parity-check matrix with a code length of 3888 and a basic parity-check matrix with a code length of 1944. R = 3 / 4

[0309] Figure 21d shows a performance comparison between a parity-check matrix with a code length of 3888 and a basic parity-check matrix with a code length of 1944. R = 5 / 6.

[0310] As can be seen from the above, under the same SNR, the BLER corresponding to the parity-check matrix is ​​lower, thus the decoding performance of the parity-check matrix is ​​better. Therefore, the parity-check matrices provided in the embodiments of this application can achieve significant improvements in decoding performance, while achieving a good trade-off between decoding performance and complexity.

[0311] In this embodiment, the impact of columns with different column weights forming small loops (or short loops) on the final performance in the prototype of the LDPC code parity-check matrix varies. For example, if columns with low column weights (e.g., column weights of 2 or 3) form small loops, the performance degradation is more severe than that caused by small loops formed by columns with high column weights. Low and high column weights are relative terms; for instance, low column weight refers to a column weight less than or equal to a first value, while high column weight refers to a column weight greater than or equal to a second value. The first value can be equal to or less than the second value. This embodiment does not limit the specific values ​​of the first and second values.

[0312] Therefore, small loops between columns with low column weights can be avoided. In this embodiment, the basic parity check matrix can be extended according to different column weights; or, the basic parity check matrix can be extended by grouping according to different column weights. In other words, regions with the same column weight in the basic parity check matrix can be extended first, that is, extended indicator matrices corresponding to regions with the same column weight are designed first. The extended indicator matrices designed in this embodiment can be designed according to different column weights, or grouped according to different column weights.

[0313] Figure 25 is a schematic diagram of the matrix prototype grouping design of the basic parity check matrix provided in an embodiment of this application. Figure 25 exemplarily shows the schematic diagram of the matrix prototype grouping design of the basic parity check matrix when the code rate R = 5 / 6 and N = 1944. As shown in Figure 25, the design of the matrix prototype of the LDPC basic parity check matrix when the code rate R = 5 / 6 and N = 1944 can be divided into 3 groups according to the column weight, and then each group is optimized sequentially according to priority. For example, firstly, for the region corresponding to the highest priority short loop optimization, the extended indicator matrix corresponding to this region can be designed first (e.g., all column weights are 2) to prioritize the performance of this region. Secondly, for the region corresponding to the second highest priority short loop optimization, the extended indicator matrix corresponding to this region can be optimized (e.g., all column weights are 3). Finally, the region corresponding to the low priority short loop optimization (e.g., all column weights are 4) is optimized. Figure 25 exemplarily shows the case of R = 5 / 6. For other code rates, the extended indicator matrix can also be designed according to the column weight. The optimization methods for grouping or dividing by column weight are similar to the examples above. Each group can be designed according to the optimization priority of small loops, which will not be listed here. The column weight example above uses the number of non-"-1" values ​​in a column as an example.

[0314] In the above-described method for designing the LDPC check matrix or extended indicator matrix, the extended indicator matrices corresponding to columns with the same column weight are within the protection scope of this application. That is, according to the above design method, the extended indicator matrices corresponding to one or more grouped regions are also within the protection scope of this application, and this principle applies to all embodiments of this application. The extended indicator matrix shown in this application can also be called an extended pattern. For example, taking Figure 25 as an example, the extended indicator matrix (or first part extended indicator matrix) corresponding to the highest priority short-loop optimization and the matrix prototype (or first part matrix prototype) of the check matrix are within the protection scope of this application. The extended indicator matrix (or second part extended indicator matrix) corresponding to the second highest priority short-loop optimization and the matrix prototype (or second part matrix prototype) of the check matrix are also within the protection scope of this application. The extended indicator matrix (or third part extended indicator matrix) corresponding to the low priority short-loop optimization and the matrix prototype (or third part matrix prototype) of the check matrix are also within the protection scope of this application. Similarly, the matrix prototypes of the extended indicator matrix and the check matrix corresponding to all regions shown in Figure 25 are also within the protection scope of the embodiments of this application.

[0315] In the extended indicator matrix, inverting all or part of the columns of the remaining matrix, excluding the matrix corresponding to the parity check matrix, also falls within the protection scope of this application. That is, inverting all or part of the columns of the matrix corresponding to the information bit portion in the extended indicator matrix also falls within the protection scope of this application. For ease of description, the remaining matrix region in the extended indicator matrix, excluding the matrix corresponding to the parity check matrix, is referred to as the information portion matrix or the system portion matrix. Since the parity check matrix in the prototype of the 11n LDPC parity check matrix has a fixed structure and includes a double diagonal structure, in order to achieve fast encoding, it is not necessary to invert the matrix corresponding to the parity check matrix in the extended indicator matrix. This application does not limit whether to invert the matrix corresponding to the parity check matrix.

[0316] In this application embodiment, the matrix obtained by performing column permutation or row permutation on the matrix prototype of the parity check matrix also falls within the protection scope of this application embodiment. That is, after performing column permutation or row permutation on the matrix prototypes of the various parity check matrices shown in this application, or after performing both row permutation and column permutation simultaneously, the matrix prototype of the parity check matrix can also be obtained. The performance of the matrix prototype before permutation and the matrix prototype after permutation is the same. The method for determining the extended indicator matrix or the method for determining the matrix prototype of the parity check matrix shown in this application embodiment also falls within the protection scope of this application embodiment. Since the matrix prototype of the parity check matrix has the above-mentioned variations, and each matrix prototype is listed in this application embodiment, all or part of the deformations of the various LDPC matrices described above are also within the protection scope of this application.

[0317] Figures 26a and 26b are schematic diagrams of the extended indicator matrix provided in the embodiments of this application. For the matrix prototype of the LDPC parity check matrix with code rate R = 5 / 6 and N = 1944 shown in Figure 25, the embodiments of this application illustrate the extended indicator matrix.

[0318] The extended indicator matrix shown in Figure 26b is obtained by inverting the information portion matrix of the extended indicator matrix shown in Figure 26a. Specifically, the inversion method is as follows: in the information portion matrix of the extended indicator matrix, "1" is inverted to "0", "0" is inverted to "1", and "-1" remains unchanged. Simultaneously, the rightmost 4x4 parity check matrix remains unchanged. Since the ring length distribution of each variable node in the extended parity check matrix obtained after inverting the information portion matrix in the above method is the same as that in the extended parity check matrix before inversion, these two extension methods can be considered equivalent under the principle of optimizing ring length distribution.

[0319] In other words, all the matrix prototypes or verification matrices of the extended indicator matrices or verification matrices given in the embodiments of this application, the extended indicator matrices obtained by inverting the corresponding information part matrices (e.g., "1" is inverted to "0", "0" is inverted to "1", and "-1" remains unchanged), and the matrix prototypes of the verification matrices obtained based on the extended indicator matrices, and the verification matrices obtained based on the extended indicator matrices, are all within the protection scope of the embodiments of this application.

[0320] In addition to the matrix prototypes and extended indicator matrices of the various check matrices shown above, this application embodiment also provides the following matrices. The R corresponding to the matrix prototype of the check matrix shown below is the same as the R corresponding to the check matrix. For example, N1 corresponding to the matrix prototype of the check matrix shown below can be equal to 3888. Simultaneously, N1 corresponding to the check matrix is ​​also equal to 3888. Explanations regarding R or N1, etc., can be found above and will not be detailed here.

[0321] For a bitrate R = 1 / 2, the following explanation is provided:

[0322] As an example, the prototype of the check matrix can be shown in Figure 27a. The prototype of the check matrix shown in Figure 27a can be determined based on the extended indicator matrix shown in Figure 27b and the matrix (a) shown in Figure 1a (i.e., R = 1 / 2).

[0323] As another example, the matrix prototype of the check matrix can be shown in Figure 28a. The matrix prototype of the check matrix shown in Figure 28a can be determined based on the extended indicator matrix shown in Figure 28b and the matrix (a) shown in Figure 1a (i.e., R = 1 / 2).

[0324] The extended indicator matrix shown in Figure 28b is obtained by inverting the information component matrix of the extended indicator matrix shown in Figure 27b. Figures 27b and 28b exemplarily show the extended indicator matrix after inverting the information component matrix, and Figures 27a and 28a exemplarily show the matrix prototype of the check matrix corresponding to the inverted extended indicator matrix. For simplicity, the extended indicator matrix after inverting the information component matrix will not be shown below.

[0325] As another example, the matrix prototype of the check matrix can be shown in Figure 29a. The matrix prototype of the check matrix shown in Figure 29a can be determined based on the extended indicator matrix shown in Figure 29b and the matrix (a) shown in Figure 1a (i.e., R = 1 / 2).

[0326] For a bitrate R = 2 / 3, the following explanation is provided:

[0327] As an example, the prototype of the parity check matrix can be shown in Figure 30a. The prototype of the parity check matrix shown in Figure 30a can be determined based on the extended indicator matrix shown in Figure 30b and matrix (b) shown in Figure 1a (i.e., R = 2 / 3). As another example, the prototype of the parity check matrix can be shown in Figure 31a. The prototype of the parity check matrix shown in Figure 31a can be determined based on the extended indicator matrix shown in Figure 31b and matrix (b) shown in Figure 1a (i.e., R = 2 / 3).

[0328] As another example, the matrix prototype of the check matrix can be shown in Figure 32a. The matrix prototype of the check matrix shown in Figure 32a can be determined based on the extended indicator matrix shown in Figure 32b and the matrix (b) shown in Figure 1a (i.e., R = 2 / 3).

[0329] For a bitrate R = 3 / 4, the following explanation is provided:

[0330] As an example, the prototype of the check matrix can be shown in Figure 33a. The prototype of the check matrix shown in Figure 33a can be determined based on the extended indicator matrix shown in Figure 33b and the matrix (c) shown in Figure 1a (i.e., R = 3 / 4).

[0331] As another example, the matrix prototype of the check matrix can be shown in Figure 34a. The matrix prototype of the check matrix shown in Figure 34a can be determined based on the extended indicator matrix shown in Figure 34b and the matrix (c) shown in Figure 1a (i.e., R = 3 / 4).

[0332] As another example, the prototype of the check matrix can be shown in Figure 35a. The prototype of the check matrix shown in Figure 35a can be determined based on the extended indicator matrix shown in Figure 35b and the matrix (c) shown in Figure 1a (i.e., R = 3 / 4).

[0333] For a bitrate R = 5 / 6, the following explanation is provided:

[0334] As an example, the prototype of the check matrix can be shown in Figure 36a. The prototype of the check matrix shown in Figure 36a can be determined based on the extended indicator matrix shown in Figure 36b and the matrix (d) shown in Figure 1a (i.e., R = 5 / 6).

[0335] As another example, the matrix prototype of the check matrix can be shown in Figure 37a. The matrix prototype of the check matrix shown in Figure 37a can be determined based on the extended indicator matrix shown in Figure 37b and the matrix (d) shown in Figure 1a (i.e., R = 5 / 6).

[0336] The following describes the communication device provided in the embodiments of this application.

[0337] This application divides the communication device into functional modules according to the above method embodiments. For example, each function can be divided into its own functional modules, or two or more functions can be integrated into one processing module. The integrated modules can be implemented in hardware or as software functional modules. It should be noted that the module division in this application is illustrative and only represents one logical functional division; other division methods may be used in actual implementation. The communication device of the embodiments of this application will be described in detail below with reference to Figures 22 to 24.

[0338] Figure 22 is a schematic diagram of a communication device provided in an embodiment of this application. As shown in Figure 22, the communication device includes a processing module 2201 and a transceiver module 2202. The transceiver module 2202 can implement corresponding communication functions, and the processing module 2201 is used to implement corresponding processing functions. The transceiver module 2202 can also be referred to as an interface, a communication interface, or a communication module, etc.

[0339] In some embodiments of this application, the communication device can be used to perform the actions performed by the first communication device in the above method embodiments. In this case, the first communication device can be the Wi-Fi device itself or a chip or functional module configurable in the device. The transceiver module 2202 is used to perform the transmission and reception related operations of the first communication device in the above method embodiments, and the processing module 2201 is used to perform the processing related operations of the first communication device in the above method embodiments.

[0340] For example, the processing module 2201 can be used to acquire an information bit sequence and perform LDPC encoding on the information bit sequence based on the parity check matrix to obtain the encoded sequence; the transceiver module 2202 can be used to output the encoded sequence.

[0341] For example, the processing module 2201 can also be used to perform other processing on the encoded sequence; the transceiver module 2202 can also be used to send or output the signal after other processing.

[0342] For example, the processing module 2201 may include an encoding module. The processing module 2201 may also include an acquisition module, a shortening module, or a segmentation module. For example, the processing module 2201 may also include at least one of the following modules: a constellation mapping module, a stream cyclic shifting module, a space-frequency mapping module, an IDFT module, and a cyclic prefix insertion and windowing module. For example, the transceiver module 2202 may include a radio frequency module, an antenna module, etc. For example, the transceiver module 2202 may include a pin module, etc.

[0343] Reusing Figure 22, in some other embodiments of this application, the communication device can be used to perform the actions performed by the second communication device in the above method embodiments. In this case, the communication device can be the Wi-Fi device itself or a chip or functional module configurable in the device. The transceiver module 2202 is used to perform the transceiver-related operations of the second communication device in the above method embodiments, and the processing module 2201 is used to perform the processing-related operations of the second communication device in the above method embodiments.

[0344] For example, the transceiver module 2202 can be used to receive or input signals transmitted through the channel; the processing module 2201 can be used to process the signal to obtain information to be decoded.

[0345] For example, the transceiver module 2202 can be used to input the information to be decoded; the processing module 2201 can perform LDPC decoding on the information to be decoded based on the parity check matrix to obtain the information bit sequence.

[0346] For example, the processing module 2201 may include a decoding module. The processing module 2201 may also include an acquisition module, etc. For example, the processing module 2201 may also include at least one of the following components: a cyclic prefix removal module, a DFT module, a deinterleaving module, a deconstellation module, and a descrambling module. For example, the transceiver module 2202 may include a radio frequency module, an antenna module, etc. For example, the transceiver module 2202 may include a pin module, etc.

[0347] Optionally, in the above embodiments, the communication device may further include a storage module, which can be used to store instructions and / or data. The processing module 2201 can read the instructions and / or data from the storage module to enable the communication device to implement the aforementioned method embodiments. For example, the storage module can store the matrix prototype of the check matrix shown above, or it can be used to store CPM coefficients or extended indicator matrices, etc., in the matrix prototype of the check matrix shown above.

[0348] In the above embodiments, the specific descriptions of terms or steps such as reference parity matrix, parity matrix, prototype of parity matrix, prototype of reference parity matrix, CPM, cyclic shift bits, spread factor, code length, and code rate can be found in the above method embodiments, and will not be described in detail here.

[0349] The specific descriptions of the transceiver module and processing module shown in the above embodiments are merely examples. For the specific functions or execution steps of the transceiver module and processing module, please refer to the above method embodiments, which will not be described in detail here.

[0350] The communication device according to the embodiments of this application has been described above. The following describes possible product forms of the communication device. Any product possessing the functions of the communication device described in FIG22 above falls within the protection scope of the embodiments of this application. The following description is merely illustrative and does not limit the product form of the communication device according to the embodiments of this application to this extent.

[0351] In one possible implementation, in the communication device shown in FIG22, the processing module 2201 can be one or more processors, and the transceiver module 2202 can be a transceiver, or the transceiver module 2202 can also be a transmitting module and a receiving module. The transmitting module can be a transmitter, and the receiving module can be a receiver. The transmitting module and the receiving module are integrated into one device, such as a transceiver. In the embodiments of this application, the processor and the transceiver can be coupled, etc., and the connection method of the processor and the transceiver is not limited in the embodiments of this application. In the process of executing the above method, the process of sending information in the above method can be the process of the processor outputting the above information. When outputting the above information, the processor outputs the above information to the transceiver so that the transceiver can transmit it. After the above information is output by the processor, it may need to undergo other processing before reaching the transceiver. Similarly, the process of receiving information in the above method can be the process of the processor receiving the input above information. When the processor receives the input information, the transceiver receives the above information and inputs it into the processor. Furthermore, after the transceiver receives the aforementioned information, the information may need to undergo further processing before being input into the processor.

[0352] As shown in Figure 23, the communication device 230 includes one or more processors 2320 and transceivers 2310.

[0353] In some embodiments of this application, the communication device can be used to execute the steps, methods, or functions performed by the first communication device described above. For example, the processor 2320 can be used to execute the functions or steps implemented by the processing module 2201 shown in FIG. 22, and the transceiver 2310 can be used to execute the functions or steps implemented by the transceiver module 2202 shown in FIG. 22. Detailed descriptions of the processor 2320 and the transceiver 2310 can be found in FIG. 22 or the method embodiments shown above, and will not be elaborated further here.

[0354] In other embodiments of this application, the communication device is used to execute the steps, methods, or functions executed by the second communication device described above. For example, the processor 2320 can be used to execute the functions or steps implemented by the processing module 2201 shown in FIG. 22, and the transceiver 2310 can be used to execute the functions or steps implemented by the transceiver module 2202 shown in FIG. 22. Detailed descriptions of the processor 2320 and the transceiver 2310 can be found in FIG. 22 or the method embodiments shown above, and will not be elaborated further here.

[0355] In various implementations of the communication device shown in Figure 23, the transceiver may include a receiver for performing a receiving function (or operation) and a transmitter for performing a transmitting function (or operation). The transceiver is also used to communicate with other devices / appliances via a transmission medium.

[0356] Optionally, the communication device 230 may further include one or more memories 2330 for storing program instructions and / or data. The memories 2330 and the processor 2320 are coupled. The coupling in this embodiment is an indirect coupling or communication connection between communication devices, units, or modules, and can be electrical, mechanical, or other forms, used for information exchange between the communication devices, units, or modules. The processor 2320 may operate in conjunction with the memories 2330. The processor 2320 may execute program instructions stored in the memories 2330. Optionally, at least one of the above-mentioned memories may be included in the processor.

[0357] This embodiment does not limit the specific connection medium between the transceiver 2310, processor 2320, and memory 2330. In Figure 23, the memory 2330, processor 2320, and transceiver 2310 are connected via a bus 2340, indicated by a thick line. The connection methods between other components are merely illustrative and not intended to be limiting. The bus can be categorized as an address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used in Figure 23, but this does not imply that there is only one bus or one type of bus.

[0358] In the embodiments of this application, the processor may be a general-purpose processor, a digital signal processor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc., and can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly manifested as being executed by a hardware processor, or being executed by a combination of hardware and software modules within the processor.

[0359] In this application embodiment, the memory may include, but is not limited to, non-volatile memory such as hard disk drive (HDD) or solid-state drive (SSD), random access memory (RAM), erasable programmable read-only memory (EPROM), read-only memory (ROM), or compact disc read-only memory (CD-ROM), etc. Memory is any storage medium capable of carrying or storing program code having instruction or data structure forms, and capable of being read and / or written by a computer (such as the communication device shown in this application), but is not limited to this. The memory in this application embodiment may also be a circuit or any other device capable of implementing storage functions, used to store program instructions and / or data.

[0360] The processor 2320 is primarily used for processing communication protocols and data, controlling the entire communication device, executing software programs, and processing software program data. The memory 2330 is primarily used for storing software programs and data. The transceiver 2310 may include control circuitry and an antenna. The control circuitry is primarily used for converting baseband signals to radio frequency signals and processing radio frequency signals. The antenna is primarily used for transmitting and receiving radio frequency signals in the form of electromagnetic waves. Input / output devices, such as touchscreens, displays, and keyboards, are primarily used for receiving user input data and outputting data to the user.

[0361] When the communication device is powered on, the processor 2320 can read the software program in the memory 2330, interpret and execute the instructions of the software program, and process the data of the software program. When data needs to be transmitted wirelessly, the processor 2320 performs baseband processing on the data to be transmitted and outputs the baseband signal to the radio frequency (RF) circuit. The RF circuit processes the baseband signal and transmits the RF signal outward in the form of electromagnetic waves through the antenna. When data is sent to the communication device, the RF circuit receives the RF signal through the antenna, converts the RF signal into a baseband signal, and outputs the baseband signal to the processor 2320. The processor 2320 converts the baseband signal into data and processes the data.

[0362] In another implementation, the radio frequency circuitry and antenna can be set up independently of the processor performing baseband processing. For example, in a distributed scenario, the radio frequency circuitry and antenna can be arranged remotely, independent of the communication device.

[0363] The communication device shown in this application embodiment may also have more components than those in Figure 23, and this application embodiment does not limit this. The methods executed by the processor and transceiver shown above are only examples, and the specific steps executed by the processor and transceiver can be referred to the methods described above.

[0364] In another possible implementation, in the communication device shown in Figure 22, the processing module 2201 can be one or more logic circuits, and the transceiver module 2202 can be an input / output interface, or a communication interface, or an interface circuit, or an interface, etc. Alternatively, the transceiver module 2202 can also be a transmitting module and a receiving module. The transmitting module can be an output interface, and the receiving module can be an input interface. The transmitting module and the receiving module are integrated into one module, such as an input / output interface. As shown in Figure 24, the communication device shown in Figure 24 includes a logic circuit 2401 and an interface 2402. That is, the processing module 2201 can be implemented using the logic circuit 2401, and the transceiver module 2202 can be implemented using the interface 2402. The logic circuit 2401 can be a chip, a processing circuit, an integrated circuit, or a system-on-a-chip (SoC) chip, etc., and the interface 2402 can be a communication interface, an input / output interface, pins, etc. For example, Figure 24 illustrates the communication device as a chip, which includes the logic circuit 2401 and the interface 2402.

[0365] In this embodiment, the logic circuit and the interface can also be coupled to each other. The specific connection method of the logic circuit and the interface is not limited in this embodiment. For example, the logic circuit 2401 can be used to execute the functions or steps implemented by the processing module 2201 shown in FIG. 22, and the interface 2402 can be used to execute the functions or steps implemented by the transceiver module 2202 shown in FIG. 22. For a detailed description of the logic circuit 2401 and the interface 2402, please refer to FIG. 22 or the method embodiment shown above, which will not be detailed here.

[0366] The communication device shown in the embodiments of this application can implement the method provided in the embodiments of this application in hardware form, or it can implement the method provided in the embodiments of this application in software form, etc., and the embodiments of this application do not limit it in this way.

[0367] This application also provides a communication system, which includes a first communication device and a second communication device, which can be used to perform the methods in any of the foregoing embodiments.

[0368] In addition, this application also provides a computer program for implementing the operations and / or processes performed by various communication devices in the method provided in this application.

[0369] This application also provides a computer-readable storage medium storing computer code that, when executed on a computer, causes the computer to perform the operations and / or processes performed by various communication devices in the methods provided in this application.

[0370] This application also provides a computer program product comprising computer code or a computer program that, when run on a computer, causes the operations and / or processes performed by various entities in the method provided in this application to be executed.

[0371] In the embodiments provided in this application, it should be understood that the disclosed systems, communication devices, and methods can be implemented in other ways. For example, the communication device embodiments described above are merely illustrative. For instance, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple modules or components may be combined or integrated into another system, or some features may be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, communication devices, or modules, or it may be an electrical, mechanical, or other form of connection.

[0372] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical modules; that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules can be selected according to actual needs to achieve the technical effects of the solutions provided in the embodiments of this application.

[0373] Furthermore, the functional modules in the various embodiments of this application can be integrated into one processing module, or each module can exist physically separately, or two or more modules can be integrated into one module. The integrated modules described above can be implemented in hardware or as software functional modules.

[0374] If the integrated module is implemented as a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned readable storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0375] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. An encoding method, characterized in that, The method includes: Obtain the information bit sequence; The information bit sequence is encoded using low-density parity-check (LDPC) encoding based on the parity-check matrix to obtain the encoded sequence. The length of the encoded sequence is N1, where N1 is n times 1944, and n is an integer greater than or equal to 2. The expansion factor of the parity-check matrix is ​​Z = 81. Output the encoded sequence.

2. A decoding method, characterized in that, The method includes: Obtain the information to be decoded, wherein the length of the information to be decoded is N1, where N1 is n times 1944, and n is an integer greater than or equal to 2; The information to be decoded is subjected to low-density parity-check (LDPC) decoding based on the parity-check matrix to obtain the information bit sequence. The expansion factor of the parity-check matrix is ​​Z = 81.

3. The method according to claim 1 or 2, characterized in that, The first and second columns of the matrix corresponding to the parity bit in the matrix prototype of the parity matrix are obtained by extending the first and last elements of the first column of the matrix corresponding to the parity bit in the matrix prototype of the basic parity matrix, either diagonally or diagonally. The code rate corresponding to the basic parity matrix is ​​the same as the code rate corresponding to the parity matrix.

4. The method according to any one of claims 1-3, characterized in that, The elements in the matrix prototype of the parity check matrix, excluding the first and second columns, are obtained by diagonally expanding all 0 elements (excluding the first column) in the matrix corresponding to the parity check bits in the matrix prototype of the basic parity check matrix. The code rate corresponding to the basic parity check matrix is ​​the same as the code rate corresponding to the parity check matrix.

5. The method according to any one of claims 1-4, characterized in that, The matrix corresponding to the information bit in the matrix prototype of the parity check matrix is ​​obtained by diagonally expanding or anti-diagonally expanding the element in the x-th row and y-th column of the matrix corresponding to the information bit in the matrix prototype of the basic parity check matrix. The element in the x-th row and j-th column is greater than or equal to 0, and x and y are both positive integers. The code rate corresponding to the basic parity check matrix is ​​the same as the code rate corresponding to the parity check matrix.

6. [Amended according to Rule 26, 10.02.2025] The method according to any one of claims 1-5, characterized in that, When the code rate R of the information bit sequence is 1 / 2, the prototype of the parity check matrix is ​​any of the following matrices: or, or, Where -1 represents a Z*Z all-zero matrix, 0 represents a Z*Z identity matrix, and elements greater than 0 represent the cyclic shift matrix CPM of the Z*Z identity matrix.

7. [Amended according to Rule 26, 10.02.2025] The method according to any one of claims 1-5, characterized in that, When the code rate R of the information bit sequence is 2 / 3, the prototype of the parity check matrix is ​​any one of the following matrices: or, or, Where -1 represents a Z*Z all-zero matrix, 0 represents a Z*Z identity matrix, and elements greater than 0 represent the cyclic shift matrix CPM of the Z*Z identity matrix.

8. [Amended according to Rule 26, 10.02.2025] The method according to any one of claims 1-5, characterized in that, When the code rate R of the information bit sequence is 3 / 4, the prototype of the parity check matrix is ​​any of the following matrices: or, or, or, Where -1 represents a Z*Z all-zero matrix, 0 represents a Z*Z identity matrix, and elements greater than 0 represent the cyclic shift matrix CPM of the Z*Z identity matrix.

9. [Amended according to Rule 26, 10.02.2025] The method according to any one of claims 1-5, characterized in that, When the code rate R of the information bit sequence is 5 / 6, the prototype of the parity check matrix is ​​any one of the following matrices: or, or, or, Where -1 represents a Z*Z all-zero matrix, 0 represents a Z*Z identity matrix, and elements greater than 0 represent the cyclic shift matrix CPM of the Z*Z identity matrix.

10. [Amended according to Rule 26, 10.02.2025] The method according to any one of claims 1-5, characterized in that, When the code rate R of the information bit sequence is 1 / 2, the prototype of the parity check matrix is ​​any of the following matrices: or, Where -1 represents a Z*Z all-zero matrix, 0 represents a Z*Z identity matrix, and elements greater than 0 represent the cyclic shift matrix CPM of the Z*Z identity matrix.

11. [Amended according to Rule 26, 10.02.2025] The method according to any one of claims 1-5, characterized in that, When the code rate R of the information bit sequence is 2 / 3, the prototype of the parity check matrix is ​​any one of the following matrices: or, Where -1 represents a Z*Z all-zero matrix, 0 represents a Z*Z identity matrix, and elements greater than 0 represent the cyclic shift matrix CPM of the Z*Z identity matrix.

12. [Amended according to Rule 26, 10.02.2025] The method according to any one of claims 1-5, characterized in that, When the code rate R of the information bit sequence is 3 / 4, the prototype of the parity check matrix is ​​any of the following matrices: or, Where -1 represents a Z*Z all-zero matrix, 0 represents a Z*Z identity matrix, and elements greater than 0 represent the cyclic shift matrix CPM of the Z*Z identity matrix.

13. [Amended according to Rule 26, 10.02.2025] The method according to any one of claims 1-5, characterized in that, When the code rate R of the information bit sequence is 5 / 6, the prototype of the parity check matrix is ​​any one of the following matrices: or, Where -1 represents a Z*Z all-zero matrix, 0 represents a Z*Z identity matrix, and elements greater than 0 represent the cyclic shift matrix CPM of the Z*Z identity matrix.

14. A communication device, characterized in that, Includes a module for performing the method as described in any one of claims 1-13.

15. A communication device, characterized in that, Includes a processor for performing the method as described in any one of claims 1-13.

16. A communication device, characterized in that, Includes logic circuits and interfaces, wherein the logic circuits and interfaces are coupled; The interface is used for inputting and / or outputting information, and the logic circuit is used for performing the method as described in any one of claims 1-13.

17. A computer-readable storage medium, characterized in that, The computer-readable storage medium is used to store a computer program, which, when executed, performs the method as described in any one of claims 1-13.

18. A computer program product, characterized in that, When the computer program product is executed, the method described in any one of claims 1-13 is performed.

19. A communication system, characterized in that, The communication system includes a first communication device and a second communication device, wherein the first communication device is used to perform the method as described in any one of claims 1, 3-13, and the second communication device is used to perform the method as described in any one of claims 2-13.

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