Array substrate, display panel, and display device

Abstract

The present disclosure provides an array substrate, a display panel, and a display device. The array substrate comprises a first pad arranged in a binding area, and further comprises: a first conductive layer located on a substrate, wherein a first driving signal line is provided in the first conductive layer; a dielectric layer located on the side of the first driving signal line away from the substrate, wherein the dielectric layer is provided with a first opening exposing at least a part of the first driving signal line, and at least a part of the first pad is located in the first opening and is directly connected to the first driving signal line; and a second conductive layer located on the side of the dielectric layer away from the first conductive layer, and at least one third conductive layer located between the dielectric layer and the second conductive layer. The first pad at least comprises the second conductive layer and the second conductive layer is located on the side of the first pad farthest from the dielectric layer, and at least a part of the first pad does not comprise at least one third conductive layer. Therefore, the present disclosure prevents a pad from being damaged in the manufacturing process of the array substrate, and improves the binding efficiency and yield of a subsequent driving chip.

Description

Array substrate, display panel and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on January 9, 2024, with application number 202410033237.3 and invention name "An array substrate, display panel and display device", the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present invention relates to the field of display technology, and in particular to an array substrate, a display panel and a display device. Background Art

[0004] The COP (Chip on Panel, or Chip on Pi, abbreviated as COP) process can effectively reduce the border width of the display device and achieve narrow borders and a high screen-to-body ratio by encapsulating the driver chip (Chip) in the non-display area of ​​the flexible display panel and then directly bending the non-display area of ​​the flexible display panel to the back side of the display panel.

[0005] In the COP packaging process, the driver chip needs to be bonded to the COP bump, or COP pad, located in the non-display area of ​​the display panel. In some display products, the pad is very prone to structural damage during the manufacturing process, resulting in poor subsequent bonding of the driver chip. Summary of the Invention

[0006] The present disclosure provides an array substrate, a display panel, and a display device, which are used to avoid damage to pads during the manufacturing process of the array substrate and improve the binding efficiency and yield of subsequent driver chips.

[0007] According to a first aspect of the present disclosure, an array substrate is provided. The array substrate includes a display area and a binding area located on one side of the display area, wherein the binding area is provided with a first pad, and further includes:

[0008] substrate;

[0009] A first conductive layer is located on the substrate; the first conductive layer includes a first driving signal line;

[0010] a dielectric layer located on a side of the first driving signal line facing away from the substrate; the dielectric layer is provided with a first opening exposing at least a portion of the first driving signal line; at least a portion of the first pad is located within the first opening and is directly connected to the first driving signal line through the first opening; and the remaining portion of the first pad is overlapped with a surface of the dielectric layer surrounding the first opening;

[0011] a second conductive layer, located on a side of the dielectric layer facing away from the first conductive layer;

[0012] at least one third conductive layer, located between the dielectric layer and the second conductive layer;

[0013] The first pads include at least a second conductive layer, with the second conductive layer located on the side of the first pads furthest from the dielectric layer. At least some of the first pads do not include at least one layer of the third conductive layer. This helps reduce the pad height, preventing pad damage during array substrate fabrication and improving subsequent driver chip bonding efficiency and yield.

[0014] In the array substrate provided by the present disclosure, at least one third conductive layer includes a first source-drain metal layer and a second source-drain metal layer arranged in sequence along the direction of the dielectric layer away from the first conductive layer; the second conductive layer is the third source-drain metal layer; the first solder pad includes at least the third source-drain metal layer, and at least part of the first solder pad does not include at least one of the first source-drain metal layer and the second source-drain metal layer.

[0015] In the array substrate provided by the present disclosure, the first pad further includes a second source-drain metal layer, and does not include the first source-drain metal layer.

[0016] In the array substrate provided by the present disclosure, the first conductive layer includes a gate metal layer.

[0017] According to a second aspect of the present disclosure, an array substrate is provided, comprising a display area and a binding area located on one side of the display area, wherein the binding area is provided with a second pad, and further comprising:

[0018] substrate;

[0019] A first conductive layer is located on the substrate; the first conductive layer includes a first driving signal line;

[0020] The dielectric layer is located on a side of the first driving signal line away from the substrate; the dielectric layer is provided with a second opening exposing at least a portion of the first driving signal line; the second pad is located on a side of the dielectric layer away from the first conductive layer;

[0021] The connecting portion has one end located in the second opening and directly connected to the first drive signal line; the other end of the connecting portion is connected to a second pad located on the surface of the dielectric layer; the orthographic projection of the second pad on the dielectric layer does not overlap with the second opening. This helps improve the flatness of the pad placement area, thereby preventing pad damage during array substrate fabrication and improving the subsequent bonding efficiency and yield of the driver chip.

[0022] In the array substrate provided in the present disclosure, the array substrate further includes:

[0023] a second conductive layer, located on a side of the dielectric layer facing away from the first conductive layer;

[0024] at least one third conductive layer, located between the dielectric layer and the second conductive layer;

[0025] The connecting portion includes at least one of the second conductive layer and the third conductive layer; the second pad includes at least the second conductive layer, and the second conductive layer is located on a side of the second pad farthest from the dielectric layer.

[0026] In the array substrate provided in the present disclosure, at least one film layer in the connecting portion and at least one film layer in the second solder pad connected to the connecting portion are located on the same layer, and the film layers in the connecting portion and the film layers in the second solder pad connected to the connecting portion that are located on the same layer are connected to each other.

[0027] In the array substrate provided in the present disclosure, at least one third conductive layer includes a first source-drain metal layer and a second source-drain metal layer sequentially arranged along the direction of the dielectric layer away from the first conductive layer; the second conductive layer is the third source-drain metal layer.

[0028] In the array substrate provided by the present disclosure, the connecting portion includes a first source-drain metal layer; and the second pad further includes a first source-drain metal layer.

[0029] In the array substrate provided by the present disclosure, the second pad further includes a second source-drain metal layer.

[0030] In the array substrate provided by the present disclosure, the connecting portion further includes a second source-drain metal layer and a third source-drain metal layer.

[0031] In the array substrate provided by the present disclosure, the second pad further includes a second source-drain metal layer, and does not include the first source-drain metal layer; the connecting portion includes the second source-drain metal layer.

[0032] In the array substrate provided by the present disclosure, the connecting portion further includes a first source-drain metal layer and a third source-drain metal layer.

[0033] In the array substrate provided in the present disclosure, the array substrate further includes:

[0034] The passivation layer is located between the first source-drain metal layer and the second source-drain metal layer; the passivation layer is provided with a third opening exposing the first source-drain metal layer.

[0035] In the array substrate provided by the present disclosure, the first conductive layer includes a gate metal layer.

[0036] According to a third aspect of the present disclosure, a display panel is provided. The display panel includes a driver chip and any one of the above array substrates; the driver chip is electrically connected to a pad on the array substrate.

[0037] According to a fourth aspect of the present disclosure, a display device is provided, comprising any one of the display panels described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the embodiments of the present invention. Obviously, the drawings introduced below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0039] FIG1 is a microscopic structure diagram of a pad in the related art;

[0040] FIG2 is a schematic top view of the structure of an array substrate provided in an embodiment of the present disclosure;

[0041] FIG3 is a schematic diagram of a cross-sectional structure of an array substrate provided in an embodiment of the present disclosure;

[0042] FIG4 is a schematic diagram of a pad manufacturing process in the related art;

[0043] FIG5 is a schematic diagram of a manufacturing process of an array substrate according to an embodiment of the present disclosure;

[0044] FIG6 is a schematic diagram of a manufacturing process of an array substrate in some technical routes;

[0045] FIG7 is an enlarged schematic diagram of a top view of the array substrate provided in an embodiment of the present disclosure;

[0046] FIG8 is a second schematic diagram of a cross-sectional structure provided in an embodiment of the present disclosure;

[0047] FIG9 is a second schematic diagram of a manufacturing process of an array substrate according to an embodiment of the present disclosure;

[0048] FIG10 is a third schematic diagram of a cross-sectional structure of an array substrate provided in an embodiment of the present disclosure;

[0049] FIG. 11 is a third schematic diagram of the manufacturing process of the array substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention will be further described below with reference to the accompanying drawings and examples. However, the example embodiments can be implemented in various forms and should not be understood as being limited to the embodiments described herein; on the contrary, these embodiments are provided to make the present invention more comprehensive and complete, and to fully convey the concepts of the example embodiments to those skilled in the art. The same figure marks in the figures represent the same or similar structures, and their repeated descriptions will be omitted. The words expressing position and direction described in the present invention are all explained with reference to the accompanying drawings as examples, but changes can be made as needed, and the changes made are all included in the scope of protection of the present invention. The drawings of the present invention are only used to illustrate the relative position relationship and do not represent the true proportion.

[0051] FIG1 is a microscopic structure diagram of a pad in related art.

[0052] The COP (Chip on Panel, or Chip on Pi, abbreviated as COP) process can effectively reduce the border width of the display device and achieve narrow borders and a high screen-to-body ratio by encapsulating the driver chip (Chip) in the non-display area of ​​the flexible display panel and then directly bending the non-display area of ​​the flexible display panel to the back side of the display panel.

[0053] During the COP packaging process, the driver chip needs to be bonded to the COP bump, or COP pad, located in the non-display area of ​​the display panel. As shown in Figure 1, taking an array substrate with a 3SD structure (including a first source / drain metal layer SD1, a second source / drain metal layer SD2, and a third source / drain metal layer SD3) as an example, the pad is very susceptible to structural damage such as notches during the manufacturing process. This makes it difficult to subsequently bond the driver chip to the pad, resulting in low production efficiency and yield.

[0054] In view of this, the present disclosure provides an array substrate for reducing structural damage generated during the pad manufacturing process, thereby improving the efficiency and yield of the subsequent driver chip binding process.

[0055] FIG2 is a schematic diagram of a top view of the array substrate provided in an embodiment of the present disclosure; FIG3 is one of the schematic diagrams of a cross-sectional structure of the array substrate provided in an embodiment of the present disclosure.

[0056] In the embodiment of the present disclosure, as shown in Figures 2 and 3 , the array substrate includes a plurality of pads B. The pads B are used to bind a driver chip so as to provide a driving signal to the array substrate through the driver chip.

[0057] In a specific implementation, the array substrate may include a display area AA and a non-display area FA.

[0058] The display area AA of the array substrate is used to set light-emitting devices to form a display panel. A pixel circuit is set in the display area AA of the array substrate. When forming a display panel, the light-emitting device is electrically connected to the pixel circuit of the array substrate, and the light-emitting device emits light under the drive of the pixel circuit to display an image. For example, the array substrate can be used to form an organic light emitting diode (OLED) display panel, wherein the pixel circuit can be a thin film transistor (TFT) pixel circuit. As shown in Figure 3, a TFT pixel circuit can include a thin film transistor T and a capacitor to form a 1T1C pixel circuit. In specific implementation, a TFT pixel circuit can include multiple thin film transistors T to form a pixel circuit structure such as 2T1C, 4T1C, 6T1C or 7T1C, which is not limited here.

[0059] A binding area FA2 is provided within the non-display area FA of the array substrate, and pads B are disposed within the binding area FA2. The driver chip is bonded to the non-display area FA of the array substrate via pads B, avoiding occupying the display area and improving the integrity of the display area. As shown in Figure 2, when applied to a flexible display panel, such as a flexible OLED display panel, the non-display area FA also includes a bending area FA1, which is located between the display area AA and the binding area FA2. Pads B are disposed within the binding area FA2. By bending the bending area FA1, the binding area FA2 can be folded toward the back of the display panel, thereby reducing the bezel size and increasing the screen-to-body ratio of the display device.

[0060] From the perspective of the cross-sectional structure of the array substrate, as shown in FIG3 , the array substrate includes: a substrate SUB, a first conductive layer 1 , a dielectric layer 4 , a second conductive layer 2 and a third conductive layer 3 .

[0061] The substrate SUB is located at the bottom of the array substrate and is used to support and carry the film layer provided on the substrate SUB. In some embodiments, the substrate SUB may be a flexible material. The array substrate can be used to make a flexible display panel to realize functions such as curved display, folding display or sliding display. The substrate SUB may be a single-layer structure or a multi-layer structure. For example, when the substrate SUB is a single-layer structure, the material of the substrate SUB may be any one of polyimide (PI), polycarbonate (PC) or polyvinyl chloride (PVC). When the substrate SUB is a multi-layer structure, it may include at least one cross-stacked PI layer and at least one barrier layer, wherein the material of the barrier layer may be a thin layer of silicon oxide (SiO), silicon nitride (SiN) or silicon oxynitride (SiON), etc., which are not limited here. In some embodiments, the material of the substrate SUB may also be a hard material, so that it can be used to make a rigid display panel, which is not limited here.

[0062] The first conductive layer 1 is located on the substrate SUB. The first conductive layer 1 is made of a conductive material such as metal. A first drive signal line 10 is provided in the first conductive layer 1. As shown in Figures 2 and 3, the first drive signal line 10 is provided in the non-display area FA of the array substrate. One end of the first drive signal line 10 is electrically connected to the pad B for transmitting the drive signal provided by the driver chip bound to the pad B. A plurality of second drive signal lines 20 are also provided in the display area AA of the array substrate. The other end of the first drive signal line 10 is electrically connected to the second drive signal line 20 provided in the display area AA. The second drive signal line 20 is also electrically connected to the pixel circuit provided in the display area AA (not shown in the figure). In the display panel, the drive signal provided by the driver chip is transmitted to the pixel circuit via the first drive signal line 10 and the second drive signal line 20, thereby driving the light-emitting device provided in the display area AA of the array substrate to emit light to display an image. In specific implementations, the first drive signal line 10 can be directly connected to the second drive signal line 20, or can be connected via other circuits, which is not limited here. In some embodiments, the first conductive layer 1 is directly provided on the substrate SUB. In some embodiments, a buffer layer (Buffer) may be further provided between the first conductive layer 1 and the substrate SUB, which is not limited here.

[0063] The dielectric layer 4 is located on the side of the first drive signal line 10 facing away from the substrate SUB. The dielectric layer 4 is made of an insulating material and provides insulation and protection for the conductive layer in the array substrate. The dielectric layer 4 can be a single-layer structure formed by a single insulating layer, or a laminated structure formed by stacking multiple insulating layers, without limitation.

[0064] As shown in FIG3 , in the non-display area FA of the array substrate, the dielectric layer 4 is provided with a first opening K1 that exposes at least a portion of the first drive signal line 10. The plurality of pads B include a first pad B1. At least a portion of the first pad B1 is located within the first opening K1. The portion of the first pad B1 located within the first opening K1 directly contacts and connects to the first drive signal line 10 exposed by the first opening K1 through the first opening K1. The remaining portion of the first pad B overlaps the surface of the dielectric layer 4 surrounding the first opening K1.

[0065] The second conductive layer 2 is located on the side of the dielectric layer 4 facing away from the first conductive layer 1. The third conductive layer 3 is located between the dielectric layer 4 and the second conductive layer 2. The array substrate provided in the embodiment of the present disclosure may include one or more third conductive layers 3.

[0066] In the display area AA of the array substrate, the second conductive layer 2 and the third conductive layer 3 are used to form structures such as the second drive signal line 20 and / or the pixel circuit. In the display area AA of the array substrate, the second drive signal line and / or the pixel circuit are dispersed across multiple conductive layers. This allows the orthographic projections of the second drive signal line and / or the pixel circuit located on different conductive layers on the substrate SUB to overlap, thereby facilitating a reduction in the area in which a single pixel circuit is provided, increasing the number of pixel circuits provided per unit area, and further improving the resolution of the display panel.

[0067] In the non-display area FA of the array substrate, at least a portion of the second conductive layer 2 and the third conductive layer 3 are used to form the pad B. In the disclosed embodiment, the first pad B1 includes at least the second conductive layer 2, and the second conductive layer 2 is located on the side of the first pad B1 farthest from the dielectric layer 4, that is, the second conductive layer 2 is located at the outermost layer of the pad B in the direction away from the substrate SUB. At least a portion of the first pad B1 does not include at least one of the third conductive layers 3 located between the first conductive layer 1 and the second conductive layer 2. For example, a portion of the first pad may include only the second conductive layer 2 but not the third conductive layer 3, thereby facilitating a reduction in the height of the portion of the first pad.

[0068] FIG4 is a schematic diagram of a pad manufacturing process in related art.

[0069] In the embodiment of the present disclosure, by reducing the height of the first pad, the probability of structural damage occurring on the pad surface can be reduced, thereby improving the yield rate in the subsequent process of binding the driver chip.

[0070] For example, in a TFT array substrate with a 3SD structure (including a first source-drain metal layer, a second source-drain metal layer and a third source-drain metal layer stacked in sequence), it includes a first conductive layer 1 and a second conductive layer 2, wherein the first conductive layer is a gate metal layer, and the second conductive layer is a third source-drain metal layer, and two third conductive layers 3 are arranged between the first conductive layer 1 and the second conductive layer 2, and the two third conductive layers 3 are respectively the first source-drain metal layer and the second source-drain metal layer.

[0071] In the 3SD structure TFT array substrate of the related art, the pad is generally composed of a first source-drain metal layer, a second source-drain metal layer, and a third source-drain metal layer. Specifically, as shown in FIG4 , a pad B is produced by opening the dielectric layer 4 to expose the first drive signal line 10, and then depositing two third conductive layers 3 and one second conductive layer 2 in the opening in sequence. The two third conductive layers 3 and one second conductive layer 2 are all used to form the structure of the pad B. Each conductive layer needs to be etched to form a pattern of the pad B. When etching the second conductive layer 2, as shown in FIG4 , a photoresist layer PR needs to be coated on the surface of the second conductive layer 2, and then the second conductive layer 2 is patterned through processes such as exposure, development, and etching to ultimately form the pattern of the pad B.

[0072] During the research process, the inventors of the present disclosure discovered that since the second conductive layer 2 is formed on the two patterned third conductive layers 3, the two third conductive layers 3 form a higher step difference at the edge of the pad B. As shown in FIG4 , in the area near the edge of the pad B, the height of the second conductive layer 2 in the area where the pad B is located is significantly higher than the height of the second conductive layer 2 in the area not where the pad B is located, and in the middle area of ​​the pad B, due to the presence of the opening, the height of the second conductive layer 2 in this area is lower. As a result, when the photoresist layer PR is coated, the photoresist flows to the position where the height of the second conductive layer 2 is lower, resulting in the thickness of the photoresist layer PR being thinner at the position where the height of the second conductive layer 2 is higher. For example, when the designed thickness a (the thickness at the position indicated by the dotted line) of the photoresist layer PR is 1.5 μm, the thickness of the photoresist layer PR actually formed at the position where the height of the second conductive layer 2 is higher is significantly thinner than the designed thickness, and the thinned thickness b is approximately 0.2 μm to 0.3 μm. Therefore, when etching the second conductive layer 2, at a position with a higher height of the second conductive layer 2, due to the thin thickness of the photoresist layer PR, the photoresist located directly above this position is completely consumed during the etching process, exposing the second conductive layer 2 (the surface of the pad B) that does not need to be etched, causing over-etching on the surface of the pad B, thereby destroying the surface structure of the pad B and affecting the binding of the subsequent driver chip.

[0073] In the disclosed embodiment, as shown in FIG3 , at least a portion of the first pad B1 excludes at least one of the third conductive layers 3 located between the first conductive layer 1 and the second conductive layer 2. For example, when forming the first pad B1, the portion of the at least one third conductive layer 3 located within the first pad B1's location region can be etched away. This allows the difference in height between the second conductive layer located within the first pad B1's location region and the second conductive layer located outside the first pad B1's location region to be reduced at the edge of the first pad B1 when forming the second conductive layer. This prevents the photoresist from flowing laterally at the edge of the first pad B1, causing the photoresist layer to be too thin. This ensures that the photoresist layer protects the second conductive layer 2 within the first pad B1's location region throughout the etching process of the second conductive layer 2, preventing damage to the first pad B1 structure caused by overetching of the second conductive layer 2. The location region of the first pad B1 specifically refers to the area covered by the orthographic projection of the first pad B1, which will not be further described in detail.

[0074] In some embodiments, all first pads B1 can be set to include the second conductive layer and not include at least one layer of the third conductive layer, or part of the first pads can be set to include the second conductive layer and not include at least one layer of the third conductive layer. As long as the probability of pad damage problem can be reduced and the efficiency and yield of driver chip binding can be improved, no limitation is made here.

[0075] In some embodiments, all pads B on the array substrate may be set as first pads B1. In some embodiments, only some of all pads B on the array substrate may be set as first pads B1, which is not limited here.

[0076] In some embodiments, the array substrate may be a thin-film transistor (TFT) array substrate. TFT array substrates utilize TFTs and capacitors to form pixel circuits. The second conductive layer 2 and the third conductive layer 3 are both source / drain metal layers, and the first conductive layer 1 is a gate metal layer. In the non-display area FA of the array substrate, the source / drain metal layer can be used to form the structure of the pad B. In the display area AA of the array substrate, the source / drain metal layer can be used to form the source and drain electrodes of the TFTs, as well as to arrange the routing of a portion of the second drive signal lines 20. For example, the routing of the second drive signal lines 20 arranged in the source / drain metal layer may include power signal lines, data signal lines, initialization signal lines, and the like. By distributing a portion of the second drive signal lines 20 in the second and third conductive layers, the orthographic projections of the power signal lines, data signal lines, initialization signal lines, and the like located on different conductive layers can overlap on the substrate SUB, thereby reducing the area of ​​the individual pixel circuit configuration region, increasing the number of pixel circuits provided per unit area, and further improving the resolution of the display panel. In the non-display area FA of the array substrate, the gate metal layer can be used to form the first drive signal lines 10. In the display area AA of the array substrate, the gate metal layer can be used to form the gate of the thin film transistor, as well as part of the second drive signal line, such as the scanning signal line and other structures, which are not limited here. In a specific implementation, the first conductive layer 1 may include a gate metal layer, or multiple gate metal layers. For example, as shown in Figure 3, the first conductive layer 1 includes a first gate metal layer G1 and a second gate metal layer G2, wherein the first drive signal line 10 is arranged in the first gate metal layer G1, and the dielectric layer 4 includes a second gate insulating layer GI2 and an interlayer dielectric layer ILD. In a specific implementation, the first drive signal line 10 can be arranged separately in the first gate metal layer G1 or the second gate metal layer G2, or simultaneously in the first gate metal layer G1 and the second gate metal layer G2, which are not limited here.

[0077] In some embodiments, the array substrate provided by the embodiments of the present disclosure can be used to manufacture OLED display panels, thereby solving the problem of poor binding of driver chips on OLED display panels. As shown in Figure 3, taking a top-gate TFT array substrate as an example, in which the first conductive layer includes a first gate metal layer G1 and a second gate metal layer G2, the second conductive layer 2 is a third source / drain metal layer SD3, and multiple third conductive layers 3 are first source / drain metal layers SD1 and second source / drain metal layers SD2, the array substrate further includes:

[0078] The active layer A is located between the first conductive layer 1 and the substrate SUB and is used to form an active region of the thin film transistor T;

[0079] A first gate insulating layer GI1 is located between the active layer A and the first gate metal layer G1;

[0080] A second gate insulating layer GI2 is located between the first gate metal layer G1 and the second gate metal layer G2;

[0081] An interlayer dielectric layer ILD is located between the second gate insulating layer GI2 and the first source / drain metal layer SD1; a portion of the patterned first source / drain metal layer SD1 is connected to the active layer A through vias that penetrate the interlayer dielectric layer ILD, the second gate insulating layer GI2, and the first gate insulating layer GI1 and expose the active layer A, thereby forming the source and drain of the thin film transistor T;

[0082] A passivation layer is located between the first source-drain metal layer SD1 and the second source-drain metal layer SD2; a portion of the pattern in the patterned second source-drain metal layer SD2 is connected to the drain electrode of the thin-film transistor T through a via hole penetrating the passivation layer, for subsequent connection between the anode of the OLED light-emitting device and the thin-film transistor T;

[0083] A first insulating layer is located between the second source / drain metal layer SD2 and the third source / drain metal layer SD3; a portion of the patterned third source / drain metal layer SD3 is connected to a portion of the patterned second source / drain metal layer SD2 via a via hole penetrating the first insulating layer, for subsequently connecting the anode of the OLED light-emitting device to the thin film transistor T;

[0084] a second insulating layer, located on a side of the third source / drain metal layer SD3 facing away from the first insulating layer;

[0085] an anode layer AND located on a side of the second insulating layer facing away from the third source / drain metal layer SD3; the anode layer AND is provided with an anode of the OLED light-emitting device, which is connected to a portion of the patterned third source / drain metal layer SD3 through a via hole penetrating the second insulating layer, and further connected to the thin film transistor T;

[0086] The pixel definition layer PDL is located on the side of the anode layer AND away from the second insulating layer; the pixel definition layer PDL is provided with an opening for exposing the anode of the OLED light emitting device, so as to form a complete OLED light emitting tube device.

[0087] It should be noted that the array substrate provided in the embodiment of the present disclosure is not limited to the structure shown in Figure 3. During specific implementation, the specific structure of the array substrate provided in the embodiment of the present disclosure can be adaptively adjusted according to the specific structure of the OLED display panel. For example, in some embodiments, only the first gate metal layer G1 can be provided in the array substrate without providing the second gate metal layer G2. In some embodiments, only two source and drain metal layers can be provided in the array substrate, wherein one source and drain metal layer is the second conductive layer 2, and the other source and drain metal layer is the third conductive layer 3. In some embodiments, the TFT in the array substrate can also adopt a bottom gate structure, which is not limited here. The improvement of the array substrate in the embodiment of the present disclosure mainly relates to the structure of the pad located in the non-display area FA of the array substrate. Unless otherwise specified, the array substrate provided in the embodiment of the present disclosure does not change in other structures compared to the array substrate in the related art. Therefore, the specific structure of the OLED array substrate provided in the embodiment of the present disclosure can refer to the OLED display panel in the related art and will not be repeated here.

[0088] In some embodiments, as shown in FIG3 , the TFT array substrate adopts a 3SD structure. Three source / drain metal layers are provided in the 3SD array substrate, namely, a first source / drain metal layer SD1, a second source / drain metal layer SD2, and a third source / drain metal layer SD3. The third conductive layer 3 includes the first source / drain metal layer SD1 and the second source / drain metal layer SD2, arranged sequentially along the dielectric layer 4 in a direction away from the first conductive layer 1. The second conductive layer 2 is the third source / drain metal layer SD3. The first pad B1 includes at least the third source / drain metal layer SD3, and at least a portion of the first pad B1 does not include at least one of the first source / drain metal layer SD1 and the second source / drain metal layer SD2. For example, in some embodiments, as shown in FIG3 , the first pad B1 includes only the third source / drain metal layer SD3 but does not include the first source / drain metal layer SD1 and the second source / drain metal layer SD2. For example, in some embodiments, the first pad B1 includes both the third source / drain metal layer SD3 and the second source / drain metal layer SD2, but does not include the first source / drain metal layer SD1.

[0089] In the embodiment of the present disclosure, the TFT array substrate may be a low-temperature polysilicon (LTPS) TFT array substrate, an oxide TFT array substrate, or a low-temperature polycrystalline oxide (LTPO) array substrate, which is not limited here.

[0090] FIG. 5 is a schematic diagram of a manufacturing process of an array substrate according to an embodiment of the present disclosure.

[0091] In some embodiments, the array substrate is an LTPS TFT array substrate. The active layer of the LTPS TFT array substrate is made of low-temperature polysilicon. Low-temperature polysilicon is relatively stable and less affected by light. When manufacturing TFTs, it is generally not necessary to form a back shield metal (BSM) below the active area of ​​the TFT.

[0092] In some embodiments, the first pad B1 on the LTPS TFT array substrate includes a second source / drain metal layer SD2 and a third source / drain metal layer SD3, but does not include the first source / drain metal layer SD1. As shown in FIG5 , the manufacturing process of the LTPS TFT array substrate may include the following steps:

[0093] 1. A first via hole H1 is formed in the dielectric layer 4 to expose the active layer A. A first source / drain metal layer SD1 is then deposited on the surface of the dielectric layer 4 and in the first via hole H1. The first source / drain metal layer SD1 is patterned to form a source S and a drain D of the thin film transistor and a portion of the second drive signal line. The first source / drain metal layer SD1 covering the area where the first pad is located is removed.

[0094] 2. A first opening K1 is formed in the dielectric layer 4 to expose the first drive signal line 10. In some embodiments, as shown in FIG5 , before forming the first opening K1, a passivation layer PVX covering the dielectric layer 4 and the first metal layer SD1 may be deposited first, and then the passivation layer PVX is etched to form a second via H2 exposing the drain electrode D. At the same time, the passivation layer PVX covering the area where the first pad is provided is removed. After the passivation layer PVX is etched, the first opening K1 is formed. In some embodiments, after the first source / drain metal layer SD1 is patterned, the first opening K1 may be formed first, and then the passivation layer PVX may be formed and etched, which is not limited here.

[0095] 3. After forming the first opening K1, a second source-drain metal layer SD2 is deposited in sequence, and the second source-drain metal layer SD2 is patterned to form a portion connected to the drain electrode D of the thin film transistor, a portion of the second drive signal line, and a first conductive film layer B11 of the first pad; a first insulating layer is deposited on the side of the second source-drain metal layer SD2 away from the substrate SUB, and the first insulating layer is etched to form a plurality of third vias H3 exposing the second source-drain metal layer SD2, and at the same time, a portion of the first insulating layer located in the setting area of ​​the first pad is removed; a third source-drain metal layer SD3 is deposited on the side of the first insulating layer away from the second source-drain metal layer SD2, and the third source-drain metal layer SD3 is patterned to form a second conductive film layer B12 connected to the second source-drain metal layer SD2, a portion of the second drive signal line, and the first pad, thereby forming the first pad B1.

[0096] 4. After the first pad B1 is formed, the manufacturing process of the subsequent film layers of the array substrate can refer to the manufacturing process of the array substrate in the related art, which will not be described in detail here.

[0097] In the embodiment shown in FIG5 , the portion of the first insulating layer located within the area where the first pad B1 is located is removed simultaneously with the process of forming the third via H3 in the first insulating layer. This saves the need for a subsequent separate etching process of the first insulating layer located within the area where the first pad B1 is located. Within the area where the first pad B1 is located, the third source / drain metal layer SD3 is deposited and directly overlies the surface of the second source / drain metal layer SD2. During the patterning process of the third source / drain metal layer SD3, the third source / drain metal layer SD3 overlying the surface of the first conductive film layer B11 of the first pad B1 is not etched away, resulting in the first pad B1 comprising both the second source / drain metal layer SD2 and the third source / drain metal layer SD3. This is because during the current production of the array substrate, the first source-drain metal layer SD1, the second source-drain metal layer SD2 and the third source-drain metal layer SD3 are usually produced using the same or similar materials. For example, the first source-drain metal layer SD1, the second source-drain metal layer SD2 and the third source-drain metal layer SD3 usually all use a three-layer structure of Ti / Al / Ti, and the etching selectivity during the etching process is relatively low. Therefore, during the production process, the third source-drain metal layer SD3 covering the surface of the first conductive film layer B11 is retained to avoid over-etching the first conductive film layer B11, thereby protecting the structure of the first pad B1.

[0098] 3 and 4 , in the related art, when manufacturing an array substrate using a 3SD structure, a first opening is typically formed before depositing the first source / drain metal layer SD1, penetrating the interlayer insulating layer ILD and the second gate insulating layer GI2 and exposing the first drive signal line 10. The first source / drain metal layer SD1, the second source / drain metal layer SD2, and the third source / drain metal layer SD3 are then sequentially deposited within the first opening. In the embodiment shown in FIG5 , however, the fabrication step of the first opening K1 is simply performed after the patterning step of the first source / drain metal layer SD1. This reduces the number of conductive film layers included in the first pad B1, thereby lowering the height of the first pad B1, without increasing the number of masks used in the fabrication process, thus helping to control fabrication costs. In addition, the step of making the first opening K1 is arranged after the patterning step of the first source-drain metal layer SD1. Compared with opening the opening to expose the first drive signal line 10 before depositing the first source-drain metal layer SD1, when depositing the first source-drain metal layer SD1, the first source-drain metal layer SD1 will not contact the first drive signal line 10, and the first drive signal line 10 can be avoided from being etched when the first source-drain metal layer SD1 is patterned, thereby avoiding affecting the surface structure of the pad.

[0099] FIG6 is a schematic diagram of a manufacturing process of an array substrate in a technical route.

[0100] For example, during the development of the 3SD structure array substrate provided in the present disclosure, the inventors also developed other technical routes to reduce the height of the first pad. For example, the first pad is configured to include only the first source / drain metal layer SD1 and the second source / drain metal layer SD2, but not the third source / drain metal layer SD3. In a specific implementation, after forming the conductive film layer of the third source / drain metal layer SD3, the portion of the third source / drain metal layer SD3 that overlaps with the first pad's location is removed through an etching process, thereby leaving the side of the first pad farthest from the dielectric layer as the second source / drain metal layer SD2. In a specific manufacturing process, as shown in FIG6 , before depositing the first source / drain metal layer SD1, a first opening K1 can be opened that penetrates the interlayer insulating layer ILD and the second gate insulating layer GI2 and exposes the first drive signal line 10. Subsequently, the first source / drain metal layer SD1, the passivation layer, the second source / drain metal layer SD2, and the first insulating layer IS are sequentially formed, wherein portions of the first source / drain metal layer SD1 and the second source / drain metal layer SD2 constitute the first pad B1. When etching the first insulating layer IS to form the third via H3 exposing the second source / drain metal layer SD2, a portion of the first insulating layer IS covering the surface of the first pad B1 is retained to insulate the third source / drain metal layer SD3 from the second source / drain metal layer SD2 on the surface of the first pad B1. This prevents direct contact between the third source / drain metal layer SD3 and the second source / drain metal layer SD2 during subsequent deposition of the third source / drain metal layer SD3, which would be difficult to etch due to the low etching selectivity between the third source / drain metal layer SD3 and the second source / drain metal layer SD2. After forming the third via H3, the third source / drain metal layer SD3 is deposited and then patterned to form a portion of the third via H3 connecting to the second source / drain metal layer SD2 and a portion of the second drive signal line. Simultaneously, the third source / drain metal layer SD3 covering the area where the first pad B1 is located is removed, thereby leaving the first pad B1 comprised only of the first source / drain metal layer SD1 and the second source / drain metal layer SD2. After the third source / drain metal layer SD3 undergoes the patterning process, a mask is required to remove the first insulating layer IS located in the area where the first pad B1 is located, thereby exposing the first pad B1. Therefore, the array substrate structure shown in FIG6 requires an additional masking process during fabrication compared to the embodiment shown in FIG5 , which is detrimental to cost control.

[0101] It can be understood that in the embodiment of the present disclosure, the second conductive layer and the third conductive layer are usually made of the same or similar materials. Therefore, in the embodiment of the present disclosure, the height of the pad is reduced by reducing the number of the third conductive layer located between the second conductive layer and the first conductive layer. Compared with etching the second conductive layer to reduce the height of the pad, this is beneficial to ensuring the structural integrity of the pad and controlling costs.

[0102] In some embodiments, the first pad B1 includes only the third source / drain metal layer SD3. During the fabrication of the array substrate, the step of fabricating the first opening K1 can be performed after the step of patterning the second source / drain metal layer SD2. When patterning the first source / drain metal layer SD1, the first source / drain metal layer SD1 covering the area where the first pad B1 is located is removed. When patterning the second source / drain metal layer SD2, the second source / drain metal layer SD2 covering the area where the first pad B1 is located is removed. Then, the first opening K1 is formed in the dielectric layer 4 to expose the first drive signal line 10. When patterning the third source / drain metal layer SD3, the portion of the third source / drain metal layer SD3 located within the area where the first pad B1 is located is retained. As shown in FIG. 3 , the first pad B1 includes only the third source / drain metal layer SD3, further reducing the thickness of the first pad B1. In the embodiment shown in FIG. 3 , during the fabrication of the array substrate, the step of fabricating the first opening K1 is performed only after the step of patterning the second source / drain metal layer SD2. This avoids increasing the number of masks during the fabrication process, facilitating cost control.

[0103] In the embodiment of the present disclosure, the first pad is a pad that is at least partially disposed in the first opening and is directly connected to the first drive signal line through the first opening. Depending on the actual situation, all pads on the array substrate may be set as first pads, or some may be set as first pads, which is not limited here. The array substrate may include multiple first pads, and the film layer structure between each first pad may be the same or different. For example, in some embodiments, all first pads may be set to include only the third source-drain metal layer. In some embodiments, some first pads may include the second source-drain metal layer and the third source-drain metal layer, and not include the first source-drain metal layer, and the remaining first pads may include only the third source-drain metal layer. In some embodiments, some first pads may include the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer, some first pads may include the second source-drain metal layer and the third source-drain metal layer, and not include the first source-drain metal layer, and the remaining first pads may include only the third source-drain metal layer. The specific configuration of the first pad is not limited here as long as it meets the effect of reducing the probability of pad damage and improving the efficiency and yield of driver chip binding.

[0104] In some embodiments, the array substrate is an oxide TFT array substrate or an LTPO TFT array substrate. The oxide TFT array substrate or the LTPO TFT array substrate includes oxide TFTs. Oxide TFTs usually use oxide semiconductors to form the active layer of the TFT. Oxide semiconductors are unstable under light conditions. Therefore, when manufacturing oxide TFTs, it is usually necessary to set a BSM under the TFT active area. In specific implementation, when manufacturing the oxide TFT array substrate or the LTPO TFT array substrate provided in the embodiment of the present disclosure, reference can be made to the manufacturing process of the oxide TFT array substrate or the LTPO TFT array substrate in the related art, and combined with the manufacturing process of the LTPS TFT array substrate in the aforementioned embodiment of the present disclosure, the manufacturing steps of the oxide TFT array substrate or the LTPO TFT array substrate can be adaptively adjusted, which will not be elaborated here.

[0105] In the embodiments shown in Figures 3 and 5 of the present disclosure, the structure of the array substrate is described by taking the array substrate used to form an OLED display panel as an example. In specific implementation, the array substrate provided by the embodiment of the present disclosure can also be used to form other types of display panels. For example, in some embodiments, the array substrate provided by the embodiment of the present disclosure can also be used to form a quantum dot light emitting diode (Quantum Dot Light Emitting Diode, referred to as QD LED) display panel or a Micro LED (Micro Light Emitinng Diode, referred to as Micro LED) display panel, etc. The structure of the array substrate used in the quantum dot light emitting diode display panel is similar to the structure of the array substrate in the OLED display panel, and will not be described in detail here. The Micro LED display panel is usually manufactured by bonding the Micro LED chip to the array substrate, so it is necessary to set a cathode and anode for bonding the Micro LED chip on the array substrate. In specific implementation, the array substrate structure of the Micro LED display panel in the related art can be adjusted, and will not be described in detail here.

[0106] In the embodiments shown in Figures 3 and 5 of the present disclosure, the array substrate is a TFT array substrate. In specific implementations, the array substrate provided in the embodiments of the present disclosure may also be other types of array substrates. By adopting the structure of the array substrate provided in the embodiments of the present disclosure, the probability of pad damage is reduced, thereby improving the efficiency and yield of driver chip bonding. This is not limited here.

[0107] FIG7 is an enlarged schematic diagram of a top view of the array substrate provided in an embodiment of the present disclosure; FIG8 is a second schematic diagram of a cross-sectional structure provided in an embodiment of the present disclosure.

[0108] The present disclosure also provides another array substrate. In an embodiment of the present disclosure, as shown in FIG2 , the array substrate includes a plurality of pads B. The pads B are used to bind a driver chip so as to provide a driving signal to the array substrate through the driver chip.

[0109] In a specific implementation, the array substrate may include a display area AA and a non-display area FA.

[0110] The display area AA of the array substrate is used to set light-emitting devices to form a display panel. A pixel circuit is set in the display area AA of the array substrate. When forming a display panel, the light-emitting device is electrically connected to the pixel circuit of the array substrate, and the light-emitting device emits light under the drive of the pixel circuit to display an image. For example, the array substrate can be used to form an organic light emitting diode (OLED) display panel, wherein the pixel circuit can be a thin film transistor (TFT) pixel circuit. As shown in Figure 8, a TFT pixel circuit can include a thin film transistor T and a capacitor to form a 1T1C pixel circuit. In specific implementation, a TFT pixel circuit can include multiple thin film transistors T to form a pixel circuit structure such as 2T1C, 4T1C, 6T1C or 7T1C, which is not limited here.

[0111] A binding area FA2 is provided within the non-display area FA of the array substrate, and pads B are disposed within the binding area FA2. The driver chip is bonded to the non-display area FA of the array substrate via pads B, avoiding occupying the display area and improving the integrity of the display area. As shown in Figure 2, when applied to a flexible display panel, such as a flexible OLED display panel, the non-display area FA also includes a bending area FA1, which is located between the display area AA and the binding area FA2. Pads B are disposed within the binding area FA2. By bending the bending area FA1, the binding area FA2 can be folded toward the back of the display panel, thereby reducing the bezel size and increasing the screen-to-body ratio of the display device.

[0112] From the cross-sectional structure of the array substrate, as shown in FIG7 and FIG8 , where FIG8 is a cross-sectional view along section line AA of FIG7 , the array substrate includes: a substrate SUB, a first conductive layer 1 , a dielectric layer 4 , a connecting portion C and a second pad B2 .

[0113] The substrate SUB is located at the bottom of the array substrate and is used to support and carry the film layer provided on the substrate SUB. In some embodiments, the substrate SUB may be a flexible material. The array substrate can be used to make a flexible display panel to realize functions such as curved display, folding display or sliding display. The substrate SUB may be a single-layer structure or a multi-layer structure. For example, when the substrate SUB is a single-layer structure, the material of the substrate SUB may be any one of polyimide (PI), polycarbonate (PC) or polyvinyl chloride (PVC). When the substrate SUB is a multi-layer structure, it may include at least one cross-stacked PI layer and at least one barrier layer, wherein the material of the barrier layer may be a thin layer of silicon oxide (SiO), silicon nitride (SiN) or silicon oxynitride (SiON), etc., which are not limited here. In some embodiments, the material of the substrate SUB may also be a hard material, so that it can be used to make a rigid display panel, which is not limited here.

[0114] The first conductive layer 1 is located on the substrate SUB. The first conductive layer 1 is made of a conductive material such as metal. A first drive signal line 10 is provided in the first conductive layer 1. As shown in Figures 2 and 8, the first drive signal line 10 is provided in the non-display area FA of the array substrate. One end of the first drive signal line 10 is electrically connected to the pad B for transmitting the drive signal provided by the driver chip bound to the pad B. A plurality of second drive signal lines 20 are also provided in the display area AA of the array substrate. The other end of the first drive signal line 10 is electrically connected to the second drive signal line 20 provided in the display area AA. The second drive signal line 20 is also electrically connected to the pixel circuit provided in the display area AA (not shown in the figure). In the display panel, the drive signal provided by the driver chip is transmitted to the pixel circuit via the first drive signal line 10 and the second drive signal line 20, thereby driving the light-emitting device provided in the display area AA of the array substrate to emit light to display an image. In specific implementations, the first drive signal line 10 can be directly connected to the second drive signal line 20, or can be connected via other circuits, which is not limited here. In some embodiments, the first conductive layer 1 is directly provided on the substrate SUB. In some embodiments, a buffer layer (Buffer) may be further provided between the first conductive layer 1 and the substrate SUB, which is not limited here.

[0115] The dielectric layer 4 is located on the side of the first drive signal line 10 facing away from the substrate SUB. The dielectric layer 4 is made of an insulating material and provides insulation and protection for the conductive layer in the array substrate. The dielectric layer 4 can be a single-layer structure formed by a single insulating layer, or a laminated structure formed by stacking multiple insulating layers, without limitation.

[0116] As shown in FIG8 , in the non-display area FA of the array substrate, the dielectric layer 4 is provided with a second opening K2 that exposes at least a portion of the first drive signal line 10. The plurality of pads B include a second pad B2. The second pad B2 is located on a surface of the dielectric layer 4 facing away from the substrate SUB, and the orthographic projection of the second pad B2 on the dielectric layer 4 does not overlap with the second opening K2.

[0117] One end of the connection portion C is located in the second opening K2 and is in direct contact with the first drive signal line 10. The other end of the connection portion C is connected to the second pad B2 located on the surface of the dielectric layer 4. As shown in Figure 8, multiple second openings K2 can be provided to expose the same first drive signal line 10 to improve the connection effect between the connection portion C and the first drive signal line 10. In specific implementation, there is no limit on the number of second openings K2 opened in the dielectric layer 4 for the same drive signal line 10, for example, there can be two. In some embodiments, only one second opening K2 can be provided for the same drive signal line 10, and the opening area of ​​the second opening K2 can be expanded to improve the connection effect between the connection portion C and the first drive signal line 10, which is not limited here.

[0118] In the disclosed embodiment, as shown in FIG8 , no hole is formed in the dielectric layer 4 directly below the second pad B2, thereby allowing the second pad B2 to be formed on a relatively flat surface. When the second pad B2 is fabricated, when the conductive film layer on the side of the second pad B2 furthest from the dielectric layer 4 is patterned, because the conductive film layer is relatively flat, the flow of the photoresist will hardly cause the photoresist layer in the area where the second pad B2 is disposed to be too thin. Consequently, when the second pad B2 is fabricated, there will be almost no over-etching of the surface of the second pad B2, which helps avoid damage to the structure of the second pad B2 and improves the efficiency and yield of subsequent driver chip bonding.

[0119] In some embodiments, as shown in FIG8 , the array substrate further includes a second conductive layer 2 and at least one third conductive layer 3. The second conductive layer 2 is located on the side of the dielectric layer 4 facing away from the first conductive layer 1, and the third conductive layer 3 is located between the dielectric layer 4 and the second conductive layer 2. In a specific implementation, unless otherwise specified, the arrangement of the second conductive layer 2 and the third conductive layer 3 can refer to the relevant description of FIG3 , and will not be repeated here. The connecting portion C includes at least one of the second conductive layer 2 and the third conductive layer 3. The second pad B2 includes at least the second conductive layer 2, and the second conductive layer 2 is located on the side of the second pad B2 farthest from the dielectric layer 4. In a specific implementation, the second conductive layer 2 and the third conductive layer 3 are generally made of the same or similar materials. For example, the second conductive layer 2 and the third conductive layer 3 can both adopt a Ti / Al / Ti stacked structure, and the etching selectivity between the second conductive layer 2 and the third conductive layer 3 is relatively low. The second conductive layer 2 is used as the outermost conductive layer of the second pad B2. During etching, the second conductive layer 2 in the setting area of ​​the second pad B2 does not need to be etched to avoid damage to the pad structure due to over-etching.

[0120] In some embodiments, all film layers included in the connection portion C may be located in different film layers than all film layers included in the pad B2. The connection portion C and the pad B2 may be connected by overlapping the different film layers. For example, if the connection portion C includes at least one film layer from the plurality of third conductive layers 3, and the pad B2 includes only the second conductive layer 2, then during the specific manufacturing process, the second conductive layer 2 included in the second pad B2 may be formed on the third conductive layer 3 included in the connection portion C by overlapping vias or directly overlapping, without limitation herein.

[0121] In some embodiments, at least one film layer in the connection portion C and at least one film layer in the second pad B2 connected to the connection portion C are located in the same layer, and the film layers in the connection portion C and the film layers in the second pad B2 connected to the connection portion C are connected to each other. For example, as shown in FIG8 , the connection portion C includes at least the second conductive layer 2, and the second pad B2 includes at least the second conductive layer 2. The connection portion C and the second pad B2 have a film layer located in the same layer, namely, the second conductive layer 2. When etching the second conductive layer 2 to form the connection portion C and the second pad B2, the portion of the second conductive layer 2 located in the connection portion C can be kept connected to the portion of the second conductive layer 2 located in the second pad B2, so that the connection between the connection portion C and the second pad B2 is directly made through the second conductive layer 2.

[0122] In some embodiments, the array substrate may be a thin-film transistor (TFT) array substrate. TFT array substrates utilize TFTs and capacitors to form pixel circuits. The second conductive layer 2 and the third conductive layer 3 are both source / drain metal layers, and the first conductive layer 1 is a gate metal layer. In the non-display area FA of the array substrate, the source / drain metal layer can be used to form the structure of the pad B. In the display area AA of the array substrate, the source / drain metal layer can be used to form the source and drain electrodes of the TFTs, as well as to arrange the routing of a portion of the second drive signal lines 20. For example, the routing of the second drive signal lines 20 arranged in the source / drain metal layer may include power signal lines, data signal lines, initialization signal lines, and the like. By distributing a portion of the second drive signal lines 20 in the second and third conductive layers, the orthographic projections of the power signal lines, data signal lines, initialization signal lines, and the like located in different conductive layers on the substrate SUB overlap, thereby reducing the area of ​​the individual pixel circuit configuration region, increasing the number of pixel circuits provided per unit area, and further improving the resolution of the display panel. In the non-display area FA of the array substrate, the gate metal layer can be used to form the first drive signal lines 10. In the display area AA of the array substrate, the gate metal layer can be used to form the gate of the thin film transistor, as well as part of the second drive signal line, such as the scanning signal line and other structures, which are not limited here. In a specific implementation, the first conductive layer 1 may include a gate metal layer, or multiple gate metal layers. For example, as shown in Figure 3, the first conductive layer 1 includes a first gate metal layer G1 and a second gate metal layer G2, wherein the first drive signal line 10 is arranged in the first gate metal layer G1, and the dielectric layer 4 includes a second gate insulating layer GI2 and an interlayer dielectric layer ILD. In a specific implementation, the first drive signal line 10 can be arranged separately in the first gate metal layer G1 or the second gate metal layer G2, or simultaneously in the first gate metal layer G1 and the second gate metal layer G2, which are not limited here.

[0123] In some embodiments, the array substrate provided by the embodiments of the present disclosure can be used to manufacture OLED display panels, thereby resolving the issue of poor driver chip binding on OLED display panels. Unless otherwise specified, the specific structure of the array substrate can be referenced in FIG3 , which uses the top-gate TFT array substrate as an example, in which the first conductive layer includes a first gate metal layer G1 and a second gate metal layer G2, the second conductive layer 2 is a third source / drain metal layer SD3, and the plurality of third conductive layers 3 are first source / drain metal layers SD1 and second source / drain metal layers SD2. A detailed description thereof is omitted here.

[0124] The improvements to the array substrate provided by the present disclosure primarily relate to the pad structure within the non-display area FA of the array substrate and the connection structure between the second pad and the first drive signal line. Unless otherwise specified, the array substrate provided by the present disclosure is structurally unchanged from the array substrate in the related art. Therefore, the specific structure of the OLED array substrate provided by the present disclosure can also be referenced to the OLED display panel in the related art and will not be elaborated upon here.

[0125] In some embodiments, as shown in FIG8 , the TFT array substrate employs a 3SD structure. Three source / drain metal layers are provided in the 3SD array substrate: a first source / drain metal layer SD1, a second source / drain metal layer SD2, and a third source / drain metal layer SD3. The third conductive layer 3 includes the first source / drain metal layer SD1 and the second source / drain metal layer SD2, arranged sequentially along the dielectric layer 4 in a direction away from the first conductive layer 1. The second conductive layer 2 is the third source / drain metal layer. In a specific implementation, the connection portion C includes at least one of the first source / drain metal layer SD1, the second source / drain metal layer SD2, and the third source / drain metal layer SD3, and the second pad B2 includes at least the third source / drain metal layer SD3.

[0126] In some embodiments, the connection portion C includes a first source / drain metal layer SD1. The second pad B2 also includes the first source / drain metal layer SD1. The portion of the connection portion C located in the first source / drain metal layer SD1 is interconnected with the portion of the second pad B2 located in the first source / drain metal layer SD1, thereby connecting the connection portion C and the second pad B2 at least through the first source / drain metal layer SD1.

[0127] FIG. 9 is a second schematic diagram of the manufacturing process of the array substrate according to an embodiment of the present disclosure.

[0128] In some embodiments, the second pad B2 further includes a second source / drain metal layer SD2. In specific implementation, as shown in FIG9 , the manufacturing process of the array substrate includes the following steps:

[0129] 1. Before depositing the first source / drain metal layer, a first via hole H1 is formed in the dielectric layer 4 to expose the active layer A, and a second opening K2 is formed in the dielectric layer 4 to expose the first driving signal line 10;

[0130] 2. Depositing a first source / drain metal layer SD1 and patterning the first source / drain metal layer SD1 to form a source electrode S and a drain electrode D of the thin film transistor connected to the active layer A, a connection portion C connected to the first drive signal line 10, and a first conductive film layer B21 of the second pad B2. As shown in FIG9 , the connection portion C and the first conductive film layer B21 of the second pad B2 are located on the same layer and are interconnected.

[0131] 3. Depositing a second source / drain metal layer SD2 in sequence, patterning the second source / drain metal layer SD2 to form a second conductive film layer B22 of the second pad B2, depositing a third source / drain metal layer SD3, and patterning the third source / drain metal layer SD3 to form a third conductive film layer B23 of the second pad B2, thereby forming the second pad B2. In some embodiments, a passivation layer is formed between the first source / drain metal layer SD1 and the second source / drain metal layer SD2. As shown in FIG9 , the passivation layer covers the connection portion C. In the area where the second pad B2 is provided, the passivation layer is provided with a third opening for exposing the first conductive film layer B21 of the second pad B2, so as to facilitate subsequent connection between the second conductive film layer B22 and the first conductive film layer B21 of the second pad B2.

[0132] 4. After the second pads B2 are formed, the manufacturing process of the subsequent film layers of the array substrate may refer to the manufacturing process of the array substrate in the related art, which will not be described in detail here.

[0133] FIG10 is a third schematic diagram of the cross-sectional structure of the array substrate provided in an embodiment of the present disclosure.

[0134] In some embodiments, the connection portion C further includes a second source / drain metal layer SD2 and a third source / drain metal layer SD3. For example, as shown in FIG10 , the connection portion C includes the first source / drain metal layer SD1, the second source / drain metal layer SD2, and the third source / drain metal layer SD3, and the second pad B2 includes the first source / drain metal layer SD1, the second source / drain metal layer SD2, and the third source / drain metal layer SD3. In a specific implementation, when patterning the second source / drain metal layer SD2, the portion of the second source / drain metal layer SD2 located at the connection portion C and the portion located at the second pad B2 may be retained, and the portion of the second source / drain metal layer SD2 located at the connection portion C and the portion located at the second pad B2 may be interconnected. When patterning the third source / drain metal layer SD3, the portion of the third source / drain metal layer SD3 located at the connection portion C and the portion located at the second pad B2 may be retained, and the portion of the third source / drain metal layer SD3 located at the connection portion C and the portion located at the second pad B2 may be interconnected. This is not limited herein. In a specific implementation, a third opening is provided in the passivation layer between the first source / drain metal layer SD1 and the second source / drain metal layer SD2 in the region where the connection portion C is located. This opening is used to expose the first source / drain metal layer SD1. This facilitates connection between the portion of the connection portion C located within the first source / drain metal layer SD1 and the portion located within the second source / drain metal layer SD2. The connection portion C comprises a large number of conductive film layers, which helps reduce the resistance of the connection portion C, lower power consumption, and improve the transmission efficiency of drive signals.

[0135] In some embodiments, the second pad B2 includes a third source / drain metal layer SD3 and a second source / drain metal layer SD2, but does not include the first source / drain metal layer SD1. The connection portion C includes the second source / drain metal layer SD2. The portion of the connection portion C located in the second source / drain metal layer SD2 communicates with the portion of the second pad B2 located in the second source / drain metal layer SD2, thereby connecting the connection portion C and the second pad B2 at least through the second source / drain metal layer SD2.

[0136] FIG. 11 is a third schematic diagram of the manufacturing process of the array substrate provided in an embodiment of the present disclosure.

[0137] In some embodiments, the second pad B2 includes a third source / drain metal layer SD3 and a second source / drain metal layer SD2, but does not include the first source / drain metal layer SD1. The connection portion C includes the first source / drain metal layer SD1, the second source / drain metal layer SD2, and the third source / drain metal layer SD3. The portion of the second source / drain metal layer SD2 located at the connection portion C is interconnected with the portion located at the second pad B2, and the portion of the third source / drain metal layer SD3 located at the connection portion C is interconnected with the portion located at the second pad B2. In a specific implementation, as shown in FIG11 , the manufacturing process of the array substrate may include the following steps:

[0138] 1. Before depositing the first source / drain metal layer, a first via hole H1 is formed in the dielectric layer 4 to penetrate the dielectric layer 4 and expose the active layer A, and a second opening K2 is formed in the dielectric layer 4 to penetrate the dielectric layer 4 and expose the first driving signal line 10;

[0139] 2. Deposit a first source / drain metal layer SD1 and pattern the first source / drain metal layer SD1 to form a source electrode S and a drain electrode D of the thin film transistor connected to the active layer A, and retain a portion connected to the first drive signal line 10. Meanwhile, remove the portion of the first source / drain metal layer SD1 located in the area where the second pad B2 is provided.

[0140] 3. Deposit the second source-drain metal layer SD2 in sequence, perform patterning on the second source-drain metal layer SD2, retain the portion of the second source-drain metal layer SD2 located in the setting area of ​​the connection portion C and the portion located in the setting area of ​​the second pad B2, so that the portion of the second source-drain metal layer SD2 located in the setting area of ​​the connection portion C and the portion located in the setting area of ​​the second pad B2 are interconnected; deposit the third source-drain metal layer SD3, perform patterning on the second source-drain metal layer SD2, retain the portion of the third source-drain metal layer SD3 located in the setting area of ​​the connection portion C and the portion located in the setting area of ​​the second pad B2. The portion of the third source-drain metal layer SD3 located in the area where the connection portion C is provided is connected to the portion of the third source-drain metal layer SD3 located in the area where the second pad B2 is provided. In some embodiments, a passivation layer is formed between the first source-drain metal layer SD1 and the second source-drain metal layer SD2. In a specific implementation, a third opening is formed in the passivation layer in the area where the connection portion C is provided to expose the first source-drain metal layer SD1, so that the first source-drain metal layer SD1, the second source-drain metal layer SD2, and the third source-drain metal layer SD3 in the connection portion C are connected to each other to form the connection portion C.

[0141] 4. After the second pads B2 are formed, the manufacturing process of the subsequent film layers of the array substrate may refer to the manufacturing process of the array substrate in the related art, which will not be described in detail here.

[0142] In the embodiments shown in Figures 7 to 11 of the present disclosure, the structure of the array substrate is described by taking the array substrate used to form an OLED display panel as an example. In specific implementation, the array substrate provided by the embodiment of the present disclosure can also be used to form other types of display panels. For example, in some embodiments, the array substrate provided by the embodiment of the present disclosure can also be used to form a quantum dot light emitting diode (Quantum Dot Light Emitting Diode, referred to as QD LED) display panel or a Micro LED (Micro Light Emitinng Diode, referred to as Micro LED) display panel, etc. The structure of the array substrate used in the quantum dot light emitting diode display panel is similar to the structure of the array substrate in the OLED display panel, and will not be described in detail here. The Micro LED display panel is usually manufactured by bonding the Micro LED chip to the array substrate, so it is necessary to set a cathode and anode for bonding the Micro LED chip on the array substrate. In specific implementation, the array substrate structure of the Micro LED display panel in the related art can be adjusted, and will not be described in detail here.

[0143] In the embodiments shown in Figures 7 to 11 of the present disclosure, the array substrate is a TFT array substrate. In specific implementations, the array substrate provided in the embodiments of the present disclosure may also be other types of array substrates. The use of the array substrate structure provided in the embodiments of the present disclosure can reduce the probability of pad damage and thereby improve the efficiency and yield of driver chip bonding, without limitation herein.

[0144] In the embodiment of the present disclosure, according to actual conditions, all or part of the pads on the array substrate can be set as second pads. In specific implementation, the array substrate may include multiple second pads, and the film layers included in each second pad may be the same or different. For example, in some embodiments, some of the second pads only include the third source-drain metal layer, some of the second pads include the third source-drain metal layer and the second source-drain metal layer, but do not include the first source-drain metal layer, and the remaining second pads include the first source-drain metal layer, the second source-drain metal layer, and the third source-drain metal layer. As long as the probability of pad damage can be reduced and the efficiency and yield of driver chip binding can be improved, no limitation is made here.

[0145] Depending on the actual situation, the film layers included in each connecting portion may be the same or different, which is not limited here.

[0146] The present disclosure also provides another array substrate, wherein some of the pads on the array substrate are configured as the first pads in the aforementioned embodiment, and some are configured as the second pads in the aforementioned embodiment. The number of the first pads and the second pads can be adjusted based on actual needs, as long as the probability of pad damage is reduced and the efficiency and yield of driver chip bonding are improved, and this is not limited here.

[0147] The present disclosure also provides a display panel. The display panel includes a driver chip and the array substrate provided by any of the aforementioned embodiments. The driver chip is bound to the array substrate and electrically connected to the pads on the array substrate. The display panel provided by the embodiment of the present disclosure has the same or similar technical effects as the array substrate provided by the embodiment of the present disclosure, and will not be described in detail here. In specific implementation, the display panel provided by the embodiment of the present disclosure can be an OLED display panel, a quantum dot light-emitting diode display panel, or a Micro LED display panel, etc., which is not limited here.

[0148] The present disclosure also provides a display device. The display device includes the display panel provided by any of the aforementioned embodiments. The display device provided by the embodiments of the present disclosure has the same or similar technical effects as the display panel provided by the embodiments of the present disclosure, and is not further described here. In specific implementations, the display device provided by the embodiments of the present disclosure can be a mobile phone, a laptop computer, a display, a monitor, etc., without limitation herein.

[0149] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0150] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. An array substrate includes a display area and a bonding area located on one side of the display area. The bonding area is provided with a first pad, wherein, Further comprising: A substrate; A first conductive layer located on the substrate; the first conductive layer includes a first driving signal line; A dielectric layer located on a side of the first driving signal line away from the substrate; the dielectric layer is provided with a first opening exposing at least a part of the first driving signal line; at least a part of the first pad is located within the first opening and is directly connected to the first driving signal line through the first opening; the remaining part of the first pad overlaps on the surface of the dielectric layer surrounding the first opening; A second conductive layer located on a side of the dielectric layer away from the first conductive layer; At least one layer of a third conductive layer located between the dielectric layer and the second conductive layer; The first pad at least includes the second conductive layer, and the second conductive layer is located on a side of the first pad farthest from the dielectric layer; at least a part of the first pad does not include at least one layer of the third conductive layer.

2. The array substrate according to claim 1, wherein, The at least one layer of the third conductive layer includes a first source-drain metal layer and a second source-drain metal layer sequentially arranged in a direction away from the first conductive layer of the dielectric layer; The second conductive layer is a third source-drain metal layer; the first pad at least includes the third source-drain metal layer, and at least a part of the first pad does not include at least one layer of the first source-drain metal layer and the second source-drain metal layer.

3. The array substrate according to claim 2, wherein, The first pad further includes the second source-drain metal layer and does not include the first source-drain metal layer.

4. The array substrate according to any one of claims 1 to 3, wherein, The first conductive layer includes a gate metal layer.

5. An array substrate includes a display area and a bonding area located on one side of the display area. The bonding area is provided with a second pad, wherein, Further comprising: A substrate; A first conductive layer located above the substrate; the first conductive layer includes a first driving signal line; A dielectric layer located on a side of the first driving signal line away from the substrate; the dielectric layer is provided with a second opening exposing at least a part of the first driving signal line; the second pad is located on a side of the dielectric layer away from the first conductive layer; A connection portion, one end of the connection portion is located within the second opening and is directly in contact connection with the first driving signal line; the other end of the connection portion is connected to the second pad located on the surface of the dielectric layer; a positive projection of the second pad on the dielectric layer does not overlap with the second opening.

6. The array substrate according to claim 5, wherein, The array substrate further includes: A second conductive layer located on a side of the dielectric layer away from the first conductive layer; At least one layer of a third conductive layer located between the dielectric layer and the second conductive layer; The connection portion includes at least one layer of the second conductive layer and the third conductive layer; the second pad at least includes the second conductive layer, and the second conductive layer is located on a side of the second pad farthest from the dielectric layer.

7. The array substrate according to claim 6, wherein, At least one layer of a film layer in the connection portion and at least one layer of a film layer in the second pad connected to the connection portion are located on the same layer, and in the film layer of the connection portion and the film layer of the second pad connected to the connection portion, the film layers located on the same layer are interconnected.

8. The array substrate according to claim 7, wherein, The at least one layer of the third conductive layer includes a first source-drain metal layer and a second source-drain metal layer sequentially arranged in a direction away from the first conductive layer of the dielectric layer; the second conductive layer is a third source-drain metal layer.

9. The array substrate according to claim 8, wherein, The connecting portion includes the first source-drain metal layer; the second pad further includes the first source-drain metal layer.

10. The array substrate according to claim 9, wherein, The second pad further includes the second source-drain metal layer.

11. The array substrate according to claim 9, wherein, The connecting portion further includes the second source-drain metal layer and the third source-drain metal layer.

12. The array substrate according to claim 8, wherein, The second pad further includes the second source-drain metal layer and does not include the first source-drain metal layer; the connecting portion includes the second source-drain metal layer.

13. The array substrate according to claim 12, wherein, The connecting portion further includes the first source-drain metal layer and the third source-drain metal layer.

14. The array substrate according to claim 10, 11 or 13, wherein, The array substrate further includes: A passivation layer located between the first source-drain metal layer and the second source-drain metal layer; the passivation layer is provided with a third opening exposing the first source-drain metal layer.

15. The array substrate according to any one of claims 5 to 13, wherein, The first conductive layer includes a gate metal layer.

16. A display panel, wherein, Including a driving chip and the array substrate according to any one of claims 1 to 4 or claims 5 to 15; the driving chip is electrically connected to the pad on the array substrate.

17. A display device, wherein, Including the display panel according to claim 16.

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