Array substrate and manufacturing method therefor, and display device

Abstract

The present application discloses an array substrate and a manufacturing method therefor, and a display device. The array substrate comprises: a base substrate (101), a target insulating layer, a light-emitting structure layer (220), and a reflection structure (120). The light-emitting structure layer (220) comprises a plurality of bottom-emitting light-emitting devices (160) arranged in an array. The reflection structure (120) is located on the light-emitting side of the light-emitting devices (160). The reflection structure (120) comprises: a first recess (121) and a reflection portion (122) provided on a first side wall (1211) of the first recess (121). The first recess (121) is formed in the target insulating layer, and the reflection portion (122) is obliquely arranged relative to the surface of the base substrate (101).

Description

Array substrate, manufacturing method thereof, and display device CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to Chinese patent application No. 202410039828.1, filed on January 10, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure belongs to the field of display technology and relates to an array substrate and a preparation method thereof, and a display device. Background Art

[0003] Electroluminescent devices are playing an increasingly important role in the display industry. For example, organic light-emitting diodes (OLEDs) have seen widespread adoption and application in recent years due to their wide color gamut, flexibility, and fast response time. As the resolution of display products increases, the size of the luminous area is limited. Therefore, increasing luminance has become a key development direction for display products based on electroluminescent devices. Summary of the Invention

[0004] In a first aspect of the present disclosure, an array substrate is provided, comprising: a base substrate; a target insulating layer disposed on one side of the base substrate; a light-emitting structure layer disposed on a side of the target insulating layer away from the base substrate, the light-emitting structure layer comprising a plurality of bottom-emitting light-emitting devices arranged in an array; and a reflective structure located on a light-emitting side of the light-emitting device. The reflective structure comprises: a first groove and a reflective portion disposed on a first sidewall of the first groove. The first groove is located in the target insulating layer. The first sidewall is a sidewall away from a light-emitting area of ​​the light-emitting device. The reflective portion is disposed obliquely relative to the surface of the base substrate, the distance from the bottom end of the reflective portion to the light-emitting area is smaller than the distance from the top end of the reflective portion to the light-emitting area, the bottom end is an end close to the base substrate, and the orthographic projection of the reflective portion on the base substrate is outside the orthographic projection range of the light-emitting area on the base substrate.

[0005] In combination with the first aspect of the present disclosure, in some optional embodiments, the array substrate further includes: a target metal layer, located on a side of the target insulating layer close to the light-emitting structure layer; the target metal layer includes: a target signal line, at least a portion of the target signal line close to the light-emitting area is overlapped on the first side wall to serve as the reflecting portion.

[0006] In combination with the first aspect of the present disclosure, in some optional implementations, the target signal line includes: one or more of: a data line, a first power line, a second power line, and a gate line.

[0007] In combination with the first aspect of the present disclosure, the target signal line includes: a gate line arranged along a first direction and a data line arranged along a second direction, the first direction intersects with the second direction, the reflecting portion close to the gate line is a part of the gate line, the reflecting portion close to the data line is a part of the data line, and the gate line and the data line are located on different sides of the light-emitting area.

[0008] In combination with the first aspect of the present disclosure, in some optional embodiments, the reflective portion close to the gate line has a first slope angle, and the reflective portion close to the data line has a second slope angle, and the first slope angle is smaller than the second slope angle.

[0009] In combination with the first aspect of the present disclosure, in some optional embodiments, the array substrate further includes: a target metal layer, located on the side of the target insulating layer close to the light-emitting structure layer; the target metal layer includes: a target signal line, the reflective portion is arranged in the same layer as the target metal layer, and the reflective portion is located in the spacing area between the light-emitting area and the target signal line close to the light-emitting area.

[0010] In combination with the first aspect of the present disclosure, in some optional embodiments, the target insulating layer includes an insulating layer located on the side of the target metal layer close to the base substrate and in contact with the target metal layer; along the direction perpendicular to the base substrate, the depth of the first groove is greater than or equal to the thickness of the insulating layer located on the side of the target metal layer close to the base substrate and in contact with the target metal layer, and is less than the sum of the thicknesses of all insulating layers of the target metal layer close to the base substrate.

[0011] In combination with the first aspect of the present disclosure, in some optional embodiments, the array substrate further includes: a driving circuit layer, located on the side of the light-emitting structure layer close to the base substrate; the driving circuit layer includes: an active layer, a first insulating layer, a first metal layer, a second insulating layer and at least one second metal layer stacked on the base substrate; the target metal layer includes one or more of the following metal layers: the first metal layer and the at least one second metal layer.

[0012] In conjunction with the first aspect of the present disclosure, in some optional embodiments, the at least one second metal layer is one, the target metal layer includes the second metal layer, and the first groove is defined on a surface of the second insulating layer distal from the base substrate. The array substrate further includes a buffer layer positioned between the active layer and the base substrate; and along a direction perpendicular to the base substrate, the depth of the first groove defined in the second insulating layer is greater than or equal to the thickness of the second insulating layer and less than or equal to the sum of the thicknesses of the second insulating layer and the buffer layer.

[0013] In conjunction with the first aspect of the present disclosure, in some optional embodiments, there are two at least one second metal layers, and the target metal layer includes the second metal layer of the two second metal layers that is relatively farther away from the base substrate. The drive circuit layer also includes a third insulating layer located between the two second metal layers, and the array substrate also includes: a buffer layer located between the active layer and the base substrate. The first groove is provided on the surface of the third insulating layer away from the base substrate; along a direction perpendicular to the base substrate, the depth of the first groove provided on the third insulating layer is greater than or equal to the thickness of the third insulating layer, and less than or equal to the sum of the thicknesses of the third insulating layer, the second insulating layer, and the buffer layer.

[0014] In combination with the first aspect of the present disclosure, in some optional embodiments, the array substrate further includes: a buffer layer located between the active layer and the base substrate; the target metal layer includes the first metal layer, and the surface of the buffer layer away from the base substrate is provided with the first groove, and along the direction perpendicular to the base substrate, the depth of the first groove provided on the buffer layer is greater than or equal to the thickness of the buffer layer, and less than the sum of the thickness of the buffer layer and the base substrate.

[0015] In conjunction with the first aspect of the present disclosure, in some optional embodiments, the array substrate further includes: a color filter layer disposed between the drive circuit layer and the light-emitting structure layer, the color filter layer including color filter units disposed corresponding to at least a portion of the light-emitting devices. The array substrate further includes: a second groove located on a side of the color filter layer close to the base substrate, the orthographic projection of the second groove on the base substrate being within the orthographic projection range of the first groove on the base substrate. The color filter unit covers the sidewalls and bottom of the second groove, and the light-emitting area of ​​the light-emitting device, the notch of the first groove, and the orthographic projection of the notch of the second groove on the base substrate are located within the orthographic projection range of the color filter unit on the base substrate.

[0016] In combination with the first aspect of the present disclosure, in some optional embodiments, the sidewall of the second groove away from the light-emitting area is a second sidewall, and an insulating protective layer is provided between the reflective portion and the color filter unit covered on the second sidewall.

[0017] In combination with the first aspect of the present disclosure, in some optional embodiments, the notch of the second groove is located above the notch of the first groove, and the bottom of the second groove is flush with or lower than the bottom of the first groove.

[0018] In combination with the first aspect of the present disclosure, in some optional embodiments, the sidewall of the second groove away from the light-emitting area is a second sidewall, and the second sidewall is arranged parallel to the first sidewall.

[0019] In combination with the first aspect of the present disclosure, in some optional embodiments, the array substrate further includes: a transistor arranged corresponding to each of the light-emitting devices, and the reflective structure is provided on a side of at least a portion of the transistors close to the light-emitting area.

[0020] In combination with the first aspect of the present disclosure, in some optional embodiments, the light-emitting structure layer further includes: a pixel defining layer having a plurality of pixel openings, each pixel opening being configured to define a light-emitting area of ​​the light-emitting device; the reflective structure is located on a side of the pixel defining layer close to the base substrate, and the orthographic projection of the reflective portion on the base substrate is outside the range of the orthographic projection of the pixel opening on the base substrate.

[0021] In combination with the first aspect of the present disclosure, in some optional embodiments, the reflecting portion includes: a first region and a second region, the first region covers the first side wall, and the second region is overlapped on the surface of the target insulating layer away from the base substrate; the width of the second region is 2 to 3 microns.

[0022] In combination with the first aspect of the present disclosure, in some optional embodiments, the width of the orthographic projection of the bottom of the first groove on the base substrate is 4 to 6 microns; and the slope angle of the reflective portion is 30 to 45 degrees.

[0023] In a second aspect of the present disclosure, a method for preparing an array substrate is provided, comprising: forming a target insulating layer on a base substrate; forming a reflective structure on the target insulating layer, the reflective structure comprising: a first groove and a reflective portion disposed on a first sidewall of the first groove; and forming a light-emitting structure layer on the target insulating layer, the light-emitting structure layer comprising a plurality of bottom-emitting light-emitting devices arranged in an array. The reflective structure is located on a light-emitting side of the light-emitting device, the first sidewall is a sidewall away from a light-emitting area of ​​the light-emitting device, the reflective portion is arranged at an angle relative to the surface of the base substrate, the distance from the bottom end of the reflective portion to the light-emitting area is shorter than the distance from the top end of the reflective portion to the light-emitting area, the bottom end is an end close to the base substrate, and the orthographic projection of the reflective portion on the base substrate is outside the orthographic projection range of the light-emitting area on the base substrate.

[0024] In a third aspect of the present disclosure, a display device is provided, comprising: the array substrate provided in the first aspect.

[0025] The above description is only an overview of the technical solutions provided by some embodiments of the present disclosure. In order to more clearly understand the technical means of the embodiments of the present disclosure, they can be implemented in accordance with the contents of the specification. In order to make the embodiments of the present disclosure more obvious and easy to understand, the specific implementation methods of the embodiments of the present disclosure are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] To more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0027] FIG1 is a schematic plan view of an array substrate according to some embodiments of the present disclosure;

[0028] FIG2 shows a schematic top view of a single light emitting device according to some embodiments of the present disclosure;

[0029] FIG3 shows a schematic top view of a single light emitting device according to some other embodiments of the present disclosure;

[0030] FIG4 shows a schematic top view of a single light emitting device according to some other embodiments of the present disclosure;

[0031] FIG5 shows a schematic diagram of a stacked structure of an array substrate according to some embodiments of the present disclosure;

[0032] FIG6 shows a schematic diagram of a stacked structure of an array substrate according to other embodiments of the present disclosure;

[0033] FIG7 shows a schematic diagram of the layout of a single color filter unit according to some embodiments of the present disclosure;

[0034] FIG8 shows a flow chart of a method for preparing an array substrate according to some embodiments of the present disclosure;

[0035] FIG9 is a schematic diagram showing a structure after forming a source / drain metal layer according to some embodiments of the present disclosure;

[0036] FIG10 shows a schematic structural diagram after forming a second groove according to some embodiments of the present disclosure;

[0037] FIG11 shows a schematic structural diagram after forming a color filter layer and a planarization layer according to some embodiments of the present disclosure;

[0038] FIG12 shows a schematic structural diagram after forming a first electrode and a pixel defining layer according to some embodiments of the present disclosure; and

[0039] FIG13 shows a schematic structural diagram of a display device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0040] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0041] It should be noted that the term "and / or" appearing in this article is only a description of the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. "Multiple" includes two or more than two situations. "Include" or "comprising" and other similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, but do not exclude other elements or objects. "Up", "down", "left", "right", etc. are only used to indicate relative position relationships. When the absolute position of the described object changes, the relative position relationship may also change accordingly.

[0042] As used herein, "about" and "slightly less than" include the stated value and the average value that is within an acceptable range of deviation from the particular value, where the acceptable range of deviation is determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0043] The terms "parallel", "perpendicular" and "equal" appearing in this document include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0044] It should be understood that in the exemplary embodiments of the present disclosure, when a layer or an element is referred to as being on another layer or substrate, it may be that the layer or element is directly on the other layer or substrate, or there may be an intermediate layer between the layer or element and the other layer or substrate. The definition direction of "thickness" and "depth" is the direction perpendicular to the substrate. "A and B are arranged in the same layer" means that after A and B adopt the same film forming process to form a film layer for forming a specific pattern, a layer structure is formed by a single composition process using the same mask. "The orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0045] Electroluminescent devices, such as OLEDs, have been widely promoted and applied in display products. For example, although ultra-large OLED display products (such as OLED TVs larger than 80 inches) currently account for a relatively small portion of the OLED market, they hold broad market prospects. However, the large size and high-resolution requirements (such as 8K) of ultra-large OLED panels during manufacturing lead to a limited light-emitting area. Increasing brightness requires reducing the area of ​​the transistor and capacitor regions, but these areas have already been reduced to their limits and are difficult to reduce further.

[0046] In view of this, the inventors conducted further research to improve the luminance of bottom-emitting light-emitting devices without increasing the luminous area. The following describes in detail the array substrate, its preparation method, and the display device provided in some embodiments of the present disclosure with reference to the accompanying drawings.

[0047] Some embodiments of the present disclosure provide an array substrate. This array substrate can be used in display products or lighting products such as automotive taillights, without limitation. When used in display products, the array substrate may also be referred to as a display substrate. This document primarily uses an array substrate used in a display product as an example for illustration.

[0048] FIG1 shows a schematic plan view of an array substrate according to some embodiments of the present disclosure. As shown in FIG1 , an array substrate 10 used in a display product may include a display area DR and a non-display area NR. The display area DR is the area on the array substrate 10 used to display an image, and the non-display area NR is the area on the array substrate 10 other than the display area DR. The non-display area NR may be located on at least one side (e.g., one side, or multiple sides) of the display area DR. For example, the non-display area NR may be arranged around the display area DR.

[0049] The display area DR is provided with a plurality of pixel units P arrayed in a first direction and a second direction. For example, the plurality of pixel units P can be arranged into M rows and N columns, where M and N are integers greater than or equal to 2. The first direction (such as the X-axis direction in FIG1 ) is the pixel row direction, and the second direction (such as the Y-axis direction in FIG1 ) is the pixel column direction. The first direction and the second direction intersect, such as being perpendicular to each other. Each pixel unit P includes a plurality of sub-pixels. In some embodiments, the shape of the sub-pixel can be circular, elliptical, triangular, square, rectangular, rhombus, trapezoid, parallelogram, pentagon, hexagon or other polygons, etc., and can be set according to the needs of the actual product, and the present disclosure does not limit this.

[0050] In some embodiments, a pixel unit P may include four sub-pixels, and the four sub-pixels may include: a first sub-pixel p1 emitting a first color light, a second sub-pixel p2 emitting a second color light, a third sub-pixel p3 emitting a third color light, and a fourth sub-pixel p4 emitting a fourth color light. In some embodiments, the four sub-pixels may be arranged in a square, which can effectively increase the aperture ratio and the area of ​​the light-transmitting region. Of course, in other embodiments, the four sub-pixels may also be arranged in a horizontal parallel manner, a diamond shape, or a vertical parallel manner, depending on the actual product needs, and this disclosure does not impose any restrictions on this.

[0051] In some embodiments, the first sub-pixel p1 may be a red sub-pixel (R) that emits red light, the second sub-pixel p2 may be a blue sub-pixel (B) that emits blue light, the third sub-pixel p3 may be a white sub-pixel (W) that emits white light, and the fourth sub-pixel p4 may be a green sub-pixel (G) that emits green light. It should be noted that the arrangement of the four sub-pixels shown in FIG1 is only an example and may be determined based on product requirements.

[0052] Of course, in other embodiments, a pixel unit P may also include more or fewer sub-pixels than those in FIG. 1 , for example, it may include three RGB sub-pixels, which may be determined according to actual product needs and is not limited in this disclosure.

[0053] A sub-pixel may include: a light-emitting device and a pixel driving circuit for driving the light-emitting device to emit light. For example, as shown in FIG1 , the array substrate 10 further includes a plurality of gate lines GL and a plurality of data lines DL. The plurality of gate lines GL and the plurality of data lines DL intersect with each other and define a plurality of pixel areas distributed in an array in the display area DR.

[0054] In some embodiments, as shown in FIG1 , the array substrate 10 may further include a scan drive circuit SC and a data drive circuit DC located in the non-display area NR. The scan drive circuit SC may be, for example, a gate drive circuit (e.g., a GOA drive circuit). The scan drive circuit SC is connected to the pixel drive circuit via the scan line GL to provide various scan signals, and the data drive circuit DC is connected to the pixel drive circuit via the data line DL to provide data signals. It should be noted that the positional relationship between the scan drive circuit SC and the data drive circuit DC, the scan line GL, and the data line DL in the array substrate 10 shown in FIG1 is only an example, and the actual arrangement position can be designed as needed. For example, a scan drive circuit SC may be provided in the non-display area NR on one side of the array substrate 10 as shown in FIG1 , or scan drive circuits SC may be provided in the non-display areas NR on opposite sides of the array substrate 10.

[0055] The pixel driving circuit may include multiple electronic components such as transistors and capacitors. In some embodiments, the pixel driving circuit may include three transistors and one capacitor, forming a 3T1C (i.e., one driving transistor, two switching transistors and one capacitor). In other embodiments, the pixel driving circuit may also include more than three transistors and at least one capacitor, such as a 4T1C (i.e., one driving transistor, three switching transistors and one capacitor), a 5T1C (i.e., one driving transistor, four switching transistors and one capacitor), or a 7T1C (i.e., one driving transistor, six switching transistors and one capacitor). The transistor may be a thin film transistor (TFT), a field effect transistor (MOS), or other switching devices with the same characteristics. In some embodiments, the thin film transistor used may include but is not limited to an oxide transistor (Oxide TFT) or a low temperature polysilicon thin film transistor (LTPS TFT). In some embodiments, the thin film transistor may be a bottom gate thin film transistor or a top gate thin film transistor, as long as the switching function can be achieved, and the present disclosure does not limit this.

[0056] It is understood that a transistor may include a control electrode, a first electrode, and a second electrode. The control electrode is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of a transistor may be structurally symmetrical, their structures may be identical, and the source of the transistor may be referred to as the first electrode, or may also be referred to as the second electrode.

[0057] In some embodiments of the present disclosure, an array substrate 10 includes: a base substrate; a target insulating layer disposed on one side of the base substrate; a light-emitting structure layer disposed on a side of the target insulating layer away from the base substrate, the light-emitting structure layer including a plurality of bottom-emitting light-emitting devices arranged in an array; and a reflective structure located on the light-emitting side of the light-emitting devices. The reflective structure includes: a first groove and a reflective portion disposed on a first sidewall of the first groove. The first groove is located in the target insulating layer, and the first sidewall is a sidewall away from the light-emitting area of ​​the light-emitting devices. The orthographic projection of the reflective portion on the base substrate is outside the orthographic projection of the light-emitting area on the base substrate. The reflective portion is disposed at an angle relative to the surface of the base substrate, and the distance from the bottom end of the reflective portion to the light-emitting area is shorter than the distance from the top end of the reflective portion to the light-emitting area. The bottom end refers to the end closest to the base substrate, and the distance refers to the lateral distance. The orthographic projection edge of the light-emitting area on the base substrate serves as a reference boundary line. The orthographic projection position of the bottom end of the reflective portion on the base substrate serves as a first reference position, and the orthographic projection position of the top end of the reflective portion on the base substrate serves as a second reference position. For each reflecting part, the above-mentioned "distance from the bottom end of the reflecting part to the luminous area" refers to the distance between the first reference position and the nearest reference boundary line, and the above-mentioned "distance from the top end of the reflecting part to the luminous area" refers to the distance between the second reference position and the nearest reference boundary line.

[0058] At least a portion of the light emitted from the bottom-emitting light-emitting device that deviates from the normal viewing direction is reflected back by the reflective portion, and after being reflected by the reflective electrode (such as the cathode) of the light-emitting device, it is emitted from the substrate area corresponding to the light-emitting device, which is beneficial for improving the light brightness without increasing the light-emitting area of ​​the bottom-emitting light-emitting device.

[0059] In some embodiments, the reflective structure can be provided on one side, two sides, three sides or each side of the light-emitting area of ​​each light-emitting device, and can be provided according to actual needs, and the present disclosure does not impose any restrictions on this. In some embodiments, a reflective structure is provided on each side, i.e., all four sides, of the light-emitting area of ​​the light-emitting device, so as to reflect back at least a portion of the light emitted from each side of the bottom-emitting light-emitting device that deviates from the normal viewing direction, thereby better improving the luminous brightness. It should be noted that the reflective structures on different sides can be connected together or disconnected; the reflective portions in the reflective structures on different sides of the same light-emitting area can be located on the same metal layer or on different metal layers; it is determined based on the shape of the light-emitting area and the layout design of the actual product, and the present disclosure does not impose any restrictions on this.

[0060] It is understandable that the reflective portion of the reflective structure needs to be tilted so that at least a portion of the light emitted by the bottom-emitting light-emitting device that deviates from the normal viewing angle direction can be reflected back to the reflective electrode (such as the cathode) of the light-emitting device, and after reflection by the reflective electrode, it is emitted from the light-emitting area corresponding to the light-emitting device. In some embodiments, taking into account the width of the space occupied by the reflective portion in the first direction and the ability to reflect the light that deviates from the normal viewing angle direction, the slope angle of the reflective portion can be 30 degrees to 45 degrees, such as 30 degrees, 35 degrees, 40 degrees or 45 degrees. The slope angle here refers to the angle between the reflective portion and the surface of the substrate. It should be noted that in other embodiments, the slope angle of the reflective portion can also be set to be larger or smaller, such as 25 degrees, 47 degrees or 50 degrees, etc., according to the needs of the actual product, and the present disclosure does not limit this.

[0061] In some embodiments, the first sidewall of the first groove is inclined relative to a direction perpendicular to the substrate and away from the light-emitting area, and the distance between the bottom end of the first sidewall and the light-emitting area is smaller than the distance between the top end and the light-emitting area. As a result, by covering the first sidewall with a film layer having reflective properties, such as a metal film layer, the reflective portion arranged obliquely relative to the substrate surface can be formed. The slope angle of the first sidewall can be set according to the desired inclination angle of the reflective portion.

[0062] In some embodiments, the array substrate 10 may further include: a target metal layer, located on the side of the target insulating layer close to the light-emitting structure layer. The target metal layer includes: a target signal line. In some embodiments, the target signal line may include: one or more of: a data line DL, a first power line VDD, a second power line VSS, and a gate line GL. The signal transmitted by the first power line VDD is a first power supply voltage signal, and the signal transmitted by the second power line VSS is a second power supply voltage signal. In some embodiments, the first power supply voltage signal may be a high-level signal, and the second power supply voltage signal may be a low-level signal, such as a ground voltage or a negative voltage with a smaller voltage value. Of course, in other embodiments, the target signal line may also include other signal lines arranged between the light-emitting areas of each light-emitting device, which is determined according to the actual product, and the present disclosure does not limit this.

[0063] There are various ways to implement the reflective portion. In some embodiments, at least a portion of the target signal line near the light-emitting area can be placed on the first sidewall of the first groove to serve as the reflective portion. This eliminates the need for a separate reflective portion, helping to reduce unnecessary space usage.

[0064] It should be noted that the target signal lines adjacent to opposite sides of the same light-emitting area can be of the same or different types. Alternatively, the target signal lines adjacent to opposite sides of some light-emitting devices can be of the same type, while the target signal lines adjacent to opposite sides of another portion of light-emitting devices can be of different types. The target signal lines adjacent to the same side of the light-emitting area of ​​different light-emitting devices can be of the same or different types. This is determined based on the actual circuit layout and is not limited in this disclosure.

[0065] Taking a square light-emitting area as an example, FIG2 shows a schematic top view of a single light-emitting device according to some embodiments of the present disclosure. Along a first direction (e.g., the X-axis in FIG2 ), the target signal line closest to the left and right sides of the light-emitting area 100 in FIG2 can be, for example, one of the signal lines V1 extending along a second direction (e.g., the Y-axis in FIG2 ), such as a data line DL, a first power line VDD, and a second power line VSS. The target signal line closest to the upper and lower sides of the light-emitting area in FIG2 can be a signal line V2 extending along the first direction, such as a gate line GL. A first groove 121 is provided in the target insulating layer beneath each target signal line. Portions of the target signal line overlap the first sidewalls of the first groove 121, forming a reflective portion 122. The first grooves 121 on the left and right sides of the light-emitting area 100 in FIG2 can extend along the second direction, while the first grooves 121 on the upper and lower sides can extend along the first direction. It should be noted that the first grooves 121 can extend in a straight line or have a bend, depending on the shape of the light-emitting area 100 in the actual product, and are not limited by this disclosure.

[0066] In some embodiments, the target signal lines include: a gate line GL arranged along a first direction and a data line DL arranged along a second direction. The reflective portion 122 on the side proximate the gate line GL is a portion of the gate line GL, and the reflective portion 122 on the side proximate the data line DL is a portion of the data line DL. The gate line GL and the data line DL are located on different sides of the light-emitting area 100 of the light-emitting device. This can reduce interference between the data lines DL and the gate line GL. That is, on the side of the light-emitting area 100 proximate the gate line GL (such as the upper and / or lower side of the light-emitting area 100 in FIG. 2 ), a portion of the gate line GL overlaps the first sidewall of the first groove 121 disposed thereunder, forming the reflective portion 122 on that side. On the side of the light-emitting area 100 proximate the data line DL (such as the left and / or right side of the light-emitting area 100 in FIG. 2 ), a portion of the data line DL overlaps the first sidewall of the first groove 121 disposed thereunder, forming the reflective portion 122 on that side.

[0067] In some embodiments, the reflective portion 122 near the gate line GL has a first slope angle, and the reflective portion 122 near the data line DL has a second slope angle, where the first slope angle is smaller than the second slope angle. This ensures that the intensity of reflected light on the gate line GL and the data line DL is approximately the same, thereby improving display uniformity.

[0068] In other embodiments, the reflective portion 122 can be provided in the same layer as the target metal layer, and the reflective portion 122 is located in the spacing area between the light-emitting area 100 and the target signal line adjacent to the light-emitting area 100. The reflective portion 122 is provided independently of the target signal line, so that it does not affect the routing of the target signal line, and the layout position is not constrained by the routing requirements of the target signal line, thereby providing a more flexible design.

[0069] Figure 3 shows a top view of a single light-emitting device according to other embodiments of the present disclosure. As shown in Figure 3, a reflective structure 120, specifically a first groove 121 and a reflective portion 122 resting on the first sidewall of the first groove 121, can be added around the light-emitting area 100 in Figure 3, such as on the top, bottom, left, and right sides. Other structures, such as target signal lines and transistors, are located on the side of the reflective structure 120 away from the light-emitting area 100. The reflective portion 122 in the reflective structure 120 can be provided on the same layer as the target metal layer to save on masking material.

[0070] It should be noted that the above two embodiments can be used alone or in combination, depending on the actual product needs, and this disclosure does not impose any restrictions on this. The combination here means that the reflective portion 122 on one or more sides of the same light-emitting area 100 is formed by overlapping the portion of the target signal line on that side closest to the first sidewall of the first groove 121 provided thereunder, and the reflective portion 122 on the other sides is formed by overlapping the metal pattern added to that side with the first sidewall of the first groove 121 provided thereunder.

[0071] FIG4 shows a schematic top view of a single light-emitting device according to some other embodiments of the present disclosure. In FIG4 , one of the target signal lines extending in the second direction, such as the data line DL, the first power line VDD, and the second power line VSS, on the left and right sides of the light-emitting area 100 closest to the light-emitting area 100, is placed on the first sidewall of the first groove 121 below it, serving as a reflective portion 122a. In FIG4 , first grooves 121 extending in the first direction are added to the upper and lower sides of the light-emitting area 100, and a metal pattern is added to the first sidewall of the first groove 121, serving as a reflective portion 122b. The reflective portion 122b can be located in the spacing area between the target signal line, such as the gate line GL, closest to the light-emitting area 100 on that side and the light-emitting area 100, and can be provided on the same layer as the target metal layer. In some embodiments, the added reflective portion 122b can be provided on the same layer as the metal layer providing the data line DL.

[0072] In some embodiments, as shown in Figures 2-4, the reflective portion 122 in the reflective structure 120 may include a first region 1221 and a second region 1222 connected to the first region 1221. The first region 1221 covers the first sidewall of the first groove 121, and the second region 1222 overlaps the surface of the target insulating layer away from the base substrate, which helps reduce the risk of peeling of the reflective portion 122. In some embodiments, the width w of the bottom of the first groove 121 can be approximately 4 to 6 microns, such as 4 microns, 5 microns, or 6 microns, the line width D of the target signal line can be approximately 7 to 10 microns, such as 7 microns, 8 microns, 9 microns, or 10 microns, and the width d of the second region 1222 can be approximately 2 to 3 microns, such as 2 microns, 2.5 microns, or 3 microns.

[0073] In some embodiments, the target insulating layer may include an insulating layer located on a side of the target metal layer close to the base substrate and in contact with the target metal layer. In a direction perpendicular to the base substrate, the depth of the first groove 121 may be greater than or equal to the thickness of the insulating layer located on a side of the target metal layer close to the base substrate and in contact with the target metal layer, and less than the sum of the thicknesses of all insulating layers on the side of the target metal layer close to the base substrate. For example, there are three insulating layers below the target metal layer, namely, insulating layer A, insulating layer B, and insulating layer C from top to bottom. The first groove 121 is opened on the surface of insulating layer A away from the base substrate, that is, the notch of the first groove is located on the surface of insulating layer A away from the base substrate; the depth of the first groove 121 may be greater than or equal to the thickness of insulating layer A and less than or equal to the sum of the thicknesses of insulating layer A and insulating layer B; or, the depth of the first groove 121 may also be greater than the sum of the thicknesses of insulating layer A and insulating layer B and less than the sum of the thicknesses of insulating layer A, insulating layer B, and insulating layer C.

[0074] FIG5 shows a schematic diagram of a stacked structure of an array substrate according to some embodiments of the present disclosure. As shown in FIG5 , the array substrate 10 may include: a base substrate 101 , and a driving circuit layer 210 and a light emitting structure layer 220 stacked on the base substrate 101 .

[0075] The base substrate 101 is made of a transparent substrate material to transmit light emitted by the bottom-emitting light-emitting device 160. In some embodiments, the base substrate 101 may be a rigid transparent substrate, such as a glass substrate, a PMMA (Polymethyl methacrylate) substrate, or a silicon substrate. In other embodiments, the base substrate 101 may be a flexible transparent substrate, such as a PET (Polyethylene terephthalate) substrate, a PEN (Polyethylene naphthalate diformic acid glycol ester) substrate, or a PI (Polyimide) substrate.

[0076] In some embodiments, the array substrate 10 may further include a buffer layer 103 located on a side of the base substrate 101 close to the driving circuit layer 210. For example, the buffer layer 103 may be made of one or more inorganic insulating materials such as silicon nitride and silicon oxide.

[0077] The light emitting structure layer 220 includes a plurality of bottom-emitting light emitting devices 160 arranged in an array. In some embodiments, the light emitting device 160 may be an electroluminescent device, such as an organic light emitting diode (OLED) device or a quantum dot light emitting diode (QLED).

[0078] Taking the light-emitting device 160 as an OLED device as an example, each light-emitting device 160 may include a first electrode 161, a light-emitting functional layer 162, and a second electrode 163, which are sequentially stacked in a direction away from the base substrate 101. For a bottom-emitting light-emitting device 160, the first electrode 161 is a transparent electrode, and the second electrode 163 is a reflective electrode. One of the first electrode 161 and the second electrode 163 serves as the anode of the light-emitting device 160, and the other serves as the cathode. In some embodiments, the first electrode 161 serves as the anode, and the second electrode 163 serves as the cathode. In some embodiments, the first electrode 161 may be made of a transparent electrode material, such as a transparent conductive oxide film such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide). In some embodiments, the second electrode 163 may be made of a reflective metal material such as magnesium (Mg) or aluminum (Al).

[0079] The light-emitting functional layer 162 may include at least: a light-emitting layer (EML), which emits light of a specific color under the drive of the first electrode 161 and the second electrode 163. The light-emitting color of the light-emitting device 160 is determined by the light-emitting layer material. In some embodiments, each light-emitting device 160 may be a light-emitting device 160 that emits white light, and color display is achieved through further color filtering. In other embodiments, the light-emitting device 160 included in the red sub-pixel (R) may be a light-emitting device that emits red light, the light-emitting device 160 included in the blue sub-pixel (B) may be a light-emitting device that emits blue light, the light-emitting device 160 included in the green sub-pixel (G) may be a light-emitting device that emits green light, and the light-emitting device 160 included in the white sub-pixel (W) may be a light-emitting device that emits white light. It can be set according to the needs of the actual product, and the present disclosure does not limit this.

[0080] In some embodiments, the light-emitting functional layer 162 may further include any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL) and an electron injection layer (EIL), which can be configured according to actual needs and are not limited in this disclosure.

[0081] In some embodiments, the light-emitting structure layer 220 may further include a pixel-defining layer 170 having a plurality of pixel openings 171. Each pixel opening 171 is configured to define a light-emitting area of ​​a light-emitting device 160. The reflective structure 120 is located on a side of the pixel-defining layer 170 that is close to the base substrate 101. The orthographic projection of the reflective portion 122 on the base substrate 101 is located outside the orthographic projection range of the pixel opening 171 on the base substrate 101. Each pixel opening 171 exposes at least a portion of the first electrode 161 of the corresponding light-emitting device 160. At least a portion of the light-emitting function layer 162 is located within the corresponding pixel opening 171 and is electrically connected to the corresponding first electrode 161.

[0082] The driving circuit layer 210 is located on the side of the light-emitting structure layer 220 close to the base substrate 101, and is at least used to form a driving circuit corresponding to each light-emitting device 160. The driving circuit is electrically connected to the first electrode 161 of the light-emitting device 160 to drive the light-emitting device 160 to emit light. Taking the application in display products as an example, the driving circuit layer 210 can be stacked between the base substrate 101 and the pixel defining layer 170, and is at least configured to form a pixel driving circuit for each sub-pixel. Of course, in addition to the pixel driving circuit, according to the needs of the actual application scenario, the driving circuit layer 210 can also be configured to form other functional circuits. For example, when used in a display product with a fingerprint recognition function, the driving circuit layer 210 can also be configured to form a photosensitive element, and the present disclosure does not limit this.

[0083] In some embodiments, the driving circuit layer 210 may include: an active layer 111, a first insulating layer 112, a first metal layer 113, a second insulating layer 114, and at least one second metal layer 115 stacked on the base substrate 101. The at least one second metal layer 115 may be one, two, or three, etc., depending on the actual product requirements, and this embodiment does not impose any limitation on this.

[0084] The transistors and capacitors included in the pixel driving circuit can be formed by the various layers of the driving circuit layer 210. In some application scenarios, for ease of distinction, the first insulating layer 112 can also be referred to as a gate dielectric layer (GI); the first metal layer 113 can also be referred to as a gate metal layer (Gate), for example, which can be used to provide a gate line GL and a gate of a transistor; the second insulating layer 114 can also be referred to as an interlayer insulating layer (ILD), and the second metal layer 115 can also be referred to as a source-drain metal layer (SD), for example, which can be used to provide a data line DL, a first power line VDD, a second power line VSS, and the source and drain of a transistor. When there are multiple second metal layers 115, they can be referred to as the first source-drain metal layer (SD1), the second source-drain metal layer (SD2), and so on, from bottom to top.

[0085] In some embodiments, the array substrate 10 may further include: a light shielding layer 102 disposed on a side of the base substrate 101 close to the buffer layer 103. The orthographic projection of the active layer 111 on the base substrate 101 may be located within the orthographic projection range of the light shielding layer 102 on the base substrate 101, thereby shielding the channel region of the transistor, preventing light from affecting the channel, reducing leakage current, and helping to reduce the impact of light on transistor characteristics. In some embodiments, the light shielding layer 102 may be made of a metal material such as molybdenum (Mo) metal, so that the light shielding layer 102 has light shielding properties and conductive properties. In some embodiments, the light shielding layer 102 may also serve as a signal transfer layer, and the light shielding layer 102 may be connected through vias to achieve the transfer of some signals. In some embodiments, the reflective portion 122 is provided separately from the target signal line, and the reflective portion 122 may be electrically connected to the light shielding layer 102 through vias to avoid charge accumulation in the independently provided reflective portion 122.

[0086] It is understandable that, in the display area of ​​the array substrate 10, in addition to signal wiring, devices such as transistors included in the corresponding driving circuits are also arranged around the light-emitting areas of each light-emitting device 160. In some embodiments, the above-mentioned reflective structure 120 is provided on the side close to the light-emitting area of ​​at least a portion of the transistors in the display area of ​​the array substrate 10. In this way, the light emitted by the light-emitting device 160 that deviates from the normal viewing direction can be reflected back to the second electrode 163 (such as the cathode) through the reflective portion 122 in these reflective structures 120, thereby improving the luminous brightness while blocking at least a portion of the light incident on the transistor, which is beneficial to reducing the impact of light on the transistor characteristics, improving the stability of the transistor characteristics, and thus improving the quality of the array substrate 10.

[0087] In some embodiments, the target metal layer may include one or more of the following metal layers: a first metal layer 113 and at least one second metal layer 115 , which may be configured according to actual product requirements.

[0088] In some embodiments, there is only one second metal layer 115, and the target metal layer includes the second metal layer 115. Accordingly, the target insulating layer may include a second insulating layer 114. As shown in FIG5 , the surface of the second insulating layer 114 away from the base substrate 101 is provided with the first groove 121. In other words, the opening of the first groove 121 is located on the surface of the second insulating layer 114 away from the base substrate 101. For example, during the preparation process, after forming the second insulating layer 114, an etching process may be used to open a hole at a predetermined position in the second insulating layer 114 to form the first groove 121.

[0089] The buffer layer 103 can be formed between the active layer 111 and the base substrate 101, and can contact the second insulating layer 114 outside the transistor region. The depth of the first groove 121 defined in the second insulating layer 114, along a direction perpendicular to the base substrate 101, can be greater than or equal to the thickness of the second insulating layer 114, and less than or equal to the sum of the thicknesses of the second insulating layer 114 and the buffer layer 103. This helps ensure the height of the first sidewall 1211, thereby ensuring that the reflective portion 122 disposed on the first sidewall 1211 has a sufficient reflection length.

[0090] For example, in the process of opening a hole in the second insulating layer 114 through an etching process to form the first groove 121, over-etching may occur, so that the bottom of the first groove 121 extends to the buffer layer 103 below the second insulating layer 114, slightly lower than the surface of the buffer layer 103 on the side away from the base substrate 101, as shown in Figure 5.

[0091] As shown in Figure 5 , light emitted from bottom-emitting light-emitting device 160 in the normal viewing direction (e.g., light L1 in Figure 5 ) can pass through the film layers directly below light-emitting device 160 and exit. Meanwhile, at least a portion of light that deviates from the normal viewing direction (e.g., light L2 in Figure 5 ) can be incident on reflective portion 122, reflected back to second electrode 163 by reflective portion 122, and then reflected by second electrode 163 to exit from the corresponding light-emitting region of light-emitting device 160, thereby effectively improving the luminous brightness and also helping to reduce crosstalk between adjacent sub-pixels. The dotted line with an arrow in Figure 5 represents the transmission path of the light reflected from reflective portion 122.

[0092] FIG6 shows a schematic diagram of the stacked structure of an array substrate according to other embodiments of the present disclosure. In other embodiments, there are two second metal layers (such as 115a and 115b shown in FIG6 ), and the driving circuit layer 210 further includes a third insulating layer 116 located between the two second metal layers 115a and 115b and a fourth insulating layer 117 located on the second metal layer 115 relatively further away from the base substrate 101, as shown in FIG6 . In some application scenarios, the third insulating layer 116 may also be referred to as a passivation layer (PVX), and the two second metal layers 115 are respectively referred to as a first source-drain metal layer (SD1) and a second source-drain metal layer (SD2) from bottom to top.

[0093] In some embodiments, the target metal layer may include the second metal layer 115 b relatively farther away from the base substrate 101 among the two second metal layers 115 a and 115 b , such as the second source-drain metal layer ( SD2 ). Accordingly, the target insulating layer may include the third insulating layer 116 .

[0094] As shown in Figure 6, the first groove 121 is defined on the surface of the third insulating layer 116 away from the base substrate 101. In some embodiments, the depth of the first groove 121 defined in the third insulating layer 116, along a direction perpendicular to the base substrate 101, can be greater than or equal to the thickness of the third insulating layer 116, and less than or equal to the sum of the thicknesses of the third insulating layer 116, the second insulating layer 114, and the buffer layer 103. This helps increase the depth range of the first groove 121, thereby increasing the area of ​​the reflective portion 122 and enhancing the light reflection capability.

[0095] In some embodiments, the target insulating layer may include only the third insulating layer 116, and the depth of the first groove 121 may be equal to the thickness of the third insulating layer 116. Of course, considering the possibility of over-etching during actual fabrication, the depth of the first groove 121 may be slightly greater than the thickness of the third insulating layer 116, that is, the bottom of the groove is slightly lower than the surface of the second insulating layer 114 at that location away from the base substrate 101. In other embodiments, the target insulating layer may also include the third insulating layer 116 and the second insulating layer 114, and the designed depth of the first groove 121 may be greater than the thickness of the third insulating layer 116 and less than or equal to the sum of the thicknesses of the third insulating layer 116 and the second insulating layer 114.

[0096] Taking the example of a design depth of the first groove 121 being the sum of the thicknesses of the third insulating layer 116 and the second insulating layer 114, the opening of the first groove 121 formed in the third insulating layer 116 is located on the surface of the third insulating layer 116 away from the base substrate 101, and the entire first groove 121 penetrates the third insulating layer 116 and the second insulating layer 114. Of course, during actual fabrication, considering the problem of over-etching, the actual depth of the first groove 121 may be slightly greater than the sum of the thicknesses of the third insulating layer 116 and the second insulating layer 114, that is, the bottom of the groove may be slightly lower than the surface of the buffer layer 103 away from the base substrate 101 at its location. This allows the reflective portion 122 provided on the first sidewall 1211 to extend from the buffer layer 103 to the third insulating layer 116, thereby reflecting more light emitted from directions deviating from the normal viewing angle, which is conducive to further improving the luminous brightness.

[0097] It should be noted that, in other embodiments, the target metal layer may also include the second metal layer 115a of the two second metal layers 115a and 115b that is relatively closer to the base substrate 101, such as the first source and drain metal layer (SD1). It can actually be set according to product needs, and this disclosure does not impose any restrictions on this.

[0098] In some other embodiments, the target metal layer may include a first metal layer 113, and accordingly, the target insulating layer may include a buffer layer 103. The first groove 121 is defined on a surface of the buffer layer 103 that is away from the base substrate 101. In a direction perpendicular to the base substrate 101, the depth of the first groove 121 defined in the buffer layer 103 is greater than or equal to the thickness of the buffer layer 103, and less than the sum of the thicknesses of the buffer layer 103 and the base substrate 101.

[0099] In some embodiments, the array substrate 10 may further include a color filter layer disposed between the driving circuit layer 210 and the light-emitting structure layer 220. The color filter layer includes color filter units 141 disposed corresponding to at least a portion of the light-emitting devices 160. For example, the color filter units 141 may include a red filter unit, a blue filter unit, and a green filter unit. When the array substrate 10 is used for display, in some embodiments, each pixel unit P includes a red sub-pixel (R), a blue sub-pixel (B), a green sub-pixel (G), and a white sub-pixel (W), and the light-emitting device 160 included in each sub-pixel is a white light-emitting device 160. In this case, a red-green light unit, a blue filter unit, and a green filter unit are disposed below the light-emitting devices 160 of the red sub-pixel (R), the blue sub-pixel (B), and the green sub-pixel (G), respectively, so that the red sub-pixel (R) emits red light, the blue sub-pixel (B) emits blue light, and the green sub-pixel (G) emits green light, thereby achieving color display.

[0100] Figure 7 shows a schematic diagram of the layout of a single color filter unit 141 according to some embodiments of the present disclosure. As shown in Figure 7, the color filter unit 141 can cover the light-emitting area and the reflective structure 120 disposed around the light-emitting area, so that the light emitted by the light-emitting area and the light reflected by the reflective portion 122 can both be filtered by the color filter unit 141.

[0101] In some embodiments, the array substrate 10 further includes a second groove 131 located on the side of the color filter layer adjacent to the base substrate 101. The orthographic projection of the second groove 131 on the base substrate 101 is within the orthographic projection of the first groove 121 on the base substrate 101. In some embodiments, if the second insulating layer 114 includes the first groove 121, a hole can be opened in the insulating layer covering the first groove 121, such as the third insulating layer 116 or the fourth insulating layer 117, to form the second groove 131. For example, if the insulating layer covering the first groove 121 is the third insulating layer 116, the hole is located within the first groove 121 and penetrates the third insulating layer 116, thereby forming a superimposed hole penetrating the second insulating layer 114 and the third insulating layer 116, i.e., the second groove 131, as shown in FIG5 . In a direction perpendicular to the base substrate 101, the depth of the second groove 131 is greater than the depth of the first groove 121 and less than the sum of the thicknesses of all insulating layers of the color filter layer adjacent to the base substrate 101.

[0102] In addition to covering the area directly opposite the light-emitting area, the color filter unit 141 may also cover the sidewalls and bottom of the second groove 131. In some embodiments, the orthographic projections of the light-emitting area of ​​the light-emitting device 160, the notch of the first groove 121, and the notch of the second groove 131 on the base substrate 101 are located within the orthographic projection range of the color filter unit 141 on the base substrate 101.

[0103] The sidewall of the second groove 131 away from the light-emitting area is a second sidewall 1311. In some embodiments, the second sidewall 1311 is also inclined away from the light-emitting area relative to a direction perpendicular to the base substrate 101. In some embodiments, the slopes of the first sidewall 1211 and the second sidewall 1311 can be substantially the same, that is, the second sidewall 1311 can be parallel to the first sidewall 1211.

[0104] By providing the second groove 131, the area of ​​the color filter unit 141 covering the reflective portion 122 can be formed into an inclined structure as shown in Figure 5. On the one hand, the light transmission distance between the reflective portion 122 and the color filter unit 141 can be shortened, so that as much light reflected by the reflective portion 122 as possible can pass through the color filter unit 141, which is beneficial to reducing the color mixing anomaly caused by the reflected light being white light; on the other hand, the inclined color filter unit 141 can also have a certain reflective effect, which can reflect a portion of the light emitted by the bottom-emitting light-emitting device 160 that deviates from the normal viewing angle direction back to the second electrode 163 and then emit it, which is beneficial to further improve the luminous brightness.

[0105] In some embodiments, along a direction perpendicular to the first side wall 1211, the distance between the first side wall 1211 of the first groove 121 and the second side wall 1311 of the second groove 131 is greater than the thickness of the reflective portion 122, and an insulating protective layer is provided between the reflective portion 122 covered on the first side wall 1211 and the color filter unit 141 covered on the second side wall 1311 to reduce the risk of oxidation of the reflective portion 122.

[0106] Taking the example of forming a first groove 121 by opening a hole in the second insulating layer 114 and forming a second groove 131 by opening a hole in the third insulating layer 116, during preparation, after depositing the insulating material used to obtain the third insulating layer 116, the bottom of the first groove 121 and the insulating material covering other side walls can be etched away, and the insulating material covering the reflecting portion 122 on the first side wall 1211 is retained as the above-mentioned insulating protective layer to protect the reflecting portion 122 from oxidation.

[0107] In some embodiments, the opening of the second groove 131 is located above the opening of the first groove 121, and the bottom of the second groove 131 is flush with or lower than the bottom of the first groove 121. As shown in FIG5 , the bottom of the second groove 131 is slightly lower than the bottom of the first groove 121. This facilitates the color filter unit 141 disposed on the second sidewall 1311 to cover the bottom to the top of the reflective portion 122 disposed on the first sidewall 1211, thereby more comprehensively filtering the light reflected by the reflective portion 122.

[0108] In some embodiments, the array substrate 10 may further include: a planar layer 150 , which is disposed on a side of the color filter layer away from the base substrate 101 , as shown in FIG. 5 .

[0109] In some embodiments, the array substrate 10 may further include: an encapsulation layer 180, which is arranged on the side of the light-emitting structure layer 220 away from the base substrate 101, as shown in FIG5 , to protect the light-emitting device 160 from water and oxygen corrosion. In some embodiments, the material of the encapsulation layer 180 may include one or more combinations of inorganic encapsulation materials such as silicon oxide or silicon nitride, and the thickness may be 1 to 1.5 microns, such as 1 micron, 1.3 microns or 1.5 microns. In other embodiments, the encapsulation layer 180 may also be a multi-layer structure, for example, it may be two inorganic encapsulation layers 180 alternately stacked, or it may include an inorganic encapsulation layer 180, an organic encapsulation layer 180 and an inorganic encapsulation layer 180 stacked in sequence. In actual implementation, it can be set according to the needs of the product, and the present disclosure does not limit this.

[0110] Figure 8 shows a flow chart of a method for preparing an array substrate according to some embodiments of the present disclosure, which is used to prepare the array substrate 10 provided in any of the above embodiments. As shown in Figure 8 , the preparation method may include the following steps S101 to S103.

[0111] Step S101, forming a target insulating layer on a base substrate;

[0112] Step S102 , forming a reflective structure on the target insulating layer, the reflective structure comprising: a first groove and a reflective portion disposed on a first sidewall of the first groove; and

[0113] In step S103, a light-emitting structure layer is formed on the target insulating layer. The light-emitting structure layer includes a plurality of bottom-emitting light-emitting devices arranged in an array. The above-mentioned reflective structure is located on the light-emitting side of the light-emitting device. The first sidewall of the first groove is the sidewall away from the light-emitting area of ​​the light-emitting device.

[0114] In steps S101 to S103 above, the reflective portion 122 is tilted relative to the surface of the base substrate 101, and the distance between the bottom end of the reflective portion 122 and the light-emitting area is shorter than the distance between the top end of the reflective portion 122 and the light-emitting area. The bottom end of the reflective portion 122 is the end closest to the base substrate 101. The orthographic projection of the reflective portion 122 on the base substrate 101 is outside the orthographic projection range of the light-emitting area of ​​the light-emitting device 160 on the base substrate 101.

[0115] In order to more clearly illustrate the preparation process, an exemplary preparation process of the array substrate 10 is described below by taking the preparation of the array substrate 10 shown in FIG. 5 as an example with reference to FIG. 9 to FIG. 12 .

[0116] A layer of light-shielding metal (LS) is deposited on the provided base substrate 101 to obtain a light-shielding metal film. In some embodiments, the light-shielding metal may be molybdenum (Mo) metal, and the thickness of the light-shielding metal film may be 300 to 700 angstroms. The light-shielding metal film is subjected to a light-shielding mask process to define a light-shielding pattern, and then wet etching and wet stripping are performed to form a light-shielding pattern, that is, the above-mentioned light-shielding layer 102 is formed. A buffer layer is deposited on the light-shielding layer 102. For example, the buffer layer 103 material may include a combination of silicon nitride and silicon oxide with a thickness of 0.3 to 0.5 microns. After the deposition is completed, the buffer layer 103 pattern is formed using photolithography technology.

[0117] An active layer 111 is deposited on the buffer layer 103 and patterned using wet photolithography. The active layer 111 can be made of, for example, indium gallium zinc oxide (IGZO) and have a thickness of 0.05 to 0.08 microns. Next, a first insulating layer 112, also known as a gate insulator (GI), is deposited. It can be made of, for example, silicon oxide and have a thickness of 0.1 to 0.2 microns. Next, a first metal layer 113, also known as a gate metal layer (Gate), is deposited. For example, a metal such as copper (Cu) can be used and have a thickness of 0.3 to 0.5 microns. A gate mask is then deposited and wet photolithography is used to form the gate and gate trace patterns. For example, using copper as the gate metal layer, wet etching can be performed using a solution such as hydrogen peroxide. After the gate wet etching is complete, the gate mask is retained for dry etching of the GI. In some embodiments, the GI can be dry-etched using a mixture of tetrafluoromethane (CF4) and oxygen (O2). For example, the flow rate of CF 4 may be 2000-2500 sccm (standard cubic centimeter per minute), and the flow rate of O 2 may be 1000-1500 sccm.

[0118] After the GI dry etching is completed, the two ends of the pre-defined channel area in the active layer 111 are subjected to conductor processing to form source-drain contact areas for connecting the source and drain respectively. In some embodiments, the conductorization can be performed using ammonia (NH3) or helium (He). After the conductorization is completed, wet stripping is performed to deposit a second insulating layer 114, which can also be called an interlayer insulating layer (ILD). For example, the material can be silicon oxide and the thickness can be 0.6 to 0.8 microns. The above-mentioned first groove 121 is opened in the ILD, and the first groove 121 is located around the pre-defined light-emitting area. It should be noted that the structure of the first groove 121 can refer to the relevant description above and will not be repeated here. In addition to the first groove 121, it is also necessary to open signal connection holes in the ILD, such as connection holes for respectively connecting the source and drain to the source-drain contact areas. The distribution of the signal connection holes can be set according to the needs of the actual product and will not be described in detail here.

[0119] In some embodiments, the width w of the bottom of the first groove 121 can be 4 to 6 microns, such as 4 microns, 5 microns, or 6 microns, and the length l can be 80 to 110 microns, such as 80 microns, 90 microns, 100 microns, or 110 microns. It should be noted that the first groove 121 can be arranged according to the shape and size of the light-emitting area of ​​each light-emitting device 160 in the actual product, as well as the distribution of devices and traces around the light-emitting area, and this disclosure does not impose any restrictions on this.

[0120] A layer of metal, such as copper or aluminum, is deposited on the ILD with a thickness of 0.7 to 0.8 microns, and the metal layer is patterned to form a second metal layer 115, which may also be referred to as a source-drain metal layer (SD). FIG9 shows a schematic diagram of the structure after the source-drain metal layer is formed according to some embodiments of the present disclosure. In some embodiments, the source-drain metal layer (SD) may include: SD metal traces and the source and drain of each transistor included in the driving circuit. For example, the SD metal traces may include: data lines DL, first power lines VDD, and second power lines VSS, etc., signal lines extending along the second direction. Along the first direction, the SD metal trace portions closest to each other on both sides of each light-emitting area are placed on the first sidewall 1211 of the first groove 121 provided therebelow, serving as the reflective portion 122 in the above-mentioned S102. α in FIG9 represents the slope angle of the reflective portion 122.

[0121] In some embodiments, the patterning of the metal layer deposited on the ILD may form, in addition to forming a source / drain metal layer (SD), a first metal pattern and a second metal pattern. The first metal pattern and the second metal pattern are located on either side of each light-emitting region along the second direction. The first metal pattern and the second metal pattern partially overlap the first sidewall 1211 of the first recess 121 disposed thereunder, serving as the reflective portion 122 in S102 above.

[0122] Next, a third insulating layer 116, also called a passivation layer (PVX), is deposited. For example, the passivation layer material can be silicon oxide and can be 0.5 to 0.6 microns thick. Then, a PVX mask is set. A PVX hole mask is set at the same position as the ILD hole below the SD metal traces (such as the data line DL, the first power line VDD, or the second power line VSS, etc.) closest to the light-emitting area along the first direction. In order to retain the PVX material covering the reflective portion 122, the PVX hole can be slightly offset from the ILD hole and can be slightly smaller than the ILD hole. The PVX layer is then etched. In some embodiments, a mixture of CF4 and O2 can be used to dry-etch the PVX layer. For example, the flow rate of CF4 can be 2000 to 2500 sccm, and the flow rate of O2 can be 800 to 1000 sccm. After PVX dry etching, wet stripping is performed. Considering the risk of oxidation when the reflective portion 122 is exposed, the PVX covering the reflective portion 122 is retained, while the PVX on the bottom of the first groove 121 and other side walls is etched to form an ILD+PVX superimposed hole, that is, the above-mentioned second groove 131 is formed. Figure 10 shows a schematic diagram of the structure after the second groove 131 is formed according to some embodiments of the present disclosure. In some embodiments, considering the influence of over-etching, the depth of the ILD+PVX superimposed hole can be 0.9 to 1.0 microns, such as 0.9 microns or 1 micron. It should be noted that the structure of the second groove 131 can refer to the relevant description above and will not be repeated here.

[0123] After that, a color filter process is performed to sequentially form a color filter layer and a flat layer 150. FIG11 shows a schematic diagram of the structure after forming the color filter layer and the flat layer 150 according to some embodiments of the present disclosure. The color filter layer includes a plurality of color filter units 141, and the color filter unit 141 can cover the ILD holes, PVX holes and the area above the reflective portion 122 arranged thereunder. As shown in FIG11 , by providing the above-mentioned second groove 131, the light transmission distance between the reflective portion 122 and the corresponding color filter unit 141 can be shortened, so that the light reflected by the reflective portion 122 can be filtered by the color filter unit 141 as much as possible, thereby helping to avoid the problem of color mixing anomalies caused by the reflected light being white light. The flat layer 150 can be made of an organic material such as a resin material to achieve a better flatness effect.

[0124] A transparent conductive material for forming the first electrode 161 is deposited on the flat layer 150. For example, a metal oxide transparent conductive material such as ITO or IZO can be used. The first electrode 161 of each light-emitting device 160 is then formed through a patterning process. Next, a pixel definition layer 170 (PDL) process is performed. For example, a PI-like material can be used for coating, exposure, and development to form a pixel opening 171 to expose at least a portion of the first electrode 161. Figure 12 shows a schematic structural diagram after the first electrode 161 and the pixel definition layer 170 are formed according to some embodiments of the present disclosure.

[0125] The array substrate 10 shown in FIG5 is obtained by sequentially forming a light-emitting functional layer 162, a second electrode 163, and an encapsulation layer 180 on the first electrode 161. For example, the light-emitting functional layer 162 may include a hole transport layer, a hole injection layer, a light-emitting layer, an electron transport layer, and an electron injection layer. The second electrode 163 may be made of a reflective and conductive metal such as magnesium or aluminum. The encapsulation layer 180 may be made of a combination of silicon nitride (SiN) and silicon oxide (SiO) and may be 1 to 1.5 microns thick.

[0126] In addition, Figure 13 shows a schematic diagram of the structure of a display device according to some embodiments of the present disclosure. As shown in Figure 13, some embodiments of the present disclosure provide a display device 20, including the array substrate 10 provided in any of the embodiments described above. The display device 20 can be, for example, a monitor, a television, a tablet computer, a laptop computer, a mobile phone, a digital photo frame, a navigation system, or any other product or component with a display function. Of course, the display device 20 provided in the embodiments of the present disclosure is not limited to the types listed above.

[0127] It should be noted that the drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures can refer to general designs. In the absence of conflict, the embodiments of the present disclosure and the features therein can be combined with each other to obtain new embodiments.

[0128] Although some embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiment and all changes and modifications that fall within the scope of the present disclosure.

Claims

1. An array substrate, comprising: A substrate; A target insulating layer disposed on one side of the substrate; A light-emitting structure layer disposed on a side of the target insulating layer away from the substrate, the light-emitting structure layer including a plurality of bottom-emitting light-emitting devices arranged in an array; And A reflection structure on a light-emitting side of the light-emitting device, the reflection structure including: a first groove and a reflection portion disposed on a first sidewall of the first groove, the first groove being located in the target insulating layer, the first sidewall being a sidewall away from a light-emitting region of the light-emitting device, the reflection portion being inclined with respect to a surface of the substrate, a distance from a bottom end of the reflection portion to the light-emitting region being less than a distance from a top end of the reflection portion to the light-emitting region, the bottom end being an end close to the substrate, and a positive projection of the reflection portion on the substrate being outside a positive projection range of the light-emitting region on the substrate.

2. The array substrate according to claim 1 further comprises: A target metal layer located on a side of the target insulating layer close to the light-emitting structure layer; The target metal layer includes: a target signal line, at least a part of a region of the target signal line close to the light-emitting region being overlapped on the first sidewall as the reflection portion.

3. The array substrate according to claim 2, wherein, The target signal line includes one or more of: a data line, a first power line, a second power line, and a gate line.

4. The array substrate according to claim 2, wherein, The target signal line includes: a gate line disposed along a first direction and a data line disposed along a second direction, the first direction intersecting the second direction, the reflection portion on a side close to the gate line being a part of the gate line, the reflection portion on a side close to the data line being a part of the data line, and the gate line and the data line being on different sides of the light-emitting region.

5. The array substrate according to claim 4, wherein, The reflection portion on a side close to the gate line has a first slope angle, and the reflection portion on a side close to the data line has a second slope angle, the first slope angle being less than the second slope angle.

6. The array substrate according to claim 1 further includes: A target metal layer located on a side of the target insulating layer close to the light-emitting structure layer; The target metal layer includes: a target signal line, the reflection portion being disposed on the same layer as the target metal layer, and the reflection portion being located in an interval region between the light-emitting region and the target signal line close to the light-emitting region.

7. The array substrate according to any one of claims 2-6, wherein, The target insulating layer includes an insulating layer located on a side of the target metal layer close to the substrate and in contact with the target metal layer; In a direction perpendicular to the substrate, a depth of the first groove is greater than or equal to a thickness of the insulating layer located on a side of the target metal layer close to the substrate and in contact with the target metal layer, and less than a sum of thicknesses of all insulating layers on a side of the target metal layer close to the substrate.

8. The array substrate according to any one of claims 2-6 further comprises: A driving circuit layer located on a side of the light-emitting structure layer close to the substrate; The driving circuit layer includes: an active layer, a first insulating layer, a first metal layer, a second insulating layer, and at least one second metal layer stacked on the substrate; the target metal layer includes one or more of the following metal layers: The first metal layer and the at least one second metal layer.

9. The array substrate according to claim 8, wherein, The at least one second metal layer is one, the target metal layer includes the second metal layer, and a first groove is formed in a surface of the second insulating layer away from the substrate; The array substrate further includes: a buffer layer between the active layer and the substrate; along a direction perpendicular to the substrate, a depth of the first groove formed in the second insulating layer is greater than or equal to a thickness of the second insulating layer and less than or equal to a sum of the thicknesses of the second insulating layer and the buffer layer.

10. The array substrate according to claim 8, wherein, The at least one second metal layer is two, and the target metal layer includes a second metal layer that is relatively farther from the substrate among the two second metal layers; The driving circuit layer further includes a third insulating layer between the two second metal layers, and the array substrate further includes: a buffer layer between the active layer and the substrate; A first groove is formed in a surface of the third insulating layer away from the substrate; along a direction perpendicular to the substrate, a depth of the first groove formed in the third insulating layer is greater than or equal to a thickness of the third insulating layer and less than or equal to a sum of the thicknesses of the third insulating layer, the second insulating layer, and the buffer layer.

11. The array substrate according to claim 8 further includes: A buffer layer between the active layer and the substrate; the target metal layer includes the first metal layer, a first groove is formed in a surface of the buffer layer away from the substrate, and along a direction perpendicular to the substrate, a depth of the first groove formed in the buffer layer is greater than or equal to a thickness of the buffer layer and less than a sum of the thicknesses of the buffer layer and the substrate.

12. The array substrate according to claim 8 further comprises: A color film layer disposed between the driving circuit layer and the light-emitting structure layer, the color film layer including color filter units corresponding to at least some of the light-emitting devices; The array substrate further includes: a second groove on a side of the color film layer close to the substrate, and a positive projection of the second groove on the substrate is within a positive projection range of the first groove on the substrate; The color filter units cover sidewalls and a bottom of the second groove, and positive projections of a light-emitting region of the light-emitting device, an opening of the first groove, and an opening of the second groove on the substrate are within a positive projection range of the color filter units on the substrate.

13. The array substrate according to claim 12, wherein, A sidewall of the second groove away from the light-emitting region is a second sidewall, and an insulating protection layer is provided between the reflection portion and the color filter units covering the second sidewall.

14. The array substrate according to claim 12, wherein, An opening of the second groove is above an opening of the first groove, and a bottom of the second groove is flush with or lower than a bottom of the first groove.

15. The array substrate according to claim 12, wherein, A sidewall of the second groove away from the light-emitting region is a second sidewall, and the second sidewall is parallel to the first sidewall.

16. The array substrate according to claim 1 further comprises: Transistors corresponding to each of the light-emitting devices, and the reflection structure is provided on a side of at least some of the transistors close to the light-emitting region.

17. The array substrate according to claim 1, wherein, The light-emitting structure layer further includes: a pixel defining layer having a plurality of pixel openings, and each pixel opening is configured to define a light-emitting region of one of the light-emitting devices; The reflection structure is located on the side of the pixel defining layer close to the substrate, and the orthographic projection of the reflection portion on the substrate is outside the orthographic projection range of the pixel opening on the substrate.

18. The array substrate according to claim 1, wherein, The reflection portion includes: a first region and a second region. The first region covers the first sidewall, and the second region is placed on the surface of the target insulating layer away from the substrate; the width of the second region is 2 to 3 micrometers.

19. The array substrate according to claim 1, wherein, The width of the bottom of the first groove is 4 to 6 micrometers; the slope angle of the reflection portion is 30 degrees to 45 degrees.

20. A method for manufacturing an array substrate, comprising: Forming a target insulating layer on a substrate; Forming a reflection structure on the target insulating layer, the reflection structure including: a first groove and a reflection portion disposed on the first sidewall of the first groove; and Forming a light-emitting structure layer on the target insulating layer, the light-emitting structure layer including a plurality of bottom-emitting light-emitting devices arranged in an array; Wherein, the reflection structure is located on the light-emitting side of the light-emitting device, the first sidewall is the sidewall away from the light-emitting region of the light-emitting device, the reflection portion is inclined with respect to the surface of the substrate, the distance from the bottom end of the reflection portion to the light-emitting region is less than the distance from the top end of the reflection portion to the light-emitting region, the bottom end is the end close to the substrate, and the orthographic projection of the reflection portion on the substrate is outside the orthographic projection range of the light-emitting region on the substrate.

21. A display device, comprising: The array substrate according to any one of claims 1-19.

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