Display panel and display device

Abstract

A display panel (100) and a display device (200). The display panel (100) comprises a display area (AA), a first bezel area (SA1), a second bezel area (SA2), and a binding area (BB), wherein the first bezel area (SA1) comprises corner areas (R). The display panel (100) further comprises: a plurality of pixel driving circuits (Q), a plurality of gate driving circuits (110), a plurality of GOA signal line groups (22), and a plurality of connection signal line groups (23). The GOA signal line groups (22) extend to the binding area (BB) via the corner areas (R). One connection signal line group (23) is electrically connected to at least one row of pixel driving circuits (Q), and is electrically connected to the plurality of gate driving circuits (110). In the same connection signal line group (23), some of connection signal lines (231) are located on a first source-drain metal layer (SD1), and the remaining connection signal lines (231) are located on a second source-drain metal layer (SD2). In each corner area (R), a first distance (D1) is formed between the orthographic projections, of a connection signal line group (23) and a GOA signal line group (22) that are adjacent, on a base substrate (10).

Description

Display panel and display device

[0001] This application claims priority to Chinese patent application No. 202410039567.3, filed on January 10, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0003] OLED (Organic Light Emitting Diode) display devices have become one of the most competitive and promising display devices due to their advantages such as self-luminescence, fast response speed, high brightness, full viewing angle, and flexible display. Summary of the Invention

[0004] In one aspect, a display panel is provided. The display panel comprises a display area, a first border area, a second border area, and a binding area, wherein the first border area includes a corner area. Along a first direction, the first border area is located on at least one side of the display area, and along a second direction, the second border area is located on one side of the display area, and the binding area is located on a side of the second border area away from the display area. The first direction and the second direction intersect. The display panel comprises a base substrate, a plurality of pixel drive circuits, a plurality of gate drive circuits, a plurality of GOA signal line groups, and a plurality of connection signal line groups. The plurality of pixel drive circuits are located on the base substrate in the display area, and the plurality of gate drive circuits are located on the base substrate in the first border area. One of the GOA signal line groups is electrically connected to one of the gate drive circuits, and the GOA signal line group extends along the first border area and extends to the binding area via the corner area. The plurality of connection signal line groups are located in the first border area, and one of the connection signal line groups is electrically connected to at least one row of the pixel drive circuits and to the plurality of gate drive circuits. The connecting signal line group includes a plurality of connecting signal lines. Within the same connecting signal line group, a portion of the connecting signal lines is located in the first source / drain metal layer, and another portion of the connecting signal lines is located in the second source / drain metal layer. The first source / drain metal layer is located between the base substrate and the second source / drain metal layer. Within the corner region, orthographic projections of adjacent connecting signal line groups and GOA signal line groups on the base substrate are spaced a first distance apart.

[0005] In some embodiments, the first pitch is greater than or equal to 1.5 μm.

[0006] In some embodiments, the display panel further comprises a gate metal layer, the gate metal layer being located between the base substrate and the first source / drain metal layer; the GOA signal line group being located in the gate metal layer. Within the corner region, along the direction in which the plurality of connection signal lines are arranged, the connection signal line closest to the GOA signal line group within the same connection signal line group is located in the second source / drain metal layer.

[0007] In some embodiments, in the same connecting signal line group: along the second direction, a plurality of connecting signal lines are alternately arranged in the second source-drain metal layer and the first source-drain metal layer.

[0008] In some embodiments, the display panel further includes a gate metal layer and a third source / drain metal layer, the gate metal layer being located between the base substrate and the first source / drain metal layer, the GOA signal line group being located in the gate metal layer, the third source / drain metal layer being located on a side of the second source / drain metal layer facing away from the first source / drain metal layer, and within the same connecting signal line group, a portion of the connecting signal lines are located in the third source / drain metal layer.

[0009] In some embodiments, in the corner area: along the arrangement direction of the plurality of connection signal lines, the connection signal line closest to the GOA signal line group in the same connection signal line group is located in the third source-drain metal layer.

[0010] In some embodiments, along the arrangement direction of the plurality of connection signal lines, in the same connection signal line group, the plurality of connection signal lines are alternately arranged in the third source-drain metal layer, the second source-drain metal layer and the first source-drain metal layer.

[0011] In some embodiments, in the same group of connection signal lines: along the arrangement direction of the plurality of connection signal lines, the minimum spacing between two adjacent connection signal lines ranges from 0.8 μm to 1.2 μm.

[0012] In some embodiments, the connection signal line located in the first source / drain metal layer is a first type of connection signal line, the connection signal line located in the second source / drain metal layer is a second type of connection signal line, and the connection signal line located in the third source / drain metal layer is a third type of connection signal line. Within the corner region, a minimum spacing between adjacent third type connection signal lines and first type connection signal lines is less than or equal to a minimum spacing between adjacent third type connection signal lines and second type connection signal lines.

[0013] In some embodiments, the plurality of first signal lines in the same first signal line group include: a plurality of initialization signal lines and a plurality of gate signal lines. In the corner region: in the same connection signal line group, the connection signal line electrically connected to the initialization signal line is located on a side of the connection signal line electrically connected to the gate signal line closer to the GOA signal line group.

[0014] In some embodiments, the display panel further includes a gate metal layer, the gate metal layer being located between the base substrate and the first source / drain metal layer; the GOA signal line group being located in the gate metal layer. The gate metal layer includes a first gate metal layer and a second gate metal layer, the first gate metal layer being located between the base substrate and the second gate metal layer. The GOA signal line group includes a plurality of GOA signal lines, and within the corner region, along the direction in which the plurality of GOA signal lines are arranged, the GOA signal line within the same GOA signal line group that is closest to the connection signal line group is located in the first gate metal layer.

[0015] In some embodiments, the display panel has a light-transmitting area, and the display area surrounds the light-transmitting area. The display panel also includes a plurality of data write signal lines, the plurality of data write signal lines being located in the display area, and one of the data write signal lines being electrically connected to at least one column of the pixel drive circuits. The plurality of data write signal lines include a target signal line, the target signal line including a connected lead portion and a winding portion, the lead portion extending along the second direction, and an extension line of the lead portion passing through the light-transmitting area, the winding portion being arranged along an edge of the light-transmitting area, and at least a portion of the winding portion extending outside the display area.

[0016] In some embodiments, the display panel further includes a light-emitting device layer and an auxiliary electrode. The light-emitting device layer is located on a side of the pixel driving circuit facing away from the base substrate, and in a direction away from the base substrate, the light-emitting device layer includes an anode layer, a light-emitting layer, and a cathode layer. The auxiliary electrode is located on at least one side of the display area, in the same layer as the anode layer, and is electrically connected to the cathode layer.

[0017] In some embodiments, a side of the auxiliary electrode close to the display area includes an opening facing the display area, and a portion of the winding portion located outside the display area in an orthographic projection on the base substrate extends into the opening.

[0018] In some embodiments, the display panel also includes a virtual signal line, which is on the same layer as the data write signal line, and the orthographic projection of the virtual signal line on the base substrate is located between the winding portion of the adjacent target signal line and the orthographic projection of the auxiliary electrode on the base substrate.

[0019] In another aspect, a display device is provided, comprising: a cover plate and a display panel according to any one of the above embodiments, wherein the cover plate is located on a light-emitting side of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0021] FIG1 is a structural diagram of a display device according to some embodiments;

[0022] FIG2 is a circuit structure diagram of a display device according to some embodiments;

[0023] FIG3 is an overall structural diagram of a display panel according to some embodiments;

[0024] FIG4 is a diagram illustrating a film layer structure of a display panel according to some embodiments;

[0025] FIG5 is an equivalent circuit diagram of a pixel driving circuit according to some embodiments;

[0026] FIG6 is a partial structural diagram of a display panel according to some embodiments;

[0027] FIG7 is an equivalent circuit diagram of a gate driving circuit according to some embodiments;

[0028] FIG8A is a partial structural diagram of a display panel according to some other embodiments;

[0029] FIG8B is a cross-sectional view taken along line EE' in FIG8A;

[0030] FIG9 is a partial enlarged view of M1 in FIG8A ;

[0031] FIG10 is a partial enlarged view of M2 in FIG8A ;

[0032] FIG11A is a partial structural diagram of a display panel according to yet other embodiments;

[0033] FIG11B is a cross-sectional view taken along the line FF' in FIG11A;

[0034] FIG12 is a partial enlarged view of M3 in FIG11A ;

[0035] FIG13A is a structural diagram of a corner region according to some embodiments;

[0036] FIG13B is a cross-sectional view taken along the line J-J' in FIG13A;

[0037] FIG14 is a partial enlarged view of W1 in FIG3 ;

[0038] FIG15 is a cross-sectional structural diagram of a display panel according to some other embodiments;

[0039] FIG16 is a diagram showing a film layer structure of a display panel according to some other embodiments;

[0040] FIG17 is a diagram showing a film layer structure of a display panel according to yet other embodiments. DETAILED DESCRIPTION

[0041] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0042] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0043] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0044] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. The term "coupled" indicates, for example, that two or more components are in direct physical or electrical contact. The term "coupled" or "communicatively coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0045] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0046] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0047] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0048] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0049] As used herein, "about," "substantially," or "approximately" includes the stated value and an average value that is within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

[0050] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0051] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0052] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0053] FIG1 is a structural diagram of a display device according to some embodiments. Referring to FIG1 , some embodiments of the present disclosure provide a display device 200 , which includes a display panel 100 .

[0054] Exemplarily, the display device 200 further includes a frame, a cover plate, and other electronic components, etc. The cover plate is located on the light-emitting side of the display panel 100 and plays a role in protecting the display panel 100 .

[0055] Exemplarily, the display device 200 may be an electroluminescent display device or a photoluminescent display device. If the display device is an electroluminescent display device, the electroluminescent display device may be an organic light emitting diode (OLED) or a quantum dot electroluminescent display device (QLED). If the display device is a photoluminescent display device, the photoluminescent display device may be a quantum dot photoluminescent display device.

[0056] Exemplarily, the display device 200 can be any display device that displays images, whether in motion (e.g., video) or fixed (e.g., still images), and whether text or images. More specifically, it is expected that the display device of the embodiments described can be implemented in or associated with a variety of electronic devices, such as (but not limited to) mobile phones, wireless devices, personal data assistants (PDAs), handheld or portable computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat-panel displays, computer monitors, automotive displays (e.g., odometer displays, etc.), navigation systems, cockpit controls and / or displays, displays of camera views (e.g., displays of rearview cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry), etc.

[0057] FIG. 2 is a circuit structure diagram of a display device according to some embodiments.

[0058] 2 , the display device 200 may include a display panel 100 and a driving control circuit 210 coupled to the display panel 100. The driving control circuit 210 is configured to provide an electrical signal to the display panel 100.

[0059] Exemplarily, the drive control circuit 210 may include a data drive circuit 201 (also referred to as a source driver IC), which is configured to provide a data drive signal (also referred to as a data signal) to the display panel 100. The drive control circuit 210 may also include a timing control circuit 202 (also referred to as a timing controller, TCON for short) coupled to the data drive circuit 201.

[0060] In some embodiments, the drive control circuit 210 may further include a gate drive circuit 110. In other embodiments, the gate drive circuit 110 may be integrated into the display panel 100. In other words, the display panel 100 may include the gate drive circuit 110. Since the gate drive circuit 110 is disposed on the display panel 100, the gate drive circuit 110 may also be referred to as a GOA (Gate Driver on Array). The following description will take the case where the gate drive circuit 110 is disposed on the display panel 100 as an example.

[0061] Specifically, the timing control circuit 202 can be coupled to the gate drive circuit 110 and can also be coupled to the data drive circuit 201. The timing control circuit 202 can be configured to receive display signals, which include, for example, power signals, video image signals, communication signals (for example, signals corresponding to the IIC communication protocol), and mode control signals (for example, mode control signals corresponding to the test mode, or mode control signals corresponding to the normal display mode). Among them, the video image signal is, for example, a MIPI (Mobile Industry Processor Interface) signal or an LVDS (Low-Voltage Differential Signaling) signal. The video image signal may include: image data and timing control signals. The image data includes, for example, pixel data of multiple sub-pixels, and the pixel data may be RGB data, etc. The timing control signal includes, for example, a data enable signal (Data Enable, which may be abbreviated as DE), a line synchronization signal (Hsync, which may be abbreviated as HS), and a field synchronization signal (Vsync, which may be abbreviated as VS).

[0062] The timing control circuit 202 may also be configured to, in response to the display signal, output a first control signal and image data to the data driving circuit 201, and output a second control signal to the gate driving circuit 110. The first control signal is configured to control the operating timing of the data driving circuit 201, and the second control signal is configured to control the operating timing of the gate driving circuit 110.

[0063] The data driving circuit 201 may be configured to convert received image data into data signals for a plurality of sub-pixels P (described below) in the display panel 100, and output the data signals to the pixel driving circuits Q (described below) in the corresponding sub-pixels P according to an operating sequence determined by a first control signal. The gate driving circuit 110 may be configured to output scan signals to the pixel driving circuits Q in the plurality of sub-pixels P according to an operating sequence determined by a second control signal.

[0064] FIG. 3 is an overall structural diagram of a display panel according to some embodiments.

[0065] Some embodiments of the present disclosure provide a display panel 100. As shown in FIG3 , the display panel 100 includes a display area (full name: Active Area, abbreviated as AA area; also referred to as an effective display area) AA, a first border area SA1, a second border area SA2, and a binding area BB. Along a first direction X, the first border area SA1 is located on at least one side of the display area AA. Along a second direction Y, the second border area SA2 is located on one side of the display area AA, and the binding area BB is located on a side of the second border area SA2 away from the display area AA. The first direction X and the second direction Y intersect.

[0066] In some examples, the first direction X and the second direction Y may be approximately perpendicular, and in this case, the angle between the first direction X and the second direction Y is approximately 90°. For example, the angle between the first direction X and the second direction Y may be 85°, 90°, or 95°.

[0067] In some examples, the first border area SA1 further includes at least one corner area R, and the boundary of the corner area R on the side of the first border area SA1 adjacent to the second border area SA2 is adjacent to the boundary of the second border area SA2. Exemplarily, along the second direction Y, both sides of the first border area SA1 include a corner area R.

[0068] As shown in FIG. 3 , the display panel 100 may include a plurality of sub-pixels P. The plurality of sub-pixels P are disposed in the display area AA. The plurality of sub-pixels may be arranged in an array.

[0069] The display panel 100 includes a plurality of sub-pixels P disposed in a display area AA. The display panel 100 can display a predetermined image in the display area AA through the light emitted by the plurality of sub-pixels P. Specifically, the plurality of sub-pixels P may include a plurality of sub-pixels emitting different luminous colors. Exemplarily, the plurality of sub-pixels P include a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first sub-pixel, the second sub-pixel, and the third sub-pixel respectively emit three primary colors of light. For example, the first sub-pixel may emit red light, the second sub-pixel may emit green light, and the third sub-pixel may emit blue light.

[0070] In some other examples, the display panel 100 may further include a white sub-pixel.

[0071] As shown in FIG3 , a sub-pixel P may include a light-emitting device O and a pixel driving circuit Q for driving the light-emitting device O to emit light.

[0072] The light-emitting device O may be one of an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a light-emitting diode (LED), and a liquid crystal light-emitting device, but is not limited thereto. The embodiments of the present disclosure do not limit the type of light-emitting device. That is, the light-emitting device O may be any other light-emitting device (e.g., a light-emitting device that emits light through discharge), as long as it can emit light so that the display panel 100 can display an image.

[0073] FIG. 4 is a diagram illustrating a film layer structure of a display panel according to some embodiments.

[0074] 3 and 4 , the display panel 100 includes a base substrate 10 , and a driving circuit layer 20 and a light emitting device layer 30 located on one side of the base substrate 10 .

[0075] In some examples, the substrate 10 may be a flexible substrate. For example, the substrate 10 may be made of an organic material. For example, the substrate 10 may be made of polyimide (PI), polycarbonate (PC), or polyvinyl chloride (PVC).

[0076] In other examples, the substrate 10 may be a rigid substrate, for example, a glass substrate or a PMMA (Polymethyl methacrylate) substrate.

[0077] The driving circuit layer 20 includes a plurality of pixel driving circuits Q (as shown in FIG3 ). The plurality of pixel driving circuits Q are arranged in multiple rows and columns within the display area AA. The pixel driving circuits Q arranged in a row along the first direction X are referred to as a pixel driving circuit row, and the pixel driving circuits Q arranged in a row along the second direction Y are referred to as a pixel driving circuit column.

[0078] The light-emitting device layer 30 is located on the side of the driver circuit layer 20 facing away from the base substrate 10. That is, the light-emitting device layer 30 is located on the side of the multiple pixel driver circuits Q facing away from the base substrate 10. The light-emitting device layer 30 includes multiple light-emitting devices O (as shown in FIG3 ). The multiple light-emitting devices O are electrically connected to the multiple pixel driver circuits Q.

[0079] In some examples, the plurality of pixel driving circuits Q and the plurality of light-emitting devices O may be electrically connected in a one-to-one correspondence. In other examples, one pixel driving circuit Q may be electrically connected to multiple light-emitting devices O, or multiple pixel driving circuits Q may be electrically connected to one light-emitting device O.

[0080] Below, the present disclosure takes the electrical connection between one pixel driving circuit Q and one light-emitting device O as an example to schematically illustrate the structure of the display panel 100 .

[0081] In some examples, the display panel 100 further includes an encapsulation layer 40, which is located on a side of the light-emitting device layer 30 facing away from the driving circuit layer 20. The encapsulation layer 40 can cover the multiple light-emitting devices O in the light-emitting device layer 30, encapsulating the light-emitting devices O to prevent moisture and oxygen from the external environment from entering the display panel 100 and damaging the organic materials in the light-emitting devices O, thereby shortening the life of the display panel 100.

[0082] In addition, the driving circuit layer 20 may further include a variety of signal lines. For example, as shown in FIG3 , the signal lines may include a data line Dt, a first power signal line Vdd, a first scan signal line GN, a second scan signal line GP, a light-emitting control signal line Em, a first reset signal line Rst-P, a second reset signal line Rst-H, a first initialization signal line (not shown in FIG3 ) Vt1, a second initialization signal line (not shown in FIG3 ) Vt2, and a third initialization signal line (not shown in FIG3 ) Vt3, etc. The above-mentioned multiple signal lines may be electrically connected to the pixel driving circuit Q to provide the pixel driving circuit Q with the signals it needs.

[0083] Exemplarily, the data line Dt is configured to provide a data write signal, the first power signal line Vdd is configured to provide a first power signal, the first scan signal line GN is configured to provide a first scan signal, the second scan signal line GP is configured to provide a second scan signal, the light emitting control signal line Em is configured to provide an enable signal, the first reset signal line Rst-P is configured to provide a first reset signal, the second reset signal line Rst-H is configured to provide a second reset signal, the first initialization signal line is configured to provide a first initialization signal, the second initialization signal line is configured to provide a second initialization signal, and the third initialization signal line is configured to provide a third initialization signal.

[0084] Among them, the first scan signal line GN, the second scan signal line GP, the light emitting control signal line Em, the first reset signal line Rst-P, the second reset signal line Rst-H, the first initialization signal line (not shown in FIG3 ) Vt1, the second initialization signal line (not shown in FIG3 ) Vt2, and the third initialization signal line (not shown in FIG3 ) Vt3 are signal lines extending along the first direction X. The data line Dt and the first power supply signal line Vdd are signal lines extending along the second direction Y.

[0085] In some embodiments, the pixel driving circuit Q includes a plurality of transistors. In some embodiments, the structure of the pixel driving circuit Q in the present disclosure includes multiple structures, which can be selected and set according to actual needs. For example, the structure of the pixel driving circuit may include "2T1C", "6T1C", "7T1C", "6T2C", "7T2C" or "8T1C", etc. Here, "T" represents a thin film transistor, and the number in front of "T" represents the number of thin film transistors; "C" represents a storage capacitor C, and the number in front of "C" represents the number of storage capacitors C. The following is an introduction taking the "8T1C" pixel driving circuit as an example.

[0086] FIG. 5 is an equivalent circuit diagram of a pixel driving circuit according to some embodiments.

[0087] 5 , the pixel driving circuit Q includes a first reset transistor T1 , a compensation transistor T2 , a driving transistor T3 , a data writing transistor T4 , a first emission control transistor T5 , a second emission control transistor T6 , a second reset transistor T7 , a third reset transistor T8 and a storage capacitor Cst.

[0088] The gate g1 of the first reset transistor T1 is electrically connected to the first reset signal line Rst-P, the first electrode s1 of the first reset transistor T1 is electrically connected to the first initialization signal line Vt1, and the second electrode d1 of the first reset transistor T1 is electrically connected to the third node N3.

[0089] A gate g2 of the compensation transistor T2 is electrically connected to the first scan signal line GN, a first electrode s2 of the compensation transistor T2 is electrically connected to the third node N3, and a second electrode d2 of the compensation transistor T2 is electrically connected to the first node N1.

[0090] A gate g3 of the driving transistor T3 is electrically connected to the first scanning signal line GN, a first electrode s3 of the driving transistor T3 is electrically connected to the second node N2, and a second electrode d3 of the driving transistor T3 is electrically connected to the third node N3.

[0091] A gate g4 of the data writing transistor T4 is electrically connected to the second scanning signal line GP, a first electrode s4 of the data writing transistor T4 is electrically connected to the data writing signal line Dt, and a second electrode d4 of the data writing transistor T4 is electrically connected to the second node N2.

[0092] A gate g5 of the first light emitting control transistor T5 is electrically connected to the light emitting control signal line Em, a first electrode s5 of the first light emitting control transistor T5 is electrically connected to the first power signal line Vdd, and a second electrode d5 of the first light emitting control transistor T5 is electrically connected to the second node N2.

[0093] The gate g6 of the second light emitting control transistor T6 is electrically connected to the light emitting control signal line Em, the first electrode s6 of the second light emitting control transistor T6 is electrically connected to the third node N3, and the second electrode d6 of the second light emitting control transistor T6 is electrically connected to the anode of the light emitting device O.

[0094] The gate g7 of the second reset transistor T7 is electrically connected to the second reset signal line Rst-H, the first electrode s7 of the second reset transistor T7 is electrically connected to the second initialization signal line Vt2, and the second electrode d7 of the second reset transistor T7 is electrically connected to the anode of the light-emitting device O and the second electrode d6 of the second light-emitting control transistor T6.

[0095] A gate g8 of the third reset transistor T8 is electrically connected to the second reset signal line Rst-H, a first electrode s8 of the third reset transistor T8 is electrically connected to the third initialization signal line Vt3, and a second electrode d8 of the third reset transistor T8 is electrically connected to the second node N2.

[0096] A first electrode of the storage capacitor Cst is electrically connected to the first node N1 , and a second electrode thereof is electrically connected to the first power signal line Vdd.

[0097] The cathode of the light emitting device O is electrically connected to a second power signal line Vss, and the second power signal line Vss is configured to provide a second power signal.

[0098] In some examples, the voltage of the first power signal provided by the first power signal line Vdd is higher than the voltage of the second power signal provided by the second power signal line Vss.

[0099] In some examples, the compensation transistor T2 may be an N-type transistor, and the first reset transistor T1, the driving transistor T3, the data writing transistor T4, the first emission control transistor T5, the second emission control transistor T6, the second reset transistor T7, and the third reset transistor T8 may be P-type transistors.

[0100] In some examples, the compensation transistor T2 may be an oxide transistor, which may be an N-type transistor, and the other transistors may be LTPS (Low Temperature Poly Silicon) transistors, which may be P-type transistors.

[0101] Among them, the N-type transistor is turned on when the gate receives a high voltage signal, while the P-type transistor is turned on when the gate receives a low voltage signal. It should be noted that the "high voltage signal" and "low voltage signal" mentioned above are popular terms. Generally speaking, the turning-on condition of the N-type transistor is that the gate-source voltage difference is greater than its threshold voltage, that is, the gate voltage of the N-type transistor is greater than the sum of its source voltage and its threshold voltage. The threshold voltage of the N-type transistor is a positive value, and the gate voltage signal that turns on the N-type transistor is called a high voltage signal. The turning-on condition of the P-type transistor is that the absolute value of the gate-source voltage difference is greater than its threshold voltage. The threshold voltage of the P-type transistor is a negative value, that is, the gate voltage of the P-type transistor is less than the sum of its source voltage and its threshold voltage. The gate voltage signal that turns on the P-type transistor is called a low voltage signal, and the voltage of the "high voltage signal" is greater than the voltage of the "low voltage signal".

[0102] In other examples, the plurality of transistors may all be P-type transistors, and in other examples, the plurality of transistors may all be N-type transistors. FIG5 illustrates an example in which the compensation transistor T2 is an N-type transistor and the other transistors are P-type transistors.

[0103] FIG6 is a partial structural diagram of a display panel according to some embodiments. FIG6 may correspond to the partial structural diagram at the lower left corner U of the display panel 100 in FIG3 . To clearly illustrate the structure of each signal line, the gate drive circuit is not illustrated. Specifically, as shown in FIG6 , along the first direction X, the gate drive circuit may be located on the side of the signal line that is behind the ion pixel P, that is, the gate drive circuit may be located on the left side of the signal line.

[0104] It should be noted that in FIG6 , the wiring at position U in the corner region R corresponds to three rows of pixel driving circuits Q for illustrative purposes. However, this does not mean that the wiring at position R in the corner region only corresponds to three rows of pixel driving circuits Q. In other words, the wiring at position R in the corner region may correspond to more than three rows of pixel driving circuits Q. The disclosed embodiments are not limited to this.

[0105] As shown in Figures 3, 5, and 6, the driving circuit layer 20 further includes multiple gate driving circuits 110, multiple first signal line groups 21, multiple GOA signal line groups 22, and multiple connection signal line groups 23. The multiple first signal line groups 21 are located in the display area AA, and each first signal line group 21 is electrically connected to a row of pixel driving circuits Q. The first signal line group 21 includes multiple first signal lines 211 extending along the first direction X and arranged in the second direction Y.

[0106] Illustratively, the plurality of first signal lines 211 in a first signal line group 21 may include: a first scan signal line GN, a second scan signal line GP, a light emission control signal line Em, a first reset signal line Rst-P, a second reset signal line Rst-H, a first initialization signal line Vt1, a second initialization signal line Vt2, and a third initialization signal line Vt3, etc. Among them, the first scan signal line GN, the second scan signal line GP, the light emission control signal line Em, the first reset signal line Rst-P, and the second reset signal line Rst-H in the first signal line group 21 may be classified as gate signal lines, and the first initialization signal line Vt1, the second initialization signal line Vt2, and the third initialization signal line Vt3 may be classified as initialization signal lines.

[0107] 6 may be a partial structural diagram of the lower left corner U of the display panel 100 in FIG3 , and therefore does not illustrate the light emission control signal line Em and the second reset signal line Rst-H for connecting to the gate drive circuit located at the lower right corner of the display panel 100. However, the structural diagram at the lower right corner of the display panel 100 is similar to that of FIG6 , and the first reset signal line Rst-P in FIG6 may be replaced with the light emission control signal line Em, and the first scan signal line GN may be replaced with the second reset signal line Rst-H.

[0108] The plurality of gate driving circuits 110 are located in the first border area SA1 , and the plurality of gate driving circuits 110 may be arranged along the first direction X. However, the embodiment of the present disclosure is not limited thereto.

[0109] FIG. 7 is an equivalent circuit diagram of a gate driving circuit according to some embodiments.

[0110] In some examples, as shown in conjunction with FIG3 and FIG7 , the gate driver circuit 110 includes a plurality of cascaded shift registers 101. The shift register 101 may include an input signal terminal Input, a first clock control signal terminal CLK, a second clock control signal terminal CLKB, an output signal terminal Output, a reset signal terminal Reset, and a low-level power signal terminal VGL.

[0111] A plurality of GOA signal line groups 22 are located in the first border area SA1. The GOA signal line group 22 includes a plurality of GOA signal lines 221. One end of each GOA signal line 221 in a GOA signal line group 22 is electrically connected to a gate driver circuit 110, and the other end of each GOA signal line 221 in the GOA signal line group 22 extends through the corner area R to the bonding area BB.

[0112] Any signal line 221 in the GOA signal line group 22 can extend along the first border area SA1, so that the GOA signal line 221 passes through the first border area SA1, the second border area SA2 to the binding area BB in sequence (as shown in Figure 3), and can be electrically connected to the circuit located in the binding area BB.

[0113] For example, the multiple GOA signal lines 221 in a GOA signal line group 22 may include a first clock signal line LCLK, a second clock signal line LCLKB, a start trigger signal line STV, a low-level power signal line LVGL, and a reset signal line LReset. However, the disclosed embodiments are not limited thereto. For example, in addition to the aforementioned signal lines, a GOA signal line group 22 may also include an output detection signal line 221b for detecting whether the gate drive circuit 110 electrically connected to the GOA signal line group 22 having the output detection signal line 221b is qualified.

[0114] One end of each GOA signal line in a GOA signal line group 22 is electrically connected to a gate driving circuit 110. Specifically, in a GOA signal line group 22: the first clock signal line LCLK can be electrically connected to the first clock control signal terminal CLK of the shift register 101, the second clock signal line LCLKB can be electrically connected to the second clock control signal terminal CLKB of the shift register 101, the start trigger signal line STV can be electrically connected to the input signal terminal Input of the shift register 101, the low-level power signal line LVGL can be electrically connected to the low-level power signal terminal VGL of the shift register 101, and the reset signal line LReset can be electrically connected to the reset signal terminal Reset of the shift register 101.

[0115] That is to say, the first clock signal line LCLK, the second clock signal line LCLKB, the start trigger signal line STV, the low-level power signal line LVGL, and the reset signal line LReset in a GOA signal line group 22 will all pass through the corner area R, so that the multiple GOA signal lines 221 in a GOA signal line group 22 can be electrically connected to the circuit located in the binding area BB to drive the gate drive circuit 110 to generate a scanning signal to the pixel drive circuit.

[0116] In addition, a plurality of initialization signal line buses may be provided in the first border area SA1 of the display panel 100, and the initialization signal line buses may also extend along the first border area SA1, so as to realize that the initialization signal line buses pass through the first border area SA1, the second border area SA2 to the binding area BB in sequence (as shown in FIG. 3).

[0117] The plurality of initialization signal line buses may include a first initialization signal bus, a second initialization signal line bus, and a third initialization signal bus. The first initialization signal bus is connected to the first initialization signal line in the first signal line group 21, the second initialization signal bus is connected to the second initialization signal line in the first signal line group 21, and the third initialization signal bus is connected to the third initialization signal line in the first signal line group 21.

[0118] As shown in Figures 3, 5, and 6, multiple connection signal line groups 23 are located in the first border area SA1. Each connection signal line group 23 may include multiple connection signal lines 231. Each connection signal line group 23 is electrically connected to at least one row of pixel drive circuits Q and to multiple gate drive circuits Q.

[0119] Based on this, the plurality of gate driving circuits 110 can be electrically connected to the pixel driving circuit Q by using the connection signal line group 23 , so as to drive the pixel driving circuit by using the scanning signal provided by the gate driving circuit 110 .

[0120] In some examples, the connection signal line group 23 can be electrically connected to the pixel driving circuit Q through the first signal line group 21. Based on this, it is equivalent to indirectly extending the first signal line 211 located in the display area AA to the first side frame SA1 using the connection signal line 231, so that the first signal line 211 located in the display area AA is electrically connected to the device in the first side frame SA1.

[0121] For one connection signal line group 23, being electrically connected to at least one row of pixel driving circuits Q and to multiple gate driving circuits Q, the following two situations may be included:

[0122] The first type: one connection signal line group 23 can be electrically connected to multiple rows of pixel driving circuits Q and multiple gate driving circuits Q. In this case, multiple gate driving circuits 110 can be used to drive multiple rows of pixel driving circuits Q simultaneously.

[0123] Based on this, one connection signal line group 23 can be electrically connected to multiple first signal line groups 21 to achieve electrical connection with multiple rows of pixel driving circuits Q. In other words, it is equivalent to one connection signal line 231 in the connection signal line group 23 being electrically connected to the same type of first signal line 211 in multiple first signal line groups 21.

[0124] Exemplarily, a connecting signal line 231 in the connecting signal line group 23 can be electrically connected to the first scanning signal line GN in the multiple first signal line groups 21, so that the gate driving circuit 110 transmits the first scanning signal via the connecting signal line 231 and the first scanning signal line GN to the control electrodes of some transistors in the pixel driving circuit Q.

[0125] Second, one connection signal line group 23 can be electrically connected to a row of pixel driving circuits Q and to multiple gate driving circuits Q. In this case, multiple pixel driving circuits Q can be used to drive the row of pixel driving circuits Q.

[0126] Based on this, one connection signal line group 23 can be electrically connected to one row of pixel driving circuits Q through one first signal line group 21 . That is, one connection signal line 231 in the connection signal line group 23 is electrically connected to one first signal line 231 in the first signal line group 21 .

[0127] Exemplarily, a connecting signal line 231 in the connecting signal line group 23 can be electrically connected to a first scanning signal line GN in a first signal line group 21, so that the gate driving circuit 110 transmits the first scanning signal via the connecting signal line 231 and the first scanning signal line GN to the control electrodes of some transistors in the pixel driving circuit Q.

[0128] It should be noted that the multiple first signal lines 211 in the same first signal line group 21 can be divided into gate signal lines and initialization signal lines. The multiple connection signal lines 231 in the connection signal line group 23 electrically connected to the first signal line group 21 can also be divided into two types of connection signal lines: gate connection signal lines and initialization connection signal lines.

[0129] Among them, the gate connection signal line in the connection signal line group 23 is used to connect the first signal line 211 (gate signal line) in the first signal line group 21 and the gate drive circuit 110, and the initialization connection signal line in the connection signal line group 23 is used to connect the first signal line 211 (initialization signal line) in the first signal line group 21 and the initialization signal routing.

[0130] Exemplarily, one end of a gate connection signal line (connection signal line 231) in the connection signal line group 23 is electrically connected to the gate drive signal line (first signal line 211), and the other end of the gate connection signal line (connection signal line 231) is electrically connected to the output terminal "Output" of the shift register 101 of a gate drive circuit 110 located in the first border area SA1. This enables the gate drive circuit 110 to output the scanning signal to the pixel drive circuit Q in the plurality of sub-pixels P.

[0131] For example, when the first signal line 211 is the first scanning signal line GN, the connecting signal line 231 can be used to electrically connect the first scanning signal line GN to the gate driving circuit Q corresponding to the first scanning signal line GN in multiple gate driving circuits 110, so as to enable the gate driving circuit 110 to transmit the first scanning signal via the connecting signal line 231 and the first scanning signal line GN to the control electrodes of some transistors in the pixel driving circuit Q.

[0132] Exemplarily, one end of an initialization connection signal line (connection signal line 231) in the connection signal line group 23 is electrically connected to the initialization signal line (first signal line 211), and the other end of the initialization connection signal line (connection signal line 231) is electrically connected to the initialization signal bus located in the first border area SA1, so as to enable the initialization signal line bus to transmit the initialization signal to the pixel driving circuit Q in multiple sub-pixels P.

[0133] For example, when the first signal line 211 is the first initialization signal line Vt1, the connecting signal line 231 can be used to electrically connect the first initialization signal line Vt1 and the first initialization signal bus, so that the first initialization signal line bus transmits the first initialization signal via the connecting signal line 231 and the first initialization signal line Vt1 to the first electrodes of some transistors in the pixel driving circuit Q.

[0134] It should be noted that, in some examples, the connection signal line 231 located in the first border area SA1 can extend to the display area AA and be electrically connected to the first signal line 211 in the display area AA. Alternatively, in other examples, the first signal line 211 located in the display area AA can extend to the first border area SA1 and be electrically connected to the connection signal line 231 located in the first border area SA1. Alternatively, in still other examples, the connection position between the connection signal line 231 and the first signal line 211 is at the junction of the display area AA and the first border area SA1.

[0135] Generally, all connecting signal lines 231 can be provided on the same layer to simplify the manufacturing process of the display panel 100. "On the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0136] However, the inventors have found that since all the connecting signal lines 231 are arranged in the same layer, in order to improve the mutual influence between two adjacent connecting signal lines 231, the minimum spacing between two adjacent connecting signal lines 231 can be set to be greater than or equal to 3μm, so as to increase the spacing between the two adjacent connecting signal lines 231 and reduce the mutual influence between the two. However, when the spacing between two adjacent connecting signal lines 231 is increased, the occupation of the space of the corner area R by all connecting signal lines 231 will be increased. Due to the spatial limitation of the corner area R of the first border area SA1, the positive projection of the GOA signal line 221 on the base substrate 10 will overlap with the positive projection of the first signal line 211 on the base substrate 10 in the corner area R. Furthermore, a capacitance will be formed between the overlapping GOA signal line 221 and the first signal line 211, which will increase the load on the GOA signal line 221 and the first signal line 211. As a result, the signal transmitted via the GOA signal line 221 and the signal transmitted via the first signal line 211 will be affected. Ultimately, this will affect the signal received by the pixel driving circuit Q, affect the display uniformity of the display panel 100 , and reduce the display effect of the display panel 100 .

[0137] It should be noted that in FIG3 , the U position is to clearly illustrate how the pixel driving circuit is electrically connected to the first signal line group 22 and the connection signal line group 23, and only one row of pixel driving circuits Q and the first signal line group 22 and the connection signal line group 23 electrically connected thereto are illustrated. However, this does not mean that in an actual product, the wiring at the corner area R position corresponds to only one row of pixel driving circuits Q. In other words, the wiring at the corner area R position can correspond to multiple rows of pixel driving circuits Q.

[0138] Figure 8A is a partial structural diagram of a display panel according to some other embodiments, and Figure 8B is a cross-sectional view taken along line E-E' in Figure 8A . Figure 8A may correspond to the partial structural diagram at position U in the lower left corner of the display panel 100 in Figure 3 . To clearly illustrate the structure of each signal line, the gate drive circuit is not illustrated. Specifically, as shown in Figure 8A , along the first direction X, the gate drive circuit may be located on the side of the signal line facing away from the pixel P, that is, the gate drive circuit may be located on the left side of the signal line.

[0139] It should be noted that FIG8A illustrates the three rows of pixel driver circuits Q corresponding to the wiring at position U in the corner region R for illustrative purposes. However, this does not mean that the wiring at position R in the corner region only corresponds to three rows of pixel driver circuits Q. In other words, the wiring at position R in the corner region may correspond to more than three rows of pixel driver circuits Q. The disclosed embodiments are not limited to this.

[0140] Based on this, as shown in Figures 8A and 8B , in the display panel 100 provided in some embodiments of the present disclosure, the driving circuit layer 20 includes a gate metal layer, a first source / drain metal layer SD1, and a second source / drain metal layer SD2, along a direction away from the base substrate 10. The gate metal layer includes a first gate metal layer Gate1 and a second gate metal layer Gate2, with the first gate metal layer Gate1 being located between the base substrate 10 and the second gate metal layer Gate2.

[0141] The first gate metal layer Gate1 may include control electrodes of at least some transistors in the pixel driving circuit Q. The first gate metal layer Gate1 may also be used to form some signal lines.

[0142] In some examples, the material of the first gate metal layer Gate1 includes a conductive metal, and the conductive metal may include at least one of aluminum, copper, and molybdenum, but the present disclosure is not limited thereto.

[0143] The second gate metal layer Gate2 is located on a side of the first gate metal layer Gate1 away from the substrate 10. The second gate metal layer Gate2 may include control electrodes of at least some transistors in the pixel driving circuit Q. The first gate metal layer Gate1 may also be used to form some signal lines.

[0144] In some examples, the second gate metal layer Gate2 may be made of the same material as the first gate metal layer Gate1. It is understood that in other examples, the second gate metal layer Gate2 may be made of a different material than the first gate metal layer Gate1. The embodiments of the present disclosure are not limited thereto.

[0145] In some examples, a gate insulating layer GI may be provided between the second gate metal layer Gate2 and the first gate metal layer Gate1. The gate insulating layer GI electrically insulates the second gate metal layer Gate2 from the first gate metal layer Gate1.

[0146] For example, the material of the gate insulating layer GI includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. The material of the gate insulating layer GI may also include silicon dioxide, but the present disclosure is not limited thereto.

[0147] The first source-drain metal layer SD1 is located on a side of the second gate metal layer Gate2 away from the first gate metal layer Gate1. That is, the first source-drain metal layer SD1 is located between the second gate metal layer Gate2 and the second source-drain metal layer SD2.

[0148] For example, the material of the first source / drain metal layer SD1 may include a titanium (Ti)-aluminum (Al)-titanium (Ti) multi-layer composite material.

[0149] Illustratively, a first planarization layer PLN1 (PLN) is provided between the first source / drain metal layer SD1 and the second gate metal layer Gate2 to electrically insulate the first source / drain metal layer SD1 from the second gate metal layer Gate2.

[0150] Exemplarily, the material of the first planarization layer PLN1 is generally an organic material. For example, the material of the first planarization layer PLN1 may include at least one of polyimide (English full name: Polyimide, English abbreviation: PI), an acrylic-based polymer, or a silicon-based polymer.

[0151] The second source / drain metal layer SD2 is located on a side of the first source / drain metal layer SD1 away from the second gate metal layer Gate2 .

[0152] In some examples, the material of the second source / drain metal layer SD2 may be the same as that of the first source / drain metal layer SD1. Alternatively, in other examples, the material of the second source / drain metal layer SD2 may be different from that of the first source / drain metal layer SD1. The embodiments of the present disclosure are not limited thereto.

[0153] In some examples, a second planarization layer PLN2 is disposed between the second source / drain metal layer SD2 and the first source / drain metal layer SD1 , and the second planarization layer PLN2 electrically insulates the second source / drain metal layer SD2 from the first source / drain metal layer SD1 .

[0154] Exemplarily, the material of the second planarization layer PLN2 is generally an organic material. For example, the material of the second planarization layer PLN2 may include at least one of polyimide (English full name: Polyimide, English abbreviation: PI), acrylic-based polymer, or silicon-based polymer.

[0155] Since the material of the source-drain metal layer (the first source-drain metal layer SD1 and the second source-drain metal layer SD2) is different from the material of the gate metal layer (the first gate metal layer Gate1 and the second gate metal layer Gate2), the material of the source-drain metal layer (the first source-drain metal layer SD1 and the second source-drain metal layer SD2) may include a titanium (Ti)-aluminum (Al)-titanium (Ti) multilayer composite material, which can reduce the resistance of the signal line formed on the source-drain metal layer, so that the formed signal line has a smaller impedance.

[0156] Based on this, the connection signal lines 231 in the connection signal line group 23 can be formed in the source-drain metal layer to reduce the impedance of the connection signal lines 231 and reduce the loss of the signals transmitted on the connection signal lines 231. In addition, in the same connection signal line group 23, some connection signal lines 231 are located in the first source-drain metal layer SD1, and other connection signal lines 231 are located in the second source-drain metal layer SD2.

[0157] It should be noted that the same type of connection signal lines 231 in each connection signal line group 23 are arranged on the same layer, and different types of connection signal lines 231 may be arranged on different layers. For example, the connection signal lines 231 in each connection signal line group 23 that are electrically connected to the first scanning signal line GN are arranged on the same layer, or the connection signal lines 231 in each connection signal line group 23 that are electrically connected to the first reset signal line Rst-P are arranged on the same layer. Furthermore, the connection signal lines 231 in each connection signal line group 23 that are electrically connected to the first scanning signal line GN are arranged on different layers from the connection signal lines 231 in the connection signal line group 23 that are electrically connected to the first reset signal line Rst-P.

[0158] Further configuration is shown in FIG9 , which is a partial enlarged view of M1 in FIG8A . In the corner region R, there is a first spacing D1 between the orthographic projections of the adjacent connection signal line group 23 and the GOA signal line group 22 on the base substrate 10 .

[0159] Among them, in the corner area R: along the direction in which the multiple connection signal lines 231 are arranged, the connection signal line group 23 closest to the GOA signal line group 22 among the multiple connection signal line groups 23 is defined as the target connection signal line group 23A, and the connection signal line 231 closest to the GOA signal line group 22 in the target connection signal line group 23A is defined as the target connection signal line 231A.

[0160] The GOA signal line group 22 closest to the connection signal line group 23 in the multiple GOA signal line groups 22 is defined as the target GOA signal line group 22A, and the GOA signal line 221 closest to the connection signal line group 23 in the target GOA signal line group 22A is defined as the target GOA signal line 221A.

[0161] In the corner region R, along the direction in which the plurality of connection signal lines 231 are arranged, the target connection signal line 231A and the target GOA signal line 221A are adjacently arranged, with a first distance D1 between them.

[0162] In this configuration, disposing the multiple connection signal lines 231 in the connection signal line group 23 in different layers, in the first source-drain metal layer SD1 and the second source-drain metal layer SD2, can reduce the orthographic projections of all the connection signal lines 231 on the base substrate 10 and the space occupied by the corner area R. Furthermore, the spacing between the connection signal line group 23 and the GOA signal line group 22 can be increased, so that the orthographic projections of the connection signal lines 231 on the base substrate 10 do not overlap with the orthographic projections of the GOA signal lines 221 on the base substrate 10. This alleviates the problem of increased load on the GOA signal lines 221 and the first signal lines 211.

[0163] In some examples, the multiple GOA signal lines 221 in the GOA signal line group 22 can be located in the gate metal layer. Based on this, the multiple connection signal lines 231 in the connection signal line group 23 are arranged in different layers in the first source-drain metal layer SD1 and the second source-drain metal layer SD2. This can also increase the spacing between the connection signal lines 231 and the GOA signal lines 221 in a direction perpendicular to the substrate 10 to prevent the formation of capacitance between the two, which would increase the load on the connection signal lines 231 and the GOA signal lines 221. The distribution of the multiple GOA signal lines 221 in the GOA signal line group 22 in the gate metal layer will be explained in detail below.

[0164] To sum up, the display panel 100 provided by the embodiment of the present disclosure, by arranging multiple connecting signal lines 231 in the connecting signal line group 23 in different layers in the first source-drain metal layer SD1 and the second source-drain metal layer SD2, can not only increase the spacing between adjacent connecting signal lines 231 and GOA signal lines 221 in the direction pointing to the display area AA along the corner area R, but also increase the spacing between the connecting signal lines 231 and the GOA signal lines 221 in the direction perpendicular to the base substrate 10, so as to improve the problem of increased load on the connecting signal lines 231 and the GOA signal lines 221, improve the display uniformity of the display panel 100, and improve the display effect of the display panel 100.

[0165] In some examples, along the direction in which the plurality of connection signal lines 231 are arranged, the line width of the connection signal lines 231 ranges from 2.4 μm to 3.5 μm.

[0166] When the line width of the connecting signal line 231 is equal to or close to 2.4 μm, the line width of the connecting signal line 231 is relatively narrow, which helps reduce the orthographic projection of all the connecting signal lines 231 on the base substrate 10 and the space occupied by the corner area R. Furthermore, the spacing between the connecting signal line group 23 and the GOA signal line group 22 can be increased to ensure that the orthographic projection of the connecting signal line 231 on the base substrate 10 does not overlap with the orthographic projection of the GOA signal line 221 on the base substrate 10. This alleviates the problem of increased load on the GOA signal line 221 and the first signal line 211.

[0167] When the line width of the connecting signal line 231 is equal to or close to 3.5 μm, the line width of the connecting signal line 231 is wider, which can reduce the impedance of the connecting signal line 231 while ensuring that the orthographic projection of the connecting signal line 231 on the base substrate 10 does not overlap with the orthographic projection of the GOA signal line 221 on the base substrate 10, thereby reducing the loss caused by the connecting signal line 231 to the signal it transmits.

[0168] In some examples, along the direction in which the plurality of connection signal lines 231 are arranged, the line width of the connection signal lines 231 ranges from 2.8 μm to 3.2 μm.

[0169] When the line width of the connecting signal line 231 is within the range of 2.8 μm to 3.2 μm along the direction in which the multiple connecting signal lines 231 are arranged, the impedance requirements of the connecting signal line 231 can be met, and the orthographic projection of the connecting signal line 231 on the base substrate 10 can be realized without overlapping with the orthographic projection of the GOA signal line 221 on the base substrate 10.

[0170] For example, along the direction in which the plurality of connection signal lines 231 are arranged, the line width of the connection signal lines 231 is approximately any one of 2.4 μm, 2.5 μm, 2.6 μm, 2.8 μm, 3 μm, 3.2 μm, 3.3 μm, 3.4 μm or 3.5 μm. However, the present disclosure is not limited thereto.

[0171] It should be noted that the example described herein uses a width of approximately 3 μm for the connecting signal line 231. Due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, and measurement errors), when the width of the connecting signal line 231 fluctuates within a range of ±10% × 3 μm, it can be considered that the width of the connecting signal line 231 satisfies the requirement of 3 μm.

[0172] In some embodiments, in combination with Figures 8A, 8B and 9, in the corner area R: along the direction in which the multiple connecting signal lines 231 are arranged, the first distance D1 between the orthographic projection of the connecting signal line group 23 on the base substrate 10 and the orthographic projection of the GOA signal line group 22 on the base substrate 10 is greater than or equal to 1.5 μm.

[0173] That is, in the corner area R: along the direction in which the multiple connection signal lines 231 are arranged, the target connection signal line 231A and the target GOA signal line 221A are arranged adjacent to each other, and the minimum spacing between the target connection signal line 231A and the target GOA signal line 221A is the first spacing D1, and the first spacing D1 is greater than or equal to 1.5μm.

[0174] When the first distance D1 is equal to or close to 1.5 μm, the orthographic projection of the target connection signal line 231A on the base substrate 10 in the corner region R can be made to not overlap with the orthographic projection of the target GOA signal line 221A on the base substrate 10, and the distance between the target connection signal line 231A and the target GOA signal line 221A is larger, thereby improving the problem of capacitance formed therebetween, which increases the load on the connection signal line 231 and the GOA signal line 221. Thus, the display uniformity of the display panel 100 is improved, and the display effect of the display panel 100 is enhanced.

[0175] In some examples, within the corner region R: along the direction in which the multiple connection signal lines 231 are arranged, the orthographic projection of the connection signal line group 23 on the base substrate 10 and the orthographic projection of the GOA signal line group 22 on the base substrate 10 have a first spacing D1 less than or equal to 45 μm.

[0176] That is, in the corner area R: along the direction in which the multiple connection signal lines 231 are arranged, the target connection signal line 231A and the target GOA signal line 221A are arranged adjacent to each other, and the minimum spacing between the target connection signal line 231A and the target GOA signal line 221A is the first spacing D1, and the first spacing D1 is greater than or equal to 45 μm.

[0177] When the first distance D1 is less than or equal to 45 μm, the minimum distance between the target connection signal line 231A and the target GOA signal line 221A can be increased while meeting the requirement of the display panel 100 on the size of the corner area R.

[0178] In some examples, the first distance D1 has a value range of 1.5 μm to 45 μm. When the first distance D1 has a value range of 1.5 μm to 45 μm, the orthographic projection of the target connection signal line 231A in the corner region R on the base substrate 10 does not overlap with the orthographic projection of the target GOA signal line 221A on the base substrate 10, and the distance between the target connection signal line 231A and the target GOA signal line 221A is large, while meeting the display panel 100's requirement for the size of the corner region R.

[0179] In other examples, the first spacing D1 has a value range of 5 μm to 45 μm. Alternatively, in yet other examples, the first spacing D1 has a value range of 10 μm to 45 μm. It is understood that, with respect to the size limitation of the first spacing D1, the first spacing D1 can be increased as much as possible while meeting the display panel 100's requirement for the corner area R size, thereby improving the problem of increased load connecting the signal line 231 and the GOA signal line 221. Thus, the display quality of the display panel 100 is improved.

[0180] For example, the first distance D1 is approximately 1.5 μm, 3 μm, 5 μm, 8 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 35 μm, 40 μm, or 45 μm. However, the present disclosure is not limited thereto.

[0181] It should be noted that the first spacing D1 is approximately 3 μm. Due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the first spacing D1 fluctuates within the range of ±10% × 3 μm, it can also be considered that the first spacing D1 is equal to 3 μm.

[0182] Figure 10 is a partial enlarged view of M2 in Figure 8A . Figure 10 may be a partial structural diagram of the lower left corner of the display panel 100 at position U in Figure 3 , and therefore does not illustrate the light-emission control signal line Em and the second reset signal line Rst-H used to connect to the gate drive circuit located at the lower right corner of the display panel 100. However, the structural diagram at the lower right corner of the display panel 100 is similar to Figure 10 , and the first reset signal line Rst-P in Figure 10 can be replaced with the light-emission control signal line Em, and the first scan signal line GN can be replaced with the second reset signal line Rst-H.

[0183] In some embodiments, as shown in FIG8A , along the direction in which the plurality of connection signal lines 231 are arranged, the minimum spacing between the connection signal line 231 closest to the display area AA in the corner area R and its adjacent pixel driving circuit Q is a second spacing D2, and the value range of the second spacing D2 is 2.5 μm to 15 μm.

[0184] When the second spacing D2 is equal to or close to 1.5 μm, the spacing between the connecting signal line 231 and its adjacent pixel driving circuit Q can be made smaller. That is, the connecting signal line 231 can be arranged close to the pixel driving circuit Q, which is equivalent to moving the connecting signal line 231 away from the GOA signal line group 22, so as to increase the spacing between the connecting signal line 231 and the GOA signal line 221 along the corner area R pointing to the display area AA, thereby improving the problem of increased load on the connecting signal line 231 and the GOA signal line 221, thereby improving the display uniformity of the display panel 100 and improving the display effect of the display panel 100. In addition, setting the second spacing D2 equal to or close to 1.5 μm can also create a gap between the connecting signal line 231 and its adjacent pixel driving circuit Q to prevent crosstalk between the two.

[0185] When the second spacing D2 is equal to or close to 15 μm, the minimum spacing between the connecting signal line 231 and the adjacent pixel driving circuit Q can be increased, thereby better preventing the formation of coupling capacitance between the connecting signal line 231 and the adjacent pixel driving circuit Q, which may affect the display effect of the display panel 100. In addition, when the second spacing D2 is equal to or close to 15 μm, the spatial restriction of the corner area R can also be met, ensuring that the orthographic projection of the connecting signal line 231 on the base substrate 10 does not overlap with the orthographic projection of the GOA signal line 221 on the base substrate 10, thereby improving the problem of increased load on the connecting signal line 231 and the GOA signal line 221, thereby improving the display uniformity of the display panel 100 and improving the display effect of the display panel 100.

[0186] In some examples, the second distance D2 has a value range of 2.5 μm to 8 μm. When the second distance D2 is within the range of 2.5 μm to 8 μm, it can meet the requirements of increasing the distance between the connection signal line 231 and the GOA signal line 221, and also meet the requirements of the distance between the connection signal line 231 and the adjacent pixel driving circuit Q, thereby improving the display uniformity of the display panel 100 and improving the display effect of the display panel 100.

[0187] In other examples, the second distance D2 has a value range of 2.5 μm to 3 μm. When the second distance D2 is within the range of 2.5 μm to 3 μm, the connection signal line 231 can be arranged close to the periphery of the pixel driving circuit Q, thereby better increasing the distance between the connection signal line 231 and the GOA signal line 221, while meeting the distance requirement between the connection signal line 231 and the adjacent pixel driving circuit Q, thereby improving the display uniformity of the display panel 100 and enhancing the display effect of the display panel 100.

[0188] For example, the second distance D2 is approximately any one of 1.5 μm, 2 μm, 2.5 μm, 3 μm, 4 μm, 5 μm, 8 μm, 10 μm, 12 μm, or 15 μm. However, the embodiments of the present disclosure are not limited thereto.

[0189] It should be noted that the second spacing D2 is approximately 3 μm. Due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the second spacing D2 fluctuates within the range of ±10% × 3 μm, it can also be considered that the second spacing D2 is equal to 3 μm.

[0190] In some embodiments, as shown in FIG. 3 , FIG. 8A , and FIG. 10 , the plurality of first signal lines 211 in the same first signal line group 21 include: a plurality of initialization signal lines 211A and a plurality of gate signal lines 211B.

[0191] The initialization signal line 211A is used to transmit a constant voltage signal to transmit the constant voltage signal to the first electrodes of some transistors in the pixel driving circuit Q to reset the nodes in the pixel driving circuit Q that are electrically connected to the transistors.

[0192] The gate signal line 211B is used to transmit a scanning signal (pulse signal) to transmit the scanning signal to the control electrode of some transistors in the pixel driving circuit Q to control the conduction or shutdown of the transistor.

[0193] In the corner region R: in the same connection signal line group 23 , the connection signal line 231 electrically connected to the initialization signal line 211A is located on a side of the connection signal line 231 electrically connected to the gate signal line 211B close to the GOA signal line 221 .

[0194] That is, in the same connection signal line group 23 , the connection signal line 231 (gate connection signal line) for transmitting the scanning signal is set and is located on the side of the connection signal line 231 (initialization connection signal line) for transmitting the constant voltage signal away from the GOA signal line group 22 .

[0195] Based on this, the spacing between the connection signal line 231 (gate connection signal line) in the connection signal line group 23 and the GOA signal line 221 can be increased to reduce the probability of capacitance formed between the connection signal line 231 (gate connection signal line) and the GOA signal line 221. Thus, the influence of the jump of the scanning signal transmitted by the connection signal line 231 (gate connection signal line) when the coupling capacitance is formed between the connection signal line 231 (gate connection signal line) and the GOA signal line in the connection signal line group 23 can be prevented. This is conducive to improving the accuracy of the scanning signal transmitted by the connection signal line 231 (gate connection signal line) in the connection signal line group 23, and improving the display effect of the display panel 100.

[0196] In some examples, the multiple first signal lines 211 in the first signal line group 21 may include: a first scanning signal line GN, a second scanning signal line GP, a light-emitting control signal line Em, a first reset signal line Rst-P, a second reset signal line Rst-H, a first initialization signal line Vt1, a second initialization signal line Vt2, and a third initialization signal line Vt3, etc.

[0197] Among them, the first scanning signal line GN, the second scanning signal line GP, the light-emitting control signal line Em, the first reset signal line Rst-P, and the second reset signal line Rst-H belong to the gate signal line 211B, and the first initialization signal line Vt1, the second initialization signal line Vt2, and the third initialization signal line Vt3 belong to the initialization signal line 211A.

[0198] Based on this, the first initialization signal line Vt1, the second initialization signal line Vt2 and the third initialization signal line Vt3 can be set between the first scanning signal line GN, the second scanning signal line GP, the light-emitting control signal line Em, the first reset signal line Rst-P, the second reset signal line Rst-H and the GOA signal line group 22.

[0199] Thus, the crosstalk between the GOA signal line closest to the connection signal line group 23 in the GOA signal line group 22 in the corner region R and the connection signal line 231 closest to the middle GOA signal line group 22 in the connection signal line group 23 is reduced. Thus, the display effect of the display panel 100 is improved.

[0200] In some embodiments, as shown in FIG. 3 , FIG. 8A , and FIG. 10 , along the first direction X, the first border area SA1 is located on at least one side of the display area AA, including the following two situations.

[0201] The first type: the first frame area SA1 is located on both sides of the display area AA. The first frame area SA1 can be located on the left side of the display area AA, or the first frame area SA1 can be located on the right side of the display area AA.

[0202] The second type: the first border area SA1 may include a first sub-border area SA11 and a second sub-border area SA12. Along the first direction X, the display area AA is located between the first sub-border area SA11 and the second sub-border area SA12. That is, the first sub-border area SA11 and the second sub-border area SA12 are equivalent to being located on the left and right sides of the display area AA, respectively, so as to realize that the first border area SA1 is located on both sides of the display area AA. Among them, the side of the first sub-border area SA11 close to the second border area SA2 includes a corner area R, and the side of the second sub-border area SA12 close to the second border area SA2 includes a corner area R.

[0203] Since each gate signal line 211B in the first connection signal line group 21 needs to correspond to a gate driver circuit 110, the following description uses the example of the first connection signal line group 21 including five gate signal lines 211B. In other words, each of the first connection signal lines 211—the first scan signal line GN, the second scan signal line GP, the light-emission control signal line Em, the first reset signal line Rst-P, and the second reset signal line Rst-H—needs to correspond to a gate driver circuit 110. In other words, the first border area SA1 needs to be provided with at least five gate driver circuits 110.

[0204] Based on this, the five gate drive circuits 110 can be dispersed in the first sub-frame area SA11 and the second sub-frame area SA12, that is, the multiple connection signal lines 231 in the same connection signal line group 23 can be dispersed in the first sub-frame area SA11 and the second sub-frame area SA12, which can help reduce the positive projection of all the connection signal lines 231 on the base substrate 10 along the direction in which the multiple connection signal lines 231 are arranged, and the space occupied by the corner area R.

[0205] Furthermore, the spacing between the connecting signal line group 23 and the GOA signal line group 22 can be increased so that the orthographic projection of the connecting signal line 231 on the base substrate 10 does not overlap with the orthographic projection of the GOA signal line 221 on the base substrate 10. This alleviates the problem of increased load on the GOA signal line 221 and the first signal line 211.

[0206] In some examples, the second scan signal line GP can be driven on both sides. That is, one end of the second scan signal line GP is electrically connected to one gate drive circuit 110, and the other end of the second scan signal line GP is electrically connected to another gate drive circuit 110. The left gate drive circuit 110 and the right gate drive circuit 110 each drive half of the second scan signal line GP, which can increase the charging time of the pixel drive circuit Q and improve the refresh rate.

[0207] At this time, the first border area SA1 needs to be provided with six gate driving circuits 110. The six gate driving circuits 110 are respectively a first gate driving circuit 111, a second gate driving circuit 112, a third gate driving circuit 113, a fourth gate driving circuit 114, a fifth gate driving circuit 115 and a sixth gate driving circuit 116.

[0208] Specifically, the first gate drive circuit 111 is electrically connected to one end of the second scanning signal line GP, the second gate drive circuit 112 is electrically connected to the other end of the second scanning signal line GP, the third gate drive circuit 113 is electrically connected to the first reset signal line Rst-P, the fourth gate drive circuit 114 is electrically connected to the first scanning signal line GN, the fifth gate drive circuit 115 is electrically connected to the light emitting control signal line Em, and the sixth gate drive circuit 116 is electrically connected to the second reset signal line Rst-H.

[0209] It should be noted that each first connecting signal line (first scanning signal line GN, second scanning signal line GP, light-emitting control signal line Em, first reset signal line Rst-P or second reset signal line Rst-H) is electrically connected to its corresponding gate drive circuit 110 through the connecting signal line 231.

[0210] For the six gate driving circuits 110 in the first border area SA1 , three gate driving circuits 110 may be located in the first sub-border area SA11 , and the other three gate driving circuits 110 may be located in the second sub-border area SA12 .

[0211] For example, the first sub-border area SA11 is provided with a first gate driving circuit 111, a third gate driving circuit 113, and a fourth gate driving circuit 114, and the second sub-border area SA12 is provided with a second gate driving circuit 112, a fifth gate driving circuit 115, and a sixth gate driving circuit 116. However, the embodiments of the present disclosure are not limited thereto.

[0212] In some embodiments, as shown in conjunction with FIG3 and FIG8A , the GOA signal line group 22 is located in the gate metal layer. The multiple GOA signal lines 221 in the GOA signal line group 22 are formed in the gate metal layer, which facilitates electrical connection between the multiple GOA signal lines 221 and some transistors in the shift register in the gate driver circuit.

[0213] Among them, the distribution of multiple GOA signal lines 221 in the same GOA signal line group 22 in the gate metal layer can include the following three configurations.

[0214] The first type: in the same GOA signal line group 22 : multiple GOA signal lines 221 are located in the first gate metal layer Gate1 .

[0215] The second type: in the same GOA signal line group 22 : multiple GOA signal lines 221 are located in the second gate metal layer Gate2 .

[0216] The third type: in the same GOA signal line group 22 : multiple GOA signal lines 221 are dispersed in the first gate metal layer Gate1 and the second gate metal layer Gate2 .

[0217] Among them, for the third arrangement of multiple GOA signal lines 221 in the same GOA signal line group 22, a portion of the GOA signal lines 221 in the same GOA signal line group 22 can be arranged in the first gate metal layer Gate1, and another portion can be arranged in the second gate metal layer Gate2. Alternatively, a portion of the GOA signal lines 221 in the same GOA signal line group 22 includes main signal lines and auxiliary signal lines, the main signal lines are arranged in the first gate metal layer Gate1, the auxiliary signal lines are arranged in the second gate metal layer Gate2, and the main signal lines and the auxiliary signal lines are electrically connected to form corresponding GOA signal lines 221. Such an arrangement is conducive to reducing the impedance of the GOA signal lines 221 and reducing the loss of the signals transmitted by the GOA signal lines 221.

[0218] In some embodiments, as shown in FIG3 and FIG8A , in the corner region R: along the direction in which the multiple GOA signal lines 221 are arranged, the GOA signal line 221 closest to the connection signal line group 23 in the same GOA signal line group 22 is located in the first gate metal layer Gate1.

[0219] Based on this, compared with placing the GOA signal line 221 closest to the connecting signal line group 23 in the same GOA signal line group 22 in the second gate metal layer Gate2, setting the GOA signal line 221 closest to the connecting signal line group 23 in the GOA signal line group 22 in the first gate metal layer Gate1 can increase the distance between the connecting signal line 231 and the GOA signal line 221 in the direction perpendicular to the substrate 10 to prevent the formation of capacitance between the two, resulting in the problem of increasing the load on the connecting signal line 231 and the GOA signal line 221.

[0220] In some examples, the plurality of GOA signal lines 221 in the GOA signal line group 22 may include a plurality of input signal lines 221 a and one output detection signal line 221 b .

[0221] Among them, multiple input signal lines 221a are used to provide signals to the gate drive circuit 110, and the output detection signal lines 221b are used to output the signals output by the gate drive circuit 110, and can be transmitted to the detection circuit located in the binding area of ​​the display panel 100 to detect whether the gate drive circuit 110 is normal.

[0222] The output detection signal line 221b can be located in the first gate metal layer Gate1. Based on this, in the corner region R: along the arrangement direction of multiple GOA signal lines 221, the GOA signal line 221 closest to the connection signal line group 23 in the same GOA signal line group 22 is the output detection signal line 221b.

[0223] Thus, the distance between the connecting signal line 231 and the output detection signal line 221 b in the direction perpendicular to the base substrate 10 is increased to prevent capacitance from being formed therebetween, thereby increasing the load on the connecting signal line 231 and the output detection signal line 221 b.

[0224] In other examples, the plurality of input signal lines 221 a in the GOA signal line group 22 include a plurality of GOA scan signal lines and a plurality of GOA constant voltage signal lines.

[0225] The plurality of scan signal lines may include a first clock signal line LCLK, a second clock signal line LCLKB, and a start trigger signal line STV. The plurality of scan signal lines may be used to provide pulse signals to the gate drive circuit 110 to control the on and off of some transistors in the gate drive circuit 110. The plurality of GOA constant voltage signal lines may include a low-level power signal line LVGL and a reset signal line LReset. The GOA constant voltage signal lines may be used to provide a constant voltage signal to the gate drive circuit 110.

[0226] In the corner region R, along the direction in which the multiple GOA signal lines 221 are arranged, the GOA constant voltage signal lines in the same GOA signal line group 22 are closer to the connection signal line group 23 than the GOA scan signal lines. That is, the GOA scan signal lines in the same GOA signal line group 22 are arranged farther from the GOA constant voltage signal lines than the connection signal line group 23.

[0227] Thus, the spacing between the GOA scan signal line and the connection signal line group 23 is increased, thereby reducing the probability of capacitance formation between the GOA scan signal line and the connection signal line 231 in the connection signal line group 23. This prevents the effect of coupling capacitance formed between the GOA scan signal line and the connection signal line 231 on the transition of the scan signal transmitted by the GOA scan signal line. This is beneficial for improving the accuracy of the scan signal transmitted by the GOA scan signal line and enhancing the display effect of the display panel 100.

[0228] In some examples, as shown in conjunction with FIG3 and FIG8A , the input signal line 221a in the GOA signal line group 22 may include a main signal line and an auxiliary signal line. The main signal line is disposed in the first gate metal layer Gate1, and the auxiliary signal line is disposed in the second gate metal layer Gate2. The main signal line and the auxiliary signal line are electrically connected to form the corresponding input signal line 221a. This configuration is conducive to reducing the impedance of the input signal line 221a and reducing the loss of the signal transmitted by the input signal line 221a.

[0229] In some embodiments, in combination with Figures 3 and 8A, based on the setting of the GOA signal line group 22 in the gate metal layer (the first gate metal layer Gate1 and / or the second gate metal layer Gate2): the corner area R can be set: along the direction in which the multiple connection signal lines 231 are arranged, the connection signal line 231 closest to the GOA signal line group 22 in the same connection signal line group 23 is located in the second source and drain metal layer SD2.

[0230] Based on this, the connection signal line 231 closest to the GOA signal line group 22 in the same connection signal line group 23 can be separated from the GOA signal line group 22 by at least one first source-drain metal layer SD1, thereby increasing the distance between the two in a direction perpendicular to the substrate 10, further reducing the risk of coupling capacitance between the two, and improving the problem of increased load on the connection signal line 231 and the GOA signal line 221. Thus, the display uniformity of the display panel 100 is improved, and the display effect of the display panel 100 is enhanced.

[0231] In some embodiments, as shown in Figures 3 and 8A, it can be set in the corner area R: along the direction in which the multiple connection signal lines 231 are arranged, the connection signal line 231 farthest from the GOA signal line group 22 in the same connection signal line group 23 is located in the first source and drain metal layer SD1.

[0232] That is, the connection signal line 231 farthest from the GOA signal line group 22 within the same connection signal line group 23 is disposed in the first source / drain metal layer SD1, closer to the gate metal layer, to reserve space in the second source / drain metal layer SD2. This ensures that, along the direction in which the multiple connection signal lines 231 are arranged, the connection signal line 231 closest to the GOA signal line group 22 within the same connection signal line group 23 is located in the second source / drain metal layer SD2. This ensures that the connection signal line 231 closest to the GOA signal line group 22 within a connection signal line group 23 is separated from the GOA signal line group 22 by at least one first source / drain metal layer SD1. This increases the spacing between the connection signal line 231 and the GOA signal line group 22 in a direction perpendicular to the substrate 10, further reducing the risk of coupling capacitance between the connection signal line 231 and the GOA signal line 221, thereby improving the load increase on the connection signal line 231 and the GOA signal line 221. This improves the display uniformity and display quality of the display panel 100.

[0233] In some embodiments, as shown in FIG3 and FIG8A , in the same connection signal line group 23 , the connection signal lines 231 are alternately arranged in the second source / drain metal layer SD2 and the first source / drain metal layer SD1 along the direction in which the connection signal lines 231 are arranged.

[0234] On the one hand, multiple connection signal lines 231 can be evenly distributed in the first source-drain metal layer SD1 and the second source-drain metal layer SD2, which facilitates the wiring layout in the first source-drain metal layer SD1 and the second source-drain metal layer SD2.

[0235] On the other hand, two adjacent connecting signal lines 231, one located in the first source / drain metal layer SD1 and the other located in the second source / drain metal layer SD2, can increase the spacing between the two connecting signal lines 231 in a direction perpendicular to the substrate 10, thereby reducing the probability of coupling capacitance forming between the two connecting signal lines 231. Furthermore, since the two adjacent connecting signal lines 231 are arranged in different layers, the spacing between them in a direction perpendicular to the substrate 10 is increased, thereby relatively reducing the spacing between the two adjacent signal lines 231 in the direction along which the multiple connecting signal lines 231 are arranged, thereby reducing the space occupied by the area formed by the orthographic projections of all the connecting signal lines 231 on the substrate 10 in the corner region R.

[0236] Thus, the spacing between the connecting signal line group 23 and the GOA signal line group 22 can be increased, so that the orthographic projection of the connecting signal line 231 on the base substrate 10 does not overlap with the orthographic projection of the GOA signal line 221 on the base substrate 10, thereby improving the problem of increased load on the GOA signal line 221 and the first signal line 211.

[0237] It should be noted that, in this context, two adjacent connection signal lines 231 refer to two connection signal lines 231 whose orthographic projections on the base substrate 10 are adjacent.

[0238] In some embodiments, in combination with Figures 3, 8A and 9, two adjacent connecting signal lines 231: one is located in the first source-drain metal layer SD1, and the other is located in the second source-drain metal layer SD2. The spacing between the two connecting signal lines 231 in the direction perpendicular to the substrate 10 can be increased to reduce the probability of forming a coupling capacitor between the two connecting signal lines 231.

[0239] Based on this, the minimum spacing (third spacing D3) between two adjacent signal lines 231 in the same signal line group 23 along the direction in which the multiple signal lines 231 are arranged can be smaller than the minimum spacing between two adjacent signal lines 231 along the direction in which the multiple signal lines 231 are arranged when all the signal lines 231 are arranged in the same layer. For example, the third spacing D3 is less than 3 μm.

[0240] Therefore, by setting two adjacent connecting signal lines 231 in different layers, the third distance D3 between any two adjacent connecting signal lines 231 can be reduced, so as to reduce the occupation of the space of the corner area R by the area formed by the orthographic projections of all the connecting signal lines 231 on the base substrate 10, and to reduce the occupation of the space of the corner area R by the area formed by the orthographic projections of all the connecting signal lines 231 in the corner area R on the base substrate 10.

[0241] Thus, the spacing between the connecting signal line group 23 and the GOA signal line group 22 in the corner area R can be increased, so that the orthographic projection of the connecting signal line 231 on the base substrate 10 does not overlap with the orthographic projection of the GOA signal line 221 on the base substrate 10, thereby improving the problem of increased load on the GOA signal line 221 and the first signal line 211.

[0242] In some examples, the third distance D3 ranges from 0.8 μm to 1.2 μm.

[0243] When the third spacing D3 is equal to or close to 0.8 μm, the minimum spacing between two adjacent signal lines 231 along the direction in which the multiple connection signal lines 231 are arranged is smaller, which can better reduce the space occupied by the area formed by the orthographic projections of all the connection signal lines 231 in the corner region R on the base substrate 10. This increases the spacing between the connection signal line group 23 and the GOA signal line group 22 in the corner region R, reduces the impact between the two, and improves the display effect of the display panel 100. Moreover, when the third spacing D3 is equal to or close to 0.8 μm, it can also meet the spacing requirements between two adjacent signal lines 231, preventing the formation of coupling capacitance between the two.

[0244] When the third spacing D3 is equal to or close to 1.2 μm, the minimum spacing between two adjacent signal lines 231 along the direction in which the multiple connection signal lines 231 are arranged is larger, which can effectively reduce the probability of coupling capacitance forming between the two adjacent signal lines 231, thereby preventing mutual influence between the two. In addition, when the third spacing D3 is equal to or close to 1.2 μm, the requirement for the first spacing D1 between the connection signal line group 23 and the GOA signal line group 22 can also be met, thereby improving the problem of increased load on the GOA signal line 221 and the first signal line 211.

[0245] For example, the third distance D3 is approximately any one of 0.8 μm, 0.9 μm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, or 1.5 μm. However, the embodiments of the present disclosure are not limited thereto.

[0246] It should be noted that the third spacing D3 is approximately 1 μm. Due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the third spacing D3 fluctuates within the range of ±10% × 1 μm, it can also be considered that the third spacing D3 is equal to 1 μm.

[0247] In some examples, in the corner region R, the line spacing (third spacing D3) between any two adjacent signal lines 231 along the direction in which the plurality of connection signal lines 231 are arranged is substantially equal. This helps improve the regularity of the arrangement of the connection signal lines 231 in the corner region R.

[0248] It should be noted that due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the difference in the line spacing between any two adjacent signal lines 231 in the second direction Y fluctuates within the range of ±10% of the line spacing between the two, it can also be considered that the difference in the line spacing between any two adjacent signal lines 231 in the second direction Y satisfies the requirement of being equal.

[0249] Figure 11A is a partial structural diagram of a display panel according to further embodiments, and Figure 11B is a cross-sectional view taken along the line F-F' in Figure 11A. Figure 11A may be a partial structural diagram of the display panel 100 at position U in the lower left corner of Figure 3. To clearly illustrate the structure of each signal line, the gate drive circuit is not shown. Specifically, as shown in Figure 11A, along the first direction X, the gate drive circuit may be located on the side of the signal line facing away from the pixel P, that is, the gate drive circuit may be located on the left side of the signal line.

[0250] It should be noted that FIG11A shows the three rows of pixel driver circuits Q corresponding to the wiring at position U in the corner region R for illustrative purposes. However, this does not mean that the wiring at position R in the corner region corresponds only to three rows of pixel driver circuits Q. In other words, the wiring at position R in the corner region may correspond to more than three rows of pixel driver circuits Q. The disclosed embodiments are not limited to this.

[0251] In some embodiments, as shown in FIG. 11A and FIG. 11B , the driving circuit layer 20 further includes a third source / drain metal layer SD3 . The third source / drain metal layer SD3 is located on a side of the second source / drain metal layer SD2 away from the first source / drain metal layer SD1 .

[0252] In some examples, the material of the third source / drain metal layer SD3 may be the same as that of the first source / drain metal layer SD1. Alternatively, in other examples, the material of the third source / drain metal layer SD3 may be different from that of the first source / drain metal layer SD1. The embodiments of the present disclosure are not limited thereto.

[0253] In some examples, a third planarization layer PLN3 is disposed between the third source / drain metal layer SD3 and the second source / drain metal layer SD2 , and the third planarization layer PLN3 electrically insulates the third source / drain metal layer SD3 from the second source / drain metal layer SD2 .

[0254] Exemplarily, the material of the third planarization layer PLN3 is generally an organic material. For example, the material of the third planarization layer PLN3 may include at least one of polyimide (English full name: Polyimide, English abbreviation: PI), acrylic-based polymer, or silicon-based polymer.

[0255] Since the material of the source-drain metal layer (the first source-drain metal layer SD1, the second source-drain metal layer SD2, and the third source-drain metal layer SD3) is different from the material of the gate metal layer (the first gate metal layer Gate1 and the second gate metal layer Gate2), the material of the source-drain metal layer (the first source-drain metal layer SD1, the second source-drain metal layer SD2, and the third source-drain metal layer SD3) may include a titanium (Ti)-aluminum (Al)-titanium (Ti) multilayer composite material, which can reduce the resistance of the signal line formed on the source-drain metal layer, so that the formed signal line has a smaller impedance.

[0256] Based on this, the connection signal lines 231 in the connection signal line group 23 can be formed in the source-drain metal layer to reduce the impedance of the connection signal lines 231 and reduce the loss of the signals transmitted on the connection signal lines 231. Specifically, in the same connection signal line group 23, a portion of the connection signal lines 231 is located in the first source-drain metal layer SD1, another portion of the connection signal lines 231 is located in the second source-drain metal layer SD2, and another portion of the connection signal lines 231 is located in the third source-drain metal layer SD3.

[0257] In this configuration, disposing the multiple connection signal lines 231 in the connection signal line group 23 in different layers in the first source-drain metal layer SD1, the second source-drain metal layer SD2, and the third source-drain metal layer SD3 can reduce the orthographic projection of all the connection signal lines 231 on the base substrate 10 and the space occupied by the corner area R. Furthermore, the spacing between the connection signal line group 23 and the GOA signal line group 22 can be increased to ensure that the orthographic projection of the connection signal line 231 on the base substrate 10 does not overlap with the orthographic projection of the GOA signal line 221 on the base substrate 10. This alleviates the problem of increased load on the GOA signal line 221 and the first signal line 211.

[0258] In addition, since the GOA signal lines 221 in the GOA signal line group 22 can be dispersed in the first gate metal layer Gate1 and the second gate metal layer Gate2, the multiple connection signal lines 231 in the connection signal line group 23 are arranged in different layers in the first source-drain metal layer SD1, the second source-drain metal layer SD2, and the third source-drain metal layer SD3. This can also increase the spacing between the connection signal lines 231 and the GOA signal lines 221 in a direction perpendicular to the substrate 10, thereby preventing the formation of capacitance therebetween, which would increase the load on the connection signal lines 231 and the GOA signal lines 221.

[0259] In some embodiments, as shown in Figures 11A and 11B, in the corner area R: along the direction in which the multiple connection signal lines 231 are arranged, the connection signal line 231 closest to the GOA signal line group 22 in the same connection signal line group 23 is located in the third source and drain metal layer SD3.

[0260] Based on this, the connection signal line 231 closest to the GOA signal line group 22 in the same connection signal line group 23 can be separated from the GOA signal line group 22 by at least the first source-drain metal layer SD1 and the second source-drain metal layer SD2. This can increase the distance between the two in a direction perpendicular to the substrate 10, further reducing the risk of coupling capacitance between the two, thereby improving the problem of increased load on the connection signal line 231 and the GOA signal line 221. Thus, the display uniformity of the display panel 100 is improved, and the display effect of the display panel 100 is enhanced.

[0261] In some embodiments, as shown in Figures 11A and 11B, it can be set in the corner area R: along the direction in which the multiple connection signal lines 231 are arranged, the connection signal line 231 farthest from the GOA signal line group 22 in the same connection signal line group 23 is located in the first source and drain metal layer SD1.

[0262] That is, the connection signal line 231 farthest from the GOA signal line group 22 within the same connection signal line group 23 is disposed in the first source / drain metal layer SD1, which is closer to the gate metal layer, to reserve space in the third source / drain metal layer SD3. This ensures that, along the direction in which the multiple connection signal lines 231 are arranged, the connection signal line 231 closest to the GOA signal line group 22 within the same connection signal line group 23 is located in the third source / drain metal layer SD3. This ensures that the connection signal line 231 closest to the GOA signal line group 22 within the same connection signal line group 23 is separated from the GOA signal line group 22 by at least two source / drain metal layers. This increases the spacing between the connection signal line 231 and the GOA signal line group 22 in a direction perpendicular to the substrate 10, further reducing the risk of coupling capacitance between the connection signal line 231 and the GOA signal line 221, thereby improving the load increase on the connection signal line 231 and the GOA signal line 221. This improves the display uniformity and display quality of the display panel 100.

[0263] In some embodiments, as shown in Figures 11A and 11B, along the direction in which the multiple connecting signal lines 231 are arranged, in the same connecting signal line group 23, the multiple connecting signal lines 231 are alternately arranged in the third source-drain metal layer SD3, the second source-drain metal layer SD2 and the first source-drain metal layer SD1.

[0264] For example, the same connection signal line group 23 includes six connection signal lines 231. Here, along the direction in which the multiple connection signal lines 231 are arranged, in the same connection signal line group 23, the first connection signal line is located in the third source-drain metal layer SD3, the second connection signal line is located in the second source-drain metal layer SD2, the third connection signal line is located in the first source-drain metal layer SD1, the fourth connection signal line is located in the third source-drain metal layer SD3, the fifth connection signal line is located in the second source-drain metal layer SD2, and the sixth connection signal line is located in the first source-drain metal layer SD1.

[0265] On the one hand, multiple connecting signal lines 231 can be evenly distributed in the first source-drain metal layer SD1, the second source-drain metal layer SD2 and the third source-drain metal layer SD3, which facilitates the routing layout in the first source-drain metal layer SD1, the second source-drain metal layer SD2 and the third source-drain metal layer SD3.

[0266] On the other hand, within the same connecting signal line group 23, three consecutively adjacent connecting signal lines 231 are: one located in the first source / drain metal layer SD1, another located in the second source / drain metal layer SD2, and yet another located in the third source / drain metal layer SD3. That is, the three consecutively adjacent connecting signal lines 231 within the same connecting signal line group 23 are distributed across three source / drain metal layers, thereby increasing the spacing between any two adjacent connecting signal lines 231 in a direction perpendicular to the base substrate 10. This can further reduce the spacing between any two adjacent signal lines 231 in the direction along which the multiple connecting signal lines 231 are arranged, thereby reducing the space occupied by the corner region R formed by the orthographic projections of all the connecting signal lines 231 on the base substrate 10. This increases the spacing between the connecting signal line group 23 and the GOA signal line group 22, thereby alleviating the problem of increased load on the GOA signal line 221 and the first signal line 211.

[0267] It should be noted that, in this context, two adjacent connection signal lines 231 refer to two connection signal lines 231 whose orthographic projections on the base substrate 10 are adjacent.

[0268] FIG12 is a partial enlarged view of M3 in FIG11A .

[0269] In some embodiments, as shown in conjunction with FIG11A , FIG11B , and FIG12 , within the corner region R, three adjacent connecting signal lines 231 in the same connecting signal line group 23 are sequentially located: one located in the first source / drain metal layer SD1, another located in the second source / drain metal layer SD2, and a third located in the third source / drain metal layer SD3. In other words, disposing any two adjacent connecting signal lines 231 in different layers can increase the spacing between the two connecting signal lines 231 in a direction perpendicular to the substrate 10, thereby reducing the likelihood of coupling capacitance forming between the two connecting signal lines 231.

[0270] Based on this, the minimum spacing (fourth spacing D4) between two adjacent signal lines 231 in the same signal line group 23 along the direction in which the multiple signal lines 231 are arranged can be smaller than the minimum spacing between two adjacent signal lines 231 along the direction in which the multiple signal lines 231 are arranged when all the signal lines 231 are arranged in the same layer. In other words, the fourth spacing D4 is less than 3 μm.

[0271] Therefore, the three adjacent connecting signal lines 231 in the same connecting signal line group 23 are distributed in three source and drain metal layers, which can reduce the fourth distance D4 between any two adjacent connecting signal lines 231, so as to reduce the occupation of the corner area R space by the area formed by the orthographic projections of all the connecting signal lines 231 on the base substrate 10, so as to reduce the occupation of the corner area R space by the area formed by the orthographic projections of all the connecting signal lines 231 in the corner area R on the base substrate 10.

[0272] Thus, the spacing between the connecting signal line group 23 and the GOA signal line group 22 in the corner area R can be increased, so that the orthographic projection of the connecting signal line 231 on the base substrate 10 does not overlap with the orthographic projection of the GOA signal line 221 on the base substrate 10, thereby improving the problem of increased load on the GOA signal line 221 and the first signal line 211.

[0273] In some examples, the fourth distance D4 ranges from 0.8 μm to 1.2 μm.

[0274] When the fourth spacing D4 is equal to or close to 0.8 μm, the minimum spacing between two adjacent signal lines 231 along the direction in which the multiple connection signal lines 231 are arranged is smaller, which can better reduce the space occupied by the area formed by the orthographic projections of all the connection signal lines 231 on the base substrate 10 in the corner region R. This increases the spacing between the connection signal line group 23 and the GOA signal line group 22 in the corner region R, reduces the impact between the two, and improves the display effect of the display panel 100. In addition, when the fourth spacing D4 is equal to or close to 0.8 μm, it can also meet the spacing requirements between two adjacent signal lines 231, preventing the formation of coupling capacitance between the two.

[0275] When the fourth spacing D4 is equal to or close to 1.2 μm, the minimum spacing between two adjacent signal lines 231 along the direction in which the multiple connection signal lines 231 are arranged is larger, which can effectively reduce the probability of coupling capacitance forming between the two adjacent signal lines 231, thereby preventing mutual influence between the two. In addition, when the fourth spacing D4 is equal to or close to 1.2 μm, the requirement for the first spacing D1 between the connection signal line group 23 and the GOA signal line group 22 can also be met, thereby improving the problem of increased load on the GOA signal line 221 and the first signal line 211.

[0276] Exemplarily, the fourth distance D4 is approximately any one of 0.8 μm, 0.9 μm, 1 μm, 1.1 μm, 1.2 μm, 1.3 μm, 1.4 μm, or 1.5 μm. However, the embodiments of the present disclosure are not limited thereto.

[0277] It should be noted that the fourth spacing D4 is approximately 1 μm. Due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the fourth spacing D4 fluctuates within the range of ±10% × 1 μm, it can also be considered that the fourth spacing D4 is equal to 1 μm.

[0278] In some examples, in the corner region R, the line spacing (fourth spacing D4) between any two adjacent signal lines 231 along the direction in which the plurality of connection signal lines 231 are arranged is substantially equal. This helps improve the regularity of the arrangement of the connection signal lines 231 in the corner region R.

[0279] It should be noted that due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the difference in the line spacing between any two adjacent signal lines 231 in the second direction Y fluctuates within the range of ±10% of the line spacing between the two, it can also be considered that the difference in the line spacing between any two adjacent signal lines 231 in the second direction Y satisfies the requirement of being equal.

[0280] Figure 13A is a structural diagram of a corner region according to some embodiments, and Figure 13B is a cross-sectional view taken along the J-J' line in Figure 13A. Figure 13A may be a partial structural diagram of the lower left corner U of the display panel 100 in Figure 3. To clearly illustrate the structure of each signal line, the gate drive circuit is not shown. Specifically, as shown in Figure 13A, along the first direction X, the gate drive circuit may be located on the side of the signal line facing away from the pixel P, that is, the gate drive circuit may be located on the left side of the signal line.

[0281] It should be noted that in FIG13A , the wiring at position U in the corner region R corresponds to three rows of pixel driving circuits Q for illustrative purposes. However, this does not mean that the wiring at position R in the corner region corresponds to only three rows of pixel driving circuits Q. In other words, the wiring at position R in the corner region can correspond to more than three rows of pixel driving circuits Q. The disclosed embodiments are not limited to this.

[0282] In some embodiments, as shown in Figures 13A and 13B, the connecting signal line 231 located in the first source-drain metal layer SD1 is a first type of connecting signal line 2311, the connecting signal line 231 located in the second source-drain metal layer SD2 is a second type of connecting signal line 2312, and the connecting signal line 231 located in the third source-drain metal layer SD3 is a third type of connecting signal line 2313.

[0283] Because the minimum distance between the third connecting signal line 2313 located in the third source-drain metal layer SD3 and the first connecting signal line 2311 located in the first source-drain metal layer SD1 in the direction perpendicular to the substrate 10 is smaller than the minimum distance between the third connecting signal line 2313 located in the third source-drain metal layer SD3 and the second connecting signal line 2312 located in the second source-drain metal layer SD2 in the direction perpendicular to the substrate 10.

[0284] Therefore, the distance between the adjacent third-type connection signal lines 2313 and the first-type connection signal lines 2311 in the direction perpendicular to the base substrate 10 can be made larger, and coupling capacitance is not easily formed between the two.

[0285] Based on this, in the corner area R: the minimum spacing (fifth spacing D5) between the adjacent third connecting signal lines 2313 and the second connecting signal lines 2312 in the substrate substrate 10 is less than or equal to the minimum spacing (sixth spacing D6) between the adjacent third connecting signal lines 2313 and the first connecting signal lines 2311 in the substrate substrate 10.

[0286] Thus, the spacing (fifth spacing D5) between adjacent third-type connecting signal lines 2313 and first-type connecting signal lines 2311 along the arrangement direction of the plurality of connecting signal lines 231 can be reduced. Furthermore, the space occupied by the area formed by the orthographic projections of all connecting signal lines 231 on the base substrate 10 in the corner region R can be further reduced, thereby reducing the space occupied by the area formed by the orthographic projections of all connecting signal lines 231 in the corner region R on the base substrate 10.

[0287] In some examples, within the corner area R: among the sequentially adjacent second connecting signal lines 2312, the third connecting signal lines 2313 and the first connecting signal lines 2311: the minimum spacing (fifth spacing D5) between the third connecting signal lines 2313 and the second connecting signal lines 2312 in the substrate substrate 10 is less than or equal to the minimum spacing (sixth spacing D6) between the third connecting signal lines 2313 and the second connecting signal lines 2312 in the substrate substrate 10.

[0288] Based on this, it is possible to prevent the minimum spacing (fifth spacing D5) between the orthographic projections of the third-type connecting signal line 2313 and its adjacent second-type connecting signal line 2312 on the base substrate 10 from being greater than the minimum spacing (sixth spacing D6) between the orthographic projections of the third-type connecting signal line 2313 and its adjacent first-type connecting signal line 2311 on the base substrate 10. Thus, within the corner region R, coupling capacitance is unlikely to form between any two adjacent connecting signal lines 231, thereby preventing the problem of increased load on the connecting signal lines 231 caused by mutual influence between the two.

[0289] In some examples, within the corner region R, the minimum spacing between at least two adjacent groups of the third type of connecting signal lines 2313 and the second type of connecting signal lines 2312 on the substrate 10 is approximately equal. In other examples, within the corner region R, the minimum spacing between at least two adjacent groups of the third type of connecting signal lines 2313 and the first type of connecting signal lines 2311 on the substrate 10 is approximately equal. In still other examples, within the corner region R, the minimum spacing between at least two adjacent groups of the second type of connecting signal lines 2312 and the first type of connecting signal lines 2311 on the substrate 10 is approximately equal. This helps improve the regularity of the arrangement of the connecting signal lines 231 at the corner region R.

[0290] FIG14 is a partial enlarged view of W1 in FIG3 . FIG14 clearly illustrates the arrangement of the data write signal line Dt in the display panel 100 , and does not illustrate other lines. For example, FIG14 does not illustrate the first connection signal line and the first power signal line.

[0291] In some embodiments, as shown in FIG14 , the display panel 100 further includes a light-transmitting area K, with a display area AA surrounding the light-transmitting area K. The drive circuit layer 20 further includes a plurality of data write signal lines Dt extending along the second direction Y and arranged in the first direction X. These lines are located in the display area AA, with each data write signal line Dt electrically connected to at least one column of pixel drive circuits Q. The data write signal line Dt is configured to provide a data write signal to the pixel drive circuits Q to which it is electrically connected. The following description uses the example of one data write signal line Dt electrically connected to one column of pixel drive circuits Q.

[0292] The multiple data write signal lines Dt include a target signal line Dt1. The target signal line Dt1 includes a lead portion H1 and a winding portion H2 connected to each other. The lead portion H1 extends along the second direction Y, and the extension line of the lead portion H1 passes through the light-transmitting area K. The winding portion H2 is arranged along the edge of the light-transmitting area K. The winding portions H2 of the multiple target signal lines Dt1 are all arranged along the edge of the light-transmitting area K, which may cause at least a portion of the winding portion H2 to extend outside the display area AA.

[0293] Based on this, the target signal line Dt1 can avoid the light-transmitting area K by using the winding portion H2 to prevent the target signal line Dt1 from reducing the transmittance of the light-transmitting area K.

[0294] Exemplarily, the light-transmitting area K may be a camera area or a fingerprint recognition area, etc. The following only takes the light-transmitting area K as an example of a camera area, but the same is applicable to fingerprint recognition.

[0295] FIG. 15 is a cross-sectional structural diagram of a display panel according to some other embodiments.

[0296] In some examples, as shown in FIG15 , the light emitting device layer 30 includes an anode layer 31, a light emitting functional layer 32, and a cathode layer 33 stacked in sequence in a direction away from the base substrate 10. The light emitting functional layer 32 includes an emitting layer (EML).

[0297] In some examples, the light-emitting functional layer 32 includes, in addition to the light-emitting layer, one or more layers of an electron transporting layer (ETL), an electron injection layer (EIL), a hole transporting layer (HTL), and a hole injection layer (HIL).

[0298] In some examples, when the display panel 100 is an electroluminescent display panel, the display panel 100 can be a top-emitting display panel, in which case the anode layer 31 close to the base substrate 10 is opaque, and the cathode layer 33 away from the base substrate 10 is transparent or translucent; the display panel 100 can also be a bottom-emitting display panel, in which case the anode layer 31 close to the base substrate 10 is transparent or translucent, and the cathode layer 33 away from the base substrate 10 is opaque; the display panel 100 can also be a double-sided light-emitting display panel, in which case the anode layer 31 close to the base substrate 10 and the cathode layer 33 away from the base substrate 10 are both transparent or translucent.

[0299] FIG16 is a diagram illustrating a film layer structure of a display panel according to some other embodiments. The structure of the display panel shown in FIG16 corresponds to the film layer structure diagram at position W2 in FIG14 .

[0300] In some examples, in combination with Figures 14 to 16, the display panel 100 also includes an auxiliary electrode 50, which is located on at least one side of the display area AA, and the auxiliary electrode 50 is in the same layer as the anode layer 31, the auxiliary electrode 50 is electrically connected to the cathode layer 33, and the auxiliary electrode 50 is also electrically connected to the second power signal line Vss (as shown in Figure 5).

[0301] Based on this, the auxiliary electrode 50 can be used to reduce the overall impedance of the cathode layer 33, reduce or eliminate the IR drop phenomenon in the cathode layer 33, and improve the display effect of the display panel 100. In addition, arranging the auxiliary electrode 50 in the same layer as the anode layer 31 can simplify the manufacturing process of the display panel 100.

[0302] It should be noted that "same layer" refers to a layer structure formed using the same film-forming process to form a specific pattern, and then using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0303] In some examples, the auxiliary electrode 50 is disposed around the display area AA, which is advantageous for increasing the size of the auxiliary electrode 50 to further reduce the overall impedance of the cathode layer 33 .

[0304] In some embodiments, as shown in Figures 14 to 16 , the auxiliary electrode 50 includes an opening G on a side near the display area AA, the opening facing the display area AA. The portion of the winding portion H2 of the target signal line Dt1 that is outside the display area AA in the orthographic projection onto the base substrate 10 extends into the opening G.

[0305] That is, the orthographic projection of the winding portion H2 extending outside the display area AA on the base substrate 10 does not overlap with the orthographic projection of the auxiliary electrode 50 on the base substrate 10. This prevents the orthographic projections of the two on the base substrate 10 from overlapping, which would increase the load on the target signal line Dt1 and affect the display quality of the display panel 100.

[0306] In some examples, the display panel further includes a peripheral area SA, which is disposed around the display area AA. The peripheral area SA includes a first border area SA1 and a second border area SA2. Furthermore, the peripheral area SA includes a third border area SA3. Along the second direction Y, the display area AA is located between the second border area SA2 and the third border area SA3.

[0307] When the distance between the light-transmitting area K and the third frame area SA3 is smaller than the distance between the light-transmitting area K and the second frame area SA2 along the second direction Y, the light-transmitting area K is closer to the third frame area SA3 than to the second frame area SA2. In this case, the auxiliary electrode 50 located in the third frame area SA3 includes an opening G on a side close to the display area AA, and the orthographic projection of the winding portion H2 extending outside the display area AA on the base substrate 10 is located in the third frame area SA3.

[0308] This configuration can prevent the length of the winding portion H2 of the target signal line Dt1 from being too long, thereby preventing the wiring layout in the display panel 100 from being increased.

[0309] In some examples, the minimum spacing between the winding portion H2 of adjacent target signal lines Dt1 and the orthographic projections of the auxiliary electrodes 50 on the base substrate 10 is greater than or equal to 5 μm. That is, the minimum spacing between the portion of the winding portion H2 of the target signal line Dt1 that is located outside the display area AA and extends into the opening G in the orthographic projection on the base substrate 10 and the boundary of the opening G on the side closest to the display area AA is greater than or equal to 5 μm.

[0310] Such an arrangement can make the minimum distance between the winding portion H2 of the adjacent target signal line Dt1 and the orthographic projection of the auxiliary electrode 50 on the base substrate 10 larger, so as to prevent the parasitic capacitance generated due to the close distance between the two, resulting in an increase in the load of the target signal line Dt1.

[0311] In some examples, a minimum distance between the winding portions H2 of adjacent target signal lines Dt1 and orthographic projections of the auxiliary electrodes 50 on the base substrate 10 is less than or equal to 15 μm.

[0312] This configuration can prevent the minimum distance between the winding portion H2 of the adjacent target signal line Dt1 and the orthographic projection of the auxiliary electrode 50 on the base substrate 10 from being too large, thereby causing the winding portion H2 of the target signal line Dt1 to occupy too much space in the peripheral area SA.

[0313] In some examples, the minimum distance between the winding portions H2 of adjacent target signal lines Dt1 and the orthographic projections of the auxiliary electrodes 50 on the base substrate 10 ranges from 5 μm to 15 μm.

[0314] Such a configuration can not only make the distance between the winding portion H2 of the adjacent target signal line Dt1 and the auxiliary electrode 50 larger to prevent the formation of capacitance therebetween and thereby increase the load on the target signal line Dt1, but also meet the display panel 100's requirement for the size of the peripheral area SA.

[0315] In some other examples, the minimum distance between the winding portions H2 of adjacent target signal lines Dt1 and the orthographic projections of the auxiliary electrodes 50 on the base substrate 10 ranges from 5 μm to 10 μm.

[0316] This configuration can not only increase the distance between the winding portion H2 of the adjacent target signal line Dt1 and the auxiliary electrode 50 to prevent the formation of capacitance therebetween and thereby increase the load on the target signal line Dt1 , but also reduce the size of the peripheral area SA of the display panel 100 .

[0317] Illustratively, the minimum distance between the winding portions H2 of adjacent target signal lines Dt1 and the orthographic projections of the auxiliary electrodes 50 on the base substrate 10 is approximately 5 μm, 6 μm, 8 μm, 10 μm, 12 μm, or 15 μm. However, the present disclosure is not limited thereto.

[0318] It should be noted that, in the following description, the minimum spacing between the winding portions H2 of adjacent target signal lines Dt1 and the orthographic projections of the auxiliary electrodes 50 on the base substrate 10 is approximately 8 μm. Due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the minimum spacing between the winding portions H2 of adjacent target signal lines Dt1 and the orthographic projections of the auxiliary electrodes 50 on the base substrate 10 fluctuates within a range of ±10% × 8 μm, it can also be considered that the minimum spacing between the winding portions H2 of adjacent target signal lines Dt1 and the orthographic projections of the auxiliary electrodes 50 on the base substrate 10 satisfies the requirement of 8 μm.

[0319] Because the winding portion H2 of the target signal line Dt1 closest to the auxiliary electrode 50 is located on a side facing away from the auxiliary electrode 50, multiple winding portions H2 of the target signal line Dt1 are located. However, no other wiring portions are located between the winding portion H2 of the target signal line Dt1 closest to the auxiliary electrode 50 and the auxiliary electrode 50. In other words, the area between the winding portion H2 of the target signal line Dt1 closest to the auxiliary electrode 50 and the auxiliary electrode 50 is a blank area.

[0320] Based on this, when forming the data write signal line Dt through etching, the different density and number of winding portions L2 on either side of the target signal line Dt1 closest to the auxiliary electrode 50 can lead to a loading effect during the etching process, resulting in uneven development and etching. Areas with less loading will have a greater amount of etching, leading to reduced line width or even line breakage. In other words, due to the significant difference in pattern density on either side of the target signal line Dt1 closest to the auxiliary electrode 50, the winding portion H2 of the target signal line Dt1 closest to the auxiliary electrode 50 is prone to reduced line width or even line breakage.

[0321] FIG17 is a diagram illustrating a film layer structure of a display panel according to some other embodiments. The structure of the display panel shown in FIG17 corresponds to the film layer structure diagram at position W2 in FIG14 .

[0322] Based on this, in some embodiments, in combination with Figures 14 and 17, the display panel 100 also includes a virtual signal line 60, which is on the same layer as the data write signal line Dt, and the orthographic projection of the virtual signal line 60 on the base substrate 10 is located between the auxiliary electrode 50 and the orthographic projection of the adjacent winding portion H2 on the base substrate 10.

[0323] In this way, routing can be provided on both sides of the target signal line Dt1 closest to the auxiliary electrode 50, and the virtual signal line 60 can be used to indirectly protect the target signal line Dt1 closest to the auxiliary electrode 50, thereby preventing the winding part H2 of the target signal line Dt1 closest to the auxiliary electrode 50 from easily becoming smaller in line width or even breaking.

[0324] In addition, the virtual signal line 60 is on the same layer as the data write signal line Dt, which not only improves the problem of the winding portion H2 of the target signal line Dt1 close to the auxiliary electrode 50 being prone to line width reduction or even breakage, but also does not require the addition of new process steps, which is conducive to simplifying the manufacturing process of the display panel 100.

[0325] It should be noted that "same layer" refers to a layer structure formed using the same film-forming process to form a specific pattern, and then using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0326] In some examples, along the second direction Y, the distance between the dummy signal line 60 and the winding portion H2 of the target signal line Dt1 closest to the auxiliary electrode 50 is approximately equal to the distance between any two adjacent data writing signal lines Dt.

[0327] This arrangement ensures that the spacing between the winding portion H2 of the target signal line Dt1 closest to the auxiliary electrode 50 and the lines on either side thereof is approximately equal, thereby better balancing the etching rates on both sides of the winding portion H2 of the target signal line Dt1 closest to the auxiliary electrode 50. This prevents the winding portion H2 of the target signal line Dt1 closest to the auxiliary electrode 50 from being susceptible to line width reduction or even line breakage due to different etching rates. Furthermore, this arrangement facilitates a regular arrangement of lines within the display panel 100.

[0328] It should be noted that due to certain uncontrollable errors (such as manufacturing process errors, equipment accuracy, measurement errors, etc.), when the spacing (seventh spacing) between the virtual signal line 60 and the winding portion H2 of the target signal line Dt1 closest to the auxiliary electrode 50 in the second direction Y is approximately equal to the difference between the spacing (eighth spacing) between any two adjacent data write signal lines Dt and fluctuates within the range of ±10% of the seventh spacing or the eighth spacing, the seventh spacing and the eighth spacing can also be considered to be equal.

[0329] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A display panel having a display area, a first border area, a second border area, and a bonding area, wherein the first border area includes a corner area; in a first direction, the first border area is located on at least one side of the display area, and in a second direction, the second border area is located on one side of the display area, and the bonding area is located on a side of the second border area away from the display area; The first direction intersects with the second direction; The display panel comprises: substrate substrate; A plurality of pixel driving circuits are located on the base substrate of the display area; A plurality of gate driving circuits are located on the base substrate in the first border area; A plurality of GOA signal line groups, one of the GOA signal line groups is electrically connected to one of the gate driving circuits, and the GOA signal line group extends along the first border area and extends to the binding area via the corner area; A plurality of connection signal line groups, located in the first border area, wherein one of the connection signal line groups is electrically connected to at least one row of the pixel driving circuits and is electrically connected to the plurality of gate driving circuits; The connecting signal line group includes multiple connecting signal lines, and in the same connecting signal line group: a part of the connecting signal lines are located in the first source-drain metal layer, and another part of the connecting signal lines are located in the second source-drain metal layer, wherein the first source-drain metal layer is located between the substrate and the second source-drain metal layer; in the corner area: adjacent connecting signal line groups and GOA signal line groups have a first spacing between their orthographic projections on the substrate.

2. The display panel according to claim 1, wherein, The first spacing is greater than or equal to 1.5 μm.

3. The display panel according to claim 1 or 2, further comprising a gate metal layer, wherein the gate metal layer is located between the base substrate and the first source-drain metal layer; and the GOA signal line group is located in the gate metal layer; In the corner area: along the arrangement direction of the plurality of connection signal lines, the connection signal line closest to the GOA signal line group in the same connection signal line group is located in the second source-drain metal layer.

4. The display panel according to any one of claims 1 to 3, wherein, In the same connecting signal line group: along the second direction, a plurality of connecting signal lines are alternately arranged in the second source-drain metal layer and the first source-drain metal layer.

5. The display panel according to claim 1 or 2, further comprising a gate metal layer and a third source-drain metal layer; The gate metal layer is located between the substrate and the first source-drain metal layer, and the GOA signal line group is located in the gate metal layer; The third source-drain metal layer is located on a side of the second source-drain metal layer away from the first source-drain metal layer; in the same connecting signal line group: another part of the connecting signal lines is located in the third source-drain metal layer.

6. The display panel according to claim 5, wherein, In the corner area: along the direction in which the plurality of connection signal lines are arranged, the connection signal line closest to the GOA signal line group in the same connection signal line group is located in the third source-drain metal layer.

7. The display panel according to claim 5 or 6, wherein, Along the direction in which the plurality of connection signal lines are arranged, in the same connection signal line group, the plurality of connection signal lines are alternately arranged in the third source-drain metal layer, the second source-drain metal layer and the first source-drain metal layer.

8. The display panel according to claim 4 or 7, wherein, In the same group of connection signal lines: along the direction in which the plurality of connection signal lines are arranged, the minimum spacing between two adjacent connection signal lines ranges from 0.8 μm to 1.2 μm.

9. The display panel according to any one of claims 5 to 7, wherein The connection signal line in the first source-drain metal layer is a first type of connection signal line, the connection signal line in the second source-drain metal layer is a second type of connection signal line, and the connection signal line in the third source-drain metal layer is a third type of connection signal line; In the corner area: the minimum distance between adjacent third connection signal lines and the first connection signal lines is less than or equal to the minimum distance between adjacent third connection signal lines and the second connection signal lines.

10. The display panel according to any one of claims 1 to 9, wherein, Among the multiple first signal lines in the same first signal line group: there are multiple initialization signal lines and multiple gate signal lines; In the corner area: in the same connection signal line group, the connection signal line electrically connected to the initialization signal line is located on the side closer to the GOA signal line group than the connection signal line electrically connected to the gate signal line.

11. The display panel according to any one of claims 1 to 10 further includes a gate metal layer, and the gate metal layer is located between the substrate and the first source-drain metal layer; the GOA signal line group is located in the gate metal layer; The gate metal layer includes a first gate metal layer and a second gate metal layer, and the first gate metal layer is located between the substrate and the second gate metal layer; The GOA signal line group includes multiple GOA signal lines. In the corner area: in the direction of arrangement of the multiple GOA signal lines, the GOA signal line closest to the connection signal line group in the same GOA signal line group is located in the first gate metal layer.

12. The display panel according to any one of claims 1 to 11 has a light-transmitting area, and the display area surrounds the light-transmitting area; the display panel further includes: Multiple data writing signal lines, located in the display area, and one data writing signal line is electrically connected to at least one column of the pixel driving circuits; The multiple data writing signal lines include a target signal line, and the target signal line includes a connected lead portion and a winding portion. The lead portion extends along the second direction, and the extension line of the lead portion penetrates the light-transmitting area. The winding portion is arranged along the edge of the light-transmitting area, and at least part of the winding portion extends outside the display area.

13. The display panel according to claim 12 further includes: A light-emitting device layer, located on the side of the pixel driving circuit away from the substrate. In the direction away from the substrate, the light-emitting device layer includes an anode layer, a light-emitting layer, and a cathode layer; An auxiliary electrode, located on at least one side of the display area, and the auxiliary electrode is on the same layer as the anode layer, and the auxiliary electrode is electrically connected to the cathode layer.

14. The display panel according to claim 13, wherein, The side of the auxiliary electrode close to the display area includes an opening, and the opening faces the display area; The part of the winding portion located outside the display area in the orthographic projection on the substrate extends into the opening.

15. The display panel according to any one of claims 12 to 14 further includes a virtual signal line, the virtual signal line being on the same layer as the data writing signal line, and a positive projection of the virtual signal line on the substrate being located between a winding portion of the adjacent target signal line and a positive projection of the auxiliary electrode on the substrate.

16. A display device includes: the display panel according to any one of claims 1 to 15; and a cover plate disposed on a light-emitting side of the display panel.

Images