Encoding method and device, and decoding method and device

Abstract

Embodiments of the present application relate to the technical field of media, and disclose an encoding method and device, and a decoding method and device, for improving the image quality of AI image encoding. The method comprises: performing AI encoding on an input image so as to obtain a feature map; performing entropy encoding on the feature map so as to obtain a bitstream; performing a transformation operation on a target area of the input image so as to obtain a transformation coefficient; encoding the transformation coefficient to the bitstream; and encoding position information to the bitstream, wherein the position information is used for indicating the position of the target area in the input image.

Description

Coding and decoding method and device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on January 18, 2024, with application number 202410077119.2 and application name “Encoding Method”, and the Chinese patent application filed with the China Intellectual Property Office on February 5, 2024, with application number 202410166019.7 and application name “Encoding and Decoding Method and Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of media technology, and in particular to encoding and decoding methods and devices. Background Art

[0003] Breakthroughs have been made in artificial intelligence (AI) image coding, significantly improving compression efficiency compared to commonly used image coding standards while maintaining comparable subjective quality. AI image coding is widely used in various fields, including cloud storage, visual surveillance, autonomous vehicles and equipment, image acquisition, storage, and management, real-time monitoring of visual data, and media distribution.

[0004] In the case of lossy coding at medium and low bit rates, the compression ratio of the AI ​​image coding scheme is significantly better than that of the traditional image coding scheme under the same quality conditions; but in the case of extremely high bit rates or near visual losslessness, the image quality of AI image coding is poor due to factors such as network capacity and network generalization.

[0005] Summary of the Invention

[0006] The present application embodiment provides an encoding method for improving the image quality of AI image encoding. To achieve the above purpose, the present application embodiment adopts the following technical solutions:

[0007] In a first aspect, embodiments of the present application provide an encoding method, comprising: performing AI encoding on an input image to obtain a feature map; performing entropy encoding on the feature map to obtain a bitstream; performing a transform operation on a target region of the input image to obtain transform coefficients; encoding the transform coefficients into the bitstream; and encoding position information into the bitstream. The position information indicates the position of the target region in the input image.

[0008] The method provided in the embodiments of this application additionally enhances the quality of localized image regions using traditional encoding schemes, compensating for the significant localized image distortion caused by the capacity and generalization of AI encoding networks. Compared to AI encoding only of the input image, additionally enhancing the quality of localized image regions using traditional encoding schemes can improve the overall image quality of AI image encoding.

[0009] In a possible implementation, the target area may be divided into a plurality of image blocks; and the transformation operation may be performed on the plurality of image blocks to obtain transformation coefficients.

[0010] The method provided in the embodiments of this application additionally divides a local region of the input image into multiple image blocks and performs a transformation operation on the local region of the input image, thereby improving the image quality of the local region of the input image. Compared to performing AI encoding only on the input image, the additional transformation operation on the local region of the input image can improve the image quality of AI image encoding.

[0011] In a possible implementation, the position information may be entropy encoded into the bitstream.

[0012] It can be seen that the position information indicating the position of the target area in the input image can be encoded into the bitstream by entropy coding.

[0013] In a possible implementation, the transform coefficients may be entropy encoded into the bitstream.

[0014] It can be seen that the transform coefficients indicating the coefficients used for performing the transform operation on the target area can be encoded into the bitstream by entropy coding.

[0015] In one possible implementation, the transform coefficients are quantized and encoded into the bitstream. Quantization can reduce the bit depth associated with the transform coefficients.

[0016] In a possible implementation, the transformation parameters may be encoded (entropy encoded) into the above-mentioned bitstream, wherein the transformation parameters are the transformation parameters used in the above-mentioned transformation operation.

[0017] In a possible implementation, the transform operation may include at least one of discrete cosine transform (DCT), discrete Fourier transform (DFT), or discrete wavelet transform (DWT).

[0018] The method provided in the embodiments of this application performs additional transform operations, such as DCT, DFT, or DWT, on local regions of the input image, thereby improving the image quality of these local regions. Compared to AI encoding alone, the additional transform operations on local regions of the input image can improve the image quality of AI image encoding.

[0019] In a possible implementation, the position information is mask information, and the mask information includes a first region, and the first region is used to indicate the target region. For example, the mask may be composed of 0s and 1s, and the region where 1s are located is the target region.

[0020] It can be seen that the position information indicating the position of the target area in the input image can be saved in the form of a mask image.

[0021] In a possible implementation, the above-mentioned transformation coefficient may be a residual.

[0022] In a second aspect, an embodiment of the present application provides a decoding method, comprising: performing entropy decoding on a bitstream to obtain a feature map; performing AI decoding on the feature map to obtain a reconstructed image; performing entropy decoding on the bitstream to obtain transform coefficients; performing an inverse transform operation on the transform coefficients to obtain reconstructed pixel values ​​of a target area; performing entropy decoding on the bitstream to obtain position information; and determining a fused image based on the position information, the reconstructed pixel values ​​of the target area, and the reconstructed image. The position information indicates the position of the target area of ​​the reconstructed image.

[0023] The method provided in the embodiments of this application additionally enhances image quality using traditional decoding solutions in localized areas, compensating for the significant localized image distortion caused by AI decoding network capacity and generalization. Compared to simply AI encoding the bitstream to reconstruct the image, additionally enhancing image quality using traditional decoding solutions in localized areas can improve the overall image quality of AI image decoding.

[0024] In a possible implementation, the target area in the reconstructed image may be determined according to the position information; and the pixel value of the target area in the reconstructed image may be updated according to the reconstructed pixel value to obtain the fused image.

[0025] In a possible implementation, entropy decoding is performed on the code stream to obtain quantized transform coefficients; and dequantization is performed on the quantized transform coefficients to obtain the transform coefficients.

[0026] In a possible implementation, the above transform coefficients may be inversely quantized.

[0027] In a third aspect, an embodiment of the present application provides an encoding device, comprising: an encoding unit and a transform unit. The encoding unit is configured to perform AI encoding on an input image to obtain a feature map. The encoding unit is further configured to perform entropy encoding on the feature map to obtain a code stream. The transform unit is configured to perform a transform operation on a target area of ​​the input image to obtain a transform coefficient. The encoding unit is further configured to encode the transform coefficient into the code stream. The encoding unit is further configured to encode position information into the code stream, wherein the position information is used to indicate the position of the target area in the input image.

[0028] In a possible implementation, the transformation unit is specifically configured to: divide the target area into a plurality of image blocks; and perform the transformation operation on the plurality of image blocks to obtain transformation coefficients.

[0029] In a possible implementation, the transform coefficients are quantized; and the quantized transform coefficients are encoded into the bitstream.

[0030] In a fourth aspect, an embodiment of the present application provides a decoding device, which includes: a decoding unit, a transformation unit and a fusion unit. The decoding unit is used to perform entropy decoding on the code stream to obtain a feature map. The decoding unit is also used to perform AI decoding on the feature map to obtain a reconstructed image. The decoding unit is also used to perform entropy decoding on the code stream to obtain a transformation coefficient. The transformation unit is used to perform an inverse transformation operation on the transformation coefficient to obtain a reconstructed pixel value of the target area. The decoding unit is also used to perform entropy decoding on the code stream to obtain position information, and the position information is used to indicate the position of the target area. The fusion unit is used to determine a fused image based on the position information, the reconstructed pixel value of the target area and the reconstructed image.

[0031] In a possible implementation, the fusion unit is specifically configured to: determine the target area in the reconstructed image according to the position information; and update the pixel value of the target area in the reconstructed image according to the reconstructed pixel value to obtain the fused image.

[0032] In a possible implementation, the decoding unit is specifically configured to: perform entropy decoding on the code stream to obtain quantized transform coefficients; and perform inverse quantization on the quantized transform coefficients to obtain the transform coefficients.

[0033] In a fifth aspect, an embodiment of the present application further provides a coding device, which includes: at least one processor, which, when the at least one processor executes program code or instructions, implements the method described in the above first aspect or any possible implementation thereof.

[0034] Optionally, the apparatus may further include at least one memory configured to store the program code or instruction.

[0035] In a sixth aspect, an embodiment of the present application further provides a decoding device, which includes: at least one processor, which, when the at least one processor executes program code or instructions, implements the method described in the above second aspect or any possible implementation thereof.

[0036] In a seventh aspect, an embodiment of the present application further provides a code stream storage method, the method comprising: obtaining and storing a code stream obtained by the method described in the first aspect or any possible implementation thereof.

[0037] In an eighth aspect, an embodiment of the present application further provides a bitstream storage device, which is used to obtain and store the bitstream obtained by the method described in the first aspect or any possible implementation thereof.

[0038] In a ninth aspect, an embodiment of the present application further provides a code stream transmission method, the method comprising: acquiring and transmitting a code stream obtained by the method described in the first aspect or any possible implementation thereof.

[0039] In a tenth aspect, an embodiment of the present application further provides a code stream transmission device, which is used to obtain and transmit the code stream obtained by the method described in the first aspect or any possible implementation thereof.

[0040] In an eleventh aspect, an embodiment of the present application further provides a computer-readable storage medium, on which is stored a code stream obtained by the method described in the first aspect or any possible implementation thereof.

[0041] In a twelfth aspect, an embodiment of the present application further provides a chip comprising: an input interface, an output interface, and at least one processor. Optionally, the chip further comprises a memory. The at least one processor is configured to execute code in the memory. When the at least one processor executes the code, the chip implements the method described in the first aspect or any possible implementation thereof.

[0042] Optionally, the chip may also be an integrated circuit.

[0043] In a thirteenth aspect, an embodiment of the present application further provides a computer-readable storage medium for storing a computer program, which includes methods for implementing the above-mentioned first aspect or any possible implementation thereof.

[0044] In a fourteenth aspect, an embodiment of the present application further provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to implement the method described in the above-mentioned first aspect or any possible implementation thereof.

[0045] The encoding and decoding device, computer storage medium, computer program product and chip provided in this embodiment are all used to execute the encoding and decoding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects of the encoding and decoding method provided above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following is a brief introduction to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0047] FIG1a is an exemplary block diagram of a decoding system provided in an embodiment of the present application;

[0048] FIG1b is an exemplary block diagram of a video decoding system provided in an embodiment of the present application;

[0049] FIG2 is an exemplary block diagram of a video encoder provided in an embodiment of the present application;

[0050] FIG3 is an exemplary block diagram of a video decoder provided in an embodiment of the present application;

[0051] FIG4 is an exemplary block diagram of a video decoding device provided in an embodiment of the present application;

[0052] FIG5 is an exemplary block diagram of a device provided in an embodiment of the present application;

[0053] FIG6 is a schematic diagram of a neural network-based image compression method provided in an embodiment of the present application;

[0054] FIG7 is a schematic diagram of an end-to-end image coding framework provided in an embodiment of the present application;

[0055] FIG8 is a schematic diagram of the structure of a neural network provided in an embodiment of the present application;

[0056] FIG9 is a schematic structural diagram of a video communication system provided in an embodiment of the present application;

[0057] FIG10 is a schematic diagram of a flow chart of an encoding method provided in an embodiment of the present application;

[0058] FIG11 is a schematic diagram of a flow chart of a decoding method provided in an embodiment of the present application;

[0059] FIG12 is a schematic structural diagram of an encoding device provided in an embodiment of the present application;

[0060] FIG13 is a schematic structural diagram of a decoding device provided in an embodiment of the present application;

[0061] FIG14 is a schematic diagram of the structure of a chip provided in an embodiment of the present application;

[0062] FIG15 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0063] FIG16 is a schematic structural diagram of another electronic device provided in an embodiment of the present application;

[0064] FIG17 is a schematic diagram of the structure of a neural network provided in an embodiment of the present application;

[0065] FIG18 is a schematic structural diagram of a machine video encoding system provided in an embodiment of the present application;

[0066] FIG19 is a schematic diagram of the structure of a code stream provided in an embodiment of the present application;

[0067] FIG20 is a schematic diagram of a layered coding method provided in an embodiment of the present application;

[0068] Figure 21 is a schematic diagram of end-to-end image encoding based on a super-prior structure provided by an embodiment of the present application. DETAILED DESCRIPTION

[0069] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the embodiments of this application.

[0070] The term "and / or" in this article is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0071] The terms "first" and "second" and so on in the description and drawings of the embodiments of this application are used to distinguish different objects, or to distinguish different processing of the same object, rather than to describe a specific order of objects.

[0072] Furthermore, the terms "including," "having," and any variations thereof, mentioned in the description of the embodiments of the present application are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not limited to the listed steps or units but may optionally include other steps or units not listed, or may optionally include other steps or units inherent to the process, method, product, or apparatus.

[0073] It should be noted that in the description of the embodiments of this application, words such as "exemplarily" or "for example" are used to indicate examples, illustrations, or explanations. Any embodiment or design described as "exemplarily" or "for example" in the embodiments of this application should not be interpreted as having priority or advantage over other embodiments or designs. Rather, the use of words such as "exemplarily" or "for example" is intended to present the relevant concepts in a concrete manner.

[0074] First, the terms involved in the embodiments of the present application are explained.

[0075] The Joint Photographic Experts Group (JPEG) artificial intelligence (AI) is a learning-based image coding standard that provides a single-stream, compact compressed domain representation, significantly improving compression efficiency over commonly used image coding standards while maintaining comparable subjective quality. JPEG AI is widely used in various fields. For example, JPEG AI can be applied to cloud storage, visual surveillance, autonomous vehicles and devices, image acquisition, storage, and management, real-time monitoring of visual data, and media distribution.

[0076] Convolutional Neural Network (CNN): A neural network that includes convolutional layers. This type of neural network may also include activation layers (such as ReLU and PReLU), pooling layers, batch normalization layers (BN layers), and fully connected layers. Typical convolutional neural networks include LeNet, AlexNet, VGGNet, and ResNet. A basic CNN consists of a backbone network and a head network; a more complex CNN consists of a backbone, neck, and head network.

[0077] Feature map: The three-dimensional data output by the convolutional layer, activation layer, pooling layer, batch normalization layer, etc. in a convolutional neural network. The three dimensions are called width, height, and channel respectively.

[0078] Backbone network: The first part of a convolutional neural network, responsible for extracting feature maps at multiple scales from the input image. It typically consists of convolutional layers, pooling layers, activation layers, and no fully connected layers. Typically, backbone layers closer to the input image output feature maps with higher resolution (width and height) but fewer channels. Typical backbone networks include VGG-16, ResNet-50, and ResNeXt-101.

[0079] Head network: The last part of the convolutional neural network, whose function is to process the feature map to obtain the prediction results of the neural network output. Common head networks include fully connected layers, softmax modules, etc.

[0080] Neck network: The middle part of the convolutional neural network, which is responsible for further integrating and processing the feature maps generated by the backbone to obtain new feature maps. Common networks include the Feature Pyramid Network (FPN) in Faster RCNN.

[0081] Bottleneck structure: A multi-layer network structure in which the input data of the network first passes through one or more neural network layers to obtain intermediate data, and the intermediate data then passes through one or more neural network layers to obtain output data, where the amount of intermediate data (i.e., the product of width, height and number of channels) is lower than the amount of input data and output data.

[0082] Data encoding and decoding includes two parts: data encoding and data decoding. Data encoding is performed on the source side (or commonly referred to as the encoder side), and generally includes processing (e.g., compressing) the original data to reduce the amount of data required to represent the original data (thereby more efficiently storing and / or transmitting). Data decoding is performed on the destination side (or commonly referred to as the decoder side), and generally includes inverse processing relative to the encoder side to reconstruct the original data. The "encoding and decoding" of the data involved in the embodiments of the present application should be understood as the "encoding" or "decoding" of the data. The encoding part and the decoding part are also collectively referred to as encoding and decoding (encoding and decoding, CODEC).

[0083] In the case of lossless data encoding, the original data can be reconstructed, that is, the reconstructed original data has the same quality as the original data (assuming there is no transmission loss or other data loss during storage or transmission). In the case of lossy data encoding, further compression is performed through quantization, etc. to reduce the amount of data required to represent the original data, but the decoder side cannot fully reconstruct the original data, that is, the quality of the reconstructed original data is lower or worse than the quality of the original data.

[0084] The embodiments of the present application can be applied to video data and other data with compression / decompression requirements. The following uses the encoding of video data (referred to as video encoding) as an example to illustrate the embodiments of the present application. Other types of data (such as image data, audio data, integer data, and other data with compression / decompression requirements) can refer to the following description, and the embodiments of the present application will not be repeated here. It should be noted that, compared to video encoding, the encoding process of data such as audio data and integer data does not require data to be divided into blocks, but the data can be directly encoded.

[0085] Video coding generally refers to processing a sequence of images to form a video or video sequence. In the field of video coding, the terms "picture", "frame" or "image" can be used as synonyms.

[0086] Several video coding standards fall under the category of "lossy hybrid video codecs" (i.e., combining spatial and temporal prediction in the pixel domain with 2D transform coding in the transform domain for applying quantization). Each image in a video sequence is typically divided into a set of non-overlapping blocks, which are typically coded at the block level. In other words, the encoder typically processes, i.e., encodes, the video at the block (video block) level, for example, by generating a prediction block through spatial (intra-frame) and temporal (inter-frame) prediction; subtracting the prediction block from the current block (currently processed / to-be-processed block) to obtain a residual block; transforming and quantizing the residual block in the transform domain to reduce the amount of data to be transmitted (compressed), while the decoder applies the inverse of the encoder's processing to the coded or compressed block to reconstruct the current block for representation. Furthermore, the encoder needs to repeat the decoder's processing steps so that the encoder and decoder generate the same predictions (e.g., intra-frame predictions and inter-frame predictions) and / or reconstructed pixels for processing, i.e., encoding, the subsequent block.

[0087] In the following embodiment of the decoding system 10 , the encoder 20 and the decoder 30 are described with reference to FIG. 1 a to FIG. 3 .

[0088] FIG1a is an exemplary block diagram of a decoding system 10 provided in an embodiment of the present application, such as a video decoding system 10 (or simply, decoding system 10) that can utilize the techniques of the embodiments of the present application. The video encoder 20 (or simply, encoder 20) and video decoder 30 (or simply, decoder 30) in the video decoding system 10 represent devices that can be used to perform various techniques according to the various examples described in the embodiments of the present application.

[0089] As shown in FIG. 1 a , a decoding system 10 includes a source device 12 for providing encoded image data 21 such as an encoded image to a destination device 14 for decoding the encoded image data 21 .

[0090] The source device 12 includes an encoder 20 , and optionally, may include an image source 16 , a preprocessor (or preprocessing unit) 18 such as an image preprocessor, and a communication interface (or communication unit) 22 .

[0091] The image source 16 may include or may be any type of image capture device for capturing real-world images, etc., and / or any type of image generation device, such as a computer graphics processor for generating computer-animated images, or any type of device for acquiring and / or providing real-world images, computer-generated images (e.g., screen content, virtual reality (VR) images, and / or any combination thereof (e.g., augmented reality (AR) images). The image source may be any type of memory or storage that stores any of the above images.

[0092] In order to distinguish the processing performed by the pre-processor (or pre-processing unit) 18 , the image (or image data) 17 may also be referred to as a raw image (or raw image data) 17 .

[0093] The preprocessor 18 is configured to receive raw image data 17 and preprocess the raw image data 17 to obtain a preprocessed image (or preprocessed image data) 19. For example, the preprocessing performed by the preprocessor 18 may include cropping, color format conversion (e.g., from RGB to YCbCr), color grading, or denoising. It will be appreciated that the preprocessor 18 may be an optional component.

[0094] The video encoder (or encoder) 20 is used to receive the pre-processed image data 19 and provide encoded image data 21 (which will be further described below with reference to FIG. 2 and the like).

[0095] The communication interface 22 in the source device 12 can be used to receive the encoded image data 21 and send the encoded image data 21 (or any other processed version) to another device such as the destination device 14 or any other device through the communication channel 13 for storage or direct reconstruction.

[0096] The destination device 14 includes a decoder 30 and, in addition or alternatively, may include a communication interface (or communication unit) 28 , a post-processor (or post-processing unit) 32 , and a display device 34 .

[0097] The communication interface 28 in the destination device 14 is used to receive the encoded image data 21 (or any other processed version) directly from the source device 12 or from any other source device such as a storage device, for example, the storage device is a encoded image data storage device, and provide the encoded image data 21 to the decoder 30.

[0098] The communication interface 22 and the communication interface 28 can be used to send or receive encoded image data (or encoded data) 21 through a direct communication link between the source device 12 and the destination device 14, such as a direct wired or wireless connection, or through any type of network, such as a wired network, a wireless network or any combination thereof, any type of private network and public network or any combination thereof.

[0099] For example, the communication interface 22 may be used to encapsulate the encoded image data 21 into a suitable format such as a message, and / or process the encoded image data using any type of transmission coding or processing for transmission over a communication link or network.

[0100] The communication interface 28 corresponds to the communication interface 22 , and can be used, for example, to receive transmission data and process the transmission data using any type of corresponding transmission decoding or processing and / or decapsulation to obtain the encoded image data 21 .

[0101] Both the communication interface 22 and the communication interface 28 can be configured as a unidirectional communication interface as indicated by the arrow pointing from the source device 12 to the corresponding communication channel 13 of the destination device 14 in Figure 1a, or a bidirectional communication interface, and can be used to send and receive messages, etc. to establish a connection, confirm and exchange any other information related to the communication link and / or data transmission such as encoded image data transmission, etc.

[0102] The video decoder (or decoder) 30 is used to receive the encoded image data 21 and provide decoded image data (or decoded image data) 31 (which will be further described below with reference to FIG. 3 and the like).

[0103] The post-processor 32 is configured to post-process the decoded image data 31 (also referred to as reconstructed image data) such as the decoded image to obtain post-processed image data 33 such as the post-processed image. The post-processing performed by the post-processing unit 32 may include, for example, color format conversion (e.g., from YCbCr to RGB), color grading, cropping, or resampling, or any other processing for generating the decoded image data 31 for display on a display device 34 or the like.

[0104] The display device 34 is configured to receive the post-processed image data 33 and display the image to a user or viewer. The display device 34 may be or include any type of display for displaying the reconstructed image, such as an integrated or external display screen or monitor. For example, the display screen may include a liquid crystal display (LCD), an organic light emitting diode (OLED) display, a plasma display, a projector, a micro-LED display, a liquid crystal on silicon (LCoS) display, a digital light processor (DLP), or any other type of display screen.

[0105] The decoding system 10 also includes a training engine 25, which is used to train the encoder 20 (especially the entropy encoding unit 270 in the encoder 20) or the decoder 30 (especially the entropy decoding unit 304 in the decoder 30) to perform entropy encoding on the image block to be encoded based on the estimated probability distribution. For a detailed description of the training engine 25, please refer to the following method test example.

[0106] Although FIG1a shows source device 12 and destination device 14 as separate devices, device embodiments may also include both source device 12 and destination device 14 or the functions of both source device 12 and destination device 14, that is, both source device 12 or the corresponding functions and destination device 14 or the corresponding functions. In these embodiments, source device 12 or the corresponding functions and destination device 14 or the corresponding functions may be implemented using the same hardware and / or software or through separate hardware and / or software or any combination thereof.

[0107] According to the description, the existence and (accurate) division of different units or functions in the source device 12 and / or the destination device 14 shown in FIG. 1 a may vary depending on actual devices and applications, which is obvious to those skilled in the art.

[0108] Please refer to Figure 1b, which is an exemplary block diagram of a video decoding system 40 provided in an embodiment of the present application. The encoder 20 (e.g., video encoder 20) or the decoder 30 (e.g., video decoder 30), or both, can be implemented by processing circuitry in the video decoding system 40 shown in Figure 1b, such as one or more microprocessors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), discrete logic, hardware, video encoding-specific processors, or any combination thereof. Please refer to Figures 2 and 3, Figure 2 is an exemplary block diagram of a video encoder provided in an embodiment of the present application, and Figure 3 is an exemplary block diagram of a video decoder provided in an embodiment of the present application. The encoder 20 can be implemented by processing circuitry 46 to include the various modules discussed with reference to the encoder 20 in Figure 2 and / or any other encoder systems or subsystems described herein. The decoder 30 can be implemented by processing circuitry 46 to include the various modules discussed with reference to the decoder 30 in Figure 3 and / or any other decoder systems or subsystems described herein. The processing circuitry 46 can be used to perform the various operations discussed below. As shown in FIG4 , if part of the technology is implemented in software, the device can store the software instructions in a suitable non-transitory computer-readable storage medium and use one or more processors to execute the instructions in hardware, thereby performing the technology of the embodiment of the present application. One of the video encoder 20 and the video decoder 30 can be integrated into a single device as part of a combined codec (encoder / decoder, CODEC), as shown in FIG1 b.

[0109] The source device 12 and the destination device 14 may include any of a variety of devices, including any type of handheld or fixed device, such as a notebook computer or laptop, a mobile phone, a smart phone, a tablet or a tablet computer, a camera, a desktop computer, a set-top box, a television, a display device, a digital media player, a video game console, a video streaming device (e.g., a content service server or a content distribution server), a broadcast receiving device, a broadcast transmitting device, and a monitoring device, etc., and may not use or use any type of operating system. The source device 12 and the destination device 14 may also be devices in a cloud computing scenario, such as a virtual machine in a cloud computing scenario. In some cases, the source device 12 and the destination device 14 may be equipped with components for wireless communication. Therefore, the source device 12 and the destination device 14 may be wireless communication devices.

[0110] The source device 12 and the destination device 14 may be installed with virtual scene applications (APPs) such as virtual reality (VR), augmented reality (AR), or mixed reality (MR), and may run the VR, AR, or MR applications based on user operations (e.g., click, touch, slide, shake, voice control, etc.). The source device 12 and the destination device 14 may capture images / videos of any objects in the environment through cameras and / or sensors, and then display virtual objects on a display device based on the captured images / videos. The virtual objects may be virtual objects in the VR, AR, or MR scenes (i.e., objects in the virtual environment).

[0111] It should be noted that in the embodiment of the present application, the virtual scene application in the source device 12 and the destination device 14 can be an application built into the source device 12 and the destination device 14 themselves, or it can be an application provided by a third-party service provider and installed by the user. There is no specific limitation on this.

[0112] In addition, the source device 12 and the destination device 14 may be installed with a real-time video transmission application, such as a live broadcast application. The source device 12 and the destination device 14 may capture images / videos through cameras and then display the captured images / videos on a display device.

[0113] In some cases, the video decoding system 10 shown in FIG1a is merely exemplary, and the techniques provided in embodiments of the present application may be applicable to video encoding settings (e.g., video encoding or video decoding) that do not necessarily include any data communication between an encoding device and a decoding device. In other examples, data is retrieved from a local memory, sent over a network, and so on. A video encoding device may encode data and store the data in a memory, and / or a video decoding device may retrieve data from a memory and decode the data. In some examples, encoding and decoding are performed by devices that do not communicate with each other but simply encode data to a memory and / or retrieve and decode data from a memory.

[0114] Please refer to Figure 1b, which is an exemplary block diagram of a video decoding system 40 provided in an embodiment of the present application. As shown in Figure 1b, the video decoding system 40 may include an imaging device 41, a video encoder 20, a video decoder 30 (and / or a video encoder / decoder implemented by a processing circuit 46), an antenna 42, one or more processors 43, one or more memory storage devices 44 and / or a display device 45.

[0115] 1b, imaging device 41, antenna 42, processing circuit 46, video encoder 20, video decoder 30, processor 43, memory 44, and / or display device 45 are capable of communicating with one another. In different embodiments, video decoding system 40 may include only video encoder 20 or only video decoder 30.

[0116] In some instances, antenna 42 can be used to transmit or receive an encoded bitstream of video data. Additionally, in some instances, display device 45 can be used to present the video data. Processing circuitry 46 can include application-specific integrated circuit (ASIC) logic, a graphics processor, a general-purpose processor, and the like. Video decoding system 40 can also include an optional processor 43, which can similarly include application-specific integrated circuit (ASIC) logic, a graphics processor, a general-purpose processor, and the like. Furthermore, memory storage 44 can be any type of memory, such as volatile memory (e.g., static random access memory (SRAM), dynamic random access memory (DRAM), etc.) or non-volatile memory (e.g., flash memory, etc.). In a non-limiting example, memory storage 44 can be implemented as cache memory. In other instances, processing circuitry 46 can include memory (e.g., cache memory, etc.) for implementing an image buffer, etc.

[0117] In some examples, video encoder 20 implemented by logic circuitry may include an image buffer (e.g., implemented by processing circuitry 46 or memory storage 44) and a graphics processing unit (e.g., implemented by processing circuitry 46). The graphics processing unit may be communicatively coupled to the image buffer. The graphics processing unit may include video encoder 20 implemented by processing circuitry 46 to implement the various modules discussed with reference to FIG. 2 and / or any other encoder systems or subsystems described herein. Logic circuitry may be used to perform the various operations discussed herein.

[0118] In some examples, the video decoder 30 may be implemented by processing circuitry 46 in a similar manner to implement the various modules discussed with reference to the video decoder 30 of FIG. 3 and / or any other decoder systems or subsystems described herein. In some examples, the logic circuit implementation of the video decoder 30 may include an image buffer (implemented by processing circuitry 46 or memory storage 44) and a graphics processing unit (e.g., implemented by processing circuitry 46). The graphics processing unit may be communicatively coupled to the image buffer. The graphics processing unit may include the video decoder 30 implemented by processing circuitry 46 to implement the various modules discussed with reference to FIG. 3 and / or any other decoder systems or subsystems described herein.

[0119] In some examples, antenna 42 may be used to receive an encoded bitstream of video data. As discussed, the encoded bitstream may include data related to the encoded video frames, indicators, index values, mode selection data, etc., as discussed herein, such as data related to encoding partitions (e.g., transform coefficients or quantized transform coefficients, optional indicators (as discussed), and / or data defining encoding partitions). Video decoding system 40 may also include video decoder 30 coupled to antenna 42 and configured to decode the encoded bitstream. Display device 45 is configured to present the video frames.

[0120] It should be understood that for the examples described herein with reference to video encoder 20, video decoder 30 can be configured to perform the reverse process. With respect to signaling syntax elements, video decoder 30 can be configured to receive and parse such syntax elements and decode the associated video data accordingly. In some examples, video encoder 20 can entropy encode the syntax elements into an encoded video bitstream. In such examples, video decoder 30 can parse such syntax elements and decode the associated video data accordingly.

[0121] For ease of description, the embodiments of the present application are described with reference to the universal video coding (VVC) reference software or the high-efficiency video coding (HEVC) developed by the joint collaboration team on video coding (JCT-VC) of the ITU-T video coding experts group (VCEG) and the ISO / IEC motion picture experts group (MPEG). Those skilled in the art will understand that the embodiments of the present application are not limited to HEVC or VVC.

[0122] Encoders and encoding methods

[0123] As shown in FIG2 , the video encoder 20 includes an input terminal (or input interface) 201, a residual calculation unit 204, a transform processing unit 206, a quantization unit 208, an inverse quantization unit 210, an inverse transform processing unit 212, a reconstruction unit 214, a loop filter 220, a decoded picture buffer (DPB) 230, a mode selection unit 260, an entropy coding unit 270, and an output terminal (or output interface) 272. The mode selection unit 260 may include an inter-frame prediction unit 244, an intra-frame prediction unit 254, and a segmentation unit 262. The inter-frame prediction unit 244 may include a motion estimation unit and a motion compensation unit (not shown). The video encoder 20 shown in FIG2 may also be referred to as a hybrid video encoder or a video encoder based on a hybrid video codec.

[0124] Images and image segmentation (images and blocks)

[0125] Encoder 20 is operable to receive, via input 201 or the like, an image (or image data) 17, for example, an image from a sequence of images forming a video or video sequence. The received image or image data may also be a pre-processed image (or pre-processed image data) 19. For simplicity, the following description uses image 17. Image 17 may also be referred to as a current image or image to be encoded (particularly when distinguishing the current image from other images in video encoding, such as previously encoded and / or decoded images in the same video sequence, i.e., a video sequence that also includes the current image).

[0126] A (digital) image is, or can be considered to be, a two-dimensional array or matrix of pixels with intensity values. The pixels in the array are also referred to as pixels (or pels, short for picture elements). The number of pixels in the array or image in the horizontal and vertical directions (or axes) determines the image size and / or resolution. To represent color, three color components are typically used, meaning that an image can be represented as or include three pixel arrays. In the RBG format or color space, an image includes corresponding arrays of red, green, and blue pixels. However, in video coding, each pixel is typically represented in a luma / chroma format or color space, such as YCbCr, which includes a luma component indicated by Y (sometimes also indicated by L) and two chroma components, indicated by Cb and Cr. The luma component Y represents the brightness or grayscale level intensity (for example, in grayscale images, both are the same), while the two chroma components (abbreviated as chroma) Cb and Cr represent the chroma or color information components. Accordingly, an image in YCbCr format includes a luma pixel array of luma pixel values ​​(Y) and two chroma pixel arrays of chroma values ​​(Cb and Cr). An image in RGB format can be converted or transformed into YCbCr format, and vice versa, a process also known as color conversion or transformation. If the image is black and white, the image may include only a luma pixel array. Accordingly, the image may be, for example, a luma pixel array in monochrome format or a luma pixel array and two corresponding chroma pixel arrays in 4:2:0, 4:2:2, and 4:4:4 color formats.

[0127] In one embodiment, an embodiment of the video encoder 20 may include an image segmentation unit (not shown in FIG. 2 ) for segmenting the image 17 into a plurality of (typically non-overlapping) image blocks 203. These blocks may also be referred to as root blocks, macroblocks (H.264 / AVC) or coding tree blocks (CTBs), or coding tree units (CTUs) in the H.265 / HEVC and VVC standards. The segmentation unit may be used to use the same block size for all images in a video sequence and a corresponding grid of defined block sizes, or to vary the block size between images or subsets or groups of images, and to segment each image into corresponding blocks.

[0128] In other embodiments, the video encoder may be configured to directly receive a block 203 of the image 17, for example, one, several or all blocks constituting the image 17. The image block 203 may also be referred to as a current image block or an image block to be encoded.

[0129] Like image 17, image block 203 is also or can be considered to be a two-dimensional array or matrix of pixels having intensity values ​​(pixel values), but image block 203 is smaller than image 17. In other words, block 203 may include one pixel array (e.g., a luminance array in the case of monochrome image 17, or a luminance array or chrominance array in the case of a color image), or three pixel arrays (e.g., one luminance array and two chrominance arrays in the case of a color image 17), or any other number and / or type of arrays depending on the color format used. The number of pixels in the horizontal and vertical directions (or axes) of block 203 defines the size of block 203. Accordingly, a block may be an M×N (M columns×N rows) pixel array, or an M×N transform coefficient array, etc.

[0130] In one embodiment, the video encoder 20 shown in FIG. 2 is configured to encode the image 17 block by block, for example, performing encoding and prediction on each block 203 .

[0131] In one embodiment, the video encoder 20 shown in FIG2 may also be configured to partition and / or encode an image using slices (also referred to as video slices), where an image may be partitioned or encoded using one or more slices (typically non-overlapping). Each slice may include one or more blocks (e.g., coding tree units (CTUs)) or one or more groups of blocks (e.g., tiles in the H.265 / HEVC / VVC standard and bricks in the VVC standard).

[0132] In one embodiment, the video encoder 20 shown in Figure 2 can also be used to segment and / or encode an image using slices / coding block groups (also called video coding block groups) and / or coding blocks (also called video coding blocks), where the image can be segmented or encoded using one or more slices / coding block groups (usually non-overlapping), each slice / coding block group may include one or more blocks (e.g., CTUs) or one or more coding blocks, etc., where each coding block can be in a shape such as a rectangle and may include one or more complete or partial blocks (e.g., CTUs).

[0133] Residual calculation

[0134] The residual calculation unit 204 is used to calculate the residual block 205 (the prediction block 265 is described in detail later) based on the image block (or original block) 203 and the prediction block 265 in the following manner: for example, the pixel value of the prediction block 265 is subtracted from the pixel value of the image block 203 pixel by pixel (pixel by pixel) to obtain the residual block 205 in the pixel domain.

[0135] Quantification

[0136] The quantization unit 208 is configured to quantize the transform coefficients 207 by, for example, scalar quantization or vector quantization to obtain quantized transform coefficients 209 . The quantized transform coefficients 209 may also be referred to as quantized residual coefficients 209 .

[0137] The quantization process may reduce the bit depth associated with some or all of the transform coefficients 207. For example, during quantization, an n-bit transform coefficient may be rounded down to an m-bit transform coefficient, where n is greater than m. The degree of quantization may be modified by adjusting a quantization parameter (QP). For example, for scalar quantization, varying degrees of scaling may be applied to achieve finer or coarser quantization. A smaller quantization step size corresponds to finer quantization, while a larger quantization step size corresponds to coarser quantization. The appropriate quantization step size may be indicated by a quantization parameter (QP). For example, the quantization parameter may be an index into a predefined set of appropriate quantization step sizes. For example, a smaller quantization parameter may correspond to fine quantization (a smaller quantization step size), while a larger quantization parameter may correspond to coarse quantization (a larger quantization step size), or vice versa. Quantization may include dividing by the quantization step size, while the corresponding or inverse dequantization performed by the inverse quantization unit 210, etc., may include multiplying by the quantization step size. Embodiments according to some standards, such as HEVC, may be used to determine the quantization step size using the quantization parameter. Generally, the quantization step size may be calculated based on the quantization parameter using a fixed-point approximation of an equation involving division. Additional scaling factors can be introduced for quantization and dequantization to restore the norm of the residual block that may have been modified by the scaling used in the fixed-point approximation of the equations for the quantization step size and quantization parameter. In one exemplary implementation, the scaling of the inverse transform and dequantization can be combined. Alternatively, a custom quantization table can be used and indicated from the encoder to the decoder in the bitstream, etc. Quantization is a lossy operation, where larger quantization step sizes result in greater losses.

[0138] In one embodiment, the video encoder 20 (correspondingly, the quantization unit 208) may be configured to output a quantization parameter (QP), for example, directly or after being encoded or compressed by the entropy coding unit 270, such that the video decoder 30 may receive and use the quantization parameter for decoding.

[0139] Dequantization

[0140] The inverse quantization unit 210 is configured to perform inverse quantization performed by the quantization unit 208 on the quantized coefficients to obtain dequantized coefficients 211. For example, the inverse quantization scheme performed by the quantization unit 208 may be performed according to or using the same quantization step size as the quantization unit 208. The dequantized coefficients 211 may also be referred to as dequantized residual coefficients 211, and correspond to the transform coefficients 207. However, due to the loss caused by quantization, the dequantized coefficients 211 are generally not identical to the transform coefficients.

[0141] reconstruction

[0142] The reconstruction unit 214 (e.g., the summer 214) is used to add the transform block 213 (i.e., the reconstructed residual block 213) to the prediction block 265 to obtain the reconstructed block 215 in the pixel domain, for example, by adding the pixel point values ​​of the reconstructed residual block 213 and the pixel point values ​​of the prediction block 265.

[0143] segmentation

[0144] The partitioning unit 262 can partition (or divide) an image block (or CTU) 203 into smaller parts, such as square or rectangular blocks. For an image with three pixel arrays, a CTU consists of N×N luminance pixel blocks and two corresponding chrominance pixel blocks. The maximum allowed size of a luminance block in a CTU is specified as 128×128 in the developing Universal Video Coding (VVC) standard, but may be specified to a value other than 128×128, such as 256×256, in the future. The CTUs of an image can be grouped / collected into slices / coding block groups, coding blocks, or bricks. A coding block covers a rectangular area of ​​an image and can be divided into one or more bricks. A brick consists of multiple CTU rows within a coding block. A coding block that is not partitioned into multiple bricks can be called a brick. However, a brick is a true subset of a coding block and is therefore not called a coding block. VVC supports two coding block group modes: raster scan slice / coding block group mode and rectangular slice mode. In raster scan CBG mode, a slice / CBG contains a sequence of CBs from a raster scan of the CBs of an image. In rectangular slice mode, a slice contains multiple bricks of an image that together form a rectangular region of the image. The bricks within a rectangular slice are arranged in the slice's brick raster scan order. These smaller blocks (also called sub-blocks) can be further split into smaller parts. This is also known as tree partitioning or hierarchical tree partitioning, where a root block at, for example, root tree level 0 (hierarchy level 0, depth 0) can be recursively split into two or more blocks at the next lower tree level, such as nodes at tree level 1 (hierarchy level 1, depth 1). These blocks can be further split into two or more blocks at the next lower level, such as nodes at tree level 2 (hierarchy level 2, depth 2), and so on, until the partitioning is completed (because the end criteria are met, such as reaching the maximum tree depth or minimum block size). Blocks that are not further split are also called leaf blocks or leaf nodes of the tree. A tree divided into two parts is called a binary tree (BT), a tree divided into three parts is called a ternary tree (TT), and a tree divided into four parts is called a quadtree (QT).

[0145] Entropy Coding

[0146] The entropy coding unit 270 is configured to apply an entropy coding algorithm or scheme (e.g., a variable length coding (VLC) scheme, a context adaptive VLC (CALVC) scheme, an arithmetic coding scheme, a binarization algorithm, context adaptive binary arithmetic coding (CABAC), syntax-based context-adaptive binary arithmetic coding (SBAC), probability interval partitioning entropy (PIPE) coding, or other entropy coding methods or techniques) to the quantized residual coefficients 209, inter-frame prediction parameters, intra-frame prediction parameters, loop filter parameters, and / or other syntax elements, resulting in coded image data 21 that can be output via an output terminal 272 in the form of a coded bitstream 21, etc., so that the video decoder 30, etc. can receive and use the parameters for decoding. The coded bitstream 21 can be transmitted to the video decoder 30 or stored in a memory for later transmission or retrieval by the video decoder 30.

[0147] Other structural variations of the video encoder 20 may be used to encode the video stream. For example, a non-transform-based encoder 20 may directly quantize the residual signal without a transform processing unit 206 for certain blocks or frames. In another implementation, the encoder 20 may have the quantization unit 208 and the inverse quantization unit 210 combined into a single unit.

[0148] Decoder and decoding method

[0149] As shown in FIG3 , a video decoder 30 is configured to receive coded image data 21 (e.g., a coded bitstream 21) encoded by, for example, an encoder 20, and obtain a decoded image 331. The coded image data or bitstream includes information for decoding the coded image data, such as data representing image blocks of a coded video slice (and / or coding block group or coding block) and related syntax elements.

[0150] 3 , decoder 30 includes an entropy decoding unit 304, an inverse quantization unit 310, an inverse transform processing unit 312, a reconstruction unit 314 (e.g., summer 314), a loop filter 320, a decoded picture buffer (DBP) 330, a mode application unit 360, an inter-prediction unit 344, and an intra-prediction unit 354. Inter-prediction unit 344 may be or include a motion compensation unit. In some examples, video decoder 30 may perform a decoding process that is generally the reverse of the encoding process described with reference to video encoder 100 of FIG. 2 .

[0151] As described with respect to encoder 20, inverse quantization unit 210, inverse transform processing unit 212, reconstruction unit 214, loop filter 220, decoded picture buffer DPB 230, inter-prediction unit 344, and intra-prediction unit 354 also constitute the "built-in decoder" of video encoder 20. Accordingly, inverse quantization unit 310 may be functionally identical to inverse quantization unit 110, inverse transform processing unit 312 may be functionally identical to inverse transform processing unit 122, reconstruction unit 314 may be functionally identical to reconstruction unit 214, loop filter 320 may be functionally identical to loop filter 220, and decoded picture buffer 330 may be functionally identical to decoded picture buffer 230. Therefore, the explanations of the corresponding units and functions of video encoder 20 apply accordingly to the corresponding units and functions of video decoder 30.

[0152] Entropy decoding

[0153] The entropy decoding unit 304 is configured to parse the bitstream 21 (or generally, the encoded image data 21) and perform entropy decoding on the encoded image data 21 to obtain quantization coefficients 309 and / or decoded coding parameters (not shown in FIG. 3 ), such as any or all of inter-frame prediction parameters (e.g., reference image indices and motion vectors), intra-frame prediction parameters (e.g., intra-frame prediction modes or indices), transform parameters, quantization parameters, loop filter parameters, and / or other syntax elements. The entropy decoding unit 304 may be configured to apply a decoding algorithm or scheme corresponding to the coding scheme of the entropy coding unit 270 of the encoder 20. The entropy decoding unit 304 may also be configured to provide inter-frame prediction parameters, intra-frame prediction parameters, and / or other syntax elements to the mode application unit 360, as well as to provide other parameters to other units of the decoder 30. The video decoder 30 may receive syntax elements at the video slice and / or video block level. In addition to, or in lieu of, slices and corresponding syntax elements, coding block groups and / or coding blocks and corresponding syntax elements may also be received or used.

[0154] Dequantization

[0155] The inverse quantization unit 310 may be configured to receive a quantization parameter (QP) (or generally information related to inverse quantization) and quantization coefficients from the encoded image data 21 (e.g., parsed and / or decoded by the entropy decoding unit 304), and inverse quantize the decoded quantization coefficients 309 based on the quantization parameter to obtain inverse quantization coefficients 311, which may also be referred to as transform coefficients 311. The inverse quantization process may include using the quantization parameter calculated by the video encoder 20 for each video block in the video slice to determine a degree of quantization, and thus a degree of inverse quantization to be performed.

[0156] reconstruction

[0157] The reconstruction unit 314 (eg, summer 314 ) is configured to add the reconstructed residual block 313 to the prediction block 365 to obtain the reconstructed block 315 in the pixel domain, eg, by adding the pixel values ​​of the reconstructed residual block 313 and the pixel values ​​of the prediction block 365 .

[0158] Other variations of the video decoder 30 may be used to decode the encoded image data 21. For example, the decoder 30 may generate an output video stream without the loop filter unit 320. For example, a non-transform-based decoder 30 may directly inverse quantize the residual signal without the inverse transform processing unit 312 for certain blocks or frames. In another implementation, the video decoder 30 may have the inverse quantization unit 310 and the inverse transform processing unit 312 combined into a single unit.

[0159] It should be understood that the processing result of the current step can be further processed in the encoder 20 and the decoder 30 and then output to the next step. For example, after interpolation filtering, motion vector derivation, or loop filtering, the processing result of interpolation filtering, motion vector derivation, or loop filtering can be further operated on, such as clipping or shifting operations.

[0160] It should be noted that further operations can be performed on the derived motion vector of the current block (including but not limited to the control point motion vector of the affine mode, the sub-block motion vector of the affine, planar, ATMVP mode, the temporal motion vector, etc.). For example, the value of the motion vector is limited to a predefined range based on the representation bit of the motion vector. If the representation bit of the motion vector is bitDepth, the range is -2^(bitDepth-1) to 2^(bitDepth-1)-1, where "^" represents a power. For example, if bitDepth is set to 16, the range is -32768 to 32767; if bitDepth is set to 18, the range is -131072 to 131071. For example, the value of the derived motion vector (e.g., the MV of four 4×4 sub-blocks in an 8×8 block) is limited so that the maximum difference between the integer parts of the four 4×4 sub-block MVs does not exceed N pixels, for example, not more than 1 pixel. Two methods of limiting the motion vector based on bitDepth are provided here.

[0161] Although the above embodiments primarily describe video coding, it should be noted that embodiments of the decoding system 10, encoder 20, and decoder 30, as well as other embodiments described herein, may also be used for still image processing or coding, i.e., processing or coding a single image in a video codec that is independent of any previous or subsequent images. In general, if image processing is limited to a single image 17, the inter-frame prediction unit 244 (encoder) and the inter-frame prediction unit 344 (decoder) may not be available. All other functionalities (also referred to as tools or techniques) of the video encoder 20 and video decoder 30, such as residual calculation 204 / 304, transform 206, quantization 208, inverse quantization 210 / 310, (inverse) transform 212 / 312, segmentation 262 / 362, intra-frame prediction 254 / 354, and / or loop filtering 220 / 320, entropy coding 270, and entropy decoding 304, may also be used for still image processing.

[0162] Please refer to Figure 4, which is an exemplary block diagram of a video decoding device 400 provided in an embodiment of the present application. Video decoding device 400 is suitable for implementing the disclosed embodiments described herein. In one embodiment, video decoding device 400 can be a decoder, such as the video decoder 30 in Figure 1a, or an encoder, such as the video encoder 20 in Figure 1a.

[0163] Video decoding device 400 includes: an input port 410 (or input port 410) and a receiver unit (Rx) 420 for receiving data; a processor, logic unit, or central processing unit (CPU) 430 for processing data; for example, processor 430 may be a neural network processor 430; a transmitter unit (Tx) 440 and an output port 450 (or output port 550) for transmitting data; and a memory 460 for storing data. Video decoding device 400 may also include optical-to-electrical (OE) components and electrical-to-optical (EO) components coupled to input port 410, receiver unit 420, transmitter unit 440, and output port 450 for outputting or receiving optical or electrical signals.

[0164] The processor 430 is implemented in hardware and software. The processor 430 can be implemented as one or more processor chips, cores (e.g., multi-core processors), FPGAs, ASICs, and DSPs. The processor 430 communicates with the input port 410, the receiving unit 420, the transmitting unit 440, the output port 450, and the memory 460. The processor 430 includes a neural network-based codec 470. The neural network-based codec 470 implements the embodiments disclosed above. For example, the neural network-based codec 470 performs, processes, prepares, or provides various encoding operations. Therefore, the neural network-based codec 470 provides substantial improvements to the functionality of the video decoding device 400 and affects the switching of the video decoding device 400 to different states. Alternatively, the neural network-based codec 470 is implemented by instructions stored in the memory 460 and executed by the processor 430.

[0165] Memory 460 includes one or more disks, tape drives, and solid-state drives and can be used as overflow data storage for storing programs when such programs are selected for execution, and for storing instructions and data read during program execution. Memory 460 can be volatile and / or non-volatile and can be read-only memory (ROM), random access memory (RAM), ternary content-addressable memory (TCAM), and / or static random-access memory (SRAM).

[0166] Please refer to FIG. 5 , which is an exemplary block diagram of an apparatus 500 provided in an embodiment of the present application. The apparatus 500 may be used as either or both of the source device 12 and the destination device 14 in FIG. 1 a .

[0167] The processor 502 in the apparatus 500 may be a central processing unit (CPU). Alternatively, the processor 502 may be any other type of device or devices, now available or developed in the future, capable of manipulating or processing information. While the disclosed implementations may be implemented using a single processor, such as the processor 502 shown, using more than one processor may provide greater speed and efficiency.

[0168] In one implementation, the memory 504 in the apparatus 500 may be a read-only memory (ROM) device or a random access memory (RAM) device. Any other suitable type of storage device may be used as the memory 504. The memory 504 may include code and data 506 that are accessed by the processor 502 via a bus 512. The memory 504 may also include an operating system 508 and application programs 510, which include at least one program that allows the processor 502 to perform the methods described herein. For example, the application programs 510 may include applications 1 through N, as well as a video decoding application that performs the methods described herein.

[0169] The apparatus 500 may also include one or more output devices, such as a display 518. In one example, the display 518 may be a touch-sensitive display that combines a display with touch-sensitive elements that can be used to sense touch input. The display 518 may be coupled to the processor 502 via the bus 512.

[0170] Although bus 512 in device 500 is described herein as a single bus, bus 512 may include multiple buses. Furthermore, secondary storage may be directly coupled to other components of device 500 or accessed via a network, and may include a single integrated unit such as a memory card or multiple units such as multiple memory cards. Thus, device 500 may have a variety of configurations.

[0171] Image encoding:

[0172] Today, multimedia data accounts for the majority of internet traffic. Image data compression plays a vital role in the storage and efficient transmission of multimedia data. Therefore, image coding technology is a highly practical technology. It is important to note that the English terms "image coding" and "image encoding" are often translated into "image coding" in Chinese. Image coding is a broad term that encompasses both the process of encoding an image into a bitstream and the process of decoding (decoding) the bitstream back into an image.

[0173] Image coding simply refers to the process of encoding an image into a bitstream. Image coding research has a long history. Researchers have proposed numerous methods and developed I-frame encoding schemes for various image and video coding standards, including JPEG, JPEG 2000, JPEG-XL, JPEG-XX, WebP, H.264 / AVC, H.264 / HEVC, H.26 / VVC, AVS3, and AV1. Most of these coding methods are based on transform, prediction, and entropy coding techniques. While these coding methods are currently widely used, the increase in image data volumes and the emergence of new media types have necessitated the need for coding methods with higher compression efficiency.

[0174] Image encoding based on deep learning:

[0175] In recent years, researchers have been studying deep learning-based image coding methods. Some have achieved promising results. For example, Balle et al. proposed an end-to-end optimized image coding method that outperforms the best existing image coding methods and even the best existing traditional coding standard, H.265 / HEVC.

[0176] Deep learning-based image coding relies on deep neural networks, typically convolutional neural networks. Several research works have proposed image coding methods based on Transformer networks. The architecture of a deep neural network can be designed manually or obtained through neural architecture search (NAS). The parameters of a deep neural network are obtained by using a loss function and a backpropagation algorithm.

[0177] Figure 6 shows a typical deep learning-based image compression method, also known as a neural network-based image compression method. Generally, a neural network-based image compression method includes the following components: a feature extraction module, a feature quantization module, an entropy coding module, an entropy decoding module, a feature dequantization module, and a feature decoding module. On the encoder side, the feature extraction module can use a nonlinear mapping activation function to obtain an extracted three-dimensional feature map through multi-layer convolution stacking. The feature quantization module quantizes the eigenvalues ​​of floating-point numbers through eigenvalue quantization to obtain quantized eigenvalues. The quantized eigenvalues ​​are losslessly entropy encoded to obtain an encoded bitstream. Upon receiving the entropy-coded bitstream, the decoder performs lossless entropy decoding to obtain the three-dimensional quantized eigenvalues. The feature decoding module decodes the features into a reconstructed image to achieve decoding.

[0178] After the image to be compressed passes through the feature extraction module and the feature quantization module, a three-dimensional feature quantization map is generated. When processing each eigenvalue in the three-dimensional feature quantization map, the entropy coding module uses the eigenvalues ​​in the processed neighborhood as context to estimate and obtain the probability distribution of the eigenvalue. Based on this probability distribution, subsequent encoding is performed to obtain the encoded bitstream.

[0179] With the outstanding performance of deep learning in various fields, researchers have proposed an end-to-end image coding solution based on deep learning. Figure 7 shows the coding framework. The specific technical solution is as follows: On the encoder side, the original image is input into the feature extraction module, and the feature map is output. The feature map passes through the side information extraction module, and the side information is output. On the encoder and decoder sides, it is input into the probability estimation module, and the probability distribution of each feature element is output to obtain the value of the feature element to be encoded. In addition, the feature map is input into the quantization module to obtain a quantized feature map. The entropy coding module performs entropy coding on each feature element in the quantized feature map based on the probability distribution of each feature element to obtain the encoded bit stream.

[0180] On the decoder side, the decoder parses the bitstream and outputs the probability distribution of the symbols to be encoded based on the accompanying information to obtain the value of the feature element to be decoded. The k-entropy decoding module performs arithmetic decoding on each feature element in the quantized feature map based on the probability distribution of each feature element to obtain the value of the feature element. The feature map is input to the image reconstruction module, and the reconstructed image is output.

[0181] Neural Networks

[0182] A neural network may include neurons. A neuron may be an operation unit that uses xs and an intercept 1 as input. The output of the operation unit may be:

[0183] Here, s=s=1,2,...,n, n is a natural number greater than 1, Ws is the weight of xs, b is the bias of the neuron, and f is the activation function of the neuron (activation function), which is used to introduce nonlinear characteristics into the neural network to convert the input signal in the neuron into the output signal. The output signal of the activation function can be used as the input of the next convolutional layer. The activation function can be a sigmoid function. A neural network is a network constructed by connecting multiple single neurons together. Specifically, the output of a neuron can be the input to another neuron. The input of each neuron can be connected to the local receptive field of the previous layer to extract the characteristics of the local receptive field. The local receptive field can be an area including several neurons.

[0184] Convolutional Neural Networks:

[0185] A convolutional neural network (CNN) is a deep neural network with a convolutional architecture. A CNN includes a feature extractor, which consists of convolutional layers and subsampling layers. The feature extractor can be considered a filter. A convolutional layer is a layer of neurons in a CNN that performs convolution processing on the input signal. In a convolutional layer of a CNN, a neuron may only be connected to a subset of neurons in an adjacent layer. A convolutional layer typically includes several feature planes, each of which may include a number of neurons arranged in a rectangular shape. Neurons on the same feature plane share a weight, which is the convolution kernel. Shared weights can be understood as a position-independent way of extracting image information. The convolution kernel can be initialized as a matrix of random size. During the training process of a CNN, appropriate weights can be obtained for the convolution kernel through learning. In addition, shared weights directly reduce the number of connections between CNN layers and reduce the risk of overfitting.

[0186] Figure 8 schematically illustrates the general concept of processing by a neural network such as a CNN. A convolutional neural network consists of an input layer, an output layer, and multiple hidden layers. The input layer provides the input (e.g., a portion of an image, as shown in Figure 8) for processing. The hidden layers of a CNN typically consist of a series of convolutional layers, which perform convolutions with multiplications or other dot products. The result of these layers is one or more feature maps, sometimes also called channels. Subsampling may be involved in some or all layers. Therefore, as shown in Figure 8, the feature maps can become smaller. The activation function in a CNN is typically a Rectified Linear Unit (RELU) layer, followed by additional convolutions such as pooling, fully connected, and normalization layers. These are called hidden layers because their inputs and outputs are masked by the activation function and the final convolution. Although these layers are colloquially referred to as convolutions, this is just convention. Mathematically, it is technically a sliding dot product or cross-correlation. This has important implications for the indices in the matrix, as it affects how weights are determined at specific index points.

[0187] When programming a CNN for image processing, as shown in Figure 8, the input is a tensor with a shape of (number of images) x (image width) x (image height) x (image depth). Then, after passing through the convolutional layer, the image is abstracted into a feature map with a shape of (number of images) x (feature map width) x (feature map height) x (feature map channels). A convolutional layer in a neural network should have the following properties: A convolution kernel defined by width and height (hyperparameters). The number of input and output channels (hyperparameters). The depth of the convolution filter (input channels) should be equal to the number of channels in the input feature map (depth).

[0188] Traditional multilayer perceptron (MLP) models have been used for image recognition in the past. However, due to the full connectivity between nodes, their dimensionality is high and does not scale well with higher resolution images. A 1000×1000 pixel image with RGB color channels has 3 million weights, which is too high to be processed efficiently at scale with full connectivity. Furthermore, this network architecture does not account for the spatial structure of the data, treating input pixels that are far apart in the same way as pixels that are close together. This ignores the locality of reference in image data, both computationally and semantically. Therefore, full connectivity of neurons is wasteful for purposes such as image recognition, which is dominated by spatially local input patterns.

[0189] Convolutional neural networks are biologically inspired variants of multilayer perceptrons, specifically designed to mimic the behavior of the visual cortex. These models alleviate the challenges posed by MLP architectures by exploiting the strong spatially local correlations present in natural images. The convolutional layer is the core building block of a CNN. The parameters of this layer consist of a set of learnable filters (the kernels mentioned above) that have a small receptive field but extend to the full depth of the input volume. During the forward pass, each filter is convolved across the width and height of the input volume, computing the dot product between the entries of the filter and the input, and producing a two-dimensional activation map for that filter. Thus, the network learns filters that activate when it detects a certain type of feature at a certain spatial location in the input.

[0190] The activation maps of all filters stacked along the depth dimension form the complete output volume of the convolutional layer. Therefore, each entry in the output volume can also be interpreted as the output of a neuron that observes a small region in the input and shares parameters with neurons in the same activation map. A feature map, or activation map, is the output activation of a given filter. Feature map and activation have the same meaning. In some papers, it is called an activation map because it is a map corresponding to the activations of different parts of the image, and a feature map because it is also a map of certain features found in the image. High activation means that a certain feature has been found.

[0191] Another important concept in CNNs is pooling, a form of nonlinear downsampling. There are several nonlinear functions that implement pooling, with max pooling being the most common. It divides the input image into a set of non-overlapping rectangles and, for each such subregion, outputs the maximum value.

[0192] Intuitively, the precise location of a feature relative to other features is less important than its coarse location. This is the idea behind pooling in convolutional neural networks. Pooling layers are used to gradually reduce the spatial size of the representation, reducing the number of parameters, memory usage, and computational overhead in the network, thereby controlling overfitting. In CNN architectures, it is common to periodically insert pooling layers between consecutive convolutional layers. Pooling provides another form of translation invariance.

[0193] Pooling layers operate independently on each depth slice of the input and resize it spatially. The most common form is a pooling layer with filters of size 2×2, applying a downsampling stride of 2 along both width and height to each depth slice in the input, discarding 75% of the activations. In this case, each maximum operation exceeds 4 numbers. The depth dimension remains unchanged.

[0194] In addition to max pooling, the pooling unit can also use other functions such as average pooling or 2-norm pooling. Average pooling was often used historically but has recently fallen out of favor compared to max pooling, which performs better in practice. Due to the large reduction in representation size, there has been a recent trend to use smaller filters or to drop pooling layers entirely. "Region of interest" pooling (also known as ROI pooling) is a variant of max pooling where the output size is fixed and the input rectangle is a parameter. Pooling is an important component of convolutional neural networks for object detection based on the Faster R-CNN architecture.

[0195] The aforementioned ReLU, short for Rectified Linear Unit, applies a non-saturating activation function. By setting negative values ​​to zero, it effectively removes negative values ​​from the activation map. This adds nonlinearity to the decision function and the entire network without affecting the receptive field of the convolutional layer. Other functions are also used to add nonlinearity, such as the saturated hyperbolic tangent and the sigmoid function. ReLU is often preferred over other functions because it trains neural networks several times faster without significantly affecting generalization accuracy.

[0196] After several convolutional and max-pooling layers, high-level reasoning in a neural network is done through fully connected layers. Neurons in a fully connected layer have connections to all activations in the previous layer, as seen in regular (non-convolutional) artificial neural networks. Therefore, their activations can be calculated as affine transformations, matrix multiplications followed by bias shifts (vector addition of learned or fixed bias terms).

[0197] The "loss layer" specifies how training penalizes deviations between predictions (outputs) and true labels and is typically the last layer in a neural network. A variety of loss functions can be used, appropriate for different tasks. Softmax loss is used to predict a single class among K mutually exclusive classes. Sigmoid cross-entropy loss is used to predict K independent probability values ​​in the range [0, 1]. Euclidean loss is used to regress to real-valued labels.

[0198] In summary, Figure 8 shows the data flow in a typical convolutional neural network. First, the input image passes through a convolutional layer and is abstracted into a feature map consisting of several channels, corresponding to the number of filters in the set of learnable filters in that layer (e.g., one channel per filter). The feature map is then subsampled using, for example, a pooling layer, which reduces the dimensionality of each channel in the feature map. The data then enters another convolutional layer, which may have a different number of output channels, resulting in a different number of channels in the feature map. As mentioned above, the number of input channels and output channels are hyperparameters of the layer. In order to establish the connectivity of the network, these parameters need to be synchronized between the two connected layers, for example, the number of input channels of the current layer should be equal to the number of output channels of the previous layer. For the first layer that processes the input data (e.g., an image), the number of input channels is typically equal to the number of channels of the data representation, such as 3 channels for RGB or YUV representation of images or videos, or 1 channel for grayscale image or video representation.

[0199] The method provided in the embodiments of the present application is applied to a video codec, such as a video codec in a video communication system, as shown in Figure 9: After a video is captured using a video capture device, it undergoes a series of pre-processing steps and is then compressed and encoded to produce an encoded bitstream. A sending module transmits the bitstream via a transmission network to a receiving module, where it is decoded by a decoder and then rendered for display. Furthermore, the encoded bitstream can also be directly stored.

[0200] The embodiment of the present application describes a neural network-based coding and decoding scheme for the enhancement layer, and its application scenario can be a layered coding scheme.

[0201] The methods provided in the embodiments of the present application can be used in devices or products that include video encoder and / or decoder functions, such as video processing hardware and software products, such as chips, and in products or devices that include such chips, such as mobile phones and other media products.

[0202] FIG10 shows a flow chart of an encoding method provided in an embodiment of the present application. As shown in FIG10 , the encoding method provided in an embodiment of the present application includes:

[0203] S1001. Perform AI encoding on the input image to obtain a feature map.

[0204] The above-mentioned AI encoding can be any AI encoder.

[0205] For example, the input image can be input into a JPEG AI encoder for AI encoding to obtain a feature map.

[0206] S1002: Perform entropy coding on the feature map to obtain a bit stream.

[0207] For example, an asymmetric numeral system (ANS) entropy encoding may be performed on the feature map to obtain a code stream.

[0208] S1003: Perform a transformation operation on the target area of ​​the input image to obtain a change coefficient.

[0209] In a possible implementation, the above-mentioned variation coefficient may be a residual.

[0210] In a possible implementation, one or more regions of the input image may be selected as target regions.

[0211] Exemplarily, one or more regions of the input image may be selected as target regions based on image distortion (image distortion degree) of the regions.

[0212] For example, a region in the input image where the image distortion (image distortion degree) is greater than an image distortion threshold may be defined as the target region.

[0213] As another example, one or more regions of interest to the human eye of the input image may be selected as the target region.

[0214] As another example, one or more regions of the input image may be randomly selected as the target region.

[0215] In a possible implementation, the transformation operation includes at least one of DCT, DFT, or DWT.

[0216] For example, a DCT transform may be performed on the target region of the input image.

[0217] In a possible implementation, the target area may be divided into a plurality of image blocks, and the transformation operation is performed on the plurality of image blocks.

[0218] For example, the target area may be divided into a plurality of image blocks according to a granularity of HxW, and the transformation operation is performed on the plurality of image blocks, where H is a positive integer and W is a positive integer, and H and W may be the same.

[0219] For example, the target area may be divided into multiple image blocks at a granularity of 8x8 based on a binary mask image, and a DCT operation may be performed on the multiple image blocks.

[0220] Among them, the binary mask image represents all 8x8 image blocks in the original image that need to be DCT transformed, and the 8x8 blocks corresponding to the points with a value of 1 in the mask image represent image blocks that need to be DCT transformed.

[0221] S1004: Encode the transform coefficients into a bitstream.

[0222] In a possible implementation, the transform coefficients may be quantized, and the quantized transform coefficients may be encoded into the bitstream.

[0223] In a possible implementation, the transform coefficients may be entropy encoded into the bitstream.

[0224] For example, the DC transform coefficients and AC transform coefficients of the input image may be encoded separately, wherein the NxN block is transformed to obtain NxN transform coefficients, the transform coefficient at the (0,0) position is the DC transform coefficient, and the transform coefficients at other positions are the AC transform coefficients.

[0225] For example, differential coding can be used for the DC transform coefficients of the input image. This involves encoding the difference between the DC component of the previous block and the previous block. The difference is divided into multiple groups based on its amplitude. Each group number is entropy-coded using a tabled asymmetric numeral systems (tANS) algorithm, and the amplitudes within each group are encoded using a fixed-length code.

[0226] For example, the DC transform coefficients of the input image can be differentially encoded according to the table shown in Table 1. Table 1 shows the group numbers, the corresponding numerical range for each group, and the number of bits required for the numerical value. When using tANS encoding for the group numbers, the probabilities P0 to P11 of each group number are first calculated, represented by 8-bit unsigned integers, and written into the bitstream. Simultaneously, the group numbers are entropy-encoded based on the probabilities P0 to P11 and written into the bitstream.

[0227] Table 1

[0228] For example, run-length coding can be used for the AC transform coefficients of the input image, wherein the coding scheme for the non-zero coefficients can be the same as the coding method for the differential amplitude of the DC transform coefficients.

[0229] Run-length coding: Encode the number R of zeros between the current non-zero coefficient and the previous non-zero coefficient, up to a maximum of 15. Then encode the current non-zero coefficient S. If the number of zeros is greater than 15, encode (15, 0). When R is 16, it indicates that all the AC transform coefficients from the current position to the last are zero. Entropy coding is performed on the number R of consecutive zeros and the group number of coefficients S using tANS: The probability Pr of R being 0 to 16 is calculated, and a 1x17 probability vector is represented by 17 8-bit unsigned integers and written into the bitstream. The probability Ps of S being 0 to 11 is calculated, and a 1x12 probability vector is represented by 12 8-bit unsigned integers and written into the bitstream. Based on Pr and Ps, entropy coding is performed on R and the group number of coefficients S using ANS. The amplitude of coefficient S is represented by a fixed-length code using the number of bits in the group and written into the bitstream.

[0230] For example, the AC transform coefficients of the input image may be run-length coded according to the table shown in Table 2. Table 2 shows the group number, the value range corresponding to each group, and the number of bits required for the value.

[0231] Table 2

[0232] S1005: Encode the position information into a bitstream.

[0233] The above-mentioned position information is used to indicate the position of the above-mentioned target area in the above-mentioned input image.

[0234] In one possible implementation, the location information may be mask information (e.g., a binary mask). The mask information includes a first region, and the first region is used to indicate a target region. For example, the mask may be composed of 0s and 1s, with the region where 1s are located being the target region.

[0235] In a possible implementation, the position information may be entropy encoded into the bitstream.

[0236] For example, for an HxW image, partitioning it into 8x8 blocks results in a binary mask with a height of ((H+7)>>3) and a width of ((W+7)>>3). The mask is converted into a one-dimensional 01 vector using raster scanning. The 01 vector generated by the mask is then entropy encoded and written into the above bitstream.

[0237] For example, run-length coding can be used to entropy encode the 01 vector generated by the mask. An unsigned 8-bit number represents the number of 0s preceding a non-zero 1. A bitstream is generated by combining the 8-bit 0s and the 1-bit 0 / 1 sequence to form a 01 sequence. (When the number of 0s is greater than 255, the 255 bits are converted to binary and written into the bitstream, and the 256th 0 is written into the bitstream.)

[0238] For another example, ANS can be used to entropy encode the 01 vector. The frequency P of 0s in the 01 vector is counted, and this frequency is used as the probability of 0. This probability P is represented by an 8-bit integer A and written into the bitstream. The probability of 1 is (256-A) / 256. Based on the probability P, ANS is used to entropy encode the 01 vector.

[0239] The method provided in the embodiments of this application additionally enhances the quality of localized image regions using traditional encoding schemes, compensating for the significant localized image distortion caused by the capacity and generalization of AI encoding networks. Compared to AI encoding only of the input image, additionally enhancing the quality of localized image regions using traditional encoding schemes can improve the overall image quality of AI image encoding.

[0240] In a possible implementation, the transformation parameters may be encoded (entropy encoded) into the above-mentioned bitstream, wherein the transformation parameters are the transformation parameters used in the above-mentioned transformation operation.

[0241] FIG11 shows a flow chart of an encoding method provided in an embodiment of the present application. As shown in FIG11 , the encoding method provided in an embodiment of the present application includes:

[0242] S1101. Perform entropy decoding on the code stream to obtain a feature map.

[0243] For example, ANS entropy decoding may be performed on the code stream to obtain a feature map.

[0244] S1102: Perform AI decoding on the feature map to obtain a reconstructed image.

[0245] The above-mentioned AI decoding can be any AI decoder.

[0246] For example, the feature map can be input into a JPEGAI decoder for AI decoding to obtain a reconstructed image.

[0247] S1103 , performing entropy decoding on the code stream to obtain transform coefficients.

[0248] Exemplarily, the DC transform coefficients and AC transform coefficients in the code stream may be entropy decoded separately.

[0249] For example, for DC coefficient decoding, the probability P0 to P11 of the DC differential value in each group can be obtained from the bitstream. The grouping of the values ​​is shown in Table 1. Using the probabilities P0 to P11, tANS entropy decoding is applied to the group number to obtain the group number of the current DC differential value from the bitstream. Based on the number of bits required for the value in that group, the corresponding bits are read from the bitstream to obtain the differential value. This differential value is then summed with the DC component of the previous block to obtain the current DC coefficient value. This process yields the DC coefficients for all DCT blocks.

[0250] For another example, for AC coefficient decoding, the probability Pr of the number of zeros R between adjacent non-zero coefficients taking values ​​between 0 and 16 can be obtained from the bitstream. This 1x17 probability vector is represented by 17 8-bit unsigned integers. The probability Ps of the AC coefficient S taking different values ​​in groups 0 to 11 can be obtained from the bitstream. This 1x12 probability vector is represented by 12 8-bit unsigned integers. Based on Pr, ANS is used to entropy decode R from the bitstream. When R is 16, the AC coefficients from the current position to the 63rd are all 0. Otherwise, based on Ps, ANS is used to entropy decode S from the bitstream to obtain the group number of coefficient S. Based on the group to which coefficient S belongs, the number of bits required for the amplitude of coefficient S is determined. The corresponding bits are read from the bitstream to obtain the AC coefficient S value, and the R positions before the current coefficient S are filled with 0s. This complete process yields the AC coefficients for all DCT blocks.

[0251] In a possible implementation, entropy decoding may be performed on the bitstream to obtain quantized transform coefficients; and dequantization may be performed on the quantized transform coefficients.

[0252] S1104 , performing an inverse transformation operation on the transformation coefficients to obtain reconstructed pixel values ​​of the target area.

[0253] S1105: Perform entropy decoding on the code stream to obtain position information.

[0254] The above-mentioned position information is used to indicate the position of the above-mentioned target area, and the above-mentioned transformation coefficient is a coefficient used to perform a transformation operation on the above-mentioned target area.

[0255] In a possible implementation, the code stream may be entropy decoded to obtain a binary mask image representing the position information.

[0256] For example, for an HxW image, partition it into 8x8 blocks, and the resulting binary mask image has a height of ((H+7)>>3) and a width of ((W+7)>>3). The mask image is converted into a 1-dimensional 01 vector using raster scanning.

[0257] For example, run length coding is used to decode the 01 vector above. An unsigned 8-bit number represents the number of 0s preceding a non-zero 1. The number of 0s and the 0 / 1 values ​​are generated from the 01 sequence in the bitstream in the order (8-bit 0s, 1-bit 0 / 1), thus obtaining the entire binary mask.

[0258] For another example, use ANS to entropy decode the 01 vector. Decoding the bitstream yields the frequency P of 0s in the 01 vector, represented by an 8-bit integer A. The probability of 1 is (256 - A) / 256. Based on probability P, entropy decoding the 01 vector using ANS yields a binary mask.

[0259] S1106 : Determine a fused image according to the position information, the reconstructed pixel values ​​of the target area, and the reconstructed image.

[0260] In a possible implementation, the target area in the reconstructed image may be determined according to the position information; and the pixel value of the target area in the reconstructed image may be updated according to the reconstructed pixel value to obtain the fused image.

[0261] Exemplarily, the area corresponding to the enhancement layer image block in the reconstructed image can be determined based on the binary mask image, and the pixel values ​​of the area corresponding to the enhancement layer image block in the reconstructed image can be set as the reconstructed pixel values ​​of the target area of ​​the reconstructed image.

[0262] The following will introduce an encoding device for executing the above encoding method in conjunction with FIG12 .

[0263] It is understandable that, in order to implement the above functions, the encoding device includes hardware and / or software modules that perform the corresponding functions. In combination with the algorithm steps of each example described in the embodiments disclosed herein, the embodiments of the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in combination with the embodiments, but such implementation should not be considered to exceed the scope of the embodiments of the present application.

[0264] In the embodiment of the present application, the encoding device can be divided into functional modules according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated modules can be implemented in the form of hardware. It should be noted that the division of modules in this embodiment is schematic and is only a logical function division. In actual implementation, other division methods can be used.

[0265] In the case of dividing each functional module according to each function, Figure 12 shows a possible schematic diagram of the composition of the encoding device involved in the above embodiment. The device can be an electronic device, or a module applied to an electronic device (such as a processor, chip, or chip system, etc.), or a logical node, logical module, or software that can realize all or part of the functions of the electronic device. As shown in Figure 12, the encoding device 1200 may include: an encoding unit 1201 and a transformation unit 1202.

[0266] The encoding unit 1201 is used to perform AI encoding on the input image to obtain a feature map.

[0267] The encoding unit 1201 is further configured to perform entropy encoding on the feature map to obtain a bit stream.

[0268] The transformation unit 1202 is configured to perform a transformation operation on the target area of ​​the input image to obtain a transformation coefficient.

[0269] The encoding unit 1201 is further configured to encode the transform coefficients into the bitstream.

[0270] The encoding unit 1201 is further configured to encode position information into the bitstream, where the position information is used to indicate the position number of the target area in the input image.

[0271] In a possible implementation, the transform unit 1202 is specifically configured to: divide the target area into a plurality of image blocks; and perform the transform operation on the plurality of image blocks to obtain transform coefficients.

[0272] In a possible implementation, the encoding unit 1201 is specifically configured to: quantize the transform coefficients; and encode the quantized transform coefficients into the bitstream.

[0273] The decoding device for executing the above decoding method will be introduced below with reference to FIG13 .

[0274] It is understandable that, in order to implement the above functions, the decoding device includes hardware and / or software modules that perform the corresponding functions. In combination with the algorithm steps of each example described in the embodiments disclosed herein, the embodiments of the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in a hardware or computer software driven hardware manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application in combination with the embodiments, but such implementation should not be considered to exceed the scope of the embodiments of the present application.

[0275] In the embodiments of the present application, the decoding device can be divided into functional modules according to the above-mentioned method examples. For example, each functional module can be divided according to each function, or two or more functions can be integrated into a processing module. The above-mentioned integrated modules can be implemented in the form of hardware. It should be noted that the division of modules in this embodiment is schematic and is only a logical functional division. In actual implementation, other division methods may be used.

[0276] In the case of dividing each functional module according to its corresponding function, Figure 13 shows a possible schematic diagram of the composition of the decoding device involved in the above embodiment. The device can be an electronic device, or a module applied to an electronic device (such as a processor, chip, or chip system, etc.), or a logical node, logical module, or software that can implement all or part of the functions of the electronic device. As shown in Figure 13, the decoding device 1300 may include: a decoding unit 1301, a transformation unit 1302, and a fusion unit 1303.

[0277] The decoding unit 1301 is configured to perform entropy decoding on the bitstream to obtain a feature map.

[0278] The decoding unit 1301 is further configured to perform AI decoding on the feature map to obtain a reconstructed image.

[0279] The decoding unit 1301 is further configured to perform entropy decoding on the bit stream to obtain transform coefficients.

[0280] The transformation unit 1302 is configured to perform an inverse transformation operation on the transformation coefficients to obtain reconstructed pixel values ​​of the target area.

[0281] The decoding unit 1301 is further configured to perform entropy decoding on the code stream to obtain position information, where the position information is used to indicate the position of the target area.

[0282] The fusion unit 1303 is configured to determine a fused image based on the position information, the reconstructed pixel values ​​of the target area, and the reconstructed image.

[0283] In a possible implementation, the fusion unit 1303 is specifically configured to: determine the target area in the reconstructed image according to the position information; and update the pixel value of the target area in the reconstructed image according to the reconstructed pixel value to obtain the fused image.

[0284] In a possible implementation, the decoding unit 1301 is specifically configured to: perform entropy decoding on the code stream to obtain quantized transform coefficients; and perform inverse quantization on the quantized transform coefficients to obtain the transform coefficients.

[0285] The present application also provides a chip, which can be a chip for the encoding device or decoding device described above. FIG14 shows a schematic diagram of the structure of a chip 1400. Chip 1400 includes one or more processors 1401 and an interface circuit 1402. Optionally, chip 1400 may also include a bus 1403.

[0286] The processor 1401 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above encoding and decoding method can be completed by a hardware integrated logic circuit in the processor 1401 or by software instructions.

[0287] Optionally, the processor 1401 may be a general-purpose processor, a digital signal processing (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The methods and steps disclosed in the embodiments of the present application may be implemented or executed. The general-purpose processor may be a microprocessor or any conventional processor.

[0288] The interface circuit 1402 can be used to send or receive data, instructions or information. The processor 1401 can use the data, instructions or other information received by the interface circuit 1402 to process it, and can send the processing completion information through the interface circuit 1402.

[0289] Optionally, the chip also includes a memory, which may include a read-only memory and a random access memory, and provides operating instructions and data to the processor. Part of the memory may also include a non-volatile random access memory (NVRAM).

[0290] Optionally, the memory stores an executable software module or a data structure, and the processor can perform corresponding operations by calling an operation instruction stored in the memory (the operation instruction may be stored in an operating system).

[0291] Optionally, the chip can be used in the encoding device or decoding device involved in the embodiments of the present application. Optionally, the interface circuit 1402 can be used to output the execution result of the processor 1401. For the encoding and decoding methods provided in one or more embodiments of the present application, reference can be made to the aforementioned embodiments and will not be repeated here.

[0292] It should be noted that the corresponding functions of the processor 1401 and the interface circuit 1402 can be implemented through hardware design, software design, or a combination of hardware and software, and there is no limitation here.

[0293] Figure 15 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. The electronic device may be an encoding device or a decoding device, a chip or functional module in an encoding device, or a chip or functional module in a decoding device. As shown in Figure 15, the electronic device 1500 includes a processor 1501, a transceiver 1502, and a communication circuit 1503.

[0294] In which, the processor 1501 is used to execute any step in the encoding and decoding method provided in the embodiment of the present application, and in the process of executing any step in the encoding and decoding method provided in the embodiment of the present application, the transceiver 1502 and the communication line 1503 can be optionally called to complete the corresponding operation.

[0295] Furthermore, the electronic device 1500 may further include a memory 1504 . The processor 1501 , the memory 1504 and the transceiver 1502 may be connected via a communication line 1503 .

[0296] The processor 1501 is a processor, a general-purpose processor, a network processor (NP), a digital signal processor (DSP), a microprocessor, a microcontroller, a programmable logic device (PLD), or any combination thereof. The processor 1501 may also be other devices with processing functions, such as circuits, devices, or software modules, without limitation.

[0297] Transceiver 1502 is used to communicate with other devices or other communication networks, such as Ethernet, radio access networks (RAN), wireless local area networks (WLAN), etc. Transceiver 1502 can be a module, circuit, transceiver, or any device capable of implementing communication.

[0298] The transceiver 1502 is mainly used for sending and receiving commands and information, and may include a transmitter and a receiver for sending and receiving commands and information, respectively. Operations other than sending and receiving commands and information are implemented by the processor.

[0299] The communication line 1503 is used to transmit information between the various components included in the electronic device 1500.

[0300] In one design, the processor can be considered as the logic circuit and the transceiver as the interface circuit.

[0301] The memory 1504 is used to store instructions, where the instructions may be computer programs.

[0302] Memory 1504 may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM may be used, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchlink DRAM (SLDRAM), and direct RAM bus RAM (DR RAM). Memory 1504 may also be a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), magnetic disk storage media or other magnetic storage devices, etc. It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0303] It should be noted that memory 1504 can exist independently of processor 1501 or can be integrated with processor 1501. Memory 1504 can be used to store instructions, program code, or data. Memory 1504 can be located within or outside electronic device 1500, without limitation. Processor 1501 is configured to execute instructions stored in memory 1504 to implement the methods provided in the above embodiments of this application.

[0304] In one example, processor 1501 may include one or more processors, such as processor 0 and processor 1 in FIG. 15 .

[0305] As an optional implementation, the electronic device 1500 includes multiple processors. For example, in addition to the processor 1501 in FIG. 15 , it may also include a processor 1509 .

[0306] As an optional implementation, the electronic device 1500 further includes an output device 1505 and an input device 1506. For example, the input device 1506 is a keyboard, a mouse, a microphone, or a joystick, and the output device 1505 is a display screen, a speaker, or the like.

[0307] It should be pointed out that the electronic device 1500 can be a chip system or a device with a similar structure as shown in Figure 15. Among them, the chip system can be composed of chips, or it can include chips and other discrete devices. The actions, terms, etc. involved in the various embodiments of this application can refer to each other without limitation. The message names or parameter names in the messages exchanged between the various devices in the embodiments of this application are only an example. Other names can also be used in the specific implementation without limitation. In addition, the component structure shown in Figure 15 does not constitute a limitation on the electronic device 1500. In addition to the components shown in Figure 15, the electronic device 1500 may include more or fewer components than those shown in Figure 15, or combine certain components, or arrange the components differently.

[0308] The processor and transceiver described in this application can be implemented on an integrated circuit (IC), an analog IC, a radio frequency integrated circuit, a mixed-signal IC, an application specific integrated circuit (ASIC), a printed circuit board (PCB), an electronic device, etc. The processor and transceiver can also be manufactured using various IC process technologies, such as complementary metal oxide semiconductor (CMOS), N-type metal oxide semiconductor (NMOS), P-type metal oxide semiconductor (positive channel metal oxide semiconductor, PMOS), bipolar junction transistor (BJT), bipolar CMOS (BiCMOS), silicon germanium (SiGe), gallium arsenide (GaAs), etc.

[0309] Figure 16 is a schematic diagram of the structure of another electronic device provided in an embodiment of the present application. The electronic device may be an encoding device or a decoding device, a chip or a functional module in an encoding device, or a chip or a functional module in a decoding device. For ease of explanation, Figure 16 only shows the main components of the electronic device, including a processor 1601, a memory 1602, a control circuit 1603, and an input / output device 1604. The processor 1601 is mainly used to process communication protocols and communication data, execute software programs, and process data of software programs. The memory 1602 is mainly used to store software programs and data. The control circuit 1603 is mainly used for power supply and transmission of various electrical signals. The input / output device 1604 is mainly used to receive data input by the user and output data to the user.

[0310] When the electronic device is a processor 1601, the control circuit 1603 may be a motherboard, the memory 1602 includes a hard disk, RAM, ROM and other media with storage functions, the processor 1601 may include a baseband processor 1601 and a central processing unit, the baseband processor is mainly used to process communication protocols and communication data, the central processing unit is mainly used to control the entire electronic device, execute software programs, and process software program data, the input and output devices 1604 include a display screen, a keyboard, and a mouse, etc.; the control circuit 1603 may further include or be connected to a transceiver circuit or transceiver, such as a network cable interface, etc., for sending or receiving data or signals, such as for data transmission and communication with other devices. Furthermore, it may also include an antenna for sending and receiving wireless signals for data / signal transmission with other devices.

[0311] An embodiment of the present application also provides an encoding device, which includes: at least one processor, when the at least one processor executes program code or instructions, it implements the above-mentioned related method steps to implement the encoding method in the above embodiment.

[0312] Optionally, the apparatus may further include at least one memory configured to store the program code or instruction.

[0313] An embodiment of the present application also provides a decoding device, which includes: at least one processor, when the at least one processor executes program code or instructions, it implements the above-mentioned related method steps to implement the decoding method in the above embodiment.

[0314] Optionally, the apparatus may further include at least one memory configured to store the program code or instruction.

[0315] An embodiment of the present application further provides a computer storage medium, which stores computer instructions. When the computer instructions are executed on a communication device, the communication device executes the above-mentioned related method steps to implement the encoding and decoding method in the above-mentioned embodiment.

[0316] The embodiment of the present application further provides a computer program product. When the computer program product is run on a computer, the computer is caused to execute the above-mentioned related steps to implement the encoding and decoding method in the above-mentioned embodiment.

[0317] The present application also provides an encoding device, which may be a chip, integrated circuit, component, or module. Specifically, the device may include a processor and a memory for storing instructions, or the device may include at least one processor configured to retrieve instructions from an external memory. When the device is running, the processor may execute the instructions, causing the chip to perform the encoding method described in each of the above method embodiments.

[0318] The present application also provides a decoding device, which can be a chip, integrated circuit, component, or module. Specifically, the device can include a processor and a memory for storing instructions, or the device can include at least one processor for retrieving instructions from an external memory. When the device is running, the processor can execute the instructions, causing the chip to perform the decoding method described in each of the above method embodiments.

[0319] An embodiment of the present application further provides a code stream storage method, which includes: acquiring and storing the code stream obtained by the above encoding and decoding method.

[0320] The embodiment of the present application further provides a code stream storage device, which is used to obtain and store the code stream obtained by the above encoding and decoding method.

[0321] An embodiment of the present application further provides a code stream transmission method, which includes: acquiring and transmitting the code stream obtained by the above encoding and decoding method.

[0322] The embodiment of the present application further provides a code stream transmission device, which is used to obtain and transmit the code stream obtained by the above encoding and decoding method.

[0323] An embodiment of the present application further provides a computer-readable storage medium, on which a code stream obtained by the above encoding and decoding method is stored.

[0324] Please refer to Figure 17, which schematically illustrates the general concept of processing by a neural network such as a convolutional neural network (CNN). A convolutional neural network consists of input and output layers, as well as multiple hidden layers. The input layer is the layer that provides the input (a portion of the input image, as shown in Figure 17) for processing. The hidden layers of a CNN typically consist of a series of convolutional layers, which perform convolutions with multiplications or other dot products. The result of the layers is one or more feature maps (represented by empty solid rectangles), sometimes also called channels. Resampling (such as subsampling) may be involved in some or all layers. As a result, the feature maps may become smaller, as shown in Figure 17. Note that convolution with stride can also reduce the size of the input feature maps (resampling). The activation function in a CNN is typically a ReLU (rectified linear unit) layer, followed by additional convolutions such as pooling, fully connected, and normalization layers. These are called hidden layers because their inputs and outputs are masked by the activation function and the final convolution. Although these layers are colloquially referred to as convolutions, this is just convention. Mathematically speaking, it is technically a sliding dot product or cross correlation. The indexing in the matrix has important implications because it affects how the weight is determined at a particular index point.

[0325] When programming a CNN to process images, as shown in Figure 17, the input is a tensor of shape (number of images) x (image width) x (image height) x (image depth). It should be noted that the image depth can be composed of the number of channels in the image. After passing through the convolutional layer, the image is abstracted into a feature map with a shape of (number of images) x (feature map width) x (feature map height) x (feature map channels). The convolutional layer in a neural network should have the following properties: a convolution kernel defined by width and height (hyperparameters). The number of input and output channels (hyperparameters). The depth of the convolution filter (input channels) should be equal to the number of channels in the input feature map (depth).

[0326] Video Coding Machines (VCM) is another popular area of ​​computer science. The main idea behind this approach is to transmit coded representations of image or video information for further processing by computer vision (CV) algorithms, such as object segmentation, detection, and recognition. Compared to traditional image and video coding, which targets human perception, quality is characterized by performance on computer vision tasks, such as object detection accuracy, rather than reconstruction quality. This is illustrated in Figure 18.

[0327] Machine video coding, also known as collaborative intelligence, is a relatively new paradigm for efficiently deploying deep neural networks in mobile cloud infrastructure. By partitioning the network between the mobile side 1810 and the cloud side 1890 (e.g., cloud servers), the computational workload can be distributed, minimizing the system's overall energy and / or latency. Generally, collaborative intelligence is a paradigm in which neural network processing is distributed across two or more distinct computational nodes; for example, devices, but generally, any functionally defined node. The term "node" here does not refer to a neural network node as described above. Instead, a (computing) node here refers to a (physically or at least logically) independent device / module that implements a portion of a neural network. Such devices can be different servers, different end-user devices, a mixture of servers and / or user devices and / or the cloud and / or processors, etc. In other words, the computational nodes can be considered to belong to the same neural network and communicate with each other to transfer encoded data within / for the neural network. For example, to perform complex computations, one or more layers can be executed on a first device (such as a device on the mobile side 1810), while one or more layers can be executed on another device (such as a cloud server on the cloud side 1890). However, the distribution can also be more refined, and a single layer can be executed on multiple devices. In this disclosure, the term "multiple" means two or more. In some existing solutions, part of the neural network functionality is executed in a device (user device or edge device, etc.) or multiple such devices, and the output (feature map) is then passed to the cloud. The cloud is a collection of processing or computing systems located outside the device that is operating part of the neural network. The concept of collaborative intelligence has also been extended to model training. In this case, data flows in both directions: from the cloud to the mobile device during the backpropagation of training, and from the mobile device to the cloud during the forward pass and inference of training (as shown in Figure 18).

[0328] Some work has proposed semantic image compression by encoding deep features and then reconstructing the input image from them. Compression based on uniform quantization was demonstrated, followed by context-based adaptive arithmetic coding (CABAC) from H.264. In some scenarios, it may be more efficient to send the output of the hidden layer (deep feature map) from the mobile component 1810 to the cloud 1890, rather than sending compressed natural image data to the cloud and performing object detection using the reconstructed image. Therefore, it may be advantageous to compress the data (features) generated by the mobile side 1810, which may include a quantization layer 1820 for this purpose. Accordingly, the cloud side 1890 may include an inverse quantization layer 1860. Efficient compression of feature maps facilitates image and video compression and reconstruction for both human perception and machine vision. Entropy coding methods, such as arithmetic coding, are a popular method for compressing deep features (i.e., feature maps).

[0329] Please refer to Figure 19, which shows a code stream structure provided by an embodiment of the present application. As shown in Figure 19, the code stream includes: an image start point (Start of Image), a file header (File Header), entropy encoded data (Entropy Encoded Data) and an image end point (End of Image).

[0330] In a possible implementation, the above-mentioned position information, the above-mentioned transformation coefficient, the Gaussian distribution parameter index number, the Gaussian distribution parameter, the target probability distribution, and the target probability distribution index number can be stored in a file header.

[0331] In one possible implementation, the target quality residual matrix or the target quality matrix may be stored in entropy coded data.

[0332] Please refer to Figure 20, which shows a schematic diagram of layered coding provided in an embodiment of the present application.

[0333] During video network transmission, especially for real-time multi-user communication over the internet, network bandwidth and device processing capabilities vary considerably among users. This differentiated network bandwidth resource creates a need for adaptive bitrate control tailored to each user. Layered coding proposes the concept of layered temporal, spatial, and quality information. By adding enhancement layer information to the base layer, video content with higher frame rates, resolutions, and quality can be achieved. Users can choose whether to use the enhancement layer bitrate to match their device processing capabilities and network bandwidth.

[0334] Figure 20 is a schematic diagram of a layered coding scheme provided in an embodiment of the present application. As shown in Figure 20 , the layered coding scheme includes: performing AI encoding on an input image to obtain a feature map; performing entropy encoding on the feature map to obtain a bitstream; writing position information for recording a target region of the input image into the bitstream; performing a transform operation on the target region of the input image; and writing transform coefficients used in the transform operation into the bitstream.

[0335] Please refer to Figure 21, which shows an end-to-end image encoding based on a super-prior structure provided by an embodiment of the present application.

[0336] As deep learning has shown excellent performance in various fields, researchers have proposed an end-to-end image coding scheme based on deep learning. A typical coding framework is shown in Figure 21. The specific scheme is as follows:

[0337] At the encoder end, the original image is input into the feature extraction module Ga, which outputs a feature map. This feature map is then fed into the quantization module to produce a quantized feature map. The feature map passes through the side information extraction module Ha, which outputs side information z. This side information z is then fed into the quantization module for quantization. This side information z is then entropy-encoded and written into the bitstream. The decoded version is then input into the probability estimation module Hs, which outputs the probability distribution of each feature element in the feature map. (Decoding after entropy encoding ensures codec synchronization.) The entropy coding module then entropy encodes each feature element in the feature map based on its probability distribution, producing a compressed bitstream. Side information is also a form of feature information, represented as a three-dimensional feature map with fewer feature elements than the feature map. Both feature maps and feature maps are MxWxH, where M is the number of channels, the same as the number of channels in the last convolution layer, and WxH is related to the width and height of the input image and the downsampling ratio (i.e., stride) set for each convolution layer in the network. In this figure, the width and height of the input image are both downsampled four times by a factor of 2.

[0338] At the decoding end, side information is first decoded and then fed into the Hs module, which outputs the probability distribution of the symbol to be decoded. The entropy decoding module arithmetically decodes each feature element in the feature map based on its probability distribution, obtaining the value of each feature element in the feature map. This decoded feature map is then fed into the image reconstruction module Gs, which outputs a reconstructed image.

[0339] It is worth noting that in the scheme shown in Figure 2, the input image contains three RGB channels, and the R, G, and B components have the same W and H. Image data of size 3xWxH can be input into the network for encoding and decoding. When the input image is in YUV444 format, the network shown in Figure 21 can also be used for encoding and decoding.

[0340] Among them, the device, computer storage medium, computer program product or chip provided in this embodiment is used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method provided above, and will not be repeated here.

[0341] It should be understood that in various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0342] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of this application.

[0343] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0344] In the several embodiments provided in the embodiments of the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the above-mentioned units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0345] The units described above as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0346] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0347] If the above functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present application, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the above methods of each embodiment of the embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0348] The above description is merely a specific implementation of the embodiments of the present application, but the scope of protection of the embodiments of the present application is not limited thereto. Any person skilled in the art can easily conceive of changes or substitutions within the technical scope disclosed in the embodiments of the present application, and such changes or substitutions should be included in the scope of protection of the embodiments of the present application. Therefore, the scope of protection of the embodiments of the present application should be based on the scope of protection of the claims.

Claims

1. A coding method, characterized in that, Comprising: Performing artificial intelligence (AI) encoding on an input image to obtain a feature map; Performing entropy encoding on the feature map to obtain a bitstream; Performing a transformation operation on a target region of the input image to obtain transformation coefficients; Encoding the transformation coefficients into the bitstream; Encoding position information into the bitstream, where the position information is used to indicate the position of the target region in the input image.

2. The method according to claim 1, wherein The performing a transformation operation on a target region of the input image to obtain transformation coefficients includes: Dividing the target region into a plurality of image blocks; Performing the transformation operation on the plurality of image blocks to obtain transformation coefficients.

3. The method according to claim 1 or 2, characterized in that, The encoding the transformation coefficients into the bitstream includes: Quantizing the transformation coefficients; Encoding the quantized transformation coefficients into the bitstream.

4. The method according to any one of claims 1 to 3, characterized in that, The transformation operation includes at least one of a discrete cosine transform (DCT), a discrete Fourier transform (DFT), or a discrete wavelet transform (DWT).

5. The method according to any one of claims 1 to 4, characterized in that The position information is mask map information, and the mask map information includes a first region, where the first region is used to indicate the target region.

6. A decoding method, characterized in that, Comprising: Performing entropy decoding on the bitstream to obtain a feature map; Performing AI decoding on the feature map to obtain a reconstructed image; Performing entropy decoding on the bitstream to obtain transformation coefficients; Performing an inverse transformation operation on the transformation coefficients to obtain reconstructed pixel values of the target region; Performing entropy decoding on the bitstream to obtain position information, where the position information is used to indicate the position of the target region; Determining a fused image based on the position information, the reconstructed pixel values of the target region, and the reconstructed image.

7. The method according to claim 6, characterized in that, The determining a fused image based on the position information, the reconstructed pixel values of the target region, and the reconstructed image includes: Determining the target region in the reconstructed image according to the position information; Updating the pixel values of the target region in the reconstructed image according to the reconstructed pixel values to obtain the fused image.

8. The method according to claim 6 or 7, characterized in that The performing entropy decoding on the bitstream to obtain transformation coefficients includes: Performing entropy decoding on the bitstream to obtain quantized transformation coefficients; Performing inverse quantization on the quantized transformation coefficients to obtain the transformation coefficients.

9. An encoding device, characterized in that, Comprising an encoding unit and a transformation unit; The encoding unit is configured to perform AI encoding on an input image to obtain a feature map; The encoding unit is further configured to perform entropy encoding on the feature map to obtain a bitstream; The transformation unit is configured to perform a transformation operation on a target region of the input image to obtain transformation coefficients; The encoding unit is further configured to encode the transformation coefficients into the bitstream; The encoding unit is further configured to encode position information into the bitstream, where the position information is used to indicate the position of the target region in the input image.

10. The device according to claim 9, characterized in that, The transformation unit is specifically configured to: Divide the target region into a plurality of image blocks; Perform the transformation operation on the plurality of image blocks to obtain transformation coefficients.

11. The device according to claim 9 or 10, characterized in that, The encoding unit is specifically configured to: Quantize the transformation coefficients; Encode the quantized transformation coefficients into the bitstream.

12. A decoding device, characterized in that, Comprising a decoding unit, a transformation unit, and a fusion unit; The decoding unit is configured to perform entropy decoding on the bitstream to obtain a feature map; The decoding unit is further configured to perform AI decoding on the feature map to obtain a reconstructed image; The decoding unit is further configured to perform entropy decoding on the bitstream to obtain transform coefficients; The transformation unit is configured to perform an inverse transformation operation on the transform coefficients to obtain the reconstructed pixel values of the target region; The decoding unit is further configured to perform entropy decoding on the bitstream to obtain position information, where the position information is used to indicate the position of the target region; The fusion unit is configured to determine a fused image according to the position information, the reconstructed pixel values of the target region, and the reconstructed image.

13. The device according to claim 12, characterized in that, Specifically, the fusion unit is configured to: Determine the target region in the reconstructed image according to the position information; Update the pixel values of the target region in the reconstructed image according to the reconstructed pixel values to obtain the fused image.

14. The device according to claim 12 or 13, characterized in that, Specifically, the decoding unit is configured to: Perform entropy decoding on the bitstream to obtain quantized transform coefficients; Perform inverse quantization on the quantized transform coefficients to obtain the transform coefficients.

15. An encoding device, characterized in that, Comprising at least one processor and a memory, the at least one processor executes a program or instructions stored in the memory, so that the encoding device implements the method according to any one of claims 1 to 5 above.

16. A decoding device, characterized in that, Comprising at least one processor and a memory, the at least one processor executes a program or instructions stored in the memory, so that the decoding device implements the method according to any one of claims 6 to 8 above.

17. A method for storing a bitstream, characterized in that, Comprising: Obtain and store the bitstream obtained by the method according to any one of claims 1 to 8.

18. A bitstream storage device, characterized in that, The device is configured to obtain and store the bitstream obtained by the method according to any one of claims 1 to 8.

19. A bitstream transmission method, characterized in that, Comprising: Obtain and transmit the bitstream obtained by the method according to any one of claims 1 to 8.

20. A bitstream transmission device, characterized in that, The device is configured to obtain and transmit the bitstream obtained by the method according to any one of claims 1 to 8.

21. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores the bitstream obtained by the method according to any one of claims 1 to 8.

22. A computer-readable storage medium, characterized in that, For storing a computer program, when the computer program runs on a computer or a processor, the computer or the processor implements the method according to any one of claims 1 to 8 above.

23. A computer program product, characterized in that, The computer program product contains instructions, when the instructions run on a computer or a processor, the computer or the processor implements the method according to any one of claims 1 to 8 above.

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