Driving circuit, display panel, and display device

Abstract

A driving circuit, a display panel, and a display device. The driving circuit comprises a control module (100), a first output module (200), a second output module (300), and a display module (500). The control module (100) outputs at least a first pulse signal (CPV1) and a third pulse signal (CPV3). The first output module (200) receives the first pulse signal (CPV1), and the first output module (200) outputs a first clock signal group (210) to the display module (500) on the basis of the first pulse signal (CPV1). The second output module (300) receives the third pulse signal (CPV3), and the second output module (300) outputs a second clock signal group (310) to the display module (500) on the basis of the third pulse signal (CPV3). The phases of the first pulse signal (CPV1) and the third pulse signal (CPV3) are independent of each other. The display module (500) comprises pixels arranged in an array and a plurality of gate lines extending in a row direction, and at least one row of gate lines controls a row of pixels.

Description

Driving circuit, display panel, and display device Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a driving circuit, a display panel, and a display device. Background Art

[0002] A display panel generally includes a plurality of gate lines and data lines, a gate driving circuit that outputs gate signals to the gate lines, and a source driving circuit that outputs data signals to the data lines.

[0003] With the continuous development of technology, various cost-reducing driving technologies have been applied to LCD products, including: Dual gate technology (one row of pixels is controlled by two rows of GOA CLK) and Triple gate technology (one row of pixels is controlled by three rows of GOA CLK). Dual gate technology is a driving technology that reduces the number of data lines of the LCD panel by half and doubles the number of gate lines. This reduces costs by halving the number of source drive circuits and doubling the number of gate drive circuits. Triple gate technology is a driving technology that reduces the number of data lines of the LCD panel by one-third and triples the number of gate lines, which can also reduce costs.

[0004] In the existing dual gate technology and triple gate technology, the gate driving circuit cannot output multiple clock signals to the gate line. Summary of the Invention

[0005] The purpose of the present application is to provide a driving circuit, a display panel and a display device that can output multiple gate control signals.

[0006] The present application discloses a driving circuit, which includes:

[0007] a control module, wherein the control module outputs at least a first pulse signal and a third pulse signal;

[0008] a first output module, wherein the first output module receives the first pulse signal and outputs a first clock signal group to the display module according to the first pulse signal;

[0009] a second output module, wherein the second output module receives the third pulse signal and outputs a second clock signal group to the display module according to the third pulse signal;

[0010] The phases of the first pulse signal and the third pulse signal are independent of each other;

[0011] The display module includes pixels arranged in an array and a plurality of gate lines extending along a row direction, and at least one row of the gate lines controls a row of the pixels.

[0012] Optionally, the gate lines 2a-1 and 2a rows jointly control the pixels in the a row, a=1, 2, 3...; the gate lines 2b-1 and 2b+1 rows control the pixels in the same column; the gate lines 2b and 2b+2 rows control the pixels in the same column; b=1, 2, 3...

[0013] Optionally, the first clock signal group corresponds to the first pulse signal and includes the 4n-3th and 4n-2th clock signals, and the second clock signal group corresponds to the third pulse signal and includes the 4n-1th and 4nth clock signals, n=1, 2, 3...; the clock signals of the first clock signal group are delayed in phase from small to large according to the serial number; the clock signals of the second clock signal group are delayed in phase from small to large according to the serial number.

[0014] Optionally, the gate lines in row 3a-2, row 3a-1 and row 3a jointly control the pixels in row a, a=1, 2, 3...; the gate line in row 3b-2 and the gate line in row 3b+1 control the pixels in the same column; the gate line in row 3b-1 and the gate line in row 3b+2 control the pixels in the same column; the gate line in row 3b and the gate line in row 3b+3 control the pixels in the same column; b=1, 2, 3...

[0015] Optionally, the first clock signal group corresponds to the first pulse signal and includes the 6n-5th, 6n-4th and 6n-3th clock signals, and the second clock signal group corresponds to the third pulse signal and includes the 6n-2th, 6n-1th and 6nth clock signals, n=1, 2, 3...; the clock signals of the first clock signal group are delayed in phase from small to large according to the serial number; the clock signals of the second clock signal group are delayed in phase from small to large according to the serial number.

[0016] Optionally, in the normal driving state, the first pulse signal includes multiple first effective level groups with equal phase differences, each of which includes two first effective levels; the third pulse signal includes multiple second effective level groups with equal phase differences, each of which includes two second effective levels; the first effective level groups and the second effective level groups are arranged at intervals; the nth first effective level group is used to generate the 6n-5th, 6n-4th and 6n-3th clock signals; the nth second effective level group is used to generate the 6n-2th, 6n-1th and 6nth clock signals; n=1, 2, 3...

[0017] Optionally, in the normal driving state, the first pulse signal includes multiple first effective level groups with equal phase differences, each of which includes three first effective levels; the third pulse signal includes multiple second effective level groups with equal phase differences, each of which includes three second effective levels; the first effective level groups and the second effective level groups are arranged at intervals; the nth first effective level group is used to generate the 4n-3 and 4n-2 clock signals; the nth second effective level group is used to generate the 4n-1 and 4n clock signals; n=1, 2, 3...

[0018] Optionally, when two rows of pixels are in synchronous driving state, the first pulse signal includes multiple third valid levels with equal phase differences; the third pulse signal includes multiple fourth valid levels with equal phase differences; the multiple third valid levels are phase-synchronized with the multiple fourth valid levels; the first output module and the second output module generate the first clock signal group and the second clock signal group according to the third valid levels and the fourth valid levels, respectively.

[0019] Optionally, when two rows of pixels are in a staggered synchronous driving state, the first pulse signal includes multiple fifth valid levels with equal phase differences; the third pulse signal includes multiple sixth valid levels with equal phase differences; the multiple fifth valid levels and the multiple sixth valid levels are spaced apart; the first output module and the second output module generate the first clock signal group and the second clock signal group according to the fifth valid level and the sixth valid level, respectively.

[0020] Optionally, the control module further outputs a second pulse signal and a fourth pulse signal;

[0021] The first output module receives the first pulse signal and the second pulse signal, and outputs a first clock signal group to the display module according to the first pulse signal and the second pulse signal;

[0022] The second output module receives the third pulse signal and the fourth pulse signal, and outputs a second clock signal group to the display module according to the third pulse signal and the fourth pulse signal.

[0023] Optionally, the control module further outputs a fifth pulse signal and a sixth pulse signal;

[0024] The driving circuit further includes a third output module;

[0025] The third output module receives the fifth pulse signal and the sixth pulse signal, and outputs a third clock signal group to the display module according to the fifth pulse signal and the sixth pulse signal.

[0026] Optionally, the row of gate lines controls a row of pixels, and the pixels in the same row are the same type of pixels; the first clock signal group corresponds to the first pulse signal and includes the 3n-2th clock signal, the second clock signal group corresponds to the third pulse signal and includes the 3n-1th clock signal, and the third clock signal group corresponds to the fifth pulse signal and includes the 3nth clock signal, n=1, 2, 3...

[0027] Optionally, in the normal driving state, the first pulse signal includes multiple first effective levels with equal phase differences; the third pulse signal includes multiple second effective levels with equal phase differences; the fifth pulse signal includes multiple seventh effective levels with equal phase differences; the phases of the first effective level, the second effective level and the seventh effective level are delayed successively; the nth first effective level is used to generate the 3n-2th clock signal; the nth second effective level is used to generate the 3n-1th clock signal; the nth seventh effective level is used to generate the 3nth clock signal, n=1, 2, 3...

[0028] Optionally, when two rows of pixels are in synchronous driving state, the first pulse signal includes multiple third valid levels with equal phase differences; the third pulse signal includes multiple fourth valid levels with equal phase differences; the fifth pulse signal includes multiple eighth valid levels with equal phase differences; the phases of the third valid level, the fourth valid level and the eighth valid level are delayed successively; the 2n-1th third valid level is used to generate the 6n-5th and 6n-2th clock signals; the 2n-1th fourth valid level is used to generate the 6n-4th and 6n-1th clock signals; the 2n-1th eighth valid level is used to generate the 6n-3th and 6nth clock signals, n=1, 2, 3...

[0029] The present application also discloses a display panel, which includes the above-mentioned driving circuit.

[0030] The present application also discloses a display device, which includes the above-mentioned display panel.

[0031] Compared with the related art, the present application outputs pulse signals with independent phases through the control module, and the pulse signals output clock signals with independent phases through the output module, thereby meeting the output of multiple gate control signals at multiple clock signal terminals.

[0032] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the specification and, together with the description, serve to explain the principles of the specification.

[0034] FIG1 is a schematic diagram of the connection structure of a driving circuit in one embodiment of the present application.

[0035] FIG2 is a schematic diagram of the connection structure of the display module in one embodiment of the present application.

[0036] FIG3 is a timing diagram of a driving circuit in an embodiment of the present application.

[0037] FIG4 is a timing diagram of a driving circuit in an embodiment of the present application.

[0038] FIG5 is a timing diagram of a driving circuit in an embodiment of the present application.

[0039] FIG6 is a schematic diagram of the connection structure of the display module in one embodiment of the present application.

[0040] FIG. 7 is a timing diagram of a driving circuit in an embodiment of the present application.

[0041] FIG8 is a timing diagram of a driving circuit in an embodiment of the present application.

[0042] FIG9 is a timing diagram of a driving circuit in an embodiment of the present application.

[0043] FIG10 is a schematic diagram of the connection structure of a driving circuit in one embodiment of the present application.

[0044] FIG11 is a schematic diagram of the connection structure of the display module in one embodiment of the present application.

[0045] FIG12 is a timing diagram of a driving circuit in an embodiment of the present application.

[0046] FIG13 is a timing diagram of a driving circuit in an embodiment of the present application. DETAILED DESCRIPTION

[0047] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this specification. Rather, they are merely examples of apparatus and methods consistent with certain aspects of this specification, as detailed in the appended claims.

[0048] The terminology used in this application is for the purpose of describing specific embodiments only and is not intended to limit the present disclosure. Unless otherwise defined, technical or scientific terms used in this specification should have the same ordinary meaning as those having ordinary skill in the art to which this application belongs. The terms "first," "second," and similar terms used in this specification and claims do not denote any order, quantity, or importance, but are simply used to distinguish different components. Similarly, terms such as "a" or "an" do not denote a limitation of quantity, but rather indicate the presence of one. "Multiple" or "several" means two or more. Unless otherwise indicated, terms such as "front," "rear," "lower," and / or "upper" are used for convenience only and are not intended to limit the scope of the present disclosure to a specific location or spatial orientation. Terms such as "include" or "comprising" mean that the elements or objects listed before "include" or "comprising" include the elements or objects listed after "include" or "comprising" and their equivalents, and do not exclude other elements or objects. Terms such as "connected" or "connected" are not limited to physical or mechanical connections and can include electrical connections, whether direct or indirect.

[0049] The terms used in this specification are for the purpose of describing specific embodiments only and are not intended to limit the present disclosure. As used in this specification and the appended claims, the singular forms "a," "an," "the," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0050] As shown in Figures 1 and 2, the present application provides a driving circuit, which includes:

[0051] A control module 100 , wherein the control module 100 outputs at least a first pulse signal CPV1 and a third pulse signal CPV3 ;

[0052] A first output module 200 , wherein the first output module 200 receives the first pulse signal CPV1 and outputs a first clock signal group 210 to the display module 500 according to the first pulse signal CPV1 ;

[0053] a second output module 300, wherein the second output module 300 receives the third pulse signal CPV3 and outputs a second clock signal group 310 to the display module 500 according to the third pulse signal CPV3;

[0054] The phases of the first pulse signal CPV1 and the third pulse signal CPV3 are independent of each other;

[0055] The display module 500 includes pixels arranged in an array and a plurality of gate lines extending along a row direction, and at least one row of the gate lines controls a row of the pixels.

[0056] The present application further provides a display panel, which includes the above-mentioned driving circuit.

[0057] The present application also provides a display device, which includes the above-mentioned display panel.

[0058] The present application outputs pulse signals with independent phases through a control module, and the pulse signals output clock signals with independent phases through an output module, thereby satisfying the output of multiple gate control signals at multiple clock signal terminals.

[0059] The following is a detailed description of each embodiment of the present application that is consistent with the above-mentioned creative concept.

[0060] As shown in FIG1 and FIG2 , the present application provides a driving circuit, which includes a control module 100 , a first output module 200 , a second output module 300 , and a display module 500 .

[0061] The control module 100 includes a System on Chip (SOC). The control module 100 outputs at least a first pulse signal CPV1 and a third pulse signal CPV3. The first pulse signal CPV1 and the third pulse signal CPV3 can be output by a single SOC or by multiple SOCs. The phases of the first pulse signal CPV1 and the third pulse signal CPV3 are independent of each other.

[0062] The first output module 200 includes an L / S IC (Level Shifter IC). The first output module 200 receives a first pulse signal CPV1, and the first output module 200 outputs a first clock signal group 210 to the display module 500 based on the first pulse signal CPV1. Optionally, the first output module 200 can receive multiple pulse signals. For example, the control module 100 also outputs a second pulse signal CPV2. The first output module 200 receives the first pulse signal CPV1 and the second pulse signal CPV2, and the first output module 200 outputs the first clock signal group 210 to the display module 500 based on the first pulse signal CPV1 and the second pulse signal CPV2. The first pulse signal CPV1 and the second pulse signal CPV2 are responsible for turning on and off, respectively, so that more valid clock signals can be output. The first clock signal group 210 can also include multiple clock signals. For example, the first clock signal group 210 can include 6, 8, 9, 10 or more clock signals.

[0063] The second output module 300 includes an L / S IC (Level Shifter IC). The second output module 300 receives the third pulse signal CPV3, and the second output module 300 outputs the second clock signal group 310 to the display module 500 based on the third pulse signal CPV3. Optionally, the second output module 300 can receive multiple pulse signals. For example, the control module 100 also outputs a fourth pulse signal CPV4. The second output module 300 receives the third pulse signal CPV3 and the fourth pulse signal CPV4, and the second output module 300 outputs the second clock signal group 310 to the display module 500 based on the third pulse signal CPV3 and the fourth pulse signal CPV4. The third pulse signal CPV3 and the fourth pulse signal CPV4 are responsible for turning on and off, respectively, so that more valid clock signals can be output. The second clock signal group 310 can also include multiple clock signals. For example, the second clock signal group 310 can include 6, 8, 9, 10 or more clock signals.

[0064] The phases of the clock signals in the first clock signal group 210 and the second clock signal group 310 are independent of each other. That is, the phases of the clock signals in the first clock signal group 210 are independently adjustable, and the phases of the clock signals in the second clock signal group 310 are also independently adjustable, without affecting each other. The phases of the clock signals in the first clock signal group 210 can be the same as, or can be ahead of, or behind the phases of the clock signals in the second clock signal group 310.

[0065] As shown in Figures 2, 6 and 11, the display module 500 includes pixels arranged in an array, several gate lines G1, G2, G3 extending in the row direction ..., several data lines D1, D2, D3 extending in the column direction ... and several GOA (Gate Driver on Array, array substrate row drive) units GOA1, GOA2, GOA3 arranged at the edge of the display module 500 .... The output end of each COA unit is connected to a gate line, for example, the output end of GOA1 is connected to G1, the output end of GOA2 is connected to G21, and the output end of GOA3 is connected to G3 .... Pixels include R (red), G (green), and B (blue) pixels. R, G, and B pixels are each arranged in an array on the display module 500. For example, in a row of pixels, from the side of the gate line close to the GOA unit to the side of the gate line away from the GOA unit, a row of pixels is arranged in a cycle according to the order of B pixels, G pixels, and R pixels. In a column of pixels, the pixels in the same column are all the same pixels. Of course, the pixel array can be configured as required, and the positions and numbers of R, G, and B pixels in the pixel array can be changed as required, as long as they can emit light that meets the display requirements. At least one row of gate lines jointly controls a row of pixels, for example, G1 controls the first row of pixels, G2 controls the second row of pixels..., or G1 and G2 can jointly control the first row of pixels, G3 and G4 jointly control the second row of pixels..., or G1, G2, and G3 jointly control the first row of pixels, G4, G5, and G6 jointly control the second row of pixels, and so on.

[0066] As shown in Figure 2, in an optional embodiment, the 2a-1 and 2a row gate lines jointly control the pixels in row a, where a = 1, 2, 3, .... The 2b-1 and 2b+1 row gate lines control the same column of pixels; the 2b and 2b+2 row gate lines control the same column of pixels. b = 1, 2, 3, .... That is, G1 and G2 jointly control the pixels in the first row, G3 and G4 jointly control the pixels in the second row, G5 and G6 jointly control the pixels in the third row, .... G1, G3, G5, ... control the pixels in the same column, and G2, G4, G6, ... control the pixels in the same column. For example, G1, G3, G5, ... jointly control the pixels in the first, third, fifth, ... columns, and G2, G4, G6, ... jointly control the pixels in the second, fourth, sixth, ... columns. One column of data lines controls two columns of pixels, for example, D1 controls the pixels in the first and second columns, D2 controls the pixels in the third and fourth columns, and D3 controls the pixels in the fifth and sixth columns, .... Among them, the pixels in the first column can be B pixels, the pixels in the second column can be G pixels, and the pixels in the third column can be R pixels, and the pixels in the subsequent columns are circulated in sequence. In this way, the pixels in the odd columns form a cycle of B pixels, R pixels, and G pixels, and the pixels in the even columns form a cycle of G pixels, B pixels, and R pixels. Of course, the position and number of R, G, and B pixels in the pixel array can be changed according to demand, as long as they can emit light that meets the display requirements. That is, under the condition that two rows of gate lines jointly control a row of pixels, any architecture that can emit light that meets the display requirements is acceptable.

[0067] The first clock signal group 210 includes the 4n-3 and 4n-2 clock signals corresponding to the first pulse signal CPV1. The second clock signal group 310 includes the 4n-1 and 4n clock signals corresponding to the third pulse signal CPV3, where n=1, 2, 3, ... . The clock signals in the first clock signal group 210 are sequentially delayed in phase from smallest to largest according to their sequence number. The clock signals in the second clock signal group 310 are sequentially delayed in phase from smallest to largest according to their sequence number. That is, the first output module 200 receives the first pulse signal CPV1 and outputs the first clock signal CLK1, the second clock signal CLK2, the fifth clock signal CLK5, the sixth clock signal CLK6, ... the 4n-3 and 4n-2 clock signals, where n=1, 2, 3, ...; the second output module 300 receives the third pulse signal CPV3 and outputs the third clock signal CLK3, the fourth clock signal CLK4, the seventh clock signal CLK7, the eighth clock signal CLK8, ... the 4n-1 and 4n clock signals, where n=1, 2, 3, .... The phase of the nth clock signal corresponds to the phase of the output signal of GOAn, n=1, 2, 3, . . . .

[0068] As shown in FIG3 , when the circuit is in a normal driving state, the first pulse signal CPV1 includes multiple first active level groups 110 with equal phase differences, each of which includes two first active levels 111. The third pulse signal CPV3 includes multiple second active level groups 120 with equal phase differences, each of which includes two second active levels 121. The first active level groups 110 and the second active level groups 120 are spaced apart. The first output module 200 and the second output module 300 generate the first clock signal group 210 and the second clock signal group 310 based on the first active levels 111 and the second active levels 121, respectively. For example, the first pulse signal CPV1 includes multiple first active level groups 110 with a phase difference of 4H. Each first active level group 110 includes two first active levels 111 with a phase difference of 1H. The third pulse signal CPV3 includes multiple second active level groups 120 with a phase difference of 4H. Each second active level group 120 includes two second active levels 121 with a phase difference of 1H. The phase of the second active level group 120 is delayed by 2H compared to the phase of the first active level group 110. The first active level 111 is used to generate the first clock signal group 210, and the second active level 121 is used to generate the second clock signal group 310. Specifically, the nth first active level group 110 is used to generate the 4n-3th and 4n-2th clock signals. The first active level 111 with a forward phase in the nth first active level group 110 is used to generate the 4n-3th clock signal, and the first active level 111 with a backward phase is used to generate the 4n-2th clock signal, where n = 1, 2, 3, .... The nth second active level group 120 is used to generate the 4n-1th and 4nth clock signals. The second active level 121 with a forward phase in the nth second active level group 120 is used to generate the 4n-1th clock signal, and the second active level 121 with a backward phase is used to generate the 4nth clock signal, where n = 1, 2, 3, .... In this way, the output module can output several clock signals with equal phase differences, wherein the phase of the nth clock signal CLKn leads the phase of the n+1th clock signal CLKn+1 by 1H. In this way, the signal output in the normal driving state of the circuit is realized. Optionally, the control module 100 also outputs a second pulse signal CPV2 and a fourth pulse signal CPV4, the phase of the second pulse signal CPV2 is the same as the phase of the first pulse signal CPV1, and the phase of the fourth pulse signal CPV4 is the same as the phase of the third pulse signal CPV3. The first output module 200 outputs the first clock signal group 210 to the display module 500 based on the first pulse signal CPV1 and the second pulse signal CPV2. The second output module 300 outputs the second clock signal group 310 to the display module 500 based on the third pulse signal CPV3 and the fourth pulse signal CPV4.

[0069] As shown in FIG4 , when the circuit is in a state of synchronously driving two rows of pixels, the first pulse signal CPV1 includes a plurality of third active levels 130 with equal phase differences. The third pulse signal CPV3 includes a plurality of fourth active levels 140 with equal phase differences. The plurality of third active levels 130 are phase-synchronized with the plurality of fourth active levels 140. The first output module 200 and the second output module 300 generate a first clock signal group 210 and a second clock signal group 310 based on the third active levels 130 and the fourth active levels 140, respectively. For example, the phase difference between adjacent third active levels 130 in the plurality of third active levels 130 is 2H, and the phase difference between adjacent fourth active levels 140 in the plurality of fourth active levels 140 is 2H. The phases of the plurality of third active levels 130 and the plurality of fourth active levels 140 are synchronized. Among them, multiple third effective levels 130 are used to generate CLK1, CLK2, CLK5, CLK6, CLK9, CLK10... in their phase order; multiple fourth effective levels 140 are used to generate CLK3, CLK4, CLK7, CLK8, CLK11, CLK12... in their phase order. In this way, the output module can output the clock signals required for synchronous driving of two rows of pixels, that is, CLK1 = CLK3 → CLK2 = CLK4 → CLK5 = CLK7 → CLK6 = CLK8 → CLK9 = CLK11 → CLK10 = CLK12..., and the clock signals at this time sequence can meet the dual gate condition for synchronous driving of two rows of pixels. Optionally, the control module 100 also outputs a second pulse signal CPV2 and a fourth pulse signal CPV4. The phase of the second pulse signal CPV2 is the same as the phase of the first pulse signal CPV1, and the phase of the fourth pulse signal CPV4 is the same as the phase of the third pulse signal CPV3. The first output module 200 outputs the first clock signal group 210 to the display module 500 according to the first pulse signal CPV1 and the second pulse signal CPV2. The second output module 300 outputs the second clock signal group 310 to the display module 500 according to the third pulse signal CPV3 and the fourth pulse signal CPV4.

[0070] As shown in FIG5 , when the circuit is in a two-row pixel staggered synchronous driving state, the first pulse signal CPV1 includes a plurality of fifth effective levels 150 with equal phase differences. The third pulse signal CPV includes a plurality of sixth effective levels 160 with equal phase differences. The plurality of fifth effective levels 150 and the plurality of sixth effective levels 160 are spaced apart. The first output module 200 and the second output module 300 generate a first clock signal group 210 and a second clock signal group 310 based on the fifth effective levels 150 and the sixth effective levels 160, respectively. For example, the phase difference between adjacent fifth effective levels 150 in the plurality of fifth effective levels 150 is 2H, and the phase difference between adjacent sixth effective levels 160 in the plurality of sixth effective levels 160 is 2H. The overall phase of the plurality of fifth effective levels 150 is 1H ahead of the phase of the plurality of sixth effective levels 160. Among them, multiple fifth effective levels 150 are used to generate CLK1, CLK2, CLK5, CLK6, CLK9, CLK10... respectively according to their phase order; multiple sixth effective levels 160 are used to generate CLK3, CLK4, CLK7, CLK8, CLK11, CLK12... respectively according to their phase order. In this way, the output module can output the clock signals required for the staggered synchronous driving of two rows of pixels, namely CLK1→CLK3→CLK2→CLK4→CLK5→CLK7→CLK6→CLK8→CLK9→CLK11→CLK10→CLK12... The clock signals at this time sequence can meet the staggered synchronous driving state of two rows of pixels under the Dual Gate condition. Optionally, the control module 100 also outputs a second pulse signal CPV2 and a fourth pulse signal CPV4. The phase of the second pulse signal CPV2 is the same as the phase of the first pulse signal CPV1, and the phase of the fourth pulse signal CPV4 is the same as the phase of the third pulse signal CPV3. The first output module 200 outputs the first clock signal group 210 to the display module 500 according to the first pulse signal CPV1 and the second pulse signal CPV2. The second output module 300 outputs the second clock signal group 310 to the display module 500 according to the third pulse signal CPV3 and the fourth pulse signal CPV4.

[0071] As shown in Figure 6, in an optional embodiment, the 3a-2, 3a-1 and 3a row gate lines jointly control the pixels in the a row, a=1, 2, 3... The 3b-2 row gate line and the 3b+1 row gate line control the pixels in the same column. The 3b-1 row gate line and the 3b+2 row gate line control the pixels in the same column. The 3b row gate line and the 3b+3 row gate line control the pixels in the same column. b=1, 2, 3... That is, G1, G2, and G3 jointly control the pixels in the first row, G4, G5, and G6 jointly control the pixels in the second row, and G7, G8, and G9 jointly control the pixels in the third row... G1, G4, and G7... control the pixels in the same column, G2, G5, and G8... control the pixels in the same column, and G3, G6, and G9... control the pixels in the same column. For example, G1, G4, G7, ... collectively control the pixels in the first, fourth, seventh, ... columns; G2, G5, G8, ... collectively control the pixels in the second, fifth, eighth, ... columns; and G3, G6, G9, ... collectively control the pixels in the third, sixth, ninth, ... columns. One data line controls three columns of pixels. For example, D1 controls the pixels in the first, second, and third columns; D2 controls the pixels in the fourth, fifth, and sixth columns; and D3 controls the pixels in the seventh, eighth, and ninth columns. The pixels in the first column can be B pixels, the pixels in the second column can be G pixels, the pixels in the third column can be R pixels, the pixels in the fourth column can be G pixels, the pixels in the fifth column can be R pixels, the pixels in the sixth column can be B pixels, the pixels in the seventh column can be R pixels, the pixels in the eighth column can be B pixels, and the pixels in the ninth column can be G pixels. Thus, the pixels in the first, fourth, seventh, and so on columns form a cycle of B pixels, G pixels, and R pixels; the pixels in the second, fifth, eighth, and so on columns form a cycle of G pixels, R pixels, and B pixels; and the pixels in the third, sixth, ninth, and so on columns form a cycle of R pixels, B pixels, and G pixels. Of course, the position and number of R, G, and B pixels in the pixel array can be changed as needed, as long as they can emit light that meets the display requirements. In other words, under the condition that three rows of gate lines jointly control one row of pixels, any architecture that can emit light that meets the display requirements is acceptable.

[0072] The first clock signal group 210 includes the 6n-5th, 6n-4th, and 6n-3th clock signals corresponding to the first pulse signal CPV1. The second clock signal group 310 includes the 6n-2th, 6n-1st, and 6nth clock signals corresponding to the third pulse signal CPV3, where n = 1, 2, 3, ... The clock signals in the first clock signal group 210 are sequentially delayed in phase from smallest to largest sequence number. The clock signals in the second clock signal group 310 are sequentially delayed in phase from smallest to largest sequence number. That is, the first output module 200 receives the first pulse signal CPV1 and outputs the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, the seventh clock signal CLK7, the eighth clock signal CLK8, the ninth clock signal CLK9, ... the 6n-5th, 6n-4th, and 6n-3th clock signals, where n = 1, 2, 3, ...; the second output module 300 receives the third pulse signal CPV3 and outputs the fourth clock signal CLK4, the fifth clock signal CLK5, the sixth clock signal CLK6, the tenth clock signal CLK10, the eleventh clock signal CLK11, the twelfth clock signal CLK12, ... the 6n-2th, 6n-1th, and 6nth clock signals, where n = 1, 2, 3, .... The phase of the nth clock signal corresponds to the phase of the output signal of the GOAn, where n = 1, 2, 3, ....

[0073] As shown in FIG7 , when the circuit is in a normal driving state, the first pulse signal CPV1 includes multiple first active level groups 110 with equal phase differences, each of which includes three first active levels 111. The third pulse signal CPV3 includes multiple second active level groups 120 with equal phase differences, each of which includes three second active levels 121. The first active level groups 110 and the second active level groups 120 are spaced apart. The first output module 200 and the second output module 300 generate the first clock signal group 210 and the second clock signal group 310 based on the first active levels 111 and the second active levels 121, respectively. For example, the first pulse signal CPV1 includes multiple first active level groups 110 with a phase difference of 6H. Each first active level group 110 includes three first active levels 111 with a phase difference of 1H. The third pulse signal CPV3 includes multiple second active level groups 120 with a phase difference of 6H, each of which includes two second active levels 121 with a phase difference of 1H. The phase of the second active level group 120 is delayed by 3H compared to the phase of the first active level group 110. The first active level 111 is used to generate the first clock signal group 210, and the second active level 121 is used to generate the second clock signal group 310. Specifically, the nth first active level group 110 is used to generate the 6n-5th, 6n-4th, and 6n-3th clock signals. The first active level 111 with the earlier phase in the nth first active level group 110 is used to generate the 6n-5th clock signal, the second first active level 111 with the later phase is used to generate the 6n-4th clock signal, and the last first active level 111 with the later phase is used to generate the 6n-3th clock signal, where n = 1, 2, 3, ... The nth second effective level group 120 is used to generate the 6n-2, 6n-1, and 6nth clock signals. The second effective level 121 with the earlier phase in the nth second effective level group 120 is used to generate the 6n-2th clock signal, the second effective level 121 with the second second phase is used to generate the 6n-1th clock signal, and the second effective level 121 with the last phase is used to generate the 6nth clock signal, where n = 1, 2, 3, etc. In this way, the output module can output several clock signals with equal phase differences, where the phase of the nth clock signal CLKn leads the phase of the n+1th clock signal CLKn+1 by 1H. In this way, the signal output in the normal driving state of the circuit is achieved. Optionally, the control module 100 also outputs a second pulse signal CPV2 and a fourth pulse signal CPV4. The phase of the second pulse signal CPV2 is the same as the phase of the first pulse signal CPV1, and the phase of the fourth pulse signal CPV4 is the same as the phase of the third pulse signal CPV3. The first output module 200 outputs the first clock signal group 210 to the display module 500 according to the first pulse signal CPV1 and the second pulse signal CPV2 .The second output module 300 outputs the second clock signal group 310 to the display module 500 according to the third pulse signal CPV3 and the fourth pulse signal CPV4 .

[0074] As shown in FIG8 , when the circuit is in a state of synchronously driving two rows of pixels, the first pulse signal CPV1 includes a plurality of third active levels 130 with equal phase differences. The third pulse signal CPV3 includes a plurality of fourth active levels 140 with equal phase differences. The plurality of third active levels 130 are phase-synchronized with the plurality of fourth active levels 140. The first output module 200 and the second output module 300 generate a first clock signal group 210 and a second clock signal group 310 based on the third active levels 130 and the fourth active levels 140, respectively. For example, the phase difference between adjacent third active levels 130 in the plurality of third active levels 130 is 2H, and the phase difference between adjacent fourth active levels 140 in the plurality of fourth active levels 140 is 2H. The phases of the plurality of third active levels 130 and the plurality of fourth active levels 140 are synchronized. Among them, multiple third effective levels 130 are used to generate CLK1, CLK2, CLK3, CLK7, CLK8, CLK9, etc. in their phase order; multiple fourth effective levels 140 are used to generate CLK4, CLK5, CLK6, CLK10, CLK11, CLK12, etc. in their phase order. In this way, the output module can output the clock signals required for synchronous driving of two rows of pixels, that is, CLK1 = CLK4 → CLK2 = CLK5 → CLK3 = CLK6 → CLK7 = CLK10 → CLK8 = CLK11 → CLK9 = CLK12, etc. This clock signal sequence can meet the requirements of the synchronous driving state of two rows of pixels under the triple gate condition. Optionally, the control module 100 also outputs a second pulse signal CPV2 and a fourth pulse signal CPV4. The phase of the second pulse signal CPV2 is the same as the phase of the first pulse signal CPV1, and the phase of the fourth pulse signal CPV4 is the same as the phase of the third pulse signal CPV3. The first output module 200 outputs the first clock signal group 210 to the display module 500 according to the first pulse signal CPV1 and the second pulse signal CPV2. The second output module 300 outputs the second clock signal group 310 to the display module 500 according to the third pulse signal CPV3 and the fourth pulse signal CPV4.

[0075] As shown in FIG9 , when the circuit is in a two-row pixel staggered synchronous driving state, the first pulse signal CPV1 includes a plurality of fifth effective levels 150 with equal phase differences. The third pulse signal CPV includes a plurality of sixth effective levels 160 with equal phase differences. The plurality of fifth effective levels 150 and the plurality of sixth effective levels 160 are spaced apart. The first output module 200 and the second output module 300 generate a first clock signal group 210 and a second clock signal group 310 based on the fifth effective levels 150 and the sixth effective levels 160, respectively. For example, the phase difference between adjacent fifth effective levels 150 in the plurality of fifth effective levels 150 is 2H, and the phase difference between adjacent sixth effective levels 160 in the plurality of sixth effective levels 160 is 2H. The overall phase of the plurality of fifth effective levels 150 is 1H ahead of the phase of the plurality of sixth effective levels 160. Among them, multiple fifth effective levels 150 are used to generate CLK1, CLK2, CLK3, CLK7, CLK8, CLK9, etc. in their phase order; multiple sixth effective levels 160 are used to generate CLK4, CLK5, CLK6, CLK10, CLK11, CLK12, etc. in their phase order. In this way, the output module can output the clock signals required for staggered synchronous driving of two rows of pixels, namely CLK1→CLK4→CLK2→CLK5→CLK3→CLK6→CLK7→CLK10→CLK8→CLK11→CLK9→CLK12, etc. The clock signals at this time sequence can meet the staggered synchronous driving state of two rows of pixels under triple gate conditions. Optionally, the control module 100 also outputs a second pulse signal CPV2 and a fourth pulse signal CPV4. The phase of the second pulse signal CPV2 is the same as the phase of the first pulse signal CPV1, and the phase of the fourth pulse signal CPV4 is the same as the phase of the third pulse signal CPV3. The first output module 200 outputs the first clock signal group 210 to the display module 500 according to the first pulse signal CPV1 and the second pulse signal CPV2. The second output module 300 outputs the second clock signal group 310 to the display module 500 according to the third pulse signal CPV3 and the fourth pulse signal CPV4.

[0076] As shown in Figures 10 and 11, in an optional embodiment, the control module 100 further outputs a fifth pulse signal CPV5. The driving circuit further includes a third output module 400. The third output module 400 includes an L / S IC (Level Shifter IC). The third output module 400 receives the fifth pulse signal CPV5 and outputs a third clock signal group 410 to the display module 500 based on the fifth pulse signal CPV5. Optionally, the third output module 400 can receive multiple pulse signals. For example, the control module 100 further outputs a sixth pulse signal CPV6. The third output module 400 receives the fifth pulse signal CPV5 and the sixth pulse signal CPV6 and outputs the third clock signal group 410 to the display module 500 based on the fifth pulse signal CPV5 and the sixth pulse signal CPV6. The fifth pulse signal CPV5 and the sixth pulse signal CPV6 are responsible for turning on and off, respectively, so that more valid clock signals can be output. The third clock signal group 410 may also include multiple clock signals. For example, the third clock signal group 410 may include 6, 8, 9, 10 or more clock signals.

[0077] The a-th row gate line controls the a-th row of pixels, where a=1, 2, 3, ... That is, G1 controls the pixels in the first row, G2 controls the pixels in the second row, G3 controls the pixels in the third row, ... Pixels in the same row are of the same type; for example, all pixels in the first row are R pixels, all pixels in the second row are G pixels, and all pixels in the third row are B pixels. The first clock signal group 210 includes the 3n-2th clock signal corresponding to the first pulse signal CPV1, the second clock signal group 310 includes the 3n-1th clock signal corresponding to the third pulse signal CPV3, and the third clock signal group 410 includes the 3nth clock signal corresponding to the fifth pulse signal CPV5, where n=1, 2, 3, ... The clock signals in the first clock signal group 210 are phase-delayed in ascending order according to their serial numbers. The clock signals in the second clock signal group 310 are phase-delayed in ascending order according to their serial numbers. The clock signals in the third clock signal group 410 are phase-delayed in ascending order according to their serial numbers. That is, the first output module 200 receives the first pulse signal CPV1 and outputs the first clock signal CLK1, the fourth clock signal CLK4, the seventh clock signal CLK7, the tenth clock signal CLK10, ... the 3n-2 clock signal, where n = 1, 2, 3, ...; the second output module 300 receives the third pulse signal CPV3 and outputs the second clock signal CLK2, the fifth clock signal CLK5, the eighth clock signal CLK8, ... the 3n-1 clock signal, where n = 1, 2, 3, .... The third clock signal group 410 receives the fifth pulse signal CPV5 and outputs the third clock signal CLK3, the sixth clock signal CLK6, the ninth clock signal CLK9, ... the 3n-1 clock signal, where n = 1, 2, 3, .... The phase of the nth clock signal corresponds to the phase of the output signal of GOAn, where n = 1, 2, 3, ....

[0078] As shown in FIG12 , when the circuit is in a normal driving state, the first pulse signal CPV1 includes multiple first active levels 111 with equal phase differences, for example, a phase difference of 4H. The third pulse signal CPV3 includes multiple second active levels 121 with equal phase differences, for example, a phase difference of 4H. The fifth pulse signal CPV5 includes multiple seventh active levels 170 with equal phase differences, for example, a phase difference of 4H. The first output module 200 generates a first clock signal group 210 based on the first active level 111. The second output module 300 generates a second clock signal group 310 based on the second active level 121. The third output module 400 generates a third clock signal group 410 based on the seventh active level 170. The phases of the first active level 111, the second active level 121, and the seventh active level 170 are sequentially delayed. For example, the second active level 121 lags behind the first active level 111 by 1H, and the seventh active level 170 lags behind the second active level 121 by 1H. The nth first active level 111 is used to generate the 3n-2th clock signal; the nth second active level 121 is used to generate the 3n-1th clock signal; and the nth seventh active level 170 is used to generate the 3nth clock signal, where n = 1, 2, 3, and so on. In this way, the output module can output multiple clock signals with equal phase differences, where the phase of the nth clock signal CLKn leads the phase of the n+1th clock signal CLKn+1 by 1 hour. This achieves signal output in the circuit's normal driving state.

[0079] As shown in FIG13 , when the circuit is in a state of synchronously driving two rows of pixels, the first pulse signal CPV1 includes multiple third active levels 130 with equal phase differences, for example, a phase difference of 4H. The third pulse signal CPV3 includes multiple fourth active levels 140 with equal phase differences, for example, a phase difference of 4H. The fifth pulse signal CPV5 includes multiple eighth active levels 180 with equal phase differences, for example, a phase difference of 4H. The phases of the third active level 130, the fourth active level 140, and the eighth active level 180 are sequentially delayed. For example, the fourth active level 140 lags behind the third active level 130 by 2H, and the eighth active level 180 lags behind the fourth active level 140 by 2H. The 2n-1th third active level is used to generate the 6n-5th and 6n-2th clock signals. The 2n-1th fourth active level is used to generate the 6n-4th and 6n-1th clock signals. The 2n-1th eighth active level is used to generate the 6n-3th and 6nth clock signals, where n=1, 2, 3, etc. In this way, the output module can output the clock signal required for synchronous driving of two rows of pixels, that is, CLK1 = CLK4 → CLK2 = CLK5 → CLK3 = CLK6 → CLK7 = CLK10 → CLK8 = CLK11 → CLK9 = CLK12..., and the clock signal at this time sequence can meet the synchronous driving state of two rows of pixels under the triple gate condition.

[0080] Of course, the present application can also adopt more phase-independent pulse signals and more output modules to output more phase-independent clock signals to meet the output of multiple gate control signals at multiple clock signal terminals.

[0081] Other embodiments of the present invention will readily occur to those skilled in the art upon consideration of the present invention and practice of the invention claimed herein. This specification is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of this specification and include common knowledge or customary techniques in the art not claimed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present invention being indicated by the following claims.

[0082] It should be understood that the present description is not limited to the exact structure that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present description is limited only by the appended claims.

[0083] The above description is only a preferred embodiment of this specification and is not intended to limit this specification. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this specification should be included in the scope of protection of this specification.

Claims

1. A driving circuit, characterized in that, Including: A control module that outputs at least a first pulse signal and a third pulse signal; A first output module that receives the first pulse signal, and the first output module outputs a first clock signal group to a display module according to the first pulse signal; A second output module that receives the third pulse signal, and the second output module outputs a second clock signal group to the display module according to the third pulse signal; The phases of the first pulse signal and the third pulse signal are independent of each other; The display module includes pixels arranged in an array and a plurality of gate lines extending in the row direction, and at least one row of the gate lines controls one row of the pixels.

2. The drive circuit according to claim 1, wherein The (2a - 1)-th and 2a-th rows of the gate lines jointly control the a-th row of the pixels, where a = 1, 2, 3...; the (2b - 1)-th row of the gate lines and the (2b + 1)-th row of the gate lines control the pixels in the same column; the 2b-th row of the gate lines and the (2b + 2)-th row of the gate lines control the pixels in the same column; b = 1, 2, 3...

3. The drive circuit according to claim 2, wherein The first clock signal group corresponding to the first pulse signal includes the (4n - 3)-th and (4n - 2)-th clock signals, and the second clock signal group corresponding to the third pulse signal includes the (4n - 1)-th and 4n-th clock signals, where n = 1, 2, 3...; the clock signals of the first clock signal group are sequentially lagged in phase in ascending order of the sequence number; the clock signals of the second clock signal group are sequentially lagged in phase in ascending order of the sequence number.

4. The drive circuit according to claim 1, wherein The (3a - 2)-th, (3a - 1)-th and 3a-th rows of the gate lines jointly control the a-th row of the pixels, where a = 1, 2, 3...; the (3b - 2)-th row of the gate lines and the (3b + 1)-th row of the gate lines control the pixels in the same column; the (3b - 1)-th row of the gate lines and the (3b + 2)-th row of the gate lines control the pixels in the same column; the 3b-th row of the gate lines and the (3b + 3)-th row of the gate lines control the pixels in the same column; b = 1, 2, 3...

5. The drive circuit according to claim 4, characterized in that, The first clock signal group corresponding to the first pulse signal includes the (6n - 5)-th, (6n - 4)-th and (6n - 3)-th clock signals, and the second clock signal group corresponding to the third pulse signal includes the (6n - 2)-th, (6n - 1)-th and 6n-th clock signals, where n = 1, 2, 3...; the clock signals of the first clock signal group are sequentially lagged in phase in ascending order of the sequence number; the clock signals of the second clock signal group are sequentially lagged in phase in ascending order of the sequence number.

6. The drive circuit according to claim 3, characterized in that, In the normal driving state, the first pulse signal includes a plurality of first effective level groups with equal phase differences, and each first effective level group includes two first effective levels; the third pulse signal includes a plurality of second effective level groups with equal phase differences, and each second effective level group includes two second effective levels; the first effective level groups and the second effective level groups are arranged at intervals; the n-th first effective level group is used to generate the (6n - 5)-th, (6n - 4)-th and (6n - 3)-th clock signals; the n-th second effective level group is used to generate the (6n - 2)-th, (6n - 1)-th and 6n-th clock signals; n = 1, 2, 3...

7. The drive circuit according to claim 5, characterized in that In the normal driving state, the first pulse signal includes a plurality of first active level groups with equal phase differences, and each of the first active level groups includes three first active levels; the third pulse signal includes a plurality of second active level groups with equal phase differences, and each of the second active level groups includes three second active levels; the first active level groups and the second active level groups are arranged at intervals; the nth first active level group is used to generate the (4n - 3)th and (4n - 2)th clock signals; the nth second active level group is used to generate the (4n - 1)th and 4nth clock signals; n = 1, 2, 3...

8. The drive circuit according to claim 3 or 5, characterized in that In the two-line pixel synchronous driving state, the first pulse signal includes a plurality of third active levels with equal phase differences; the third pulse signal includes a plurality of fourth active levels with equal phase differences; the plurality of third active levels and the plurality of fourth active levels are phase-synchronized; the first output module and the second output module respectively generate the first clock signal group and the second clock signal group according to the third active level and the fourth active level.

9. The drive circuit according to claim 3 or 5, characterized in that, In the two-line pixel misaligned synchronous driving state, the first pulse signal includes a plurality of fifth active levels with equal phase differences; the third pulse signal includes a plurality of sixth active levels with equal phase differences; the plurality of fifth active levels and the plurality of sixth active levels are arranged at intervals; the first output module and the second output module respectively generate the first clock signal group and the second clock signal group according to the fifth active level and the sixth active level.

10. The drive circuit according to claim 1, wherein The control module also outputs a second pulse signal and a fourth pulse signal; The first output module receives the first pulse signal and the second pulse signal, and the first output module outputs a first clock signal group to the display module according to the first pulse signal and the second pulse signal; The second output module receives the third pulse signal and the fourth pulse signal, and the second output module outputs a second clock signal group to the display module according to the third pulse signal and the fourth pulse signal.

11. The drive circuit according to claim 1, characterized in that, The control module also outputs a fifth pulse signal and a sixth pulse signal; The driving circuit further includes a third output module; The third output module receives the fifth pulse signal and the sixth pulse signal, and the third output module outputs a third clock signal group to the display module according to the fifth pulse signal and the sixth pulse signal.

12. The drive circuit according to claim 11, characterized in that One row of gate lines controls one row of the pixels, and the pixels in the same row are of the same type; the first clock signal group corresponding to the first pulse signal includes the (3n - 2)th clock signal, the second clock signal group corresponding to the third pulse signal includes the (3n - 1)th clock signal, and the third clock signal group corresponding to the fifth pulse signal includes the 3nth clock signal, n = 1, 2, 3...

13. The drive circuit according to claim 12, wherein In the normal driving state, the first pulse signal includes a plurality of first active levels with equal phase differences; the third pulse signal includes a plurality of second active levels with equal phase differences; the fifth pulse signal includes a plurality of seventh active levels with equal phase differences; the phases of the first active level, the second active level, and the seventh active level are delayed in sequence; the nth first active level is used to generate the (3n - 2)th clock signal; the nth second active level is used to generate the (3n - 1)th clock signal; the nth seventh active level is used to generate the 3nth clock signal, where n = 1, 2, 3,....

14. The drive circuit according to claim 12, wherein In the two-line pixel synchronous driving state, the first pulse signal includes a plurality of third active levels with equal phase differences; the third pulse signal includes a plurality of fourth active levels with equal phase differences; the fifth pulse signal includes a plurality of eighth active levels with equal phase differences; the phases of the third active level, the fourth active level, and the eighth active level are delayed in sequence; the (2n - 1)th third active level is used to generate the (6n - 5)th and (6n - 2)th clock signals; the (2n - 1)th fourth active level is used to generate the (6n - 4)th and (6n - 1)th clock signals; the (2n - 1)th eighth active level is used to generate the (6n - 3)th and 6nth clock signals, where n = 1, 2, 3,....

15. A display panel, characterized in that, The display panel includes the driving circuit according to any one of claims 1-14.

16. A display device, characterized in that, The display device includes the display panel according to claim 15.

Images