Display device

Abstract

Provided is a novel display device. A first element layer has a first transistor. In the first transistor, a semiconductor layer having a channel formation region has silicon. A second element layer has a second transistor. In the second transistor, a semiconductor layer having a channel formation region has metal oxide. The first element layer is provided with a display drive unit and a processor circuit unit. The display drive unit has a latch circuit having a function for holding image data, and an amplifier circuit having a function for outputting an analog voltage corresponding to the image data. The processor circuit unit has an analog-to-digital conversion circuit that converts the analog voltage into a digital signal, and an arithmetic circuit that acquires a correction value in response to the digital signal. The latch circuit has a function for correcting the analog voltage by adding the correction value to the image data.

Description

display device

[0001] One aspect of the present invention relates to a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof.

[0003] In recent years, there has been a demand for higher-definition display devices. Devices requiring high-definition display devices include, for example, devices for virtual reality (VR), augmented reality (AR), substitutional reality (SR), or mixed reality (MR), which have been actively developed in recent years. VR, AR, SR, and MR are also collectively referred to as xR.

[0004] Display devices used in xR devices are required to be compact as well as high-definition. Examples of display devices for xR include light-emitting devices equipped with light-emitting elements such as organic electroluminescence (EL) elements and light-emitting diodes (LEDs).

[0005] For display devices used in xR devices, configurations have been proposed that are high-definition, compact, and multifunctional. For example, Patent Documents 1 and 2 disclose configurations in which, in addition to configurations related to image display such as pixel circuits and display drive circuits, functional circuits having functions for performing arithmetic processing such as image processing are provided integrally with the pixel circuits, display drive circuits, etc.

[0006] International Publication No. 2022 / 118141 International Publication No. 2022 / 118151

[0007] Display devices used in xR devices have a small pixel size. Therefore, the image data voltage (analog voltage) applied to each pixel is very small. In the amplifier circuit of each column that supplies an analog voltage to a signal line connected to the pixel circuit, if the output voltage varies greatly depending on the input voltage, a difference in potential will occur even for analog voltages corresponding to the same gradation level. As a result, there is a risk of a significant deterioration in the display quality of the display unit controlled according to the analog voltage.

[0008] One way to correct variations in amplifier circuits is to provide capacitors and resistors to correct offset voltages. However, in display devices used in xR devices, providing capacitors and resistors in each column where an amplifier circuit is provided can result in a large layout area. Furthermore, with offset voltage correction, it is difficult to correct variations between amplifier circuits in each column, for example, between amplifier circuits in adjacent columns.

[0009] An object of one embodiment of the present invention is to provide a miniaturized display device.An object of one embodiment of the present invention is to provide a display device with excellent display quality.An object of one embodiment of the present invention is to provide a display device with excellent convenience.An object of one embodiment of the present invention is to provide a novel display device.

[0010] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0011] One embodiment of the present invention is a display device having a first element layer and a second element layer over the first element layer, in which the first element layer has a first transistor, and the first transistor has a semiconductor layer having a channel formation region containing silicon. The second element layer has a second transistor, and the semiconductor layer having the channel formation region contains metal oxide. The first element layer is provided with a display driver unit and a processor circuit unit. The display driver unit has a latch circuit having a function of holding image data and an amplifier circuit having a function of outputting an analog voltage according to the image data. The processor circuit unit has an analog-to-digital conversion circuit that converts the analog voltage into a digital signal and an arithmetic circuit that acquires a correction value according to the digital signal. The latch circuit has a function of correcting the analog voltage by adding the correction value to the image data.

[0012] One embodiment of the present invention is a display device including a first element layer and a second element layer over the first element layer, in which the first element layer includes a first transistor, and a semiconductor layer having a channel formation region containing silicon. The second element layer includes a second transistor, and the semiconductor layer having the channel formation region contains metal oxide. The first element layer is provided with a display driver unit and a processor circuit unit. The display driver unit has a latch circuit having a function of holding image data and an amplifier circuit having a function of outputting an analog voltage according to the image data. The amplifier circuit is provided for each of a plurality of signal lines, and the plurality of signal lines are each electrically connected to an analog-digital conversion circuit via a switch circuit. The processor circuit unit includes an analog-digital conversion circuit that converts an analog voltage into a digital signal and an arithmetic circuit that acquires a correction value according to the digital signal. The analog voltage is input to the analog-digital conversion circuit by sequentially turning on switch circuits electrically connected to the plurality of signal lines. The latch circuit has a function of correcting the analog voltage by adding the correction value to the image data.

[0013] In one embodiment of the present invention, the display device is preferably such that the display driver is provided in a region overlapping with the display.

[0014] In one embodiment of the present invention, the display device preferably has a display driver unit including a gate line driver circuit and a source line driver circuit, and the processor circuit unit has a function of switching the drive frequency of the gate line driver circuit and the drive frequency of the source line driver circuit.

[0015] In one embodiment of the present invention, the display device preferably has a display portion provided on the second element layer, the display portion having a pixel circuit that controls light emission of a light-emitting element, and the light-emitting element being provided on the second element layer.

[0016] Other aspects of the present invention will be described in the following embodiments and in the drawings.

[0017] According to one embodiment of the present invention, a miniaturized display device can be provided. Alternatively, according to one embodiment of the present invention, a display device with excellent display quality can be provided. Alternatively, according to one embodiment of the present invention, a display device with excellent convenience can be provided. Alternatively, according to one embodiment of the present invention, a novel display device can be provided.

[0018] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0019] FIG. 1A is a perspective view illustrating an example of the configuration of a display device, and FIG. 1B is a block diagram illustrating an example of the configuration of a display device. FIG. 2 is a schematic diagram illustrating an example of the configuration of a display device. FIG. 3 is a block diagram illustrating an example of the configuration of a display device. FIG. 4 is a circuit diagram illustrating an example of the configuration of a display device. FIG. 5 is a timing chart illustrating an example of the configuration of a display device. FIG. 6 is a flowchart illustrating an example of the configuration of a display device. FIG. 7 is a block diagram illustrating an example of the configuration of a display device. FIGS. 8A to 8C are circuit diagrams illustrating an example of the configuration of a display device. FIGS. 9A to 9C are schematic diagrams illustrating an example of the configuration of a display device. FIGS. 10A to 10D are circuit diagrams illustrating an example of the configuration of a display device. FIGS. 11A to 11D are circuit diagrams illustrating an example of the configuration of a display device. FIGS. 12A and 12B are circuit diagrams illustrating an example of the configuration of a display device. FIG. 13 is a block diagram illustrating an example of the configuration of a display device. FIG. 14 is a block diagram illustrating an example of the configuration of a display device. FIG. 15 is a schematic diagram illustrating an example of the configuration of a display device. FIGS. 16A and 16B are block diagrams illustrating an example of the configuration of a display device. FIGS. 17A to 17C are block diagrams illustrating an example of the configuration of a display device. FIG. 18A is a perspective view illustrating an example of the configuration of a display device, and FIG. 18B is a block diagram illustrating an example of the configuration of a display device. FIG. 19 is a schematic diagram illustrating an example of the configuration of a display device. FIGS. 20A to 20H are circuit diagrams illustrating an example of the configuration of a display device. FIGS. 21A and 21B are circuit diagrams illustrating an example of the configuration of a display device. FIG. 22A is a perspective view illustrating an example of the configuration of a display device, and FIG. 22B is a block diagram illustrating an example of the configuration of a display device. FIG. 23 is a schematic diagram illustrating an example of the configuration of a display device. FIGS. 24A and 24B are schematic diagrams illustrating an example of the configuration of a display device. FIG. 25 is a cross-sectional schematic diagram illustrating an example of the configuration of a display device. FIG. 26 is a cross-sectional schematic diagram illustrating an example of the configuration of a display device. FIG. 27 is a cross-sectional schematic diagram illustrating an example of the configuration of a display device. FIG. 28 is a cross-sectional schematic diagram illustrating an example of the configuration of a display device. FIGS. 29A to 29E are schematic diagrams illustrating an example of an electronic device.

[0020] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different forms and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0021] In addition, in the drawings, the size, layer thickness, or area may be exaggerated for clarity, and therefore, are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes, values, etc. shown in the drawings.

[0022] In this specification and the like, unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0023] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is used in an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. For example, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0024] Embodiment 1 A display device according to one embodiment of the present invention will be described.

[0025] 1A and 2 are perspective views of a display device 100 according to one embodiment of the present invention. FIG. 1B is a block diagram illustrating a configuration of the display device 100. The display device 100 includes an element layer 30 on an element layer 20 and a sealing substrate 40 on the element layer 30. The element layer 30 includes a display portion 31, and a light-emitting element layer 60 is provided between the sealing substrate 40 and the display portion 31. In FIG. 2, the element layer 20, the element layer 30, the light-emitting element layer 60, the sealing substrate 40, and the like are shown separated from each other to make the configuration of the display device 100 easier to understand.

[0026] The element layer 20 includes, for example, a display driver 22 , a processor circuit 70 , a storage unit 71 , and a terminal unit 29 .

[0027] The display driver 22, the processor circuit 70, and the memory 71 are configured with Si CMOS, for example, transistors having silicon in their channel formation regions (Si transistors). The element layer 20 is an element layer having Si transistors. By configuring multiple circuits, such as the display driver 22, the processor circuit 70, and the memory 71, with Si transistors, each circuit, which is preferably highly integrated, can be provided in the element layer 20.

[0028] Furthermore, by configuring the element layer 20 as an element layer having Si transistors, it can be configured to have various functional circuits such as a sensor circuit, a communication circuit, a control circuit, etc. Furthermore, by configuring the display driver 22, the processor circuit 70, and the memory 71 to be arranged in the same layer, it is possible to arrange the processor circuit 70 and the memory 71 by utilizing an area in the element layer 20 where the display driver 22 is not arranged. Therefore, it is possible to increase the degree of freedom in layout, such as by distributing the processor circuit 70 and the memory 71 in the element layer 20.

[0029] For the Si transistor, it is preferable to use silicon with high crystallinity, such as single crystal silicon or polycrystalline silicon, since high field effect mobility can be achieved and higher speed operation is possible.

[0030] The display driver 22 provided in the element layer 20 is connected to the display unit 31 provided in the element layer 30. The display driver 22 has a function of supplying image data to the display unit 31. The display driver 22 can be any of various circuits such as a shift register circuit, a level shifter circuit, an inverter circuit, a latch circuit, an amplifier circuit, an analog switch circuit, or a logic circuit.

[0031] The latch circuit included in the display driver 22 is a circuit that has a function of holding image data supplied to the display device 100. The amplifier circuit included in the display driver 22 is a circuit that has a function of outputting an analog voltage based on image data supplied to the display unit 31 to a source line (signal line).

[0032] The latch circuit has a memory circuit that stores a correction value for correcting image data supplied to the display device 100. The correction value is data corresponding to the difference between the analog voltage output by the amplifier circuit based on reference image data and the analog voltage output by providing the reference image data to another amplifier circuit. The latch circuit has a function of correcting the analog voltage output by the amplifier circuit to the source line by correcting the image data supplied to the display device 100 according to the correction value. The correction value held in the memory circuit of the latch circuit is supplied from the processor circuit unit 70.

[0033] The processor circuit unit 70 provided in the element layer 20 is connected to a storage unit 71 included in the element layer 20, and has a function of executing processing based on programs and data stored in the storage unit 71. The processor circuit unit 70 has an analog-to-digital conversion circuit for converting the analog voltage supplied to the display unit 31 by the display drive unit 22 into digital data, and an arithmetic circuit for performing arithmetic processing based on the digital data and acquiring a correction value for correcting image data supplied to the display device 100.

[0034] The analog voltage input to the analog-digital circuit of the processor circuit unit 70 is the analog voltage output from the amplifier circuit of the display drive unit 22. An amplifier circuit is provided for each column to supply an analog voltage based on image data to the pixel circuits. The analog voltage can be supplied to the analog-digital circuit via the same wiring by sequentially turning on the switch circuits for each column. By supplying the different analog voltages output from the amplifier circuits of each column to the analog-digital conversion circuit via the same wiring, conversion can be performed with reduced variation due to the influence of the wiring.

[0035] In this specification, the direction in which the source lines are arranged is referred to as the column direction, and the direction in which the gate lines are arranged is referred to as the row direction. As described above, an amplifier circuit that supplies an analog voltage to the source lines is provided in each column.

[0036] Furthermore, in a configuration in which different analog voltages output from the amplifier circuits of each column are supplied to an analog-digital conversion circuit, the analog voltages output from the amplifier circuits of each column can be corrected based on a reference analog voltage. This makes it possible to correct variations in the output voltages of the amplifier circuits in different columns. Furthermore, in a configuration in which different analog voltages output from the amplifier circuits of each column are supplied to an analog-digital conversion circuit, it is possible to reduce the number of capacitors, resistors, and other elements used to cancel offset voltages in the amplifier circuits. This makes it possible to reduce the circuit area required for the amplifier circuits.

[0037] The arithmetic circuit included in the processor circuit unit 70 calculates a correction value based on digital data corresponding to the analog voltage output by the amplifier circuit of each column. The correction value is calculated, for example, by calculating the difference between digital data corresponding to the analog voltage output by an amplifier circuit that receives reference image data and digital data corresponding to the analog voltage output by another amplifier circuit that receives the reference image data. For example, the correction value for each column can be calculated by using digital data corresponding to the analog voltage of the amplifier circuit of the first column as standard data and calculating the difference between this and digital data corresponding to the analog voltage of the amplifier circuit of the second column and thereafter. Alternatively, the arithmetic circuit included in the processor circuit unit 70 can calculate the average value of the analog voltages output by multiple amplifier circuits and then calculate the difference from this average value to calculate the correction value for each column. This configuration enables correction even when the analog voltages output by the amplifier circuits vary slightly or significantly.

[0038] The correction value obtained by the arithmetic circuit of the processor circuit unit 70 is supplied to the display drive unit 22 provided in the element layer 20 as described above, and by adding the correction value to the original image data, it is possible to correct the image data in accordance with the variations in the analog voltage of the amplifier circuit.

[0039] In one embodiment of the present invention, the display device 100 may be configured such that image data is corrected in the display driver 22 based on a correction value calculated by a processor circuit 70 provided within the display device 100. The correction value used to correct the image data (output data) is calculated within the processor circuit 70 based on the analog voltage output by the amplifier circuit and held in a latch circuit included in the display driver 22 provided in the same element layer 20 as the processor circuit 70. This configuration can reduce the impact of signal delay compared to a configuration in which image data is corrected in a circuit external to the display device before being supplied to the display device. Furthermore, because the connection between the processor circuit 70 and the display driver 22 is made via wiring within the same element layer 20, there is no impact from bus width limitations that arise when data is transferred via an external circuit. As a result, the data transfer rate for the correction value from the processor circuit 70 to the display driver 22 can be increased.

[0040] The memory unit 71 connected to the processor circuit unit 70 includes a plurality of memory circuits (memory cells). As the memory unit 71, various storage devices using various storage methods can be used. For example, a dynamic random access memory (DRAM), a static random access memory (SRAM), a phase-change memory (PCM), a resistive random access memory (ReRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), an antiferroelectric memory, or the like can be used.

[0041] The element layer 30 in which the display portion 31 is provided is a layer including an OS transistor. With this structure, the display portion 31 including the OS transistor can be stacked with the element layer 20.

[0042] An OS transistor has a characteristic of having an extremely low off-state current. Therefore, when an OS transistor is used as a transistor provided in a pixel circuit, in particular, written data can be held for a long period of time.

[0043] Examples of metal oxides that can be used in OS transistors include In oxide, Zn oxide, Zn—Sn oxide, Ga—Sn oxide, In—Ga oxide, In—Zn oxide, and In-M-Zn oxide (where M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf). Metal oxides using Ga as M are particularly preferred for OS transistors because they can provide transistors with excellent electrical characteristics, such as field-effect mobility, by adjusting the ratio of elements. The oxide containing indium and zinc may also contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0044] 2, a light emitting element layer 60 is provided above the display section 31 of the element layer 30. The light emitting element layer 60 has a plurality of light emitting elements, and the light emission brightness is controlled by a pixel circuit 51 provided in the display section 31. The light emitting element layer 60 can also be considered as part of the display section 31.

[0045] The display unit 31 includes pixels 50 each having a plurality of pixel circuits 51. The pixels 50 each include a pixel circuit 51 and a light-emitting element (not shown) provided in a light-emitting element layer 60 on the pixel circuit 51. The pixel circuits 51 included in the display unit 31 include OS transistors. The pixel circuits 51 correspond to pixel circuits included in sub-pixels for color display. Details of the pixel circuits 51 and the light-emitting elements will be described later.

[0046] Each of the three sub-pixels controls the amount of light emitted, for example, red light, green light, or blue light. The color of light controlled by each of the three sub-pixels is not limited to a combination of red (R), green (G), and blue (B), but can also be cyan (C), magenta (M), and yellow (Y). The areas of the three sub-pixels do not need to be the same. If the light-emitting efficiency and reliability differ depending on the emitted color, the area of ​​the sub-pixel can be changed for each emitted color.

[0047] An FPC (Flexible Printed Circuit) or the like is connected to the terminal portion 29. Although an example in which the element layer 30 and the sealing substrate 40 are not formed in the region overlapping with the terminal portion 29 is illustrated, the terminal portion 29 may also be formed on the element layer 30.

[0048] In one embodiment of the present invention, a correction value can be calculated in a processor circuit in a display device, and image data can be corrected according to the correction value. This configuration can reduce the layout area of ​​capacitors and resistors required for the offset voltage correction, compared to a configuration in which an amplifier circuit corrects an offset voltage and corrects an analog voltage output from the amplifier circuit.

[0049] Additionally, one embodiment of the present invention can be configured to calculate a correction value to correct variations in the amplifier circuits of each column by sequentially converting analog voltages output by the amplifier circuits of each column into digital data. In this case, for example, variations in the analog voltages output between adjacent amplifier circuits can be corrected. The configuration of one embodiment of the present invention is particularly effective in cases where the pixel size per pixel is small and the analog voltage applied to each pixel is very small, such as in display devices used in xR devices. One embodiment of the present invention can improve the display quality of a display unit controlled in response to an analog voltage.

[0050] FIG. 3 is a block diagram illustrating an example of the configuration of the display driver 22, the processor circuit 70, and the display unit 31.

[0051] The display drive unit 22 has a gate line drive circuit 32 and a source line drive circuit 33. The circuit included in the gate line drive circuit 32 functions as, for example, a scanning line drive circuit (gate line drive circuit). The circuit included in the source line drive circuit 33 functions as, for example, a signal line drive circuit (source line drive circuit). The gate line drive circuit 32 is a circuit that drives gate lines connected to pixel circuits 51. The source line drive circuit 33 is a circuit that drives source lines connected to pixel circuits 51.

[0052] As shown in FIG. 3, the source line driver circuit 33 includes an LVDS (Low Voltage Differential Signaling) circuit 41, a serial-to-parallel conversion circuit 42, a latch circuit 43, a level shifter circuit 44, a digital-to-analog conversion circuit 45, and an amplifier circuit 46.

[0053] The gate line driving circuit 32 included in the display driving unit 22 is a circuit that outputs timing signals that control the conductive state of transistors whose gates are connected to gate lines in pixel circuits.

[0054] The LVDS circuit 41 is a circuit for receiving data based on LVDS, a signal transmission means. LVDS is a communication technology that allows relatively high-speed operation, low power consumption due to small-amplitude signals, a reduction in the number of wirings, and mitigation of the effects of noise. Receiving data via LVDS from outside the display device 100 can reduce the effects of noise such as EMI (Electro-Magnetic Interference).

[0055] The serial-parallel conversion circuit 42 is connected to the LVDS circuit 41. The serial-parallel conversion circuit 42 can convert the single-ended signal from the LVDS circuit 41 into a parallel signal and supply it to the latch circuit 43.

[0056] The latch circuit 43 is a circuit for transferring the signal supplied from the serial-parallel conversion circuit 42, for example, image data, as a certain data group to the level shifter circuit 44. For example, the latch circuit 43 sequentially holds the supplied image data and transfers it to the level shifter circuit 44 when the data for one row in the display unit 31 is complete.

[0057] The latch circuit 43 has a memory circuit 43M that stores data based on the correction value. The latch circuit 43 corrects the image data supplied to the latch circuit 43 according to the data stored in the memory circuit 43M. The memory circuit 43M can store correction value data according to the amplifier circuit 46 provided for each column. The image data can be corrected, for example, by adding (or subtracting) the correction value data stored in the memory circuit 43M to the image data supplied to the latch circuit 43. The image data correction is based on the variation in the analog voltage of the amplifier circuit for each column. Therefore, the signal transferred from the latch circuit 43 to the level shifter circuit 44 can be image data in which the variation in the analog voltage of the amplifier circuit for each column has been corrected.

[0058] The level shifter circuit 44 is a circuit for increasing the signal level, for example, the amplitude voltage of the image data output from the latch circuit 43. This configuration makes it possible to control the on / off state of a transistor included in the downstream digital-to-analog conversion circuit 45.

[0059] The digital-to-analog conversion circuit 45 is a circuit that converts the digital image data into an analog voltage.

[0060] The amplifier circuit 46 is a circuit for amplifying the analog voltage supplied from the digital-analog conversion circuit 45. The amplifier circuit 46 supplies the analog voltage to the pixel circuit 51 via a wiring SL (also referred to as a source line). The amplifier circuit 46 also supplies the analog voltage to the analog-digital conversion circuit 77 via a switch circuit (not shown) and a wiring ACL.

[0061] The display unit 31 has a plurality of pixel circuits 51. The pixel circuits 51 can use transistors, capacitors, and the like.

[0062] The processor circuit unit 70 has an analog-to-digital conversion circuit 77 and an arithmetic circuit 78. One terminal of a switch circuit is connected to the output terminal of the amplifier circuit 46 of each column. The other terminal of the switch circuit is connected to a wiring ACL. The wiring ACL is connected to the analog-to-digital conversion circuit 77. An analog voltage is supplied to the analog-to-digital conversion circuit 77 via the switch circuit and the wiring ACL. The analog-to-digital conversion circuit 77 converts the analog voltage into a digital signal and sequentially outputs it to the arithmetic circuit 78. The arithmetic circuit 78 arithmetically processes the digital signal to calculate data Dc based on the correction value, and outputs the data Dc to the above-mentioned memory circuit 43M for storage.

[0063] 4 is a circuit diagram for explaining the connection between the analog-to-digital conversion circuit 77 and the amplifier circuit 46. Illustrated in FIG. 4 are 1 to N (N is an integer of 2 or more) columns of digital-to-analog conversion circuits 45 (digital-to-analog conversion circuits 45_1 to 45_N), amplifier circuits 46 (amplifier circuits 46_1 to 46_N), switch circuits 47_1 to 47_N, wirings SL (wirings SL_1 to SL_N), wirings ACL, pixel circuits 51, selection circuits 48, and the analog-to-digital conversion circuit 77.

[0064] The selection circuit 48 is a circuit that outputs signals SEL_1 to SEL_N for sequentially turning on the switch circuits 47_1 to 47_N. Note that although the switch circuits 47_1 to 47_N are illustrated as analog switches in FIG. 4 as an example, other circuits that turn on or off the connection between the wiring SL and the wiring ACL can also be used.

[0065] 5 is a timing chart for explaining the operation of each circuit shown in FIG. 5. Signals or voltages of the signals SEL_1, SEL_2, and SEL_N, the wirings SL_1, SL_2, and SL_N, and the wiring ACL are illustrated in FIG. 5. Note that the signals SEL_1 to SEL_N are described as being in an on state at H level and in an off state at L level.

[0066] During the period from time T00 to time T01 shown in FIG. 5, the analog voltages of the wirings SL_1, SL_2, and SL_N are respectively set to the voltage V ＳＬ＿１ , voltage V ＳＬ＿２ , voltage V ＳＬ＿Ｎ This becomes:

[0067] 5, the signal SEL_1 is set to an H level. The switch circuit 47_1 between the wiring SL_1 and the wiring ACL is turned on. The voltage of the wiring ACL is set to the voltage V of the wiring SL_1. ＳＬ＿１ Therefore, the voltage V ＳＬ＿１ is supplied, and a digital signal corresponding to the magnitude of the voltage is supplied to the arithmetic circuit 78.

[0068] 5, the signal SEL_2 is set to an H level. The switch circuit 47_2 between the wiring SL_2 and the wiring ACL is turned on. The voltage of the wiring ACL is set to the voltage V ＳＬ＿２ Therefore, the voltage V ＳＬ＿２ is supplied, and a digital signal corresponding to the magnitude of the voltage is supplied to the arithmetic circuit 78. The arithmetic circuit 78 calculates, for example, a voltage V ＳＬ＿１ and voltage V ＳＬ＿２ By calculating the difference between the analog voltages, a correction value for correcting the variations in the analog voltages between the amplifier circuits 46_1 and 46_2 can be supplied to the latch circuit.

[0069] 5, the signal SEL_N is set to the H level. The switch circuit 47_N between the wiring SL_N and the wiring ACL is turned on. The voltage of the wiring ACL is set to the voltage V of the wiring SL_N. ＳＬ＿Ｎ Therefore, the voltage V ＳＬ＿Ｎ is supplied, and a digital signal corresponding to the magnitude of the voltage is supplied to the arithmetic circuit 78.

[0070] FIG. 6 is a flowchart illustrating the operation of acquiring a correction value based on an analog voltage in the processor circuit section 70 and storing it in the memory circuit 43M of the latch circuit 43.

[0071] Step S01 shown in FIG. 6 is a step of inputting standard data. The input of the standard data corresponds to supplying reference image data to the display device 100. The image data supplied to the display device 100 is data for causing the amplifier circuit of each column in the source line driving circuit 33 to output a predetermined analog voltage. By inputting the standard data, the wiring SL of each column is supplied with a voltage V ＳＬ This becomes:

[0072] Step S02 shown in FIG. 6 is a step of sequentially outputting analog voltages from the amplifier circuits 46 in the first to Nth columns. ＳＬ V varies depending on the performance of the amplifier circuit 46. ＳＬ＿１ , voltage V ＳＬ＿２ , voltage V ＳＬ＿Ｎ The voltages with different values ​​are supplied to the analog-to-digital conversion circuit 77 via the wiring ACL in order from the first column by sequentially turning on the switch circuits 47 described with reference to FIG.

[0073] 6 is a step of analog-to-digital conversion of the analog voltages of the amplifier circuits that are sequentially supplied. The analog voltages of the amplifier circuits in the first to Nth columns are sequentially converted into digital data and supplied to the arithmetic circuit 78. Because the analog voltages output from different amplifier circuits 46 are supplied to the analog-to-digital conversion circuit 77 via the same wiring ACL, the analog voltage values ​​of the amplifier circuits in different columns can be converted into digital data more accurately.

[0074] 6 is a step for obtaining a correction value. By calculating the difference between reference data (for example, digital data corresponding to the analog voltage of the amplifier circuit in the first column) and digital data corresponding to the analog voltage of the amplifier circuit in the second column and thereafter, a correction value corresponding to the variation in the analog voltage of the amplifier circuit in the first column to the Nth column can be calculated.

[0075] Step S05 shown in Figure 6 is a step of outputting the correction value to the latch circuit. The correction value calculated by the arithmetic circuit 78 of the processor circuit unit 70, corresponding to the variations in the analog voltages of the amplifier circuits in the first to Nth columns, is output to the latch circuit 43 in the display drive unit 22. The connection between the processor circuit unit 70 and the display drive unit 22 is made via wiring in the same element layer 20, so there is no influence of the bus width limitations that occur when connecting via an external circuit. Therefore, the data transfer rate for the correction value from the processor circuit unit 70 to the display drive unit 22 can be increased.

[0076] 6 is a step of storing the correction value in a memory circuit included in the latch circuit. The correction value is stored in memory circuit 43M in latch circuit 43. With this configuration, image data can be corrected in display drive unit 22 based on the correction value calculated by processor circuit unit 70 provided in display device 100.

[0077] Note that the configuration of one embodiment of the present invention is not limited to the configuration described with reference to Figures 1A to 6. For example, a configuration may be adopted in which data based on the correction value calculated by the processor circuit unit is output to an external image data correction circuit.

[0078] The display device 100 shown in Figure 7 illustrates a configuration in which data Dc based on a correction value calculated in an arithmetic circuit 78 possessed by a processor circuit unit 70 is output to an image data correction circuit 80 external to the display device 100 via a terminal unit 29.

[0079] The image data correction circuit 80 has a function of generating corrected image data based on data Dc based on the correction value supplied from the display device 100. The corrected image data can be supplied to the display device 100 via the terminal unit 29.

[0080] In the configuration of Figure 7, data Dc based on a correction value calculated within the display device 100 to correct variations in the analog voltage output by the amplifier circuit 46 is output to an image data correction circuit 80 external to the display device 100. In this configuration, although the data Dc based on the correction value is output to an external circuit, because the data Dc is digital data, the impact of signal degradation is small. Furthermore, the data Dc based on the correction value is acquired at certain times, such as when the display device 100 is started up, and therefore is acquired infrequently. Therefore, it can be said that the impact of outputting the data Dc based on the correction value to the image data correction circuit 80 external to the display device 100 is small.

[0081] 7 also allows a correction value to be calculated in a processor circuit unit inside the display device, and image data to be corrected according to the correction value, as described in Figures 1A to 6. This configuration allows a reduction in the layout area of ​​the capacitors and resistors required for the offset voltage correction configuration, compared to a configuration in which the offset voltage is corrected by an amplifier circuit and the analog voltage output by the amplifier circuit is corrected.

[0082] 7 can also be configured to calculate a correction value by sequentially converting the analog voltages output by the amplifier circuits of each column into digital data, as described with reference to FIGS. 1A to 6 , to correct variations in the amplifier circuits of each column. In this case, for example, variations in the analog voltages output between adjacent amplifier circuits can be corrected. The configuration of one embodiment of the present invention is particularly effective in cases where the pixel size per pixel is small and the analog voltage applied to each pixel is very small, such as in display devices used in xR devices. One embodiment of the present invention can improve the display quality of a display unit controlled according to an analog voltage.

[0083] 8A is a schematic diagram illustrating the connection relationship between the display driver 22 and the display unit 31. As described above, in one aspect of the present invention, the display driver 22 and the display unit 31 are provided on different layers, so that the display unit 31 can be provided above the display driver 22.

[0084] As described above, the display drive unit 22 has a gate line drive circuit 32 and a source line drive circuit 33. The gate line drive circuit 32 is connected to pixel circuits 51 of the display unit 31 provided above via wiring GL (gate lines). The source line drive circuit 33 is connected to pixel circuits 51 of the display unit 31 provided above via wiring SL (source lines).

[0085] In the display driver 22, the gate line driver circuit 32 and the source line driver circuit 33 are each provided in a vertically (or horizontally) long rectangular shape. In this case, in the element layer 20, the processor circuit 70 is preferably arranged so as to fill the area in the display driver 22 where the gate line driver circuit 32 and the source line driver circuit 33 are not provided, as shown in Fig. 8B. With this configuration, the processor circuit 70 and the display driver 22 can be arranged in the element layer 20 without being separated from each other.

[0086] The schematic diagram shown in FIG. 8C is a configuration example in which a plurality of sets of display units 31, gate line driving circuits 32, and source line driving circuits 33 shown in FIG. 8A are arranged side by side. The display units 31, gate line driving circuits 32, and source line driving circuits 33 are arranged in a matrix of m rows and n columns (m and n are each integers equal to or greater than 1). In this specification, the section in the first row and first column is referred to as display unit 31[1,1], and the section in the mth row and nth column is referred to as display unit 31[m,n]. Display units 31[1,1] to 31[m,n] can be combined to form the display unit 31. Note that display units 31[1,1] to 31[m,n] may also be referred to as sub-display units. The display unit 31 can display a single image by combining multiple sub-display units. FIG. 8C shows a case in which m is 4 and n is 4. The display unit 31 is divided into 16 sections. Each of the divided display portions 31[1,1] to 31[m,n] includes a gate line driver circuit 32 connected to a wiring GL and a source line driver circuit 33 connected to a wiring SL.

[0087] By providing the display section 31 and the display driver 22 in an overlapping region, the connection distance (wiring length) between the pixel circuit and the peripheral driver circuit can be made extremely short. As a result, wiring resistance and parasitic capacitance are reduced, which shortens the time required for charging and discharging, enabling high-speed driving. In addition, power consumption can be reduced. Furthermore, miniaturization and weight reduction can be achieved.

[0088] Furthermore, the display unit 31 is configured to have a gate line driver circuit 32 and a source line driver circuit 33 for each of the display units 31[1,1] to 31[m,n]. Therefore, the display unit 31 can rewrite the image for each of the display units 31[1,1] to 31[m,n]. For example, it is possible to rewrite image data only in sections of the display unit 31 where changes have occurred in the image, and to retain the image data in sections where no changes have occurred, thereby reducing power consumption. For example, it is possible to reduce the number of times per unit time that image data is rewritten in one of the sub-display units 31[1,1] to 31[m,n] compared to the number of times per unit time that image data is rewritten in the other sub-display units, thereby reducing power consumption.

[0089] Furthermore, the display device 100 can individually set the drive frequency (frame frequency, frame rate, refresh rate, etc.) for displaying images for each of the display units 31[1,1] to 31[m,n]. Therefore, by combining with eye tracking or the like, it becomes possible to apply foveated rendering, a type of rendering that varies the frame rate for each region depending on the user's line of sight. This allows for a configuration that outputs images with excellent display quality and low load.

[0090] In a display device according to one embodiment of the present invention, pixel circuits and display driver units are stacked and the divided display units 31 are driven at different drive frequencies, thereby achieving low power consumption. For example, the drive frequencies of the divided display units 31 are varied depending on the movement of the gaze. Note that information about the movement of the gaze (gazing point G) can be obtained by an eye tracking method such as a pupil center corneal reflection method or a bright / dark pupil effect method. Alternatively, the information may be obtained by an eye tracking method using a laser, ultrasound, or the like.

[0091] FIG. 9A shows a display unit 31 divided into 32 sections, or 4 rows and 8 columns. FIG. 9A also shows a first region S1 to a third region S3, each centered around a gaze point G. The display unit 31 divides each of the divided sections into either a first section 29A overlapping the first region S1 or the second region S2, or a second section 29B overlapping the third region S3. The display unit 31 divides each of the divided sections into either a first section 29A or a second section 29B. In this case, the first section 29A overlapping the first region S1 and the second region S2 is a display section that includes an area overlapping with the gaze point G, and the second section 29B is located outside the first section 29A and far from the user's gaze point G (see FIG. 9B).

[0092] The gate line driving circuit 32 and source line driving circuit 33 of each divided display unit 31 can be individually controlled. For example, the display unit corresponding to the second unit 29B overlaps with the third region S3, which includes the stable fixation field, the induced field, and the auxiliary field, and is therefore less discriminative to the user. Therefore, even if the number of times image data is rewritten per unit time (hereinafter also referred to as "image rewriting count") for the display unit belonging to the second unit 29B is less than that for the display unit corresponding to the first unit 29A, the degradation in the actual display quality perceived by the user (hereinafter also referred to as "actual display quality") is small. Even if the drive frequency of the display unit corresponding to the second unit 29B is lower than that of the display unit corresponding to the first unit 29A, the degradation in the actual display quality is small.

[0093] Lowering the drive frequency can reduce the power consumption of the display device. On the other hand, lowering the drive frequency also reduces the display quality, particularly when displaying moving images. According to one aspect of the present invention, by setting the drive frequency of the display unit corresponding to the second section 29B lower than the drive frequency of the display unit corresponding to the first section 29A, it is possible to reduce the power consumption of sections with low user visibility while suppressing a substantial decrease in display quality. According to one aspect of the present invention, it is possible to maintain display quality while reducing power consumption.

[0094] The drive frequency of the display unit corresponding to the first section 29A can be 30 Hz to 500 Hz, preferably 60 Hz to 500 Hz. The drive frequency of the display unit corresponding to the second section 29B is preferably equal to or lower than the drive frequency of the first section 29A, more preferably equal to or lower than half the drive frequency of the display unit corresponding to the first section 29A, and even more preferably equal to or lower than one-fifth the drive frequency of the display unit corresponding to the first section 29A.

[0095] Furthermore, among the display units corresponding to the third region S3, a third section 29C may be set outside the second section 29B (see FIG. 9C ), and the drive frequency of the display unit corresponding to the third section 29C may be lower than that of the display unit corresponding to the second section 29B. The drive frequency of the display unit corresponding to the third section 29C is preferably equal to or lower than that of the display unit corresponding to the second section 29B, more preferably equal to or lower than half the drive frequency of the display unit corresponding to the second section 29B, and even more preferably equal to or lower than one-fifth the drive frequency of the display unit corresponding to the second section 29B. By significantly reducing the number of times the image is rewritten, power consumption can be further reduced. Furthermore, image data rewriting may be stopped as necessary. Stopping image data rewriting can further reduce power consumption.

[0096] When such a driving method is performed, it is preferable to use a transistor with extremely low off-state current as the transistor constituting the pixel circuit 51. For example, an OS transistor is preferable as the transistor constituting the pixel circuit 51. Since the off-state current of an OS transistor is extremely low, image data supplied to the pixel circuit 51 can be held for a long period of time by stopping the output signal output from the gate line driver circuit.

[0097] Furthermore, when the video scene displayed on the display unit 31 changes, an image with significantly different brightness, contrast, or color tone from the immediately preceding image may be displayed. In such a case, a difference occurs in the timing of image switching between the first section 29A and a section with a lower drive frequency than the first section 29A, resulting in a significant difference in brightness, contrast, or color tone between the two sections, which may result in a loss of substantial display quality. In such a case, for example, the image in sections other than the first section 29A may be rewritten at the same drive frequency as the first section 29A, and then the drive frequency of the sections other than the first section 29A may be lowered.

[0098] Furthermore, when it is determined that the amount of change in the gaze point G has exceeded a certain amount, the display units other than the display unit corresponding to first section 29A may also rewrite the images at the same drive frequency as the display unit corresponding to first section 29A, and when it is determined that the amount of change is within the certain amount, the drive frequency of the display units other than the display unit corresponding to first section 29A may be reduced. Furthermore, when it is determined that the amount of change in the gaze point G is small, the drive frequency of the display units other than the display unit corresponding to first section 29A may be further reduced.

[0099] The divided display sections that make up the display unit 31 are not limited to the first section 29A, the second section 29B, and the third section 29C. Four or more sections may be set in the display unit 31. By setting multiple sections in the display unit 31 and gradually lowering the drive frequency, it is possible to further reduce the actual degradation of display quality.

[0100] Furthermore, high-speed rewriting can be realized by simultaneously rewriting image data on all divided display sections 31 instead of on each divided display section 31. High-speed rewriting can be realized by simultaneously rewriting image data on all divided display sections 31 instead of on each divided display section 31.

[0101] In addition, in the display device 100 exemplified in this embodiment, the display unit 31 is divided into eight sections in the column direction (FIGS. 9A to 9C), so the length of the wiring GL connecting the gate line driving circuit and the pixel circuit is reduced to one-eighth, which reduces the resistance and parasitic capacitance of the wiring GL to one-eighth, improving signal degradation and delay and making it easier to ensure time for rewriting image data.

[0102] According to the display device 100 of one embodiment of the present invention, the time required for writing image data is short, and therefore high-speed rewriting of a display image can be realized. Therefore, a display device with high display quality can be realized, and in particular, a display device excellent in displaying moving images can be realized.

[0103] Furthermore, according to the display device 100 of one embodiment of the present invention, the output signals output by the gate line driver circuit can be controlled independently for each divided display portion, and therefore the divided display portions can have different shapes or sizes. As a result, the display portion 31 can be configured with display portions having different shapes or sizes. Therefore, the display portion 31 is not limited to a rectangular shape, and can have an excellent design, such as a circular shape.

[0104] 10A to 12B show configuration examples of pixel circuits applicable to the pixel circuit 51, and light-emitting elements connected to the pixel circuit 51. Note that in the following description, the light-emitting element is not limited to an organic EL element, and may be a self-luminous light-emitting device such as an LED, a micro LED, a QLED (Quantum-dot Light Emitting Diode), a semiconductor laser, or the like.

[0105] In this specification and the like, the term “element” may be replaced with “device.” For example, a display element and a light-emitting element may be replaced with, for example, a display device and a light-emitting device, respectively.

[0106] A pixel circuit 51A shown in Fig. 10A includes a transistor 55A, a transistor 55B, and a capacitor 56. Fig. 10A also shows a light-emitting element 61 connected to the pixel circuit 51A. Fig. 10A also shows a wiring SL, a wiring GL, a power supply line ANO, and a power supply line VCOM.

[0107] The transistor 55A has a gate connected to the wiring GL, one of its source and drain connected to the wiring SL, and the other connected to the gate of the transistor 55B and one electrode of the capacitor 56. The transistor 55B has one of its source and drain connected to the power supply line ANO, and the other connected to the anode of the light-emitting element 61. The other electrode of the capacitor 56 is connected to the anode of the light-emitting element 61. The light-emitting element 61 has a cathode connected to the power supply line VCOM. The anode and cathode of the light-emitting element 61 can be switched as needed by changing the magnitude of the potential supplied.

[0108] 10B is a configuration in which a transistor 55C is added to the pixel circuit 51A. The transistor 55C has a gate connected to a wiring GL, one of a source and a drain connected to an anode of the light-emitting element 61, and the other connected to a wiring V0.

[0109] A pixel circuit 51C shown in FIG. 10C is an example in which transistors having a pair of gates are used as the transistors 55A and 55B of the pixel circuit 51A. A pixel circuit 51D shown in FIG. 10D is an example in which the same transistors are used in the pixel circuit 51B. This can increase the current that the transistors can pass. Note that, although transistors having a pair of gates are used for all the transistors here, this is not a limitation. Alternatively, a transistor having a pair of gates connected to different wirings may be used. For example, reliability can be improved by using a transistor in which one of the gates is connected to the source.

[0110] 11A has a configuration in which a transistor 55D is added to the pixel circuit 51B. Three gate lines (a wiring GL1, a wiring GL2, and a wiring GL3) are connected to the pixel circuit 51E.

[0111] The gate of the transistor 55D is connected to a wiring GL3, one of the source and drain of the transistor 55D is connected to the gate of the transistor 55B, and the other is connected to a wiring V0. The gate of the transistor 55A is connected to a wiring GL1, and the gate of the transistor 55C is connected to a wiring GL2.

[0112] By simultaneously turning on transistors 55C and 55D, the source and gate of transistor 55B have the same potential, and when the threshold voltage of transistor 55B is higher than 0 V, transistor 55B can be turned off. This makes it possible to forcibly cut off the current flowing through light-emitting element 61. Such a pixel circuit is suitable for use in a display method in which display periods and off periods are alternately provided.

[0113] 11B is an example in which a capacitor 56A is added to the pixel circuit 51E. The capacitor 56A functions as a storage capacitor.

[0114] 11C and 11D are examples in which transistors each having a pair of gates are applied to the pixel circuit 51E or 51F, respectively. Transistors each having a pair of gates connected to each other are applied to the transistor 55A, the transistor 55C, and the transistor 55D, and a transistor each having one gate connected to its source is applied to the transistor 55B.

[0115] 11A to 11D show examples in which the circuit can be configured using only n-channel OS transistors. However, one embodiment of the present invention is not limited to this. For example, a pixel circuit may include an OS transistor and a Si transistor. Specifically, in the pixel circuit 51A of FIG. 10A, it is preferable that the transistor 55A be an OS transistor and the transistor 55B be a Si transistor.

[0116] 12A shows an example of the circuit configuration of a pixel circuit (pixel circuit 51J). FIG. 12B is a diagram schematically showing the hierarchical relationship between an element layer 20 including a display driver 22, an element layer 30 including a pixel circuit 51, and a light-emitting element layer 60 including a light-emitting element 61.

[0117] 12A and 12B includes a transistor 55A, a transistor 55B, a transistor 55C, and a capacitor 56. The transistors 55A, 55B, and 55C can be OS transistors. Each of the OS transistors 55A, 55B, and 55C preferably includes a back gate electrode. In this case, the back gate electrode can be configured to receive the same signal as the gate electrode, or a signal different from the gate electrode can be applied to the back gate electrode.

[0118] The transistor 55B has a gate electrode connected to the transistor 55A, a first electrode connected to the light-emitting element 61, and a second electrode connected to the power supply line ANO. The power supply line ANO is a wiring for applying a potential for supplying a current to the light-emitting element 61.

[0119] Transistor 55A has a first electrode connected to the gate electrode of transistor 55B, a second electrode connected to a wiring SL that functions as a source line, and a gate electrode that has the function of controlling the conductive state or non-conductive state based on the potential of wiring GL1 that functions as a gate line.

[0120] The transistor 55C includes a first electrode connected to the wiring V0, a ​​second electrode connected to the light-emitting element 61, and a gate electrode that controls the conductive state or non-conductive state based on the potential of the wiring GL2 that functions as a gate line. The wiring V0 is a wiring for applying a reference potential and a wiring for outputting a current flowing through the pixel circuit 51 to the display driver 22.

[0121] The capacitor 56 includes a conductive film connected to the gate electrode of the transistor 55B and a conductive film connected to the second electrode of the transistor 55C.

[0122] The light-emitting element 61 has a first electrode connected to the first electrode of the transistor 55B and a second electrode connected to a power supply line VCOM. The power supply line VCOM is a wiring for applying a potential for supplying a current to the light-emitting element 61.

[0123] This allows the intensity of light emitted by the light-emitting element 61 to be controlled in accordance with an image signal applied to the gate electrode of the transistor 55B. Also, the reference potential of the wiring V0 applied via the transistor 55C can suppress variations in the gate-source potential of the transistor 55B.

[0124] Furthermore, a current value that can be used to set pixel parameters can be output from the wiring V0. More specifically, the wiring V0 can function as a monitor line for outputting to the outside the current flowing through the transistor 55B or the current flowing through the light-emitting element 61. The current output to the wiring V0 may be converted into a voltage by a source follower circuit or the like.

[0125] In the configuration example shown in FIG. 12B , the wiring connecting the pixel circuit 51J and the display driver 22 can be shortened, thereby reducing the wiring resistance of the wiring. Furthermore, the parasitic capacitance of the wiring can be reduced. Therefore, data can be written at high speed, allowing the display unit 31 to be driven at high speed. This ensures a sufficient frame period even when the number of pixel circuits 51 is increased, thereby increasing the pixel density of the display unit 31. Furthermore, increasing the pixel density of the display unit 31 can increase the resolution of images displayed on the display unit 31. For example, the pixel density of the display unit 31 can be set to 1,000 ppi or more, 5,000 ppi or more, or 7,000 ppi or more. Therefore, the display device 100 can be used, for example, as a display device for xR (xR) such as AR or VR. The display device 100 according to one embodiment of the present invention can be suitably applied to electronic devices, such as HMDs, in which the display unit is close to the user.

[0126] As described above, the display device 100 of one embodiment of the present invention has a stacked structure in which an element layer including the display portion 31 and the memory portion 71 and an element layer including the display driver portion 22 and the processor circuit portion 70 are stacked. Stacking element layers including the respective circuits enables the miniaturization of the display device 100. Furthermore, by providing the display driver portion 22 overlapping the display portion 31, the width of the frame around the display portion 31 can be significantly narrowed, thereby increasing the area of ​​the display portion 31. Therefore, the resolution of the display portion 31 can be increased. Therefore, the display quality of the display device 100 can be improved.

[0127] Furthermore, when the resolution of the display unit 31 is constant, the occupied area per pixel can be increased. Thus, the luminance of the display unit 31 can be increased. Furthermore, the aperture ratio of the pixel can be increased. For example, the aperture ratio of the pixel can be set to 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less. Furthermore, by increasing the occupied area per pixel, the current density supplied to the pixel can be reduced. Thus, the load on the pixel is reduced, and the reliability of the display device 100 can be improved.

[0128] Furthermore, by stacking an element layer having the display unit 31 and the memory unit 71 and an element layer having the display driver 22 and the processor circuit unit 70, the wiring connecting them can be shortened. This reduces wiring resistance and parasitic capacitance, allowing the operating speed of the display device 100 to be increased. Furthermore, the power consumption of the display device 100 can be reduced.

[0129] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0130] (Embodiment 2) In this embodiment, a display device having different configurations and functions from the display drive unit 22 and processor circuit unit 70 illustrated in the above-mentioned embodiment 1 will be described. The processor circuit unit 70 described in the above-mentioned embodiment 1 is capable of performing general-purpose arithmetic processing, and therefore can execute the functions described in this embodiment in addition to the functions described in the above-mentioned embodiment 1. Note that in this embodiment, repeated explanations of components that are assigned the same reference numerals as in the above-mentioned embodiment may be omitted.

[0131] 13 is a block diagram illustrating a configuration of a display device 100_X1 according to one embodiment of the present invention. The display device 100_X1 illustrated in FIG. 13 includes a display driver 22, a processor circuit 70, and a display unit 31, similar to FIG. 1B . The circuits included in the processor circuit 70 and the display driver 22 can be connected via a bus 37.

[0132] 13 also illustrates an image data comparison circuit 200 that supplies control data EN_I to the interface 39 of the display device 100_X1 and image data EN_V to the video interface 39_V of the display device 100_X1. The processor circuit unit 70 and the interface 39 can be connected via a bus unit 37.

[0133] The interface 39 functions as an interface to which control data EN_I, which is arithmetically processed by the processor circuit unit 70, is supplied. The video interface 39_V functions as an interface to which image data EN_V is supplied from outside the display device 100_X1.

[0134] The display drive unit 22 has a plurality of timing controllers. The plurality of timing controllers can be provided according to the number of partitions included in the display unit 31. In Fig. 13, timing controllers 34_1 to 34_4 are illustrated as an example. The processor circuit unit 70 and the timing controllers 34_1 to 34_4 can be connected via a bus unit 37.

[0135] The display driver 22 includes a plurality of gate line driver circuits controlled by a plurality of timing controllers. The plurality of gate line driver circuits can be provided in accordance with the plurality of timing controllers. Gate line driver circuits 32_1 to 32_4 are illustrated in FIG. 13 as an example.

[0136] The display driver 22 includes a controller 35 having a frame memory 36. The frame memory 36 has a function of holding image data EN_V supplied to a video interface 39_V. The controller 35 is connected to the video interface 39_V.

[0137] The display driver 22 has a plurality of source line driver circuits controlled by a controller 35. The number of source line driver circuits can be determined according to the number of partitions included in the display unit 31. In FIG. 13 , source line driver circuits 33_1 to 33_4 are shown as an example. The processor circuit unit 70 and the controller 35 are connected via a bus unit 37.

[0138] The display unit 31 is shown divided into a plurality of sections. In Fig. 13, as an example, the display unit 31 is divided into 16 display units 31[1,1] to 31[4,4] arranged in four rows and four columns.

[0139] Each of the gate line driver circuits 32_1 to 32_4 corresponds to a row-direction section of the display portions 31[1,1] to 31[4,4]. Each of the source line driver circuits 33_1 to 33_4 corresponds to a column-direction section of the display portions 31[1,1] to 31[4,4]. The display of the display portion 31[1,1] is controlled by, for example, the gate line driver circuit 32_1 and the source line driver circuit 33_1. The display of the display portion 31[4,4] is controlled by, for example, the gate line driver circuit 32_4 and the source line driver circuit 33_4.

[0140] The processor circuit unit 70 has the function of controlling the settings of the controller 35 and the timing controllers 34_1 to 34_4 in accordance with the calculation results obtained by processing the control data EN_I supplied to the interface 39, and switching the drive frequencies for driving the gate line drive circuit 32 (gate line drive circuits 32_1 to 32_4) and the source line drive circuit 33 (source line drive circuits 33_1 to 33_4).

[0141] The image data comparison circuit 200 compares image data for successive frame periods displayed on the display unit 31, for example, and outputs control data EN_I according to the comparison result. The control data EN_I is data for switching the operation of the gate line drive circuit and source line drive circuit corresponding to a section when the image data for successive frame periods includes a section for display based on the same image data. The image data EN_V is image data based on the control of the control data EN_I.

[0142] 14 is a block diagram illustrating an example of the configuration of an image data comparison circuit 200 that outputs control data EN_I and image data EN_V to the display device 100_X1. The image data comparison circuit 200 includes a comparison circuit 201, a frame memory 202, and a control circuit 203.

[0143] The comparison circuit 201 is a circuit for comparing image data between different frames. For example, when image data VD1 and image data VD2 of different frames are input consecutively to the image data comparison circuit 200, the comparison circuit 201 compares the image data VD1 (image data of the previous frame) with the image data VD2 (image data of the input frame) for each section of the display unit 31. The image data VD1 is held in the frame memory 202 and can be read out to the comparison circuit 201 under the control of the control circuit 203. Reading of the image data of the previous frame from the frame memory 202 to the comparison circuit 201 continues as long as the image data to be compared match, and ends when the image data to be compared do not match.

[0144] If there is no change in the compared section in the image data between different frames, the control circuit 203 transmits control data EN_I. In this case, the control data EN_I is data for switching the operation of the gate line driving circuit and source line driving circuit corresponding to the section, as described above. Therefore, based on the calculation results in the processor circuit unit 70, the source line driving circuit and gate line driving circuit can be controlled so that image data is not updated in that section. As a result, the power required to drive the source line driving circuit and gate line driving circuit required to update the image data of that section can be reduced.

[0145] Furthermore, if there is no change in the compared section of image data between different frames, the image data EN_V corresponding to that section, i.e., the data contained in the image data VD2, is not transmitted to the display device 100_X1. This reduces the frequency of image data updates, allowing the frequency of the clock signal for driving the source line driver circuit and the gate line driver circuit to be lowered. Furthermore, it is possible to stop the supply of power supply voltage to the amplifier circuit in the source line driver circuit and stop the clock signal to the gate line driver circuit. As a result, the power required for transmitting image data can be reduced.

[0146] As described above, OS transistors can be used in the pixel circuits 51 included in the display unit 31. OS transistors have a very small off-state current. Therefore, by lowering the frequency of the clock signal for driving the source line driver circuit and the gate line driver circuit, the refresh frequency when displaying a still image on the display unit 31 can be reduced. In this specification and the like, the technology for reducing the refresh frequency may be referred to as "idling stop driving" or "IDS driving." In the display device 100_X1, applying IDS driving to each section can reduce the power consumption required to drive the display unit 31.

[0147] If there is a change in the compared section of image data between different frames, the control circuit 203 transmits control data EN_I. In this case, the control data EN_I is data for updating the image data through the operation of the gate line driving circuit and the source line driving circuit. Therefore, based on the calculation results in the processor circuit unit 70, the source line driving circuit and the gate line driving circuit can be controlled to update the image data in the corresponding section.

[0148] Furthermore, if there is a change in the compared sections in the image data between different frames, the control circuit 203 transmits the image data EN_V, i.e., the data contained in the image data VD2, to the display device 100_X1. The display unit 31 of the display device 100_X1 is updated from a display based on the image data VD2 to a display based on the image data VD1.

[0149] Fig. 15 is a timing chart illustrating the operation of the display device 100_X1 illustrated in Fig. 13. In the timing chart illustrated in Fig. 15, the operation is explained by dividing it into periods P0 to P4.

[0150] Period P0 represents a period during which normal drive is performed, during which images are updated in all sections. The interface 39 and the processor circuit unit 70 are set to perform normal drive. The processor circuit unit 70 sets the timing controllers 34_1 to 34_4 to perform normal drive, for example, at a drive frequency of 90 Hz (shown as 90Hz_DV in the figure). Although not shown, the controller 35 is also set in the same way. Depending on the settings of the timing controllers 34_1 to 34_4 and the controller 35, the gate line drive circuits 32_1 to 32_4 and the source line drive circuits 33_1 to 33_4 are set to normal operation (shown as 90Hz in the figure). In the display unit 31, image data is updated at 90 Hz in the display units 31[1,1] to 31[4,4] (normal drive).

[0151] Period P1 represents a period during which control data EN_I is supplied from the external image data comparison circuit 200 to the interface 39. Specifically, as an example, control data EN_I for switching the update frequency of the image data of the display unit 31[2,2] is supplied. During this period, the processor circuit unit 70 is set to perform normal driving. Therefore, in the display unit 31, following period P0, image data is updated at 90 Hz in the display units 31[1,1] to 31[4,4] (normal driving).

[0152] Period P2 represents a period during which control data EN_I is supplied from the interface 39 to the processor circuit unit 70 and arithmetic processing based on the control data EN_I is performed. During this period, the processor circuit unit 70 is set to perform normal driving. Therefore, in the display unit 31, following period P1, image data is updated at 90 Hz in display units 31[1,1] to 31[4,4] (normal driving).

[0153] Period P3 represents a control period during which the processor circuit unit 70 performs arithmetic processing of the control data EN_I, thereby switching the settings of the timing controller 34_2 and the controller 35, which update the image data of the display unit 31[2,2]. The timing controller 34_2, which controls the gate line drive circuit 32_2 corresponding to the display unit 31[2,2], is set to the low-frequency drive switch setting IDS_EN. Similarly, the setting of the controller 35, which controls the source line drive circuit 33_2, is also switched. During this period, the processor circuit unit 70 is set to normal drive. Therefore, in the display unit 31, image data is updated at 90 Hz (normal drive) for the display units 31[1,1] to 31[4,4] following period P0.

[0154] During period P4, the timing controller 34_2 switches from the low-frequency drive setting IDS_EN to a setting for low-frequency drive (shown as 1 Hz_DV in the figure), for example, at a drive frequency of 1 Hz. By switching the timing controller 34_2 to the low-frequency drive setting IDS_EN, the gate line drive circuit 32_2 and source line drive circuit 33_2 corresponding to the display unit 31[2,2] are set to IDS drive (shown as 1 Hz in the figure). Note that the gate line drive circuits 32_1, 32_3, and 32_4 and the source line drive circuits 33_1, 33_3, and 33_4 are sections where image data is updated, and continue normal operation (shown as 90 Hz in the figure).

[0155] As described above, the processor circuit unit of this embodiment is capable of general-purpose arithmetic processing, and therefore, in addition to the functions described in the first embodiment, it is also capable of arithmetic processing of data for switching the operation of the gate line driver circuits and source line driver circuits corresponding to the sections of the display unit, and of switching the settings according to the arithmetic processing. Therefore, it is possible to switch the settings between normal drive and IDS drive for each section of the display unit, thereby achieving low power consumption.

[0156] 16A is a block diagram illustrating a configuration of a display device 100_X2 according to one embodiment of the present invention. The display device 100_X2 illustrated in FIG. 16A includes a display driver 22, a processor circuit 70, and a display unit 31 (not shown), similar to FIG. 1B .

[0157] The display device 100_X2 shown in Fig. 16A includes a display driver 22 and a processor circuit unit 70. The processor circuit unit 70 shown in Fig. 16A can execute a program for a built-in self test (BIST). The processor circuit unit 70 shown in Fig. 16A can also verify the operation of the display driver 22 based on the program for the BIST.

[0158] The signal 70_OUT output by the processor circuit unit 70 includes information on the result of arithmetic processing based on a BIST program for verifying the operation of the processor circuit unit 70. The signal 70_OUT is input to the processor circuit unit 70, and the normal operation of the processor circuit unit 70 can be verified. The normal operation of the processor circuit unit 70 can be determined by comparing the signal 70_OUT with an expected value in the processor circuit unit 70, and the result can be output to the outside as a signal BIST_OUT.

[0159] The signal 70_OUT is also input to the display driver 22. The display driver 22 outputs a signal 22_OUT based on the signal for BIST contained in the signal 70_OUT. The signal 22_OUT output by the display driver 22 includes information on the result of arithmetic processing based on a BIST program for verifying the operation of the display driver 22. The signal 22_OUT is input to the processor circuit unit 70, and the normal operation of the display driver 22 can be verified. The normal operation of the display driver 22 can be determined by comparing the signal 70_OUT with an expected value in the processor circuit unit 70, and output to the outside as a signal BIST_OUT.

[0160] 16B is a diagram for explaining the BIST operation of the processor circuit unit 70 and the display drive unit 22. In FIG. 16B, the operation will be explained by dividing it into periods P11 to P16.

[0161] A period P11 represents a power-off state, in which the display drive unit 22 and the processor circuit unit 70 are powered off (P_OFF).

[0162] A period P12 represents a power-on state, in which the display driver 22 and the processor circuit 70 are powered on (P_ON).

[0163] A period P13 represents an initialization state, in which the display driver 22 and the processor circuit 70 are initialized (INI).

[0164] A period P14 represents the BIST operation of the processor circuit unit 70. The operation of the processor circuit unit 70 is verified based on a program for the BIST of the processor circuit unit 70. The display driver 22 continues initialization (INI).

[0165] A period P15 represents the BIST operation of the display drive unit 22. The processor circuit unit 70 provides the display drive unit 22 with a signal 70_OUT based on a BIST program (BIST_22) for the display drive unit 22. The display drive unit 22 outputs a signal 22_OUT based on the BIST program to the processor circuit unit 70, and operation verification is performed in the processor circuit unit 70.

[0166] A period P16 represents a period for outputting the operation verification results. The processor circuit unit 70 outputs a signal (BIST_OUT) indicating whether the display drive unit 22 and the processor circuit unit 70 are operating normally to the outside. As a result, it is possible to determine whether the display drive unit 22 and the processor circuit unit 70 are operating normally or defectively.

[0167] The processor circuit unit 70 described in the first embodiment is capable of general-purpose arithmetic processing. Therefore, the processor circuit unit 70 can execute a BIST program. To improve the quality of the operational test, a wide variety of test patterns must be prepared for BIST. When BIST is executed using dedicated hardware within a chip, the circuit size tends to increase. On the other hand, the display device 100_X2, which includes a processor circuit unit 70 capable of executing a BIST program, can perform arithmetic processing based on other programs in addition to BIST, thereby enabling effective use of the processor circuit unit 70. Furthermore, when designing dedicated hardware within a chip, the test patterns that can be generated are fixed. However, the processor circuit unit 70 capable of executing a BIST program can generate new test patterns by updating the program, allowing for flexible change of test patterns.

[0168] 17A is a block diagram illustrating a configuration of a display device 100_X3 according to one embodiment of the present invention. The display device 100_X3 illustrated in FIG. 17A includes a display driver 22, a processor circuit 70, and a display unit 31 (not illustrated), similar to FIG. 1B .

[0169] 17A includes a memory controller 73 in addition to a display driver 22 and a processor circuit unit 70. The processor circuit unit 70 and the memory controller 73 can be connected via a bus unit 37. The display driver 22 includes a controller 35 having the frame memory 36 described above, and a source line driver circuit 33.

[0170] 17A has a function of controlling the memory controller 73 to update the address value of the image data stored in the frame memory 36. This configuration makes it possible to reuse the image data stored in the frame memory 36. Therefore, it is possible to reduce the amount of image data supplied from outside the display device 100_X3.

[0171] The processor circuit unit 70 has a function of controlling the controller 35 and the memory controller 73 in accordance with the calculation results obtained by processing the control data EN_I supplied to an interface (not shown). Here, the control data EN_I supplied to the processor circuit unit 70 is information regarding image data having different addresses between different frames. Image data having different addresses between different frames can be used repeatedly by updating the addresses.

[0172] The memory controller 73 has a function of updating the address value of an area in the image data that can be used repeatedly between different frames. For example, it can update the address of the image data VD of the previous frame and control the display of the image data combined with separately supplied image data EN_V.

[0173] 17B and 17C are schematic diagrams illustrating an example of updating the address values ​​of areas in image data that can be used repeatedly between different frames. Fig. 17B is a schematic diagram of image data VD of the previous frame. Fig. 17C is a schematic diagram of image data EN_V that is supplied separately. The schematic diagrams of image data VD and image data EN_V include areas 99 (hatched areas) of the same image data that have different addresses.

[0174] The memory controller 73 changes the address when the address of the image data in region 99 in the image data VD is, for example, "ADDR_1 to ADDR_k (k is an integer equal to or greater than 2)." Specifically, the memory controller 73 changes the address so that the address of the image data in region 99 in the image data EN_V becomes, for example, "ADDR_1+x to ADDR_k+x (x is an integer equal to or greater than 1)." By changing the address in this way, it is possible to use part of the image data VD of the previous frame when displaying the image data EN_V. Since the image data EN_V supplied from the outside can be data excluding the image data in region 99, it is possible to reduce the amount of data supplied from the outside.

[0175] The processor circuit unit 70 described in the first embodiment is capable of general-purpose arithmetic processing. Therefore, the processor circuit unit 70 can be configured to execute processing to change the address of image data based on the results of comparing image data between different frames. Changing the address of image data makes it possible to use part of the image data of the previous frame. This configuration makes it possible to reduce the amount of image data supplied from an external device.

[0176] In this embodiment, a modified example of a structure of a display device according to one embodiment of the present invention will be described. Note that in this embodiment, repeated description of components having the same reference numerals as those in the above embodiment may be omitted.

[0177] 18A and 19 are perspective views of a display device 100A according to one embodiment of the present invention. FIG. 18B is a block diagram illustrating a configuration of the display device 100A. The display device 100A includes an element layer 30 over an element layer 20 and a sealing substrate 40 over the element layer 30. The element layer 30 includes a display unit 31 and a memory unit 71, and a light-emitting element layer 60 is provided between the sealing substrate 40 and the display unit 31. In FIG. 19 , the element layer 20, the element layer 30, the light-emitting element layer 60, the sealing substrate 40, and the like are shown separated from each other to make the configuration of the display device 100A easier to understand.

[0178] In this embodiment, a part or all of the memory unit 71 included in the processor circuit unit 70 provided in the element layer 20 is provided in the element layer 30. The rest of the description of the element layer 20 is the same as that in the first embodiment.

[0179] The element layer 30 is provided with a display unit 31, as in the first embodiment. As described above, the element layer 30 is also provided with a memory unit 71. The memory unit 71 provided in the element layer 30 includes a plurality of memory circuits 72. In the configuration of the display device 100A, the display unit 31 and the memory unit 71 are each provided in the element layer 30.

[0180] The memory unit 71 has a function of storing programs or data used in the processor circuit unit 70. The memory unit 71 can be provided overlapping the processor circuit unit 70. Some circuits provided in the processor circuit unit 70 can be arranged in an element layer 30 different from the element layer 20, thereby reducing the area of ​​the processor circuit unit 70. The layout area of ​​the memory unit 71 provided in the element layer 30 (the area of ​​the region where the memory circuit 72 is arranged) can be larger than the layout area of ​​the memory unit 71 provided in the processor circuit unit 70, thereby increasing the storage capacity for storing programs or data used in the processor circuit unit 70. Note that the memory circuit 72 included in the memory unit 71 and the pixel circuit 51 included in the display unit 31 both include OS transistors.

[0181] The storage unit 71 may be a nonvolatile oxide semiconductor random access memory (NOSRAM) or a dynamic oxide semiconductor random access memory (DOSRAM).

[0182] NOSRAM is a memory in which the memory cells are two-transistor (2T) or three-transistor (3T) gain cells and the access transistors are OS transistors. OS transistors have extremely small leakage currents, which are currents that flow between the source and drain in the off state. NOSRAM allows data to be read without destroying the data (non-destructive readout).

[0183] DOSRAM refers to a RAM having 1T (transistor) 1C (capacitor) type memory cells. Like NOSRAM, DOSRAM is a memory that utilizes the low off-state current of OS transistors.

[0184] NOSRAM and DOSRAM are types of memory devices that use OS transistors.

[0185] The memory circuit 72 included in the memory unit 71 and the pixel circuit 51 included in the display unit 31 include OS transistors. With this configuration, the display unit 31 and the memory unit 71 can be arranged in the element layer 30. By arranging the memory unit 71 and the display unit 31 in the same layer, the memory unit 71 can be arranged in a region of the element layer 30 where the display unit 31 is not arranged.

[0186] 19 , the storage unit 71 is provided in a region that overlaps with the processor circuit unit 70, around the region where the display unit 31 is provided. The storage unit 71 can be configured to be provided in at least a part of the region around the display unit 31. With this configuration, the storage unit 71 can be arranged so as to fill the region of the element layer 30 where the display unit 31 is not provided. Therefore, the storage capacity can be increased by arranging the storage unit 71 without compromising the display quality, such as by reducing the area of ​​the display unit 31.

[0187] The storage unit 71 connected to the processor circuit unit 70 can also be used as a storage unit for saving (backing up) programs or data used in the processor circuit unit 70. In this way, a normally-off CPU (also referred to as an "Noff-CPU") can be realized by combining a storage unit using an OS transistor with a processor circuit. An Noff-CPU is an integrated circuit including normally-off transistors that are in a non-conducting state (also referred to as an off state) even when a gate voltage of 0 V is applied.

[0188] A Noff-CPU can stop the power supply to circuits within the Noff-CPU that are not required to operate, putting those circuits into a standby state. Circuits that have had their power supply stopped and are now in a standby state do not consume power. Therefore, a Noff-CPU can minimize power consumption. Furthermore, a Noff-CPU can retain information necessary for operation, such as setting conditions, for a long period of time even if power supply is stopped. To return from a standby state, it is sufficient to simply resume power supply to the circuit, and there is no need to rewrite setting conditions, etc. For example, a high-speed return from a standby state is possible. In this way, a Noff-CPU can reduce power consumption without significantly reducing operating speed.

[0189] 19, the storage capacity of the storage unit 71 connected to the processor circuit unit 70 can be increased, making it suitable for storing data (weight data) corresponding to weight parameters used in the product-sum calculations of the neural network. In this case, the processor circuit unit 70 can execute the product-sum calculations using the weight data in the storage unit 71. By configuring the processor circuit unit 70 to perform parallel processing of the product-sum calculations of the neural network, it is possible to process large amounts of input data simultaneously, enabling data processing in a short period of time.

[0190] Next, configuration examples of memory cells including OS transistors will be described with reference to Fig. 20A to Fig. 20H. Note that memory circuits 72A to 72H shown in Fig. 20A to Fig. 20H are memory cells using OS transistors, and Fig. 20A to Fig. 20F can be roughly classified as NOSRAMs, and Fig. 20G and Fig. 20H can be roughly classified as DOSRAMs.

[0191] 20A shows an example of a circuit configuration applicable to the memory circuit 72. Here, the memory circuit 72A is a two-transistor (2T) gain cell. The memory circuit 72A includes transistors MW1 and MR1 and a capacitor CS1. The transistor MW1 is a write transistor, and the transistor MR1 is a read transistor. The back gates of the transistors MW1 and MR1 are connected to a wiring BGL.

[0192] Since the read transistor is an OS transistor, the memory circuit 72A does not consume power to retain data. Therefore, the memory circuit 72A is a low-power memory cell that can retain data for a long period of time, and the memory unit 71 can be used as a nonvolatile memory device.

[0193] The memory circuit 72B shown in FIG. 20B is a 3T-type gain cell and includes transistors MW2, MR2, MS2, and a capacitor CS2. The transistors MW2, MR2, and MS2 are a write transistor, a read transistor, and a select transistor, respectively. The back gates of the transistors MW2, MR2, and MS2 are connected to a wiring BGL. The memory circuit 72B is connected to word lines RWL and WWL, bit lines RBL and WBL, a capacitance line CDL, and a power supply line PL2. For example, a voltage GND (low-level power supply voltage) is input to the capacitance line CDL and the power supply line PL2.

[0194] 20C and 20D show other configuration examples of a 2T gain cell. In a memory circuit 72C shown in FIG. 20C, the readout transistor is an n-channel Si transistor. In a memory circuit 72D shown in FIG. 20D, the readout transistor is a p-channel Si transistor. As shown in FIGS. 20C and 20D, a configuration in which an OS transistor and a Si transistor are combined as transistors in a memory cell may also be used.

[0195] Since metal oxides used in OS transistors are n-type (n-channel) metal oxides, such as In—Ga—Zn oxide, a complementary metal oxide semiconductor (CMOS) circuit can be formed by combining an OS transistor with a Si transistor to form a memory cell. Therefore, compared with a memory cell formed solely with n-channel transistors, a circuit having both high driving capability due to the use of Si transistors and low power consumption due to the low off-state current of the OS transistor can be realized. Furthermore, since there is no need to separately fabricate n-type (n-channel) and p-type (p-channel) Si transistors, the process cost of the transistors can be reduced.

[0196] 20E and 20F show other configuration examples of a 3T gain cell. In a memory circuit 72E shown in Fig. 20E, the readout transistor and the selection transistor are configured as n-channel Si transistors. In a memory circuit 72F shown in Fig. 20F, the readout transistor and the selection transistor are configured as p-channel Si transistors. In the example of Fig. 20F, a voltage Vdd (high-level power supply voltage) is input to the power supply line PL2.

[0197] In the above-described gain cell, a bit line that serves as both a read bit line RBL and a write bit line WBL may be provided.

[0198] 20G and 20H show examples of a 1T1C (capacitor) type memory cell. A memory circuit 72G shown in FIG. 20G is connected to a word line WL, a bit line BL, a capacitance line CDL, and a wiring BGL. The memory circuit 72G has a transistor MW3 and a capacitor CS3. The back gate of the transistor MW3 is connected to the wiring BGL. The memory circuit 72H shown in FIG. 20H illustrates the configuration of a ferroelectric memory using a capacitor FE1 having a ferroelectric material in the capacitor CS3. For example, the ferroelectric material may be HfZrO Ｘ can be used.

[0199] The circuit configuration of the memory circuit 72 in the memory portion 71 can be a circuit configuration including only OS transistors, a circuit configuration including a combination of OS transistors and Si transistors, or the like.

[0200] 21A shows an example of the circuit configuration of a memory cell (memory circuit 72E). Fig. 21B is a diagram schematically showing the hierarchical relationship between the element layer 20 including the processor circuit unit 70, the element layer 30 including the memory circuit 72, and the light-emitting element layer 60. Note that in the memory unit 71 in which the memory circuit 72E is provided, the configuration of the light-emitting element layer 60 is not shown, but for example, the light-emitting element layer 60 may be provided with a light-emitting element 61.

[0201] 21A and 21B include transistors MW2, MR2, MS2, and a capacitor CS2. The transistor MW2 can be an OS transistor, and the transistors MR2 and MS2 can be Si transistors. For example, as shown in FIG. 21B, the transistors MR2 and MS2 are provided in the element layer 20, and the transistor MW2 is provided in the element layer 30. Note that although the capacitor CS2 is illustrated in the element layer 30, it may also be provided in the element layer 20. Furthermore, although the wirings (word lines RWL, WWL, bit lines RBL, WBL) and the like are illustrated in the element layer 20, they may also be provided in the element layer 30.

[0202] As described above, the display device 100A of this embodiment has a configuration in which an element layer having the display unit 31 and the memory unit 71 is stacked with an element layer having the display driver 22 and the processor circuit unit 70. By stacking the layers in which each circuit is provided, the display device 100A can be made smaller. Furthermore, since the display driver 22 can be provided overlapping the display unit 31, the area of ​​the display unit 31 can be increased. This increases the resolution of the display unit 31, thereby improving the display quality of the display device 100A.

[0203] Furthermore, by stacking the element layer having the memory unit 71 and the element layer having the processor circuit unit 70, the wiring connecting them can be shortened. This reduces the wiring resistance and parasitic capacitance, and increases the operating speed of the processor circuit unit 70. Furthermore, the power consumption of the display device 100A is reduced.

[0204] In this embodiment, a modified example of a structure of a display device according to one embodiment of the present invention will be described. Note that in this embodiment, repeated description of components having the same reference numerals as those in the above embodiment may be omitted.

[0205] 22A and 23 are perspective views of a display device 100B according to one embodiment of the present invention. FIG. 22B is a block diagram illustrating a configuration of the display device 100B. The display device 100B includes an element layer 30A over an element layer 20, an element layer 30B over the element layer 30A, and a sealing substrate 40 over the element layer 30B. The element layer 30B includes a display unit 31, and a light-emitting element layer 60 is provided between the sealing substrate 40 and the display unit 31. The element layer 30A also includes a memory unit 71. In FIG. 23 , the element layer 20, the element layer 30A, the element layer 30B, the light-emitting element layer 60, the sealing substrate 40, and the like are shown separated from one another to make the configuration of the display device 100B easier to understand.

[0206] The description of the element layer 20 is the same as that in the first embodiment.

[0207] The memory unit 71 provided in the element layer 30A includes a plurality of memory circuits 72. The description in Embodiment 3 may be referred to for a configuration example of the memory circuits 72 included in the memory unit 71. In the configuration of the display device 100B, the display unit 31 and the memory unit 71 are provided in different layers, that is, the element layer 30A and the element layer 30B, respectively. This allows the display unit 31 to have a larger area and the memory unit 71 to have a larger capacity. Note that although the memory circuits 72 included in the memory unit 71 and the pixel circuits 51 included in the display unit 31 are provided in different layers, they both include OS transistors.

[0208] In one embodiment of the present invention, the storage unit 71 can be provided in the element layer 30A, which is an element layer different from the element layer 30B in which the display unit 31 is provided. This increases the storage capacity of the display device 100B and the display area. The storage unit 71 can be used as a storage circuit that stores programs or data used in the processor circuit unit 70.

[0209] As described above, the display device 100B of one embodiment of the present invention has a stacked structure including an element layer including the display portion 31, an element layer including the memory portion 71, and an element layer including the display driver portion 22 and the processor circuit portion 70. Stacking the layers including the circuits can reduce the size of the display device 100B. Furthermore, since the display driver portion 22 can be provided overlapping the display portion 31, the area of ​​the display portion 31 can be increased. Therefore, the resolution of the display portion 31 can be increased, and the display quality of the display device 100B can be improved.

[0210] Furthermore, by stacking an element layer having the display unit 31, an element layer having the memory unit 71, and an element layer having the display driver 22 and the processor circuit unit 70, it is possible to shorten the wiring connecting them. This reduces wiring resistance and parasitic capacitance, allowing the operating speed of the display device 100B to be increased. Furthermore, the power consumption of the display device 100B is reduced.

[0211] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0212] Embodiment 5 In this embodiment, a structural example of a display module to which a display device of one embodiment of the present invention can be applied will be described.

[0213] The display device of this embodiment can be a high-resolution display panel. For example, the display device of one embodiment of the present invention can be used for a display portion of a wristwatch-type or bracelet-type information terminal (wearable device), a VR device such as a head-mounted display, or a head-mountable wearable device such as a glasses-type AR device.

[0214] 24A shows a perspective view of a display module 980. The display module 980 includes a display device 200A and an FPC 990. Note that the display panel included in the display module 980 is not limited to the display device 200A, and may be a display device 200B described later.

[0215] The display module 980 includes a substrate 991 and a substrate 992. The display module 980 includes a display portion 981. The display portion 981 is a region for displaying an image.

[0216] 24B is a perspective view schematically illustrating the configuration on the substrate 991 side. A circuit portion 982, a display portion 983 on the circuit portion 982, and a pixel portion 984 on the display portion 983 are stacked on the substrate 991. A terminal portion 985 for connecting to an FPC 990 is provided in a portion of the substrate 991 that does not overlap with the pixel portion 984. The terminal portion 985 and the circuit portion 982 are connected by a wiring portion 986 composed of a plurality of wirings.

[0217] The layer including the circuit portion 982 can be applied with circuits having each structure included in the element layer 20 described in the above-described Embodiment 1 and the like. In addition to the pixel circuit 983a, circuits included in the memory portion or the like included in the element layer 30 described in the above-described Embodiment 1 and the like can be applied to the layer including the display portion 983. By appropriately increasing the number of layers in which elements are provided, the circuits having each structure included in the element layer 20 described in the above-described Embodiment 1 and the like can be applied.

[0218] The pixel portion 984 has a plurality of periodically arranged pixels 984a. An enlarged view of one pixel 984a is shown on the right side of Fig. 24B. The pixel 984a has a light-emitting device 410R that emits red light, a light-emitting device 410G that emits green light, and a light-emitting device 410B that emits blue light.

[0219] The display portion 983 includes a plurality of pixel circuits 983a arranged periodically. Each pixel circuit 983a controls light emission of three light-emitting devices included in one pixel 984a. As described in Embodiment 1, a memory portion (not shown) may be provided in the layer where the display portion 983 is provided. Alternatively, the pixel circuit 983a may include a memory cell (not shown) included in the memory portion. Each pixel circuit 983a may include three circuits for controlling light emission of one light-emitting device. For example, the pixel circuit 983a may include at least one selection transistor, one current control transistor (drive transistor), and a capacitor for each light-emitting device. A gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This achieves an active matrix display panel.

[0220] The circuit portion 982 includes a circuit for driving each pixel circuit 983a in the display portion 983. For example, it preferably includes one or both of a gate line driver circuit and a source line driver circuit. In addition, it may include at least one of an arithmetic circuit, a memory circuit, a power supply circuit, and the like. Furthermore, a transistor provided in the circuit portion 982 may constitute part of the pixel circuit 983a. For example, the pixel circuit 983a may include a transistor included in the display portion 983 and a transistor included in the circuit portion 982.

[0221] The FPC 990 functions as wiring for supplying a video signal, a power supply voltage, and the like from the outside to the circuit portion 982. An IC may be mounted on the FPC 990.

[0222] The display module 980 can have a structure in which a layer having a display portion 983 and a layer having a circuit portion 982 are stacked below the pixel portion 984, thereby enabling the aperture ratio (effective display area ratio) of the display portion 981 to be extremely high. For example, the aperture ratio of the display portion 981 can be set to 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less. Furthermore, the pixels 984a can be arranged at extremely high density, thereby enabling the resolution of the display portion 981 to be extremely high. For example, the pixels 984a are preferably arranged in the display portion 981 at a resolution of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more.

[0223] Because such a display module 980 has extremely high resolution, it can be suitably used in VR devices such as head-mounted displays or glasses-type AR devices. For example, even in a configuration in which the display unit of the display module 980 is viewed through lenses, the display module 980 has an extremely high-resolution display unit 981, so that even when the display unit is enlarged with lenses, the pixels are not visible, allowing for a highly immersive display. Furthermore, the display module 980 is not limited to this, and can be suitably used in electronic devices having relatively small display units. For example, it can be suitably used in the display unit of a wearable electronic device such as a wristwatch.

[0224] [Display Device 200A] A display device 200A illustrated in FIG. 25 has a stacked structure of a transistor 810 in which a channel is formed in a substrate 801 and a transistor 820 in which a channel is formed and a semiconductor layer containing metal oxide.

[0225] Substrate 801 corresponds to substrate 991 in FIGS. 24A and 24B.

[0226] The transistor 810 has a channel formation region in a substrate 801. The substrate 801 can be, for example, a semiconductor substrate such as a single crystal silicon substrate. The transistor 810 includes a part of the substrate 801, a conductive layer 811, a low-resistance region 812, an insulating layer 813, and an insulating layer 814. The conductive layer 811 functions as a gate electrode. The insulating layer 813 is located between the substrate 801 and the conductive layer 811 and functions as a gate insulating layer. The low-resistance region 812 is a region in which the substrate 801 is doped with impurities and functions as one of a source and a drain. The insulating layer 814 is provided to cover a side surface of the conductive layer 811.

[0227] An element isolation layer 815 is provided between two adjacent transistors 810 so as to be buried in the substrate 801 .

[0228] An insulating layer 961 is provided to cover the transistor 810, and a conductive layer 951 is provided over the insulating layer 961. An insulating layer 962 is provided to cover the conductive layer 951, and a conductive layer 952 is provided over the insulating layer 962. The conductive layer 951 and the conductive layer 952 each function as a wiring. An insulating layer 963 and an insulating layer 832 are provided to cover the conductive layer 952, and the transistor 820 is provided over the insulating layer 832.

[0229] The transistor 820 is a transistor (OS transistor) in which a metal oxide (also referred to as an oxide semiconductor) is used for a semiconductor layer in which a channel is formed.

[0230] The transistor 820 includes a semiconductor layer 821 , an insulating layer 823 , a conductive layer 824 , a pair of conductive layers 825 , an insulating layer 826 , and a conductive layer 827 .

[0231] An insulating layer 832 is provided over the insulating layer 963. The insulating layer 832 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 963 to the transistor 820 and prevents oxygen from being released from the semiconductor layer 821 toward the insulating layer 832. The insulating layer 832 can be, for example, a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0232] A conductive layer 827 is provided over the insulating layer 832, and an insulating layer 826 is provided to cover the conductive layer 827. The conductive layer 827 functions as a first gate electrode of the transistor 820, and part of the insulating layer 826 functions as a first gate insulating layer. An oxide insulating film such as a silicon oxide film is preferably used for at least a portion of the insulating layer 826 that is in contact with the semiconductor layer 821. The top surface of the insulating layer 826 is preferably planarized.

[0233] The semiconductor layer 821 is provided over the insulating layer 826. The semiconductor layer 821 preferably includes a metal oxide (also referred to as an oxide semiconductor) film exhibiting semiconductor characteristics. A pair of conductive layers 825 is provided over and in contact with the semiconductor layer 821 and functions as a source electrode and a drain electrode.

[0234] An insulating layer 828 is provided to cover top surfaces and side surfaces of the pair of conductive layers 825 and side surfaces of the semiconductor layer 821, and an insulating layer 964 is provided over the insulating layer 828. The insulating layer 828 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 964 or the like to the semiconductor layer 821 and prevents oxygen from being released from the semiconductor layer 821. The insulating layer 828 can be an insulating film similar to the insulating layer 832.

[0235] An opening reaching the semiconductor layer 821 is provided in the insulating layer 828 and the insulating layer 964. An insulating layer 823 in contact with the top surface of the semiconductor layer 821 and a conductive layer 824 are buried in the opening. The conductive layer 824 functions as a second gate electrode, and the insulating layer 823 functions as a second gate insulating layer.

[0236] The top surface of the conductive layer 824, the top surface of the insulating layer 823, and the top surface of the insulating layer 964 are planarized so that their heights are the same or approximately the same, and insulating layers 829 and 965 are provided to cover them.

[0237] The insulating layers 964 and 965 function as interlayer insulating layers. The insulating layer 829 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 965 or the like to the transistor 820. The insulating layer 829 can be formed using an insulating film similar to the insulating layers 828 and 832.

[0238] A plug 974 connected to one of the pair of conductive layers 825 is provided so as to be embedded in the insulating layer 965, the insulating layer 829, and the insulating layer 964. Here, the plug 974 is preferably configured so that the side surfaces of the openings of the insulating layer 965, the insulating layer 829, the insulating layer 964, and the insulating layer 828 and part of the top surface of the conductive layer 825 are covered with the conductive layer. In this case, the conductive layer covering the plug 974 is preferably made of a conductive material through which hydrogen and oxygen do not easily diffuse.

[0239] Furthermore, a capacitor 840 is provided on the insulating layer 965. The capacitor 840 and the transistor 820 are connected by a plug 974.

[0240] The transistor 820 can be used as a transistor that forms a pixel circuit. The transistor 810 can be used as a transistor that forms a pixel circuit or a transistor that forms a driver circuit (gate line driver circuit, source line driver circuit) for driving the pixel circuit. The transistors 810 and 820 can be used as transistors that form various circuits such as memory cells.

[0241] The capacitor 840 has a conductive layer 941, a conductive layer 945, and an insulating layer 943 located therebetween. The conductive layer 941 functions as one electrode of the capacitor 840, the conductive layer 945 functions as the other electrode of the capacitor 840, and the insulating layer 943 functions as a dielectric of the capacitor 840.

[0242] The conductive layer 941 is provided over the insulating layer 961 and is buried in the insulating layer 954. The conductive layer 941 is connected to one of the source and the drain of the transistor 810 by a plug 971 buried in the insulating layer 961. The insulating layer 943 is provided to cover the conductive layer 941. The conductive layer 945 is provided in a region overlapping with the conductive layer 941 with the insulating layer 943 interposed therebetween.

[0243] An insulating layer 955a is provided to cover the capacitor 840, an insulating layer 955b is provided over the insulating layer 955a, and an insulating layer 955c is provided over the insulating layer 955b.

[0244] An inorganic insulating film can be preferably used for each of the insulating layers 955a, 955b, and 955c. For example, it is preferable to use a silicon oxide film for the insulating layer 955a and the insulating layer 955c, and a silicon nitride film for the insulating layer 955b. This allows the insulating layer 955b to function as an etching protection film. In this embodiment, an example is shown in which part of the insulating layer 955c is etched to form a recess, but the insulating layer 955c does not necessarily have to have a recess.

[0245] The light emitting device 410R, the light emitting device 410G, and the light emitting device 410B are provided on the insulating layer 955c.

[0246] In the display device 200A, a separate light-emitting device is fabricated for each emitted color, resulting in minimal change in chromaticity between low-luminance and high-luminance emission. Furthermore, because the organic layers 412R, 412G, and 412B are spaced apart from one another, crosstalk between adjacent subpixels can be suppressed even in a high-resolution display panel. This allows for the realization of a high-resolution, high-quality display panel.

[0247] In the region between adjacent light emitting devices, an insulating layer 425, a resin layer 426, and a layer 428 are provided.

[0248] The pixel electrodes 411R, 411G, and 411B of the light-emitting device are connected to one of the source and drain of the transistor 810 via a plug 956 embedded in insulating layers 955a, 955b, and 955c, a conductive layer 941 embedded in insulating layer 954, and a plug 971 embedded in insulating layer 961. The height of the top surface of the insulating layer 955c and the height of the plug 956 are the same or approximately the same. Various conductive materials can be used for the plug. Note that the pixel electrodes 411R, 411G, and 411B may be collectively referred to as pixel electrodes 411.

[0249] A protective layer 421 is provided on the light-emitting devices 410R, 410G, and 410B. A substrate 470 is attached to the protective layer 421 with an adhesive layer 471.

[0250] No insulating layer covering the upper end of each pixel electrode 411 is provided between two adjacent pixel electrodes 411. This allows the distance between adjacent light-emitting devices to be extremely narrow, resulting in a high-definition or high-resolution display device.

[0251] With this configuration, not only pixel circuits but also driving circuits etc. can be formed directly below the light-emitting device, which makes it possible to make the display panel smaller than when driving circuits are provided around the periphery of the display area.

[0252] 26 has a stacked structure of a transistor 820A containing a metal oxide in a semiconductor layer in which a channel is formed and a transistor 820B containing a metal oxide in a semiconductor layer in which a channel is formed. This structure allows the use of transistors in which the metal oxide in the semiconductor layer has a different composition of constituent elements. Therefore, a display device using OS transistors with different transistor characteristics can be provided. For example, the upper transistor 820A can be used as a transistor in a pixel circuit that drives a light-emitting device, and the lower transistor 820B can be used as a transistor in a memory cell.

[0253] This configuration allows the circuits located directly below the light-emitting devices to be arranged more densely, making it possible to make the display panel smaller than when the driving circuits are located around the periphery of the display area.

[0254] [Display Devices 200C and 200D] Display device 200C shown in Fig. 27 has a configuration in which an insulating layer 423 and a lens 424 are added to display device 200A. Display device 200D shown in Fig. 28 has a configuration in which an insulating layer 423 and a lens 424 are added to display device 200B.

[0255] The display device of one embodiment of the present invention preferably includes a lens array (e.g., a microlens array) overlapping with the light-emitting device. By providing the lens array overlapping with the light-emitting device, light emitted from the light-emitting device can be efficiently utilized. This allows a highly reliable display device to be realized.

[0256] 27 shows an example in which lenses 424 are provided on light-emitting devices 410R, 410G, and 410B via a protective layer 421 and an insulating layer 423. By forming the lenses 424 directly on the substrate on which the light-emitting devices are formed, it is possible to improve the accuracy of alignment between the light-emitting devices and the lens array.

[0257] 27 shows an example in which a layer having a planarization function is used as the insulating layer 423. For example, it is preferable to use an inorganic material for the protective layer 421 and an organic material for the insulating layer 423. Alternatively, the lens 424 may be provided directly on the protective layer 421 without using the insulating layer 423.

[0258] The convex surface of the lens 424 may face the substrate 470 side or the light-emitting device side.

[0259] The lens 424 can be formed using at least one of an inorganic material and an organic material. For example, a material containing a resin can be used for the lens. Alternatively, a material containing at least one of an oxide and a sulfide can be used for the lens. The lens 424 can be formed directly on the substrate or the light-emitting device, or a separately formed lens array can be attached to the substrate or the light-emitting device.

[0260] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0261] Embodiment 6 In this embodiment, electronic devices to which a display device according to one embodiment of the present invention can be applied will be described.

[0262] A display device according to one embodiment of the present invention can be applied to a display portion of an electronic device. Therefore, an electronic device with high display quality, extremely high resolution, or high reliability can be realized.

[0263] Examples of electronic devices using a display device according to one embodiment of the present invention include display devices such as televisions and monitors, lighting devices, desktop or notebook personal computers, word processors, and DVD (Digital Versatile Examples of such equipment include image playback devices that play back still images or videos stored on recording media such as a CD (disc), portable CD players, radios, tape recorders, headphone stereos, stereos, table clocks, wall clocks, cordless telephone handsets, transceivers, car phones, mobile phones, personal digital assistants, tablet terminals, portable game machines, fixed game machines such as pachinko machines, calculators, electronic organizers, e-book terminals, electronic translators, voice input devices, video cameras, digital still cameras, electric shavers, high-frequency heating devices such as microwave ovens, air conditioning equipment such as electric rice cookers, electric washing machines, electric vacuum cleaners, hot water heaters, electric fans, hair dryers, air conditioners, humidifiers, and dehumidifiers, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerator-freezers, DNA storage freezers, flashlights, and tools such as chainsaws, smoke detectors, and medical equipment such as dialysis machines. Further examples include industrial equipment such as emergency lights, traffic lights, conveyor belts, elevators, escalators, industrial robots, power storage systems, and power storage devices for power leveling and smart grids. Mobile bodies propelled by fuel-powered engines or electric motors powered by power from power storage devices may also be included in the category of electronic devices. Examples of such mobile bodies include electric vehicles (EVs), hybrid vehicles (HVs) equipped with both internal combustion engines and electric motors, plug-in hybrid vehicles (PHVs), tracked vehicles in which the tires and wheels of these vehicles are replaced with tracks, mopeds including electrically assisted bicycles, motorcycles, electric wheelchairs, golf carts, small or large ships, submarines, helicopters, aircraft, rockets, artificial satellites, space probes, planetary probes, and spaceships.

[0264] An electronic device according to one embodiment of the present invention may include a secondary battery (battery), and it is preferable that the secondary battery can be charged using contactless power transmission.

[0265] Examples of secondary batteries include lithium ion secondary batteries, nickel-metal hydride batteries, nickel-cadmium batteries, organic radical batteries, lead-acid batteries, air secondary batteries, nickel-zinc batteries, and silver-zinc batteries.

[0266] An electronic device according to one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0267] An electronic device according to one embodiment of the present invention may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0268] An electronic device according to one embodiment of the present invention can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, etc.

[0269] Furthermore, electronic devices having multiple display units can have a function of mainly displaying image information on one part of the display units and mainly displaying text information on another part, or a function of displaying a stereoscopic image by displaying an image taking into account parallax on the multiple display units. Furthermore, electronic devices having an image receiving unit can have a function of capturing a still image or a video, a function of automatically or manually correcting the captured image, a function of storing the captured image in a recording medium (external or built in the electronic device), a function of displaying the captured image on the display unit, etc. Note that the functions of the electronic device of one embodiment of the present invention are not limited to these, and can have various functions.

[0270] A display device according to one embodiment of the present invention can display high-resolution images. Therefore, the display device can be suitably used in portable electronic devices, wearable electronic devices, e-book readers, etc. For example, the display device can be suitably used in xR devices such as VR devices and AR devices.

[0271] 29A shows the appearance of a head-mounted display 710. The head-mounted display 710 includes a mounting portion 711, a lens 712, a main body 713, a display portion 714, a cable 715, and the like. A battery 716 is built into the mounting portion 711. A display device according to one embodiment of the present invention can be applied to the display portion 714.

[0272] A cable 715 supplies power from a battery 716 to the main body 713. The main body 713 is equipped with a wireless receiver and the like, and can display received video information such as image data on a display unit 714. In addition, a camera provided in the main body 713 captures the movement of the user's eyeballs and / or eyelids, and calculates the user's line of sight based on the information, thereby enabling the user's line of sight to be used as an input means.

[0273] The attachment unit 711 may also be provided with a plurality of electrodes at positions that come into contact with the user. The main body 713 may have a function of recognizing the user's line of sight by detecting current flowing through the electrodes in accordance with the movement of the user's eyeballs. The main body 713 may also have a function of monitoring the user's pulse by detecting the current flowing through the electrodes. The attachment unit 711 may also have various sensors such as a temperature sensor, a pressure sensor, an acceleration sensor, etc., and may have a function of displaying the user's biological information on the display unit 714. The attachment unit 711 may also detect the movement of the user's head, and change the image displayed on the display unit 714 in accordance with the movement.

[0274] 29B shows the appearance of the head-mounted display 720. The head-mounted display 720 is a goggle-type information processing device.

[0275] The head-mounted display 720 includes a housing 721, operation buttons 723, a band-shaped fixture 724, and two display units 722. The two display units 722 allow the user to view one display unit per eye. This allows high-resolution images to be displayed, even when performing 3D display using parallax. The fixture 724 is also provided with a battery 725. While the battery 725 may be provided in the housing 721, providing the battery 725 in the fixture 724 is preferable because it allows the center of gravity of the head-mounted display 720 to be positioned rearward, improving the wearing comfort for the user. In addition to the battery 725, a drive circuit for operating the display units 722 may also be provided in the fixture 724 to adjust the center of gravity of the head-mounted display 720.

[0276] The operation button 723 has a function of a power button, etc. In addition to the operation button 723, other buttons may be provided.

[0277] A display device according to one embodiment of the present invention can be applied to the display portion 722. The display device according to one embodiment of the present invention has extremely high definition, and therefore, pixels are less visible to a user, and more realistic images can be displayed.

[0278] FIG. 29C shows the exterior of camera 730 with viewfinder 740 .

[0279] The camera 730 includes a housing 731, a display portion 732, operation buttons 733, a shutter button 734, etc. A detachable lens 736 is attached to the camera 730.

[0280] Here, the camera 730 has a structure in which the lens 736 can be detached from the housing 731 and replaced, but the lens 736 and the housing may be integrated.

[0281] The camera 730 can capture an image by pressing a shutter button 734. The display portion 732 also functions as a touch panel, and an image can be captured by touching the display portion 732.

[0282] The housing 731 of the camera 730 has a mount with electrodes, and can be connected to a finder 740 as well as a strobe device and the like.

[0283] The finder 740 includes a housing 741, a display portion 742, a button 743, and the like.

[0284] The housing 741 has a mount that engages with the mount of the camera 730, and the viewfinder 740 can be attached to the camera 730. The mount also has electrodes, and images received from the camera 730 can be displayed on the display unit 742 via the electrodes.

[0285] The button 743 functions as a power button, and can be used to switch the display of the display unit 742 on and off.

[0286] The display device according to one embodiment of the present invention can be applied to the display portion 732 of the camera 730 and the display portion 742 of the finder 740 .

[0287] Note that in FIG. 29C , the camera 730 and the finder 740 are separate electronic devices that are detachable; however, a finder including a display device according to one embodiment of the present invention may be built into the housing 731 of the camera 730.

[0288] 29D includes a housing 751, a display portion 752, a microphone 757, a speaker portion 754, a camera 753, an operation switch 755, and the like. A display device according to one embodiment of the present invention can be used for the display portion 752. The display portion 752 has a touch panel function. The information terminal 750 includes an antenna, a battery, and the like inside the housing 751. The information terminal 750 can be used as, for example, a smartphone, a mobile phone, a tablet information terminal, a tablet personal computer, an e-book reader, or the like.

[0289] 29E shows an example of a wristwatch-type information terminal. Information terminal 760 includes a housing 761, a display unit 762, a band 763, a buckle 764, operation switches 765, an input / output terminal 766, and the like. Information terminal 760 also includes an antenna, a battery, and the like inside housing 761. Information terminal 760 can execute various applications such as mobile phone calls, e-mail, text browsing and creation, music playback, internet communication, and computer games.

[0290] The display unit 762 also has a touch sensor, allowing operation by touching the screen with a finger or a stylus. For example, an application can be started by touching an icon 767 displayed on the display unit 762. The operation switch 765 can have various functions, such as time setting, power on / off operation, wireless communication on / off operation, silent mode activation / deactivation, and power saving mode activation / deactivation. For example, the functions of the operation switch 765 can be set by an operating system incorporated in the information terminal 760.

[0291] The information terminal 760 is also capable of performing short-range wireless communication according to a communication standard. For example, hands-free conversation is also possible by mutual communication with a wirelessly enabled headset. The information terminal 760 is also provided with an input / output terminal 766, and can transmit and receive data to and from other information terminals via the input / output terminal 766. Charging can also be performed via the input / output terminal 766. Note that charging may be performed by wireless power supply without using the input / output terminal 766.

[0292] 29A to 29E , electronic devices to which the display device according to one embodiment of the present invention can be applied may be connected to an external server via a network. Alternatively, the electronic device may not perform processing requiring high computing power, but may instead perform the processing requiring high computing power on a server connected via a network. This type of processing is also referred to as a thin client. A user (client) terminal (the electronic device in this case) performs only limited processing, while the server performs advanced processing, such as application execution and management, on the server side, thereby reducing the scale of processing on the client side. This eliminates the need for a computing device with high computing performance in the electronic device, thereby facilitating cost reduction, weight reduction, and miniaturization. Furthermore, the electronic device according to one embodiment of the present invention may perform processing by combining the thin client and processing requiring high computing power on the electronic device side.

[0293] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes or the like.

[0294] <Additional Notes Regarding the Description of the Present Specification, etc.> The following additional notes are provided regarding the above-described embodiments and the explanations of the respective configurations in the embodiments.

[0295] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0296] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or the content (or even a part of the content) described in one or more other embodiments.

[0297] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0298] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0299] In addition, in the present specification and the like, in the block diagrams, components are classified by function and shown as mutually independent blocks. However, in actual circuits, etc., it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately.

[0300] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0301] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like.

[0302] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0303] Furthermore, in this specification and the like, the terms voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), then voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0304] In this specification and the like, terms such as "film" and "layer" can be interchanged. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0305] In this specification, a switch refers to a device that has a function of controlling whether a current flows by being in a conductive state (on state) or a non-conductive state (off state), or a device that has a function of selecting and switching a path for a current to flow.

[0306] In this specification, the channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between a source and a drain in a region where a channel is formed.

[0307] In this specification, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0308] In this specification and the like, the "on state" of a transistor refers to, for example, a state in which the source and drain of the transistor can be considered to be short-circuited. For example, the "on state" refers to a state in which the voltage between the gate and source of an n-channel transistor is higher than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is lower than the threshold voltage. Note that the "on state" of a transistor refers to a state in which current can flow between the source and drain. Therefore, the "on state" of a transistor may also be referred to as the "conducting state" of the transistor.

[0309] In this specification and the like, the "off state" of a transistor refers to a state in which the source and drain of the transistor can be considered to be cut off. For example, the "off state" refers to a state in which the voltage between the gate and source of an n-channel transistor is lower than the threshold voltage, or a state in which the voltage between the gate and source of a p-channel transistor is higher than the threshold voltage. The "off state" of a transistor may also be referred to as the "non-conducting state" of the transistor.

[0310] In this specification and the like, the voltage between the gate and the source (gate-source) may be referred to as the “gate voltage,” the voltage between the drain and the source (drain-source) may be referred to as the “drain voltage,” and the voltage between the backgate and the source (backgate-source) may be referred to as the “backgate voltage.” Also, the current flowing from the drain to the source may be referred to as the “drain current.”

[0311] In this specification and the like, unless otherwise specified, the "off-state current" of a transistor refers to the drain current when the transistor is in an off state. Note that in this specification and the like, the off-state current and the current flowing from the gate to the source and drain (also referred to as gate leakage current) may also be referred to as leakage current.

[0312] In this specification, "connection" includes, as an example, "electrical connection." When the term "electrical connection" is used to define the connection relationship between circuit elements as a physical entity, "electrical connection" includes, as examples, "direct connection" and "indirect connection." "A and B are directly connected" refers to a case where A and B are connected without a circuit element (e.g., a transistor or a switch; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" refers to a case where A and B are connected via one or more circuit elements.

[0313] Here, when "A and B are indirectly connected," it refers to the following connection relationship, for example. That is, assuming that a circuit is operating, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, such a circuit can be defined as an entity, and "A and B are indirectly connected." Note that even if there is a time when electrical signal transmission or potential interaction does not occur between A and B, if there is a time during the operation of the circuit when electrical signal transmission or potential interaction occurs between A and B, it can be defined as "A and B are indirectly connected." Note that "A and B are indirectly connected" is a definition of the connection relationship between circuit elements as an entity. Therefore, for example, even when a power supply voltage is not supplied to a circuit and the circuit is not operating, the circuit can be defined as an entity, and "A and B are indirectly connected" (however, for example, this is limited to the case where electrical signal transmission or potential interaction occurs between A and B during the operation of the circuit when a power supply voltage is supplied to the circuit and the circuit is operating).

[0314] Specific examples of "indirect connection" are given below. First, an example of "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. Another example of "A and B are indirectly connected" is when A and B are connected via one or more switches. When "A and B are indirectly connected," assuming that the circuit is operating, it is assumed that there is at least one time when one transistor between A and B is in an on state, a conductive state, or a state in which current can flow. Note that "A and B are indirectly connected" also includes cases where there is a time when one transistor between A and B is in an off state or a non-conductive state. When "A and B are indirectly connected," if multiple transistors are connected between A and B, it is assumed that there is at least one time when each of the multiple transistors between A and B is in an on state, a conductive state, or a state in which current can flow, assuming that the circuit is operating. In other words, when "A and B are indirectly connected," it is not necessary for all of the multiple transistors to be in an on state, a conductive state, or a state in which current can flow simultaneously. Therefore, when "A and B are indirectly connected," it also includes cases where the multiple transistors between A and B are in an off state or a non-conductive state at the same time or at different times. As another example, when A and C are connected via the source and drain of transistor TrP and B and C are connected via the source and drain of transistor TrQ, it can be defined as "A and C are indirectly connected," "B and C are indirectly connected," or "A and B are indirectly connected." However, as will be described later, when a constant potential V is supplied to C from a power supply, GND, or the like, it can be said that "A and C are indirectly connected" or "B and C are indirectly connected," but it cannot be said that "A and B are indirectly connected."

[0315] While we have provided examples of cases where an "indirect connection" can and cannot be established, we will now present another example of a case where an "indirect connection" cannot be established. Even if an electrical signal exchange or potential interaction occurs between A and B during the operation of the circuit, there are exceptional cases where it cannot be said that "A and B are indirectly connected." An example of such an exceptional case is when A and B are connected via an insulator. In other words, when A and B are connected via an insulator, it cannot be said that "A and B are indirectly connected." A specific example of a case where A and B are connected via an insulator is when a capacitive element is connected between A and B. Another example of a case where A and B are connected via an insulator is when a gate insulating film of a transistor is interposed between A and B. In this case, it cannot be said that "A (the gate of the transistor) and B (the source or drain of the transistor) are indirectly connected."

[0316] Another example of a case in which it cannot be said that "A and B are indirectly connected" is when there is no timing when an electrical signal is exchanged or when potential interaction occurs between A and B. For example, a path from A to B may have multiple transistors connected via their sources and drains, and a constant potential V is supplied to a node between the transistors from a power supply, GND, or the like. In this case, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and V are indirectly connected" or "B and V are indirectly connected." Note that if A and C are connected via the source and drain of transistor TrP, and B and C are connected via the source and drain of transistor TrQ, and a constant potential V is supplied to C from a power supply, GND, or the like, it cannot be said that "A and B are indirectly connected," but it is possible to say that "A and C are indirectly connected" or "B and C are indirectly connected."

[0317] Although an example of "indirect connection" has been given above, as an example, the definition of "indirect connection" is included in the definition of "electrical connection," so if "A and B are indirectly connected," it can also be said that "A and B are electrically connected."

[0318] Next, specific examples of "direct connection" are shown. An example of "A and B are directly connected" is when A and B are connected without any circuit element between them. Note that when A and B are connected to a power supply that supplies a constant potential V or to GND without any circuit element between them, it can be said that "A and B are directly connected," "A and V are directly connected," or "B and V are directly connected." Note that even when A (or B) is connected to a constant potential V via the source and drain of a transistor, it can still be said that "A and B are directly connected." Note that because A and V or B and V are connected via the source and drain of a transistor, they cannot be said to be directly connected, and it can be said that "A and V are indirectly connected" or "B and V are indirectly connected."

[0319] Although an example of "direct connection" has been given above, as an example, the definition of "direct connection" is included in the definition of "electrical connection," so when "A and B are directly connected," it can also be said that "A and B are electrically connected."

[0320] 20: element layer, 22: display driver, 29: terminal section, 30: element layer, 31: display section, 32: gate line driver circuit, 33: source line driver circuit, 40: sealing substrate, 41: LVDS circuit, 42: serial-parallel conversion circuit, 43: latch circuit, 43M: memory circuit, 44: level shifter circuit, 45: digital-to-analog conversion circuit, 46: amplifier circuit, 47: switch circuit, 48: selection circuit, 50: pixel, 51: pixel circuit, 60: light-emitting element layer, 61: light-emitting element, 70: processor circuit section, 71: memory section, 72: memory circuit, 77: analog-to-digital conversion circuit, 78: arithmetic circuit, 80: image data correction circuit, 100: display device

Claims

A display device having a first element layer and a second element layer on the first element layer, wherein the first element layer has a first transistor, the first transistor has a semiconductor layer having a channel formation region containing silicon, the second element layer has a second transistor, the second transistor has a semiconductor layer having a channel formation region containing a metal oxide, the first element layer is provided with a display driving unit and a processor circuit unit, the display driving unit has a latch circuit having a function of holding image data and an amplifier circuit having a function of outputting an analog voltage according to the image data, the processor circuit unit has an analog-to-digital conversion circuit for converting the analog voltage into a digital signal and an arithmetic circuit for obtaining a correction value according to the digital signal, the latch circuit has a function of correcting the analog voltage by adding the correction value to the image data, A display device. 　 In claim 1, the second element layer is provided with a display unit, the display driving unit is provided in a region overlapping with the display unit, A display device. 　 In claim 1 or 2, the second element layer is provided with a display unit, the display unit has a pixel circuit for controlling the light emission of a light emitting element, the light emitting element is provided on the second element layer, A display device. 　 In claim 1, the display driving unit has a gate line driving circuit and a source line driving circuit, the processor circuit unit has a function of switching the driving frequency of the gate line driving circuit and the driving frequency of the source line driving circuit, A display device. 　 A display device having a first element layer and a second element layer on the first element layer, wherein the first element layer has a first transistor, the first transistor has a semiconductor layer having a channel formation region containing silicon, the second element layer has a second transistor, the second transistor has a semiconductor layer having a channel formation region containing a metal oxide, the first element layer is provided with a display driving unit and a processor circuit unit, the display driving unit has a latch circuit having a function of holding image data and an amplifier circuit having a function of outputting an analog voltage according to the image data, the processor circuit unit has an analog-to-digital conversion circuit for converting the analog voltage into a digital signal and an arithmetic circuit for obtaining a correction value according to the digital signal, the amplifier circuit is provided for each of a plurality of signal lines, Each of the plurality of the signal lines is electrically connected to the analog-to-digital conversion circuit via a switch circuit. The analog voltage is input to the analog-to-digital conversion circuit by sequentially turning on the switch circuits that are electrically connected to the plurality of the signal lines. The latch circuit has a function of correcting the analog voltage by adding the correction value to the image data. A display device. 　 In claim 5, The second element layer is provided with a display portion. The display driving portion is provided in a region overlapping with the display portion. A display device. 　 In claim 5 or 6, The second element layer is provided with a display portion. The display portion has a pixel circuit that controls the light emission of a light-emitting element. The light-emitting element is provided on the second element layer. A display device. 　 In claim 5, The display driving portion has a gate line driving circuit and a source line driving circuit. The processor circuit portion has a function of switching the driving frequency of the gate line driving circuit and the driving frequency of the source line driving circuit. A display device.

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