Shift register, driving circuit, driving method, display substrate, and display apparatus

Abstract

The present disclosure relates to the technical field of display. Provided are a shift register, a driving circuit, a driving method, a display substrate, and a display apparatus. The shift register comprises: an input circuit, which is configured to control the potential of a first node under the control of a first input signal from a first input end and a second input signal from a second input end; a control circuit, which is configured to control the potential of a second node to be different from the potential of the first node under the control of the potential of the first node, the second input signal, and a reset signal from a reset end; and an output circuit, which is configured to output a scanning signal under the control of the potentials of the first node and the second node.

Description

Shift register, driving circuit, driving method, display substrate and display device

[0001] This application claims priority to Chinese patent application No. 202410107450.4 filed on January 25, 2024, the contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a shift register, a driving circuit, a driving method, a display substrate, and a display device. Background Art

[0003] The gate-on-array (GOA) circuit integrated on the array substrate scans the display panel's pixel array row by row to provide gate drive signals. Common GOA circuits use inverter modules, such as Darlington inverters. These inverter modules create a DC path between the high and low voltage levels connected to the GOA circuit, affecting its stability. Summary of the Invention

[0004] The present disclosure provides a shift register, a driving circuit, a driving method, a display substrate, and a display device.

[0005] According to a first aspect, the present disclosure provides a shift register, comprising: an input circuit, configured to control the potential of a first node under the control of a first input signal from a first input terminal and a second input signal from a second input terminal; a control circuit, configured to control the potential of the second node to be different from the potential of the first node under the control of the potential of the first node, the second input signal and a reset signal from a reset terminal; and an output circuit, configured to output a scan signal under the control of the potentials of the first node and the second node.

[0006] For example, the control circuit controls the potential of the second node under the control of the potential of the first node, the second input signal and the reset signal from the reset terminal, and is configured to: charge the second node with the first voltage of the first power supply under the control of the first level of the first node, the reset signal and the second input signal; and pull down the potential of the second node under the control of the second level of the first node.

[0007] For example, the control circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor; wherein the control electrode of the first transistor is electrically connected to the second input terminal, the first electrode of the first transistor is electrically connected to the first power supply, and the second electrode of the first transistor is electrically connected to the control electrode of the third transistor; the control electrode of the second transistor is electrically connected to the reset terminal, the first electrode of the second transistor is electrically connected to the first power supply, and the second electrode of the second transistor is electrically connected to the control electrode of the third transistor; the first electrode of the third transistor is electrically connected to the first power supply, and the second electrode of the third transistor is electrically connected to the second node; the control electrode of the fourth transistor is electrically connected to the first node, the first electrode of the fourth transistor is electrically connected to the control electrode of the third transistor, and the second electrode of the fourth transistor is electrically connected to the second power supply; and the control electrode of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the second node, and the second electrode of the fifth transistor is electrically connected to the third power supply.

[0008] For example, the control circuit further includes a first capacitor; wherein a first end of the first capacitor is electrically connected to the first power source, and a second end of the first capacitor is electrically connected to the control electrode of the third transistor.

[0009] For example, the control circuit further includes a first capacitor; wherein a first end of the first capacitor is electrically connected to the control electrode of the third transistor, and a second end of the first capacitor is electrically connected to the third power supply.

[0010] For example, the output circuit includes: a shift signal output terminal configured to output a shift signal.

[0011] For example, the output circuit includes a plurality of output terminals, and the plurality of output terminals are configured to output a plurality of scanning signals, and the plurality of scanning signals are used to drive a plurality of rows of sub-pixel units.

[0012] According to a second aspect, the present disclosure provides a driving circuit comprising a plurality of cascaded shift registers provided by embodiments of the present disclosure.

[0013] For example, the first input terminal of the nth stage shift register is electrically connected to the shift signal output terminal of the n-2th stage shift register, and the second input terminal of the nth stage shift register is electrically connected to the shift signal output terminal of the n+2th stage shift register, where n is a positive integer.

[0014] According to a third aspect, the present disclosure provides a display device comprising a display panel; and a driving circuit as provided in an embodiment of the present disclosure; wherein the display panel comprises a plurality of sub-pixel units arranged in an array, and the driving circuit is used to drive the sub-pixel units.

[0015] According to the fourth aspect, the present disclosure provides a driving method, which is applied to the shift register provided by the embodiment of the present disclosure, including: controlling the potential of the first node through the input circuit under the control of the first input signal from the first input end and the second input signal from the second input end; controlling the potential of the second node to be different from the potential of the first node through the control circuit under the control of the potential of the first node, the second input signal and the reset signal from the reset end; and outputting a scan signal through the output circuit under the control of the potential of the first node and the second node.

[0016] According to the fifth aspect, the present disclosure provides a display substrate, comprising: a shift register; and a compensation circuit configured to compensate for an input signal or an output signal of the shift register to obtain multiple scanning signals to control the relative difference between the fall times of the multiple scanning signals.

[0017] For example, the compensation circuit is configured to compensate for the input signal of the shift register to obtain multiple scanning signals: compensate for multiple clock signals from multiple clock ends to control the relative difference between the fall times of the multiple clock signals, obtain multiple compensated clock signals, so that the shift register outputs multiple scanning signals based on the multiple compensated clock signals.

[0018] For example, the compensation circuit includes a plurality of compensation sub-circuits, and the number of the plurality of compensation sub-circuits is the same as the number of the plurality of clock terminals.

[0019] For example, each compensation sub-circuit in the multiple compensation sub-circuits includes a compensation resistor and a compensation capacitor; wherein the first end of the compensation resistor is electrically connected to the clock end, and the second end of the compensation resistor is electrically connected to the shift register; and the first end of the compensation capacitor is electrically connected to the clock end, and the second end of the compensation capacitor is electrically connected to the fourth power supply.

[0020] For example, the compensation circuit includes: multiple clock signal lines, configured to compensate for multiple clock signals to obtain multiple compensated clock signals; wherein the length of one clock signal line among the multiple clock signal lines is less than the length of the remaining clock signal lines among the multiple clock signal lines, or the width of one clock signal line among the multiple clock signal lines is greater than the width of the length of the remaining clock signal lines among the multiple clock signal lines.

[0021] For example, the shift register includes a plurality of driving capacitors, the number of the plurality of driving capacitors is the same as the number of the plurality of clock terminals; wherein the capacitance of one driving capacitor among the plurality of driving capacitors is smaller than the capacitance of the remaining driving capacitors among the plurality of driving capacitors.

[0022] For example, the compensation circuit includes multiple output signal lines, which are configured to compensate for the output signals of the shift register to obtain multiple scanning signals; wherein the length of one output signal line among the multiple output signal lines is smaller than the length of the remaining output signal lines among the multiple output signal lines, or the width of one output signal line among the multiple output signal lines is larger than the width of the length of the remaining output signal lines among the multiple output signal lines.

[0023] For example, the shift register includes: an input circuit, configured to control the potential of a first node under the control of a first input signal from a first input terminal and a second input signal from a second input terminal; a control circuit, configured to control the potential of a second node under the control of the potential of the first node, the second input signal and a reset signal from a reset terminal; and an output circuit, configured to output a scan signal under the control of the potentials of the first node and the second node.

[0024] According to a sixth aspect, the present disclosure further provides a display device, comprising a display substrate as provided in an embodiment of the present disclosure.

[0025] According to the seventh aspect, the present disclosure also provides a driving method, which is applied to a display substrate as provided in an embodiment of the present disclosure, including: compensating the input signal or output signal of the shift register through a compensation circuit to obtain multiple scanning signals to control the relative difference between the fall times of the multiple scanning signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG1 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure;

[0027] FIG2A is a schematic structural diagram of a shift register according to another embodiment of the present disclosure;

[0028] FIG2B is a schematic structural diagram of a shift register according to another embodiment of the present disclosure;

[0029] FIG2C is a schematic structural diagram of a shift register according to another embodiment of the present disclosure;

[0030] FIG3 is a schematic diagram of signal timing of a shift register according to an embodiment of the present disclosure;

[0031] FIG4A is a schematic diagram of voltage and current in an exemplary shift register;

[0032] FIG4B is a schematic diagram of voltage and current in a shift register according to an embodiment of the present disclosure;

[0033] FIG5 is a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure;

[0034] FIG6 is a schematic structural diagram of a display device according to an embodiment of the present disclosure;

[0035] FIG7 is a flowchart of a driving method according to an embodiment of the present disclosure;

[0036] FIG8 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure;

[0037] FIG9 is a schematic structural diagram of a display substrate according to another embodiment of the present disclosure;

[0038] FIG10A is a schematic diagram showing the brightness of a display panel driven by a shift register before compensation;

[0039] FIG10B is a schematic diagram showing the brightness of a display panel driven by a shift register after compensation according to an embodiment of the present disclosure;

[0040] FIG11A is a capacitance matching diagram of a capacitor C2 according to an embodiment of the present disclosure;

[0041] FIG11B is a schematic diagram of capacitance matching of capacitors C3 to C6 according to an embodiment of the present disclosure;

[0042] FIG12A is a schematic diagram of a simulation of an output signal before capacitance matching according to an embodiment of the present disclosure;

[0043] FIG12B is a schematic diagram of a simulation of an output signal after capacitance matching according to an embodiment of the present disclosure;

[0044] FIG13 is a schematic diagram of compensation of a signal line according to an embodiment of the present disclosure;

[0045] FIG14A is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure;

[0046] FIG14B is a schematic structural diagram of a display substrate according to another embodiment of the present disclosure;

[0047] 15A to 15D are layered layouts of the display substrate shown in FIG. 14A ;

[0048] 16A to 16D are layered layouts of the display substrate shown in FIG. 14B ;

[0049] FIG17 is a schematic structural diagram of a display device according to another embodiment of the present disclosure; and

[0050] FIG. 18 is a flowchart of a driving method according to another embodiment of the present disclosure. DETAILED DESCRIPTION

[0051] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure. It should be noted that throughout the drawings, the same elements are represented by the same or similar figure marks. In the following description, some specific embodiments are only for descriptive purposes and should not be understood as any limitation to the present disclosure, but are only examples of the embodiments of the present disclosure. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure. It should be noted that the shapes and sizes of the components in the figures do not reflect the actual size and proportion, but only illustrate the contents of the embodiments of the present disclosure.

[0052] Unless otherwise defined, technical or scientific terms used in the embodiments of the present disclosure shall have the same general meaning as those skilled in the art. The terms "first," "second," and similar terms used in the embodiments of the present disclosure do not denote any order, quantity, or importance, but are merely used to distinguish different components.

[0053] In addition, in the description of the embodiments of the present disclosure, the term "connected" or "connected to" may refer to a direct connection between two components or a connection between two components via one or more other components. In addition, the two components may be connected or coupled via a wired or wireless manner.

[0054] The source and drain of the switching transistor used in the embodiments of the present disclosure are symmetrical, so the source and drain are interchangeable. In the embodiments of the present disclosure, depending on their functions, the control electrode may be referred to as the control electrode, one of the source and drain may be referred to as the first electrode, and the other of the source and drain may be referred to as the second electrode.

[0055] It should be noted that in the description of the embodiments of the present disclosure, the symbol OUTPUT can represent both a scan signal and the output terminal of the scan signal. Similarly, the symbol INPUT can represent both an input signal and the input terminal of the input signal, the symbol VDD can represent both a power supply and the voltage provided by the power supply, and the symbol VGL can represent both a power supply and the voltage provided by the power supply. For example, the power supply VGL can provide a low voltage, such as ground. The power supply VDD can provide a high level. The following embodiments are the same, and similar parts are not repeated here.

[0056] FIG1 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure.

[0057] As shown in FIG. 1 , the shift register 100 includes an input circuit 110 , a control circuit 120 , and an output circuit 130 .

[0058] In the embodiment of the present disclosure, the input circuit 110 is electrically connected to the first input terminal INPUT1 and the second input terminal INPUT2 , the control circuit 120 is electrically connected to the second input terminal INPUT2 and the reset terminal RST, and the output circuit 130 is electrically connected to the output terminal OUTPUT.

[0059] The input circuit 110 and the control circuit 120 are electrically connected to a first node Q, the input circuit 110 and the output circuit 130 are electrically connected to a first node Q, and the control circuit 220 and the output circuit 130 are electrically connected to a second node QB.

[0060] In the embodiment of the present disclosure, the input circuit 110 is configured to control the potential of the first node Q under the control of a first input signal INPUT1 from a first input terminal INPUT1 and a second input signal INPUT2 from a second input terminal INPUT2. The control circuit 120 is configured to control the potential of the second node QB to be different from the potential of the first node Q under the control of the potential of the first node Q, the second input signal INPUT2, and a reset signal RST from a reset terminal RST. The output circuit 130 is configured to output a scan signal OUTPUT under the control of the potentials of the first node Q and the second node QB.

[0061] For example, when the first node Q is at a low level, the control circuit 120 controls the second node QB to be at a high level. When the first node Q is at a high level, the control circuit 120 controls the second node QB to be at a low level.

[0062] In the embodiment of the present disclosure, the control circuit 120 may be an inverter of the shift register 100. The control circuit 120 is further electrically connected to power supplies providing a high level and a low level, respectively. The potential of the first node Q, the second input signal INPUT2, and the reset signal RST control the on and off state of the control circuit 120.

[0063] In the embodiment of the present disclosure, under the control of the first level of the first node Q, the reset signal RST, and the second input signal INPUT2, the control circuit 220 charges the second node QB with the first voltage of the first power supply. Under the control of the second level of the first node Q, the control circuit 120 pulls down the level of the second node QB.

[0064] In the embodiment of the present disclosure, the first level is a low level, the second level is a high level, the first voltage provided by the first power supply is a high level, and the control circuit 120 is also electrically connected to the second power supply, and the second voltage provided by the second power supply is a low level.

[0065] When the level of either the reset signal RST or the second input signal INPUT2 is high, the first power supply is connected to the second node QB, and the control circuit 220 charges the second node QB with the first voltage of the first power supply, so that the second node QB is at a high level. At this time, under the control of the low level of the first node Q, the second node QB is disconnected from the second power supply. In this case, the second node QB is at a high level, and the second node QB is connected to the first power supply and disconnected from the second power supply.

[0066] When the reset signal RST and the second input signal INPUT2 are both at a low level, the first power supply is disconnected from the second node QB. Under the control of the high level of the first node Q, the second power supply is connected to the second node QB. The control circuit 220 pulls down the level of the second node QB, so that the second node QB is at a low level. In this case, the second node QB is at a low level, and the second node QB is connected to the second power supply and disconnected from the first power supply.

[0067] In the embodiment of the present disclosure, under the control of the level of the first node Q, the second input signal INPUT2 and the reset signal RST, a DC path can be avoided between the two power supplies providing high level and low level, thereby avoiding leakage in the shift register 100 and improving the stability of the shift register 100.

[0068] 2A , 2B and 2C are schematic structural diagrams of a shift register according to another embodiment of the present disclosure.

[0069] As shown in FIG. 2A , the shift register 200 a includes an input circuit 210 a , a control circuit 220 a , and an output circuit 230 a .

[0070] In the disclosed embodiment, input circuit 210a includes transistors M1 to M13, transistor M19, transistor M20, transistor M34, and capacitor C1. Transistors M11 and M34 are dual-gate transistors. Control circuit 220a includes transistors M14 to M18, which form an inverter. Output circuit 230a includes transistors M21 to M33 and capacitors C2 to C6. Transistors M1 to M34 are all N-type transistors.

[0071] In the embodiment of the present disclosure, the control electrodes of transistor M1 and transistor M2 are electrically connected to the selection control signal terminal OE, the first electrode of transistor M1 is electrically connected to the first input terminal CR(N-2), the second electrode of transistor M1 is electrically connected to the first electrode of transistor M2, and the second electrode of transistor M2 is electrically connected to node H.

[0072] A first electrode of transistor M3 is electrically connected to a first electrode of transistor M2, a second electrode of transistor M3 is electrically connected to power supply VDD1, and a control electrode of transistor M3 is electrically connected to node H. A first terminal of capacitor C1 is electrically connected to node H, and a second terminal is electrically connected to power supply VDD1.

[0073] A first electrode of transistor M4 is electrically connected to clock terminal CLKA, a control electrode of transistor M4 is electrically connected to node H, and a second electrode of transistor M4 is electrically connected to a first electrode of transistor M5. A second electrode of transistor M5 is electrically connected to a first electrode of transistor M6, and a second electrode of transistor M6 is electrically connected to a first node Q. The control electrodes of transistor M5 and transistor M6 are electrically connected to clock terminal CLKA.

[0074] The control electrodes of transistor M7 and transistor M8 are electrically connected to the first input terminal CR(N-2). A first electrode of transistor M7 is electrically connected to the power supply VDD1, and a second electrode of transistor M7 is electrically connected to the first electrode of transistor M8. A second electrode of transistor M8 is electrically connected to the first node Q. The control electrodes of transistor M34_1 and transistor M34_2 are electrically connected to the power supply VDD3. A first electrode of transistor M34_1 is electrically connected to the power supply VDD3, a second electrode of transistor M34_1 is electrically connected to the first electrode of transistor M34_2, and a second electrode of transistor M34_2 is electrically connected to the first electrode of transistor M8.

[0075] The control electrodes of transistors M9 and M10 are electrically connected to a reset terminal RST. A first electrode of transistor M9 is electrically connected to a first node Q, and a second electrode of transistor M9 is electrically connected to a first electrode of transistor M10 and a first electrode of transistor M6. A second electrode of transistor M10 is electrically connected to a power supply VGL1, and a control electrode of transistor M34_1 and a control electrode of transistor M34_2 are electrically connected to a power supply VDD3. A first electrode of transistor M34_1 is electrically connected to a power supply VDD3, a second electrode of transistor M34_1 is electrically connected to a first electrode of transistor M34_2, and a second electrode of transistor M34_2 is electrically connected to a first electrode of transistor M8.

[0076] The control electrodes of transistors M11_1 and M11_2 are electrically connected to a first node Q. A first electrode of transistor M11_1 is electrically connected to a power supply VDD1, a second electrode of transistor M11_1 is electrically connected to a first electrode of transistor M11_2, and a second electrode of transistor M11_2 is electrically connected to a first electrode of transistor M10.

[0077] The control electrodes of transistor M12 and transistor M13 are electrically connected to the second input terminal CR(N+2). A first electrode of transistor M12 is electrically connected to the first node Q, a second electrode of transistor M12 is electrically connected to a first electrode of transistor M13, and a second electrode of transistor M13 is electrically connected to a first electrode of transistor M10.

[0078] The control electrodes of transistors M19 and M20 are electrically connected to the second node QB. A first electrode of transistor M19 is electrically connected to the first node Q, a second electrode of transistor M19 is electrically connected to a first electrode of transistor M20, and a second electrode of transistor M20 is electrically connected to the power supply VGL1 of transistor M10.

[0079] In the embodiment of the present disclosure, the control electrode of the transistor M14 is electrically connected to the second input terminal CR(N+2), the first electrode of the transistor M14 is electrically connected to the power supply VDD2, and the second electrode of the transistor M14 is electrically connected to the control electrode of the transistor M16.

[0080] The control electrode of transistor M15 is electrically connected to the reset terminal RST, the first electrode of transistor M15 is electrically connected to the power supply VDD2, the second electrode of transistor M15 is electrically connected to the control electrode of transistor M16, the first electrode of transistor M16 is electrically connected to the power supply VDD2, and the second electrode of transistor M16 is electrically connected to the second node QB.

[0081] The control electrode of transistor M17 is electrically connected to the first node Q, the first electrode of transistor M17 is electrically connected to the control electrode of transistor M16, and the second electrode of transistor M17 is electrically connected to the power supply VGL3. The control electrode of transistor M18 is electrically connected to the first node Q, the first electrode of transistor M18 is electrically connected to the second node QB, and the second electrode of transistor M18 is electrically connected to the power supply VGL1.

[0082] In the embodiment of the present disclosure, the output circuit 230a includes multiple output terminals, each of which is configured to output multiple scan signals, and the multiple scan signals are used to drive multiple rows of sub-pixel units. For example, the multiple output terminals include an output terminal OUT(N), an output terminal OUT(N+1), an output terminal OUT(N+2), and an output terminal OUT(N+3). The output terminals OUT(N), OUT(N+1), OUT(N+2), and OUT(N+3) can be used to drive four rows of sub-pixels.

[0083] It should be noted that the present disclosure does not limit the number of output terminals.

[0084] A control electrode of the transistor M21, a control electrode of the transistor M23, a control electrode of the transistor M25, a control electrode of the transistor M27, and a control electrode of the transistor M29 are electrically connected to the first node Q. A first electrode of the transistor M21 is electrically connected to the clock terminal CLKD1, and a second electrode of the transistor M21 is electrically connected to the shift signal output terminal CR(N). The shift signal output terminal CR(N) is configured to output the shift signal CR(N).

[0085] A first electrode of transistor M23 is electrically connected to clock terminal CLK1, and a second electrode of transistor M23 is electrically connected to output terminal OUT(N). A first electrode of transistor M25 is electrically connected to clock terminal CLK2, and a second electrode of transistor M25 is electrically connected to output terminal OUT(N+1). A first electrode of transistor M27 is electrically connected to clock terminal CLK3, and a second electrode of transistor M27 is electrically connected to output terminal OUT(N+2). A first electrode of transistor M29 is electrically connected to clock terminal CLK4, and a second electrode of transistor M29 is electrically connected to output terminal OUT(N+3).

[0086] A first end of capacitor C2, a first end of capacitor C3, a first end of capacitor C4, a first end of capacitor C5, and a first end of capacitor C6 are electrically connected to a first node Q. A second end of capacitor C2 is electrically connected to the shift signal output terminal CR(N). A second end of capacitor C3 is electrically connected to the output terminal OUT(N). A second end of capacitor C4 is electrically connected to the output terminal OUT(N+1). A second end of capacitor C5 is electrically connected to the output terminal OUT(N+2). A second end of capacitor C6 is electrically connected to the output terminal OUT(N+3).

[0087] The control electrodes of transistors M22, M24, M26, M28, and M30 are electrically connected to a second node QB. The second electrodes of transistors M22, M24, M26, M28, and M30 are electrically connected to a power supply VGL2.

[0088] A first electrode of transistor M22 is electrically connected to the shift signal output terminal CR(N), and the shift signal output terminal CR(N) is configured to output the shift signal CR(N). A first electrode of transistor M24 is electrically connected to the output terminal OUT(N). A first electrode of transistor M26 is electrically connected to the output terminal OUT(N+1). A first electrode of transistor M27 is electrically connected to the output terminal OUT(N+2). A first electrode of transistor M30 is electrically connected to the output terminal OUT(N+3).

[0089] The control electrode of transistor M31 is electrically connected to the clock terminal CLKA. A first electrode of transistor M31 is electrically connected to a first electrode of transistor M32, a second electrode of transistor M32 is electrically connected to the power supply VGL1, and a control electrode of transistor M32 is electrically connected to node H. A control electrode of transistor M33 is electrically connected to the clock terminal CLKA. A control electrode of transistor M33 is electrically connected to the first input terminal CR(N-2), a first electrode of transistor M33 is electrically connected to the second node QB, and a second electrode of transistor M33 is electrically connected to the power supply VGL1.

[0090] As shown in FIG. 2B , the shift register 200 b includes an input circuit 210 b , a control circuit 220 b , and an output circuit 230 b .

[0091] In the embodiment of the present disclosure, the structures of the input circuit 210 b and the output circuit 230 b are similar to those of the input circuit 210 a and the output circuit 230 a described above, respectively, and are not described again for the sake of brevity.

[0092] In the embodiment of the present disclosure, the control circuit 220b further includes a capacitor C7 based on the control circuit 220a described above. A first terminal of the capacitor C7 is electrically connected to the power supply VDD2, and a second terminal of the capacitor C7 is electrically connected to the control electrode of the transistor M16.

[0093] As shown in FIG. 2C , the shift register 200 c includes an input circuit 210 c , a control circuit 220 c , and an output circuit 230 c .

[0094] In the embodiment of the present disclosure, the structures of the input circuit 210c and the output circuit 230c are similar to those of the input circuit 210a and the output circuit 230a described above, respectively, and are not described again for the sake of brevity.

[0095] In the embodiment of the present disclosure, the control circuit 220 c further includes a capacitor C7 based on the control circuit 220 a described above.

[0096] In the embodiment of the present disclosure, a first terminal of the capacitor C7 is electrically connected to the control electrode of the transistor M16 , and a second terminal of the capacitor C7 is electrically connected to the power source VGL1 .

[0097] FIG3 is a schematic diagram of signal timing of a shift register according to an embodiment of the present disclosure.

[0098] Figure 3 shows the signal timing diagram corresponding to a frame of display. The signal period corresponding to a frame of display includes a display period and a blanking period. During the display period of a frame of display, the shift register provides a scanning drive signal for the scanning transistor. During the blanking period of a frame of display, the shift register provides a sensing drive signal for the sensing transistor.

[0099] As shown in FIG3 , clock terminals CLK1 to CLK12 are clock terminals connected to three cascaded shift registers, and clock terminals CLK1 to CLK12 provide clock signals CLK1 to CLK12 to the three cascaded shift registers. For example, the shift registers may be the shift registers shown in FIG2A , FIG2B , and FIG2C , each of which includes four output terminals electrically connected to four clock terminals. Clock terminals CLKD1 to CLKD3 are electrically connected to transistors M21 of the three shift registers, respectively. The timing of the clock signals CLKD1 to CLKD3 provided by clock terminals CLKD1 to CLKD3 is the same as the timing of the shift signal CR(N) output by the Nth stage shift register, the shift signal CR(N+1) output by the N+1th stage shift register, and the shift signal CR(N+2) output by the N+2th stage shift register.

[0100] In the shift register 200a shown in FIG2A , the second input signal provided by the second input terminal CR(N+2) electrically connected to the control electrode of transistor M14 can be a reset signal for the pixel row corresponding to the output terminal OUT(n). The reset terminal RST electrically connected to the control electrode of transistor M15 can be an overall reset signal for the multiple cascaded shift registers 200a.

[0101] When the reset signal RST is high, the shift signal CR(N+2) (the second input signal) is low. Under the control of the high reset signal RST, transistor M15 is turned on. Transistor M14 is turned off by the second input signal CR(N+2). Voltage VDD2 is applied to the control electrode of transistor M16 through transistor M15, turning transistor M16 on. Voltage VDD2 charges the second node QB through transistor M16.

[0102] When the reset signal RST is high, the selection control signal OE and the first input signal CR(N-2) are low. Transistors M1, M2, M7, and M8 are turned off. At this time, the potential of the first node Q is low. Transistors M17 and M18 are turned off by the low potential of the first node Q.

[0103] When the reset signal RST and the second input signal CR(N+2) are both low, transistors M14, M15, and M16 are turned off. Since the potential of the first node Q remains low at this time, transistors M17 and M18 are turned off, and the potential of the second node QB remains high.

[0104] When the reset signal RST is low and the first input signal CR(N-2) is high, transistors M7 and M8 are turned on. Voltage VDD1 charges the first node Q through transistors M7 and M8, causing the potential of the first node Q to be high, and transistors M17 and M18 are turned on. Because both the reset signal RST and the second input signal CR(N+2) are low, transistors M14, M15, and M16 are turned off. At this point, the potential of the second node QB gradually decreases until it is pulled down to a low level.

[0105] When the potential of the first node Q becomes low again, the second input signal CR(N+2) is high, transistors M14 and M16 are turned on, transistors M17 and M18 are turned off, and the potential of the second node QB is high.

[0106] In the shift register 200b shown in FIG2B , when the reset signal RST is at a high level, the second input signal CR(N+2) is at a low level. Under the control of the high level of the reset signal RST, the transistor M15 is turned on. The transistor M14 is turned off by the second input signal CR(N+2). The voltage VDD2 is applied to the control electrode of the transistor M16 through the transistor M15, turning on the transistor M16. The voltage VDD2 charges the capacitor C7 and the second node QB through the transistor M16.

[0107] When the reset signal RST is high, the selection control signal OE and the first input signal CR(N-2) are low. Transistors M1, M2, M7, and M8 are turned off. At this time, the potential of the first node Q is low. Transistors M17 and M18 are turned off by the low potential of the first node Q.

[0108] When the reset signal RST and the second input signal CR(N+2) are both at a low level, transistors M14, M15, and M16 are turned off. Since the potential of the first node Q remains at a low level at this time, transistors M17 and M18 are turned off. Capacitor C7 keeps the potential of the second node QB at a high level.

[0109] When the reset signal RST is low and the first input signal CR(N-2) is high, transistors M7 and M8 are turned on. Voltage VDD1 charges the first node Q through transistors M7 and M8, causing the potential of the first node Q to be high, and transistors M17 and M18 are turned on. Because both the reset signal RST and the second input signal CR(N+2) are low, transistors M14, M15, and M16 are turned off. At this point, the voltage on capacitor C7 is released through transistors M17 and M18, and the potential of the second node QB gradually decreases until it is pulled down to a low level.

[0110] When the potential of the first node Q becomes low again, the second input signal CR(N+2) is high, transistors M14 and M16 are turned on, transistors M17 and M18 are turned off, and the potential of the second node QB is high.

[0111] The operating principles of the shift register 200 c shown in FIG2C are similar to those of the shift register 200 b shown in FIG2B , and are not described again for the sake of brevity.

[0112] In one example, the control electrodes of transistors M14 and M15 are electrically connected to a power supply VDD2. A first electrode of transistor M14 is electrically connected to the power supply VDD2, a second electrode of transistor M14 is electrically connected to a first electrode of transistor M15, a second electrode of transistor M15 is electrically connected to a control electrode of transistor M16, a first electrode of transistor M16 is electrically connected to the power supply VDD2, and a second electrode of transistor M16 is electrically connected to a second node QB. The control electrodes of transistors M17 and M18 are electrically connected to a first node Q, a first electrode of transistor M17 is electrically connected to the control electrode of transistor M16, and a second electrode of transistor M17 is electrically connected to a power supply VGL3. A first electrode of transistor M18 is electrically connected to a second node QB, and a second electrode of transistor M18 is electrically connected to a power supply VGL1.

[0113] In the exemplary shift register, the voltage provided by power supply VDD2 is high. Under the control of voltage VDD2 from power supply VDD2, transistors M14 and M15 are turned on. Voltage VDD2 is applied to the control electrode of transistor M16 through transistors M14 and M15, turning on transistor M16. When input signal CR(N-2) provided by input terminal CR(N-2) is high, the high level is applied to first node Q. Under the control of the high level of first node Q, transistors M17 and M18 are turned on. Voltage VDD2 is applied to second node QB through transistor M16, and second node QB is now connected to power supply VGL1. Because the voltage provided by power supply VGL1 is low and the potential of second node QB is high, a path is formed between the high and low levels, generating a large current. This can cause the transistors in the Darlington inverter circuit to burn out, thereby affecting the stability of shift register 100.

[0114] Because transistors M14 and M15 in the exemplary shift register are always on, a path is formed between the high and low levels when transistor M17 is on. To address the issues with the exemplary shift register, the shift register provided by the present disclosure controls the on / off switching of transistors M14 and M15 based on a second input signal INPUT2 and a reset signal RST, thereby preventing a DC path from forming between the two power supplies providing the high and low levels. This prevents leakage in the shift register provided by the present disclosure and improves the stability of the shift register.

[0115] Figure 4A is a schematic diagram of voltage and current in an exemplary shift register. Figure 4B is a schematic diagram of voltage and current in a shift register according to an embodiment of the present disclosure.

[0116] Graph (a) in FIG4A and graph (a) in FIG4B show the voltage change of the second node QB, and graph (b) in FIG4A and graph (b) in FIG4B show the voltage change of the first node Q. Graph (c) in FIG4A and graph (c) in FIG4B show the current change at the source of transistor M17, that is, the current change flowing from power supply VDD2 to power supply VGL3. Graph (d) in FIG4A and graph (d) in FIG4B show the current change at the source of transistor M18, that is, the current change flowing from power supply VDD2 to power supply VGL1.

[0117] As shown in FIG4A , when the potential of the first node Q is at a high level, the maximum transient current of the current flowing from the power supply VDD2 to the power supply VGL3 is 80 uA, and the maximum transient current flowing from the power supply VDD2 to the power supply VGL1 is 37 uA.

[0118] As shown in FIG4B , when the potential of the first node Q is high, the maximum instantaneous current flowing from the power supply VDD2 to the power supply VGL3 is 50 μA, and the maximum instantaneous current flowing from the power supply VDD2 to the power supply VGL1 is 16 μA. Compared with FIG4A , the maximum instantaneous current in the shift register shown in FIG4B is reduced.

[0119] In shift register 200a, shift register 200b and shift register 200c, when the potential of the first node Q is at a high level, there will be no large current for a long time in shift register 200a, shift register 200b and shift register 200c, reducing the risk of transistors in shift register 200a, shift register 200b and shift register 200c being burned.

[0120] FIG5 is a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure.

[0121] As shown in Fig. 5 , the driving circuit 500 includes N cascaded shift registers, where N is a positive integer greater than 1. The N shift registers include a shift register ST1, a shift register ST2, a shift register ST3, ..., and a shift register STN.

[0122] In the embodiment of the present disclosure, the shift register may be any one of the shift register 100, the shift register 200a, the shift register 200b, and the shift register 200c described above. For example, the N shift registers are all shift register 200a. For example, the N shift registers are all shift register 200b. This will not be repeated here.

[0123] In the embodiment of the present disclosure, in the cascaded N shift registers, the first input terminal INPUT1 of the n-th stage shift register is electrically connected to the shift signal output terminal CR(N-2) of the n-2-th stage shift register, and the second input terminal INPUT of the n-th stage shift register is electrically connected to the shift signal output terminal CR(N+2) of the n+2-th stage shift register, where n is a positive integer less than N.

[0124] For example, the first input signal terminal INPUT1 of the third-stage shift register ST3 is electrically connected to the shift signal output terminal CR1 of the first-stage shift register ST1, and the second input signal terminal INPUT2 of the third-stage shift register ST2 is electrically connected to the shift signal output terminal CR5 of the fifth-stage shift register.

[0125] In the embodiment of the present disclosure, the first input signal terminal INPUT1 of the first stage shift register ST1 is electrically connected to the scan trigger signal terminal STV, and the second input signal terminal INPUT2 of the Nth stage shift register STN is electrically connected to the anti-static terminal ESD.

[0126] In the disclosed embodiment, the reset terminal RST of the N cascaded shift registers is electrically connected to the reset terminal rst, and the select control signal terminal OE is electrically connected to the select control signal terminal oe. The clock terminal CLKD1 is electrically connected to the clock terminal clkd, and the clock terminal CLKA is electrically connected to the clock terminal clka. The clock terminal CLK1 is electrically connected to the clock signal terminal clk1, the clock terminal CLK2 is electrically connected to the clock signal terminal clk2, the clock terminal CLK3 is electrically connected to the clock signal terminal clk3, and the clock terminal CLK4 is electrically connected to the clock signal terminal clk4.

[0127] FIG6 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.

[0128] As shown in FIG. 12 , a display device 600 may include a display panel 610 and a driving circuit 620 .

[0129] In the embodiment of the present disclosure, the driving circuit 610 may be the driving circuit 500 described above, which will not be described in detail here.

[0130] In the embodiment of the present disclosure, the display panel 610 includes a plurality of sub-pixel units Pixel arranged in an array, and the driving circuit 610 is used to drive the sub-pixel units Pixel.

[0131] It should be noted that the number of sub-pixel units included in the display panel 610 is only for illustrative purposes, and the present disclosure does not limit the number of sub-pixel units.

[0132] FIG. 7 is a flowchart of a driving method according to an embodiment of the present disclosure.

[0133] As shown in FIG. 7 , the driving method may include operations S710 to S730 .

[0134] In the embodiment of the present disclosure, the driving method may be applied to the shift register 100 , the shift register 200 a , the shift register 200 b , and the shift register 200 c described above.

[0135] In operation S710 , a potential of a first node is controlled by an input circuit under control of a first input signal from a first input terminal and a second input signal from a second input terminal.

[0136] In operation S720 , the potential of the second node is controlled by the control circuit under the control of the potential of the first node, the second input signal, and the reset signal from the reset terminal.

[0137] In operation S730, a scan signal is output through an output circuit under control of the potentials of the first node and the second node.

[0138] In the embodiment of the present disclosure, operations S710 to S730 are similar to the operations performed by the shift register 200a, the shift register 200b, and the shift register 200c described above, and are not described again herein.

[0139] FIG8 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure.

[0140] As shown in FIG. 8 , a display substrate 800 includes a compensation circuit 810 and a shift register 820 .

[0141] In the embodiment of the present disclosure, the compensation circuit 810 is configured to compensate the input signal or the output signal of the shift register 810 to obtain a plurality of scanning signals, so as to control the relative difference between the falling times of the plurality of scanning signals.

[0142] The number of input signals received and output signals output by the shift register 810 shown in FIG8 is only for illustration.

[0143] In an embodiment of the present disclosure, the shift register 820 may include: an input circuit, configured to control the potential of the first node under the control of a first input signal from the first input terminal and a second input signal from the second input terminal; a control circuit, configured to control the potential of the second node under the control of the potential of the first node, the second input signal and the reset signal from the reset terminal; and an output circuit, configured to output a scan signal under the control of the potentials of the first node and the second node.

[0144] In the embodiment of the present disclosure, the shift register 820 may be the shift register 100, the shift register 200a, the shift register 200b, and the shift register 200c described above, which will not be described in detail for the sake of brevity.

[0145] In the embodiment of the present disclosure, the compensation circuit 810 is used to compensate the input signal or output signal of the shift register 810, so as to control the relative difference between the fall times of multiple input signals, or control the relative difference between the fall times of multiple output signals, thereby reducing the relative difference between the fall times of multiple scanning signals driving the pixel circuit.

[0146] In an embodiment of the present disclosure, the compensation circuit 810 compensates the input signal of the shift register 820 to obtain multiple scanning signals, which are configured as follows: compensating multiple clock signals from multiple clock terminals to control the relative difference between the fall times of the multiple clock signals to obtain multiple compensated clock signals, so that the shift register 820 outputs multiple scanning signals based on the multiple compensated clock signals.

[0147] For example, in shift register 200a, transistors M21, M23, M25, M27, and M29 share a first node Q. Capacitors C2, C3, C4, C5, and C6 provide a bootstrapping function, thereby enhancing the voltage level of first node Q. However, since clock signals CLK1, CLK2, CLK3, and CLK4 are transmitted sequentially, the degree of bootstrapping applied to first node Q varies. Consequently, the fall times TF of scan signals OUT(N), OUT(N+1), OUT(N+2), and OUT(N+3) vary.

[0148] Because the fall times TF of the scan signals OUT(N), OUT(N+1), OUT(N+2), and OUT(N+3) are different, when the same data voltage is written to four rows of sub-pixels in the pixel circuit, the different currents of the scan signals will cause the brightness of the sub-pixels in different rows to differ. In this case, bright and dark lines will appear on the display.

[0149] To avoid this phenomenon, compensation circuit 810 can compensate the clock signals CLK1, CLK2, CLK3, and CLK4 at the clock terminals CLK1, CLK2, CLK3, and CLK4 electrically connected to shift register 200a to increase the fall times TF of the clock signals CLK1, CLK2, CLK3, and CLK4. Driven by the compensated clock signals, the fall times of the four scanning signals can be increased, thereby reducing the relative difference between the fall times of the four scanning signals. The relative difference is the ratio of the difference between the fall times of the four scanning signals to the fall time of any scanning signal.

[0150] For example, before the clock signals are compensated by compensation circuit 810, the fall time of clock signal CLK1 is 400 ns and the fall time of clock signal CLK2 is 440 ns. At this time, the difference between the fall time of clock signal CLK1 and the fall time of clock signal CLK2 is 40 ns, and the relative difference is 40 / 400 = 10%.

[0151] After the clock signals are compensated using compensation circuit 810, the fall time of clock signal CLK1 increases to 450 ns and the fall time of clock signal CLK2 increases to 480 ns. At this point, the difference between the fall time of clock signal CLK1 and the fall time of clock signal CLK2 is 30 ns, and the relative difference is 30 / 450 = 6.7%.

[0152] In the embodiment of the present disclosure, the compensation circuit 810 can be integrated on a driver chip together with the shift register 820. The compensation circuit 810 can also be externally connected to the driver chip, and the shift register 820 can be integrated on the driver chip.

[0153] In the embodiment of the present disclosure, the compensation circuit 810 compensates the clock signal and increases the difference between the fall times of multiple clock signals, which can reduce the relative difference between the fall times of multiple scanning signals, thereby reducing the difference between multiple scanning signals and improving the brightness difference between different sub-pixel rows in the pixel circuit.

[0154] FIG. 9 is a schematic structural diagram of a display substrate according to another embodiment of the present disclosure.

[0155] As shown in FIG. 9 , a display substrate 900 includes a compensation circuit 910 and a shift register 920 .

[0156] In the embodiment of the present disclosure, when the shift register 920 includes multiple output terminals, the compensation circuit 910 includes multiple compensation sub-circuits, and the number of the multiple compensation sub-circuits is the same as the number of the multiple clock terminals.

[0157] For example, the shift register 200a described above includes four output terminals, so the compensation circuit 910 is electrically connected to four clock terminals, and the compensation circuit 910 includes four compensation sub-circuits.

[0158] In the embodiment of the present disclosure, each compensation subcircuit in the plurality of compensation subcircuits includes a compensation resistor and a compensation capacitor. For example, the compensation subcircuit 911 includes a compensation resistor R1 and a compensation capacitor C1, and the compensation subcircuit 912 includes a compensation resistor R2 and a compensation capacitor C2.

[0159] In the embodiment of the present disclosure, a first end of the compensation resistor R1 is electrically connected to the clock terminal CLK1, and a second end of the compensation resistor R1 is electrically connected to the shift register 920. A first end of the compensation capacitor C1 is electrically connected to the clock terminal CLK1, and a second end of the compensation capacitor C1 is electrically connected to the power supply VDD.

[0160] A first terminal of the compensation resistor R2 is electrically connected to the clock terminal CLK2, and a second terminal of the compensation resistor R2 is electrically connected to the shift register 920. A first terminal of the compensation capacitor C2 is electrically connected to the clock terminal CLK2, and a second terminal of the compensation capacitor C2 is electrically connected to the power supply VDD.

[0161] The power sources electrically connected to the compensation capacitors C1 and C2 may be the same or different.

[0162] In the embodiment of the present disclosure, the clock signal is externally compensated by the compensation circuit 910, so that the fall time of all clock signals is increased, thereby increasing the fall time of the output scanning signal. The resistance of the compensation resistor and the capacitance of the compensation capacitor in the compensation subcircuit can be determined by formula (1):

[0163] τ represents the difference in the fall time of the scan signal, in seconds. R is the resistance of the compensation resistor, in ohms. C is the capacitance of the compensation capacitor, in farads. V0 is the initial voltage of the compensation capacitor, V1 is the voltage of the compensation capacitor after it is charged or released, and Vt is the voltage across the compensation capacitor at time t.

[0164] Formula (1) can be used to determine the values ​​of the resistance of the compensation resistor and the capacitance of the compensation capacitor when the difference in the fall time of the scanning signal is τ. The resistances of the compensation resistors included in each of the multiple compensation sub-circuits can be equal or unequal. The capacitances of the compensation capacitors included in each of the multiple compensation sub-circuits can be equal or unequal.

[0165] In the embodiment of the present disclosure, a compensation resistor and a compensation capacitor may be provided on a printed circuit board to perform external compensation on the clock signal.

[0166] Figure 10A is a schematic diagram of the brightness of a display panel driven by a shift register before compensation. Figure 10B is a schematic diagram of the brightness of a display panel driven by a shift register after compensation according to an embodiment of the present disclosure. Figures 10A and 10B show the brightness of sub-pixels in rows 1 to 12 of a pixel circuit. The solid line shows the brightness of the sub-pixels obtained by actual measurement, and the dotted line shows the brightness of the sub-pixels obtained by simulation. For example, Figure 10A shows the brightness of a display panel driven by the shift register 920 alone. Figure 10B shows the brightness of a display panel driven by the compensation circuit 910 and the shift register 920.

[0167] Graph (a) in FIG10A and graph (a) in FIG10B show the brightness of a sub-pixel at grayscale 32, and graph (b) in FIG10A and graph (b) in FIG10B show the brightness of a sub-pixel at grayscale 63. Graph (c) in FIG10A and graph (c) in FIG10B show the brightness of a sub-pixel at grayscale 128. Graph (d) in FIG10A and graph (d) in FIG10B show the brightness of a sub-pixel at grayscale 255.

[0168] As shown in Figure 10A, the measured results are similar to the simulated structure. The brightness of the sub-pixels in the 4th row, the 8th row, and the 12th row is greater than the brightness of the sub-pixels in the adjacent rows. This shows that the difference between the fall time TF of the scanning signal driving the sub-pixels in the 4th row and the fall time TF of the scanning signal driving the sub-pixels in the adjacent rows is significant. The difference between the fall time TF of the scanning signal driving the sub-pixels in the 8th row and the fall time TF of the scanning signal driving the sub-pixels in the adjacent rows is significant. The difference between the fall time TF of the scanning signal driving the sub-pixels in the 12th row and the fall time TF of the scanning signal driving the sub-pixels in the adjacent rows is significant.

[0169] As shown in Figure 10B, the measured results are similar to the simulated structure. The brightness difference between the sub-pixels in the first row to the 12th row is small. This shows that the difference between the fall time of the scanning signal driving the sub-pixels in the first row to the 12th row is small.

[0170] Figure 11A is a schematic diagram of capacitance matching of capacitor C2 according to an embodiment of the present disclosure. Figure 11B is a schematic diagram of capacitance matching of capacitors C3 to C6 according to an embodiment of the present disclosure.

[0171] For example, Figure 11A shows a schematic diagram illustrating the change between the falling time of the scan signal output by the shift register 920 and the capacitance of capacitor C2. Figure 11B shows a schematic diagram illustrating the change between the falling time of the scan signal output by the shift register 920 and the capacitance of capacitors C3 to C6.

[0172] In the disclosed embodiment, capacitor C2 is electrically connected to the shift signal output section CR(N) and serves as a cascade capacitor. Capacitors C3 through C6 are electrically connected to output terminals OUT(N) through OUT(N+3), respectively, and serve as drive capacitors. Capacitors C2 through C6 are capacitance-matched to minimize variations in the fall times of multiple output signals.

[0173] In the embodiment of the present disclosure, the number of driving capacitors is the same as the number of clock terminals. By setting the capacitance of capacitors C2 to C6, the influence of capacitive coupling on the clock signal can be reduced, thereby reducing the difference between the fall times of the scanning signals.

[0174] In an embodiment of the present disclosure, the capacitance of one of the plurality of drive capacitors is smaller than the capacitance of the remaining drive capacitors. For example, referring to FIG10A , the fall time of the scan signal used to drive the fourth row of sub-pixels differs significantly from the fall time of the other scan signals. Therefore, the capacitance of the drive capacitor electrically connected to the output terminal outputting the scan signal driving the fourth row of sub-pixels is smaller than that of the other drive capacitors.

[0175] Figure 11A shows the change in the fall time of the four scanning signals when capacitors C3 to C6 are fixed at 0 and only the capacitance of capacitor C2 is changed. When capacitor C2 is less than 4pF, the difference in the fall time of the four scanning signals decreases as the capacitance of capacitor C2 increases. When capacitor C2 is greater than 4pF, the difference in the fall time of the four scanning signals increases as the capacitance of capacitor C2 increases. When capacitor C2 = 4pF, the difference in the fall time of the four scanning signals is minimal.

[0176] Figure 11B (a) shows the change in the fall time of the four scanning signals when the capacitance of capacitor C2 is fixed at 4pF, the capacitance of capacitors C4, capacitors C5 and capacitors C6 are fixed at 0, and only the size of C3 is changed. Figure 11B (b) shows the change in the fall time of the four scanning signals when the capacitance of capacitor C2 is fixed at 4pF, the capacitance of capacitors C3, capacitors C5 and capacitors C6 are fixed at 0, and only the size of capacitor C4 is changed. Figure 11B (c) shows the change in the fall time of the four scanning signals when the capacitance of capacitor C2 is fixed at 4pF, the capacitance of capacitors C3, capacitors C4 and capacitors C6 are fixed at 0, and only the size of capacitor C5 is changed. Figure 11B (d) shows the change in the fall time of the four scanning signals when the capacitance of capacitor C2 is fixed at 4pF, the capacitance of capacitors C3, capacitors C4 and capacitors C5 are fixed at 0, and only the size of capacitor C6 is changed.

[0177] In FIG11B (a), when the capacitance C3 is less than 0.5 pF, the difference between the fall times of the four scanning signals decreases as the capacitance of the capacitor C3 increases. When the capacitance C3 is greater than 0.5 pF, the difference between the fall times of the four scanning signals increases as the capacitance of the capacitor C3 increases. When the capacitance C3 is equal to 0.5 pF, the difference in the fall times of the four scanning signals is the smallest.

[0178] In FIG11B (b), when capacitance C4 < 0.5 pF, the difference between the fall times of the four scanning signals decreases as the capacitance of capacitor C3 increases. When capacitance C4 > 0.5 pF, the difference between the fall times of the four scanning signals increases as the capacitance of capacitor C4 increases. When capacitance C4 = 0.5 pF, the difference in the fall times of the four scanning signals is minimal.

[0179] In FIG11B (c), when capacitance C5 < 1 pF, the difference between the fall times of the four scan signals decreases as the capacitance of capacitor C3 increases. When capacitance C5 > 1 pF, the difference between the fall times of the four scan signals increases as the capacitance of capacitor C5 increases. When capacitance C5 = 1 pF, the difference in the fall times of the four scan signals is minimal.

[0180] 11B (d), when the capacitance C6>0pF, the difference between the falling times of the four scanning signals increases as the capacitance of the capacitor C6 increases. When the capacitance C6=0pF, the difference between the falling times of the four scanning signals is the smallest.

[0181] In the embodiment of the present disclosure, based on the difference in brightness between the sub-pixels in the first row to the fourth row, it can be determined that the difference between the fall times of the scanning signals used to drive the sub-pixels in the first row to the fourth row is small, while the difference between the fall times of the scanning signals used to drive the sub-pixels in the fourth row and the fall times of the scanning signals of the first three rows is large. Therefore, the capacitances of capacitors C3, C4, and C5 can be increased, thereby increasing the coupling capability of capacitors C3, C4, and C5, and correspondingly increasing the fall time TF of the scanning signal. At the same time, the capacitance of capacitor C6 can be reduced, thereby reducing the coupling capability of capacitor C6, and correspondingly decreasing the fall time TF of the scanning signal.

[0182] Therefore, after matching, the capacitance C2 = 4 pF, after matching, the capacitance C3 = 0.5 pF, after matching, the capacitance C4 = 0.5 pF, after matching, the capacitance C5 = 1 pF, and after matching, the capacitance C6 = 0 pF. The capacitance after matching is C2 > C5 > C3 = C4 > C6.

[0183] Figure 12A is a schematic diagram of a simulation of an output signal before capacitance matching according to an embodiment of the present disclosure. Figure 12B is a schematic diagram of a simulation of an output signal after capacitance matching according to an embodiment of the present disclosure.

[0184] Figures 12A and 12B show the voltage changes of the first node Q, the scan signal OUT(1), the scan signal OUT(2), the scan signal OUT(3), and the scan signal OUT(4) in the shift register. Figures 12A and 12B show the voltage changes of the first node Q, the voltage changes of the scan signal OUT(1), the voltage changes of the scan signal OUT(2), the voltage changes of the scan signal OUT(3), and the voltage changes of the scan signal OUT(4).

[0185] The bootstrap degree of the first node Q when each scan signal is output is determined according to the voltage of the first node Q when the scan signals OUT(1), OUT(2), OUT(3) and OUT(4) are at high levels.

[0186] As shown in FIG12A , the bootstrap degrees of the first node Q corresponding to the scan signals OUT(1), OUT(2), OUT(3), and OUT(4) are different. The bootstrap degree of the first node Q corresponding to the scan signal OUT(4) is smaller than the bootstrap degrees of the first node Q corresponding to the scan signals OUT(1), OUT(2), and OUT(3).

[0187] The fall times of scan signal OUT(1), scan signal OUT(2), scan signal OUT(3), and scan signal OUT(4) are also different. The fall times of scan signal OUT(1), scan signal OUT(2), scan signal OUT(3), and scan signal OUT(4) are 428.53 ns, 432.99 ns, 439.13 ns, and 480.67 ns, respectively. The maximum difference ΔTF between the fall times of the four scan signals is 480.67-428.53=52.14 ns.

[0188] As shown in FIG12B , the difference between the voltages of the first node Q corresponding to the scan signals OUT(1), OUT(2), OUT(3), and OUT(4) is reduced, and the difference in the degree of bootstrapping of the first node Q corresponding to the scan signals OUT(1), OUT(2), OUT(3), and OUT(4) is small. The fall times of the scan signals OUT(1), OUT(2), OUT(3), and OUT(4) are 427.4 ns, 430.62 ns, 431.29 ns, and 457.19 ns, respectively. The maximum difference ΔTF between the fall times of the four scan signals is 457.19-427.4=29.79 ns. After the capacitor matching, the fall time difference is reduced from 52.14 ns to 22.35 ns, a 43% reduction.

[0189] In one embodiment, the compensation circuit includes a plurality of output signal lines, each electrically connected to a plurality of output terminals, configured to compensate for an output signal of the shift register to obtain and output a plurality of scanning signals.

[0190] In the embodiment of the present disclosure, referring to FIG10A , the fall time of the scanning signal used to drive the fourth row of sub-pixels differs significantly from the fall time of the other scanning signals. Therefore, the length of the output signal line that outputs the scanning signal driving the fourth row of sub-pixels is shorter than the lengths of the remaining output signal lines among the plurality of output signal lines, and the width of the output signal line that outputs the scanning signal driving the fourth row of sub-pixels is wider than the lengths of the remaining output signal lines among the plurality of output signal lines.

[0191] In the disclosed embodiment, the length and width of the output signal line can be adjusted on the periphery line glass (PLG) area of ​​the glass substrate to achieve RC compensation of the PLG line before entering the GOA area. Since the output signal lines are usually arranged from the outside to the inside, the lengths of the output signal lines are different. The resistance of the output signal line can be determined by formula (2):

[0192] R represents the resistance of the output signal line, L represents the length of the output signal line, S represents the width of the output signal line, and RS represents the square resistance. The square resistance of the output signal lines is the same. When the width and length of the output signal lines are different, the resistance of each output signal line is different.

[0193] The resistance of the output signal line significantly affects the AC signal, affecting both the fall time and the signal voltage of the scanning signal. When a shift register is electrically connected to multiple output signal lines, the shift register is sensitive to the fall time of the scanning signal, so the multiple output signal lines can be arranged with unequal widths within the display.

[0194] For example, for an output signal line arranged on the outside, since the length L of the output signal line is longer, the width S of the output signal line is increased, thereby reducing the resistance of the output signal line. For an output signal line arranged on the inside, since the length L of the output signal line is shorter, the width S of the output signal line is reduced, thereby increasing the resistance of the output signal line.

[0195] Through software simulation, the resistance of the output signal line is extracted, and the length and width of all output signal lines are fine-tuned.

[0196] In an embodiment of the present disclosure, a compensation circuit includes multiple clock signal lines. The multiple clock signal lines are electrically connected to multiple clock terminals, respectively, for inputting multiple clock signals into a shift register. The multiple clock signal lines are configured to compensate the multiple clock signals to generate multiple compensated clock signals.

[0197] In the disclosed embodiment, referring to FIG10A , the fall time of the scanning signal used to drive the fourth row of sub-pixels differs significantly from the fall time of the other scanning signals. Therefore, the length of the clock signal line electrically connected to the aforementioned clock terminal CLK4 is shorter than the length of the remaining clock signal lines among the multiple clock signal lines, and the width of the clock signal line electrically connected to the aforementioned clock terminal CLK4 is greater than the width of the remaining clock signal lines among the multiple clock signal lines.

[0198] The resistances of the plurality of clock signal lines are extracted through software simulation, and lengths and widths of all the plurality of clock signal lines are fine-tuned to adjust the resistances of the plurality of clock signal lines.

[0199] FIG. 13 is a schematic diagram of compensation of a signal line according to an embodiment of the present disclosure.

[0200] As shown in Figure 13, Figure (a) shows the original state of the signal line. To increase the resistance of the signal line, the length of the signal line can be increased by routing it as shown in Figure (b), thereby increasing the resistance. To increase both the resistance of the signal line and the capacitor, a metal layer can be added above or below the signal line to compensate for the capacitance, as shown in Figure (c).

[0201] In PLG, RC compensation can be performed on the clock signal layer above the DC signal (power supply such as VGL / VDD). This is because the DC signal does not jump and is not easily affected by capacitance and noise.

[0202] Figure 14A is a schematic diagram of the structure of a display substrate according to an embodiment of the present disclosure. Figure 14B is a schematic diagram of the structure of a display substrate according to another embodiment of the present disclosure.

[0203] 14A and 14B illustrate the layout of the transistor M23 , the transistor M25 , the transistor M27 , the transistor M29 , the output signal line L1 , the output signal line L2 , the output signal line L3 , and the output signal line L4 in the display substrate.

[0204] The output signal line L1 is electrically connected to the transistor M23 , the output signal line L2 is electrically connected to the transistor M25 , the output signal line L3 is electrically connected to the transistor M27 , and the output signal line L4 is electrically connected to the transistor M29 .

[0205] As shown in FIG14A , transistors M23, M25, M27, and M29 are positioned at different locations. Transistors M23 and M29 are located closer to the output terminal, while transistors M25 and M27 are located further away from the output terminal. To ensure that the resistances of output signal lines L1, L2, L3, and L4 are similar, output signal lines L2 and L3 may be padded to equalize their lengths.

[0206] Output signal lines L2 and L3 can be bent in the blank areas of the PLG, increasing their length to prevent interference from high-frequency signals. If PLG space is limited, they can also be routed above the DC signal lines (the ones connected to the power supply).

[0207] In the shift register, since the scan signal OUT(4) has a long fall time, the resistance and capacitance that need to be compensated can be calculated based on formula (1) and the fall time difference, thereby fine-tuning the output signal line L4 to perform RC compensation. The compensation method can refer to the wiring method shown in Figure 13.

[0208] The capacitors and resistors used to compensate the output signal lines L1, L2, L3, and L4 may be different, and the routing lengths of the output signal lines L1, L2, L3, and L4 on the layout may also be different.

[0209] Since there are RC loads on the output signal lines L1, L2, L3 and L4, when providing scanning signals for a larger display screen, there will be differences in the scanning signals provided to the sub-pixels at the far and near ends.

[0210] For example, the driver circuits composed of shift registers can be distributed on the left and right sides of the pixel array. Within each row of subpixels in the pixel array, the subpixels on the two sides are closer to the corresponding shift registers and are therefore considered near-end pixels. Within each row of subpixels, the subpixels in the middle are farther from the corresponding shift registers and are therefore considered far-end pixels.

[0211] The resistances of the output signal lines L1 , L2 , L3 , and L4 are changed by the wiring method shown in FIG. 14B to compensate for the near and far terminal pixels.

[0212] As shown in Figure 14, the resistance of output signal lines L1, L2, L3, and L4 is increased by increasing their lengths. When the resistance of output signal lines L1, L2, L3, and L4 is increased, the relative difference between output signal lines L1, L2, L3, and L4 can be reduced, thereby reducing the difference in scanning signals received by pixels at the near and far terminals.

[0213] For example, capacitance compensation can be achieved through overlap. When there is overlap between the output signal line and the metal layer, overlap capacitance can be generated. This can be reduced by drilling holes in the lower layer of the output signal line.

[0214] 15A to 15D are layered layouts of the display substrate shown in FIG. 14A .

[0215] Figure 15A shows the shield layer of the display substrate shown in Figure 14A, Figure 15B shows the active layer of the display substrate shown in Figure 14A, Figure 15C shows the gate insulation (Gate Insulator, GI) layer of the display substrate shown in Figure 14A, and Figure 15D shows the gate layer of the display substrate shown in Figure 14A.

[0216] 16A to 16D are layered layouts of the display substrate shown in FIG. 14B .

[0217] Figure 16A shows the shield layer of the display substrate shown in Figure 14B, Figure 16B shows the active layer of the display substrate shown in Figure 14B, Figure 16C shows the gate insulation (Gate Insulator, GI) layer of the display substrate shown in Figure 14B, and Figure 16D shows the gate layer of the display substrate shown in Figure 14B.

[0218] FIG17 is a schematic structural diagram of a display device according to another embodiment of the present disclosure.

[0219] As shown in FIG. 17 , a display device 1700 includes a display substrate 1710 .

[0220] In the embodiment of the present disclosure, the display substrate 1710 may be the display substrate 800 or the display substrate 900 described above, which will not be described in detail for the sake of brevity.

[0221] FIG. 18 is a flowchart of a driving method according to another embodiment of the present disclosure.

[0222] As shown in FIG. 18 , the driving method may include operation S1810 .

[0223] In the embodiment of the present disclosure, the driving method may be applied to the display substrate 800 and the display substrate 900 described above.

[0224] In operation S1810, an input signal or an output signal of a shift register is compensated by a compensation circuit to obtain a plurality of scan signals, so as to control relative differences between falling times of the plurality of scan signals.

[0225] In the embodiment of the present disclosure, operation S18710 is similar to the operation performed by the display substrate 800 and the display substrate 900 described above, and is not repeated here.

[0226] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the above-mentioned module, program segment, or a part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0227] Those skilled in the art will appreciate that various combinations and / or combinations of features described in the various embodiments and / or claims of this disclosure may be made, even if such combinations or combinations are not explicitly described in this disclosure. In particular, various combinations and / or combinations of features described in the various embodiments and / or claims of this disclosure may be made, without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0228] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be used in combination to advantage. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A shift register comprising: an input circuit configured to control a potential of the first node under control of a first input signal from the first input terminal and a second input signal from the second input terminal; a control circuit configured to control the potential of the second node to be different from the potential of the first node under the control of the potential of the first node, the second input signal and a reset signal from a reset terminal; as well as The output circuit is configured to output a scan signal under the control of the potentials of the first node and the second node.

2. The shift register according to claim 1, wherein: The control circuit controls the potential of the second node under the control of the potential of the first node, the second input signal and the reset signal from the reset terminal, and is configured to: charging the second node by a first voltage of a first power supply under the control of a first level of the first node, the reset signal, and the second input signal; as well as Under the control of the second level of the first node, the potential of the second node is pulled down.

3. The shift register according to claim 1 or 2, wherein: The control circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor and a fifth transistor; wherein the control electrode of the first transistor is electrically connected to the second input terminal, the first electrode of the first transistor is electrically connected to a first power supply, and the second electrode of the first transistor is electrically connected to the control electrode of the third transistor; The control electrode of the second transistor is electrically connected to the reset terminal, the first electrode of the second transistor is electrically connected to the first power supply, and the second electrode of the second transistor is electrically connected to the control electrode of the third transistor; A first electrode of the third transistor is electrically connected to the first power supply, and a second electrode of the third transistor is electrically connected to the second node; a control electrode of the fourth transistor electrically connected to the first node, a first electrode of the fourth transistor electrically connected to the control electrode of the third transistor, and a second electrode of the fourth transistor electrically connected to a second power supply; and A control electrode of the fifth transistor is electrically connected to the first node, a first electrode of the fifth transistor is electrically connected to the second node, and a second electrode of the fifth transistor is electrically connected to a third power source.

4. The shift register according to claim 3, wherein: The control circuit further includes a first capacitor; The first end of the first capacitor is electrically connected to the first power source, and the second end of the first capacitor is electrically connected to the control electrode of the third transistor.

5. The shift register according to claim 3, wherein: The control circuit further includes a first capacitor; The first end of the first capacitor is electrically connected to the control electrode of the third transistor, and the second end of the first capacitor is electrically connected to the third power supply. The shift register according to claim 1 , wherein: The output circuit includes: The shift signal output terminal is configured to output a shift signal.

7. The shift register according to any one of claims 1 to 6, wherein: The output circuit includes a plurality of output terminals, and the plurality of output terminals are configured to output a plurality of scanning signals, and the plurality of scanning signals are used to drive a plurality of rows of sub-pixel units.

8. A driving circuit comprising a plurality of cascaded shift registers according to any one of claims 1 to 7.

9. The driving circuit according to claim 8, wherein: The first input terminal of the nth stage shift register is electrically connected to the shift signal output terminal of the n-2th stage shift register, and the second input terminal of the nth stage shift register is electrically connected to the shift signal output terminal of the n+2th stage shift register, where n is a positive integer.

10. A display device comprising: Display panel; as well as The driving circuit according to claim 8 or 9; The display panel includes a plurality of sub-pixel units arranged in an array, and the driving circuit is used to drive the sub-pixel units.

11. A driving method, applied to the shift register according to any one of claims 1 to 7, comprising: Under the control of a first input signal from the first input terminal and a second input signal from the second input terminal, the potential of the first node is controlled by the input circuit; Under the control of the potential of the first node, the second input signal and the reset signal from the reset terminal, controlling the potential of the second node to be different from the potential of the first node through the control circuit; as well as Under the control of the potentials of the first node and the second node, a scan signal is output through the output circuit.

12. A display substrate, comprising: shift register; as well as The compensation circuit is configured to compensate the input signal or the output signal of the shift register to obtain a plurality of scanning signals so as to control the relative difference between the falling times of the plurality of scanning signals.

13. The display substrate according to claim 12, wherein: The compensation circuit compensates the input signal of the shift register to obtain multiple scanning signals and is configured to: compensate multiple clock signals from multiple clock terminals to control the relative difference between the fall times of the multiple clock signals to obtain multiple compensated clock signals, so that the shift register outputs the multiple scanning signals based on the multiple compensated clock signals.

14. The display substrate according to claim 13, wherein: The compensation circuit includes a plurality of compensation sub-circuits, and the number of the plurality of compensation sub-circuits is the same as the number of the plurality of clock terminals.

15. The display substrate according to claim 14, wherein: Each of the plurality of compensation subcircuits comprises a compensation resistor and a compensation capacitor; wherein a first end of the compensation resistor is electrically connected to a clock end, and a second end of the compensation resistor is electrically connected to the shift register; and A first terminal of the compensation capacitor is electrically connected to the clock terminal, and a second terminal of the compensation capacitor is electrically connected to a fourth power supply.

16. The display substrate according to claim 13, wherein: The compensation circuit comprises: a plurality of clock signal lines, configured to compensate the plurality of clock signals to obtain a plurality of compensated clock signals; The length of one of the multiple clock signal lines is smaller than the length of the remaining clock signal lines, or the width of one of the multiple clock signal lines is larger than the width of the remaining clock signal lines.

17. The display substrate according to claim 13, wherein: The shift register includes a plurality of driving capacitors, and the number of the plurality of driving capacitors is the same as the number of the plurality of clock terminals; The capacitance of one driving capacitor among the plurality of driving capacitors is smaller than the capacitance of the remaining driving capacitors among the plurality of driving capacitors.

18. The display substrate according to claim 12 or 13, wherein: The compensation circuit comprises: a plurality of output signal lines, configured to compensate the output signal of the shift register to obtain the plurality of scanning signals; The length of one of the multiple output signal lines is shorter than the length of the remaining output signal lines, or the width of one of the multiple output signal lines is greater than the width of the remaining output signal lines.

19. The display substrate according to claim 12, wherein: The shift register comprises: an input circuit configured to control a potential of the first node under control of a first input signal from the first input terminal and a second input signal from the second input terminal; a control circuit configured to control the potential of the second node under the control of the potential of the first node, the second input signal, and a reset signal from a reset terminal; and The output circuit is configured to output a scan signal under the control of the potentials of the first node and the second node.

20. A display device comprising: The display substrate according to any one of claims 12 to 19.

21. A driving method, applied to the display substrate according to any one of claims 12 to 19, comprising: The input signal or the output signal of the shift register is compensated by a compensation circuit to obtain a plurality of scanning signals, so as to control the relative differences between the falling times of the plurality of scanning signals.

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