Display panel and display device

Abstract

A display panel. The display panel comprises spacer structures (24) and a partition unit (21). The orthographic projection of a first packaging structure (170 1) on a base substrate (11) covers the orthographic projection of the partition unit (21) on the base substrate (11), and the orthographic projection of a second packaging structure (1704) on the base substrate (11) covers the orthographic projections of the spacer structures (24) on the base substrate (11). The orthographic projection of the partition unit (21) on the base substrate (11) is located between the orthographic projections of two adjacent spacer structures (24) on the base substrate (11), so that the height of the second packaging structure (1704) is raised, the height of the first packaging structure (1701) is reduced, and a step between the second packaging structure (1704) and the first packaging structure (1701) is reduced. As a result, the first packaging structure (1701) and the second packaging structure (1704) form a closed complete structure, preventing cracks from appearing around an opening (300) of a packaging layer. Also provided is a display device comprising the display panel.

Description

Display panel and display device

[0001] Cross-references

[0002] This disclosure claims priority to Chinese patent application number 202410096221.7 filed on January 23, 2024, entitled “Display Panel and Display Device,” and the entire contents of this Chinese patent application are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0004] In order to enhance user experience, display devices are developing towards full-screen, among which the punch-hole screen is a trend in the development of full-screen, which is a technology that sets holes on the display panel to increase the screen-to-body ratio.

[0005] For display panels with openings, when the light-emitting material layer and the common electrode are separated, cracks are likely to appear in the packaging layer around the openings. The cracks become the intrusion paths for water and oxygen, which intrudes and causes the light-emitting material layer to corrode and fail, affecting normal display.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0007] The purpose of the present disclosure is to overcome the problem that cracks may easily appear around the opening of the encapsulation layer when the encapsulation layer separates the light-emitting material layer and the common electrode, and to provide a display panel and a display device.

[0008] According to one aspect of the present disclosure, a display panel is provided, comprising an aperture area, a display area, and a transition area connecting the display area and the aperture area, wherein the aperture area is provided with an aperture, the display panel comprises a base substrate, a spacer structure, at least one partition unit, and an encapsulation layer, wherein the spacer structure is provided on one side of the base substrate and is located in the transition area, the spacer structure surrounds the aperture, the spacer structure comprises a plurality of spacer layers sequentially arranged in a direction away from the base substrate, at least one spacer layer comprises two or more spacer units spaced apart; at least one partition unit is provided on a side of the spacer structure away from the base substrate and is located in the transition area, the partition unit surrounds the aperture, The partition unit and the spacer structure are insulated from each other, and the orthographic projection of the partition unit on the base substrate is located between the orthographic projections of two adjacent spacer units of at least one spacer layer on the base substrate; the encapsulation layer is arranged on the side of the partition unit away from the base substrate, and the encapsulation layer includes a first encapsulation structure and a second encapsulation structure, the second encapsulation structure is connected to both ends of the first encapsulation structure, the orthographic projection of the first encapsulation structure on the base substrate covers the orthographic projection of the partition unit on the base substrate, and the orthographic projection of the second encapsulation structure on the base substrate covers the orthographic projection of the spacer unit between the two adjacent partition units on the base substrate.

[0009] In one embodiment of the present disclosure, the display panel also includes a first gate insulating layer, a first gate electrode layer, a second gate insulating layer and a second gate electrode layer, the first gate insulating layer is arranged on one side of the base substrate; the first gate electrode layer is arranged on the side of the first gate insulating layer away from the base substrate; the second gate insulating layer is arranged on the side of the first gate electrode layer close to the base substrate; the second gate electrode layer is arranged on the side of the second gate insulating layer away from the base substrate, and the spacer structure includes a first spacer layer and a second spacer layer, the first spacer layer and the first gate electrode layer are arranged in the same layer and the same material, and the second spacer layer and the second gate electrode layer are arranged in the same layer and the same material.

[0010] In one embodiment of the present disclosure, the display panel also includes a third gate insulation layer and a third gate layer. The third gate insulation layer is arranged on the side of the second gate layer close to the base substrate, and the third gate layer is arranged on the side of the third gate insulation layer close to the base substrate. The pad structure also includes a third pad layer, and the third pad layer and the third gate layer are arranged in the same layer and material.

[0011] In one embodiment of the present disclosure, the first spacer layer includes a plurality of first spacer units arranged at intervals, and the second spacer layer includes a plurality of second spacer units arranged at intervals, the orthographic projections of the first spacer units on the base substrate overlap with the orthographic projections of the second spacer units on the base substrate, and both are covered by the orthographic projections of the second packaging structure on the base substrate.

[0012] In one embodiment of the present disclosure, the third spacer layer is arranged on the side of the second spacer layer away from the base substrate, and the third spacer layer includes a plurality of third spacer units arranged at intervals, and the orthographic projection of the third spacer unit on the base substrate overlaps with the orthographic projection of the first spacer unit and the second spacer unit on the base substrate.

[0013] In one embodiment of the present disclosure, the display panel further includes an interlayer dielectric layer, which is disposed on a side of the first gate insulating layer away from the base substrate. The interlayer dielectric layer is provided with a dielectric layer opening, and the partition unit is disposed in the dielectric layer opening.

[0014] In one embodiment of the present disclosure, the third spacer layer includes a plurality of spacer portions spaced apart from each other, the orthographic projection of the spacer portion on the base substrate being located between two adjacent first spacer units, and the orthographic projection of the partition unit on the base substrate being located within the orthographic projection of the spacer portion on the base substrate.

[0015] In one embodiment of the present disclosure, one of the first spacer layer, the second spacer layer or the third spacer layer is a whole layer structure, and the orthographic projections of the spacer units and the partition units of the other two layers on the base substrate are located within the orthographic projection of the third spacer layer on the base substrate.

[0016] In one embodiment of the present disclosure, the first packaging structure includes a first packaging part and a second packaging part, the second packaging part is connected to the two ends of the first packaging part, and the two second packaging parts are respectively connected to the two second packaging structures. The display panel also includes a blocking layer, which is arranged on the side of the packaging layer away from the base substrate, and the orthographic projection of the blocking layer on the packaging layer overlaps with at least the second packaging parts and the second packaging structure at both ends of the first packaging part.

[0017] In one embodiment of the present disclosure, the blocking layer includes a plurality of blocking units, each of which includes two first sub-blocking units, whose orthographic projections on the encapsulation layer overlap with the second encapsulation parts and the second encapsulation structure at both ends of the first encapsulation part.

[0018] In one embodiment of the present disclosure, the blocking unit further includes a second sub-blocking unit connected between the two first sub-blocking units, and an orthographic projection of the second sub-blocking unit on the base substrate covers the first packaging portion.

[0019] In one embodiment of the present disclosure, the barrier layer includes a barrier portion, which is a whole-layer structure. The orthographic projection of the barrier portion on the base substrate covers the first packaging structure and the second packaging structure between the two first packaging structures.

[0020] In one embodiment of the present disclosure, the display panel also includes a touch layer group, which is arranged on a side of the packaging layer away from the base substrate. The touch layer group includes a first touch control layer and a second touch control layer. The barrier layer is arranged in the same layer and material as one of the first touch control layer and the second touch control layer.

[0021] In one embodiment of the present disclosure, the partition unit includes a first partition structure, a second partition structure, and a third partition structure connected in sequence in a direction away from the base substrate. The width of the second partition structure is smaller than the width of the first partition structure and the third partition structure on the adjacent two sides. The orthographic projection of the first partition structure on the base substrate overlaps with the orthographic projection of the spacer units on both sides of the partition unit on the base substrate.

[0022] In one embodiment of the present disclosure, the display panel also includes a blocking dam, which is arranged on one side of the substrate and is located in the transition area. The transition area includes a first sub-transition area and a second sub-transition area. The first sub-transition area is located between the edge of the blocking dam and the edge of the opening, and the second sub-transition area is located between the edge of the blocking dam and the edge of the display area. The first sub-transition area is provided with at least one partition unit, and the second sub-transition area is provided with at least one partition unit. The partition unit of the first sub-transition area is a first partition unit, and the partition unit of the second sub-transition area is a second partition unit. The number of first partition units is greater than the number of second partition units.

[0023] In one embodiment of the present disclosure, the display panel further includes a power-off isolation unit, which is disposed between two first partition units closest to the blocking dam and at least partially covers a side of the first partition unit away from the base substrate.

[0024] According to another aspect of the present disclosure, a display device is provided, including the display panel provided by one aspect of the present disclosure.

[0025] The display panel disclosed herein includes a spacer structure and a partition unit, and the encapsulation layer includes a first encapsulation structure and a second encapsulation structure. The orthographic projection of the first encapsulation structure on the base substrate overlaps the orthographic projection of the partition unit on the base substrate, and the orthographic projection of the second encapsulation structure on the base substrate overlaps the orthographic projection of the spacer structure on the base substrate. The orthographic projection of the partition unit on the base substrate is located between two adjacent spacer structures, so that the partition unit and the spacer structure are staggered. This can raise the height of the second encapsulation structure, reduce the height of the first encapsulation structure, and reduce the step difference between the second encapsulation structure and the first encapsulation structure. This can form a closed and complete structure for the first encapsulation structure and the second encapsulation structure, avoid cracks in the encapsulation layer around the opening, slow down or prevent corrosion of the luminescent material layer, and ensure normal display of the display panel.

[0026] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0028] 1 is a partial cross-sectional schematic diagram of a display panel according to an embodiment of the present disclosure when the orthographic projection of a partition unit on a base substrate is located within the orthographic projection of a spacer structure on the base substrate.

[0029] 2 is a cross-sectional schematic diagram of a display panel according to an embodiment of the present disclosure, when the orthographic projection of a partition unit on a base substrate is located between two adjacent first spacer units and the barrier layer includes a plurality of barrier units.

[0030] FIG3 is a plan view of a display panel according to an embodiment of the present disclosure, wherein the orthographic projection of the partition unit on the base substrate is located between two adjacent first spacer units, and the barrier layer includes a plurality of barrier portions.

[0031] FIG4 is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure when a power-off isolation unit is provided between two first partition units closest to the barrier dam.

[0032] FIG5 is a partial cross-sectional schematic diagram of a display panel according to an embodiment of the present disclosure when the spacer structure includes a first spacer layer and a second spacer layer.

[0033] FIG6 is a partial cross-sectional schematic diagram of a display panel according to an embodiment of the present disclosure when the spacer structure includes a first spacer layer, a second spacer layer, and a third spacer layer.

[0034] 7 is a partial cross-sectional schematic diagram of the display panel according to an embodiment of the present disclosure when the partition unit is disposed in the dielectric layer opening and the orthographic projection of the third spacer unit on the base substrate is located between two adjacent first spacer units.

[0035] 8 is a partial cross-sectional schematic diagram of the display panel according to an embodiment of the present disclosure when the orthographic projections of two adjacent first spacer units on the base substrate are located within the orthographic projection of the third spacer layer on the base substrate.

[0036] FIG9 is a partial cross-sectional schematic diagram of a display panel according to an embodiment of the present disclosure, wherein the spacer structure may further include a fourth spacer layer and a fifth spacer layer, and the first planarization layer is thinned as a whole.

[0037] 10 is a partial cross-sectional schematic diagram of a display panel according to an embodiment of the present disclosure, wherein the spacer structure may further include a fourth spacer layer and a fifth spacer layer, and the first planarization layer of the blocking dam is retained while the first planarization layer of the remaining portion of the transition region is directly removed.

[0038] FIG11 is a partial cross-sectional schematic diagram of the display panel according to the embodiment of the present disclosure, when a portion of the first planarization layer between two adjacent fourth spacer units is removed.

[0039] 12 is a partial cross-sectional schematic diagram of the display panel according to an embodiment of the present disclosure, when a portion of the first planarization layer between two adjacent fourth spacer units is removed and a dielectric layer opening is provided on the interlayer dielectric layer.

[0040] 13 is a partial cross-sectional schematic diagram of the display panel according to the embodiment of the present disclosure when the orthographic projections of the two blocking portions on the base substrate respectively cover all the first encapsulation structures and the second encapsulation structures in the first sub-transition region and the second sub-transition region.

[0041] 14 is a partial cross-sectional schematic diagram of the display panel according to an embodiment of the present disclosure when the orthographic projections of two first sub-blocking units on the encapsulation layer overlap with the second encapsulation portions and the second encapsulation structure at both ends of the first encapsulation portion, respectively.

[0042] 15 is a partial cross-sectional schematic diagram of a display panel according to an embodiment of the present disclosure, wherein a second sub-blocking unit is connected between two first sub-blocking units and an orthographic projection of the second sub-blocking unit on the base substrate covers the first packaging portion.

[0043] FIG16 is a partial plan view of an opening and its surroundings of a display panel according to an embodiment of the present disclosure.

[0044] FIG17 is a layout of the first gate layer around the opening according to an embodiment of the present disclosure.

[0045] FIG18 is a layout of the second gate layer around the opening according to an embodiment of the present disclosure.

[0046] FIG19 is a layout of the first source / drain metal layer around the opening according to an embodiment of the present disclosure.

[0047] FIG20 is a layout of the second source / drain metal layer around the opening according to an embodiment of the present disclosure.

[0048] FIG21 is a layout of the first planarization layer around the opening involved in an embodiment of the present disclosure.

[0049] FIG22 is a layout of the second planarization layer around the opening involved in an embodiment of the present disclosure.

[0050] 23 is a layout of the first gate layer, the second gate layer, the first source-drain metal layer, the second source-drain metal layer, the first planarization layer, and the second planarization layer around the opening involved in an embodiment of the present disclosure.

[0051] In the figure: 100 - display area; 200 - transition area, 2001 - first sub-transition area, 2002 - second sub-transition area, 300 - opening;

[0052] 11- substrate, 12- buffer layer;

[0053] 13 - driving circuit layer, 131 - first active layer, 1321 - first gate insulating layer, 1322 - second gate insulating layer, 1323 - third gate insulating layer, 1324 - fourth gate insulating layer, 1331 - first gate electrode, 1332 - second gate electrode, 134 - interlayer dielectric layer, 1341 - dielectric layer opening, 135 - first source electrode, 136 - drain electrode, 137 - protective layer, 138 - second source electrode, 1391 - first gate line, 1392 - second gate line, 1393 - first data line, 1394 - second data line;

[0054] 14-planarization layer group, 141-first planarization layer, 142-second planarization layer;

[0055] 15-pixel definition layer, 151-pixel opening;

[0056] 16-light-emitting layer, 161-pixel electrode, 162-light-emitting element, 163-common electrode;

[0057] 17-encapsulation layer, 171-first inorganic encapsulation layer, 172-organic encapsulation layer, 173-second inorganic encapsulation layer, 1701-first encapsulation structure, 1702-first encapsulation part, 1703-second encapsulation part, 1704-second encapsulation structure;

[0058] 18 - touch control layer, 181 - first passivation layer, 182 - first touch control layer, 183 - second passivation layer, 184 - second touch control layer;

[0059] 19-covering layer;

[0060] 20-blocking dam;

[0061] 201-first insulating layer, 202-second insulating layer, 203-third insulating layer;

[0062] 21-partition unit, 211-first partition unit, 212-second partition unit, 213-third partition structure, 214-second partition structure, 215-first partition structure;

[0063] 22 - luminescent material portion, 221 - first luminescent material portion, 222 - second luminescent material portion, 223 - third luminescent material portion;

[0064] 23 - common electrode portion, 231 - first common electrode portion, 232 - second common electrode portion, 233 - third common electrode portion;

[0065] 24-gasket structure, 241-first gasket layer, 2411-first gasket unit, 242-second gasket layer, 2421-second gasket unit, 243-third gasket layer, 2431-third gasket unit, 244-fourth gasket layer, 2441-fourth gasket unit, 245-fifth gasket layer, 2451-fifth gasket unit;

[0066] 251-blocking unit, 2511-first sub-blocking unit, 2512-second sub-blocking unit, 252-blocking portion;

[0067] 26-Power-off isolation unit. DETAILED DESCRIPTION

[0068] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0069] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0070] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0071] To enhance user experience, display devices are moving towards full-screen displays. Punch-hole displays, a technology that incorporates a hole in the display panel and houses the camera, thereby increasing the display's screen-to-body ratio, are a key trend in the current development of full-screen displays. To ensure optimal display quality, a partition unit is required to separate the cathode and light-emitting material layers, which are then encapsulated with an encapsulation layer.

[0072] As shown in Figure 1, the display panel includes a base substrate 11, a spacer structure 24, a partition unit 21 and an encapsulation layer 17. The spacer structure 24 is arranged on one side of the base substrate 11, and the partition unit 21 is arranged on the side of the spacer structure 24 away from the base substrate 11. The orthographic projection of the partition unit 21 on the base substrate 11 is located within the orthographic projection of the spacer structure 24 on the base substrate 11. The encapsulation layer 17 is arranged on the side of the spacer unit away from the base substrate 11. The encapsulation layer 17 is arranged on the side of the partition unit away from the base substrate 11. The encapsulation layer 17 includes a first encapsulation structure 1701 and a second encapsulation structure 1704. The second encapsulation structure 1704 is connected to both ends of the first encapsulation structure 1701. The orthographic projection of the first encapsulation structure 1701 on the base substrate 11 covers the orthographic projection of the partition unit 21 on the base substrate 11. The orthographic projection of the second encapsulation structure 1704 on the base substrate 11 is located between the orthographic projections of adjacent partition units 21 on the base substrate 11.

[0073] The spacer structure 24 includes multiple spacer layers arranged along the thickness of the display panel. Each spacer layer includes multiple spacer units spaced apart from each other. The orthographic projections of the spacer units of different spacer layers on the base substrate 11 overlap, resulting in a large step difference between the side of the first encapsulation structure 1701 away from the base substrate 11 and the side of the second encapsulation structure 1704 away from the base substrate 11. This makes it easy for the encapsulation layer 17 to crack at the connection between the first encapsulation structure 1701 and the second encapsulation structure 1704. This allows water vapor to invade through these cracks. The invasion of water and oxygen causes corrosion and failure of the luminescent material layer, affecting normal display. Therefore, how to slow down or prevent corrosion of the luminescent material layer and improve the encapsulation effect of the display panel is the main improvement direction of the embodiment of the present disclosure.

[0074] Based on this, an embodiment of the present disclosure provides a display panel. As shown in Figures 2 to 18, the display panel has an opening 300 area, a display area 100, and a transition area 200 connecting the display area 100 and the opening 300 area. The opening 300 area is provided with an opening 300. The display panel includes a base substrate 11, a spacer structure 24, at least one partition unit 21, and an encapsulation layer 17. The spacer structure 24 is provided on one side of the base substrate 11 and is located in the transition area 200. The spacer structure 24 surrounds the opening 300. The spacer structure 24 includes a plurality of spacer layers sequentially arranged in a direction away from the base substrate 11, and at least one spacer layer includes two or more spacer units arranged at intervals. At least one partition unit 21 is provided on a side of the spacer structure 24 away from the base substrate 11 and is located in the transition area 200. The partition unit 21 surrounds the opening 300. The partition unit 21 and the spacer structure 24 are insulated from each other, the orthographic projection of the partition unit 21 on the base substrate 11 is located between the orthographic projections of two adjacent spacer units on the base substrate 11, and the height of the partition unit 21 is greater than the height of the spacer structure 24; the encapsulation layer 17 is provided on the side of the partition unit 21 away from the base substrate 11, the encapsulation layer 17 includes a first encapsulation structure 1701 and a second encapsulation structure 1704, the second encapsulation structure 1704 is connected to both ends of the first encapsulation structure 1701, the orthographic projection of the first encapsulation structure 1701 on the base substrate 11 covers the orthographic projection of the partition unit 21 on the base substrate 11, and the orthographic projection of the second encapsulation structure 1704 on the base substrate 11 covers the orthographic projection of the spacer structure 24 on the base substrate 11.

[0075] The orthographic projection of the first encapsulation structure 1701 on the base substrate 11 overlaps the orthographic projection of the partition unit 21 on the base substrate 11, and the orthographic projection of the second encapsulation structure 1704 on the base substrate 11 overlaps the orthographic projection of the spacer structure 24 on the base substrate 11. The orthographic projection of the partition unit 21 on the base substrate 11 is located between two adjacent spacer structures 24, so that the partition unit 21 and the spacer structure 24 are staggered. This can raise the height of the second encapsulation structure 1704, reduce the height of the first encapsulation structure 1701, and reduce the step difference between the second encapsulation structure 1704 and the first encapsulation structure 1701. This can form a closed and complete structure between the first encapsulation structure 1701 and the second encapsulation structure 1704, thereby preventing cracks in the encapsulation layer 17 around the opening 300, slowing down or preventing corrosion of the light-emitting material layer, and ensuring normal display of the display panel.

[0076] The display panel involved in the embodiments of the present disclosure will be described in detail below with reference to specific embodiments.

[0077] As shown in Figures 2 to 4 , a display panel may generally include a base substrate 11, a driving circuit layer 13, a planarization layer group 14, and a light-emitting layer 16. The driving circuit layer 13 is disposed on one side of the base substrate 11, the planarization layer group 14 is disposed on a side of the driving circuit layer 13 away from the base substrate 11, and the light-emitting layer 16 is disposed on a side of the planarization layer group 14 away from the base substrate 11. In addition, the display panel may further include a buffer layer 12, which is disposed between the base substrate 11 and the driving circuit layer 13.

[0078] The base substrate 11 may be an inorganic material or an organic material. For example, in one embodiment of the present disclosure, the base substrate 11 may be made of a glass material such as soda-lime glass, quartz glass, or sapphire glass, or may be made of a metal material such as stainless steel, aluminum, or nickel.

[0079] In another embodiment of the present disclosure, the substrate 11 may be a flexible substrate 11. For example, the substrate 11 may be made of polyimide (PI). The substrate 11 may also be a composite of multiple layers. For example, in one embodiment of the present disclosure, the substrate 11 may include a bottom film layer, a pressure-sensitive adhesive layer, a first polyimide layer, and a second polyimide layer stacked in sequence.

[0080] In the display area 100, the driving circuit layer 13 is provided with a driving circuit for driving the light-emitting unit. The driving circuit is located in the display area 100. Any driving circuit may include a transistor, which may be a thin film transistor. The thin film transistor may be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor. Taking a top-gate thin film transistor as an example, the driving circuit layer 13 may include a first active layer 131, a first gate layer, a second gate layer, a first gate insulating layer 1321, a second gate insulating layer 1322, and a first source and drain metal layer, which are sequentially arranged in a direction away from the base substrate 11.

[0081] The first active layer 131 is disposed on one side of the base substrate 11. The material of the first active layer 131 can be amorphous silicon semiconductor material, low-temperature polysilicon semiconductor material, metal oxide semiconductor material, organic semiconductor material, or other types of semiconductor materials. Therefore, the thin film transistor can be an N-type thin film transistor or a P-type thin film transistor. The first active layer 131 can include a channel region and two doped regions of different doping types located on either side of the channel region.

[0082] The first gate insulating layer 1321 is disposed on a side of the active layer away from the substrate 11. The first gate insulating layer 1321 may cover the active layer and the substrate 11. The first gate layer may include a first gate electrode 1331. The first gate electrode 1331 is disposed on a side of the first gate insulating layer 1321 away from the substrate 11 and directly opposite the active layer. That is, the projection of the first gate electrode 1331 on the substrate 11 is within the projection of the active layer on the substrate 11. For example, the projection of the first gate electrode 1331 on the substrate 11 coincides with the projection of the channel region of the active layer on the substrate 11. The second gate insulating layer 1322 is disposed on a side of the first gate electrode 1331 away from the substrate 11. The second gate insulating layer 1322 may cover the first gate electrode 1331 and the first gate insulating layer 1321. The second gate layer may include a second gate electrode 1332. The second gate electrode 1332 is disposed on a side of the second gate insulating layer 1322 away from the substrate 11 and directly opposite the active layer. The first gate insulating layer 1321 and the second gate insulating layer 1322 are both made of insulating materials such as silicon oxide.

[0083] The thin film transistor may further include an interlayer dielectric layer 134, which is disposed on a side of the first gate electrode 1331 away from the base substrate 11. The interlayer dielectric layer 134 may cover the first gate electrode 1331 and the first gate insulating layer 1321. A first source-drain metal layer is disposed on a surface of the interlayer dielectric layer 134 away from the base substrate 11, and the first source-drain metal layer may include a first source electrode 135 and a drain electrode 136. The first source electrode 135 and the drain electrode 136 are connected to the first active layer 131. For example, the first source electrode 135 and the drain electrode 136 are respectively connected to the two corresponding doped regions of the first active layer 131 through vias.

[0084] A protective layer 137 may also be provided on the side of the first source electrode 135 away from the base substrate 11, and the protective layer 137 covers the first source electrode 135 and the drain electrode 136. A first planarization layer 141 is provided on the side of the protective layer 137 away from the base substrate 11, and the first planarization layer 141 covers the protective layer 137. It should be noted that the first source electrode 135 and the drain electrode 136 are located in the first source-drain metal layer of the driving circuit layer 13, and the second source electrode 138 is located in the second source-drain metal layer of the driving circuit layer 13.

[0085] A second source / drain metal layer is disposed on the side of the first planarization layer 141 away from the base substrate 11, and the surface of the first planarization layer 141 away from the base substrate 11 is flat. The second source / drain metal layer may also include a second source electrode 138, which is connected to the first source electrode 135. A second planarization layer 142 is disposed on the side of the second source electrode 138 away from the base substrate 11, and covers the second source electrode 138 and the first planarization layer 141.

[0086] The pixel defining layer 15 is disposed on the side of the first planarizing layer 141 or the second planarizing layer 142 away from the array substrate. The pixel defining layer 15 has a plurality of pixel openings 151. The light-emitting layer 16 may include a plurality of light-emitting units, each of which is disposed within a different pixel opening 151. Each light-emitting unit may include a pixel electrode 161, a light-emitting element 162, and a common electrode 163. The pixel electrode 161 is located on the surface of the first planarizing layer 141 or the second planarizing layer 142 away from the base substrate 11. The light-emitting element 162 is disposed on the surface of the pixel electrode 161 away from the base substrate 11. The common electrode 163 is disposed on the surface of the light-emitting element 162 away from the base substrate 11. The pixel electrode 161 and the common electrode 163 can be used to drive the light-emitting element 162 to emit light, thereby displaying an image.

[0087] The pixel electrode 161 is connected to the first source electrode 135 or the second source electrode 138. A pixel defining layer 15 is provided on the side of the pixel electrode 161 away from the substrate 11. When the thin film transistor includes only the first source electrode 135, the pixel electrode 161 is connected to the first source electrode 135, and the pixel defining layer 15 covers the pixel electrode 161 and the first planarization layer 141. When the thin film transistor also includes the second source electrode 138, the pixel electrode 161 is connected to the second source electrode 138, and the pixel defining layer 15 covers the pixel electrode 161 and the second planarization layer 142.

[0088] The common electrode 163 can serve as a cathode, and the pixel electrode 161 can serve as an anode. The light-emitting element 162 can be driven to emit light by applying a signal to the pixel electrode 161. The specific light-emitting principle will not be described in detail here. The light-emitting element 162 may include an electro-induced organic light-emitting material and may be formed by a process such as evaporation. For example, the light-emitting element 162 may include a hole injection layer, a hole transport layer, a light generating layer, an electron transport layer, and an electron injection layer sequentially stacked on the pixel electrode 161 layer. It should be noted that the light-emitting element 162 may include a red light-emitting element 162, a green light-emitting element 162, and a blue light-emitting element 162, depending on the color of the light emitted.

[0089] In addition, the display panel of the present disclosure may further include an encapsulation layer 17. Encapsulation layer 17 is disposed on the side of light-emitting layer 16 away from substrate 11, thereby encapsulating light-emitting layer 16 and preventing corrosion by water and oxygen. Encapsulation layer 17 may have a single-layer or multi-layer structure, and the material of encapsulation layer 17 may include organic or inorganic materials, without particular limitation herein.

[0090] In this embodiment, the encapsulation layer 17 may include a first inorganic encapsulation layer 171, an organic encapsulation layer 172 and a second inorganic encapsulation layer 173. The first inorganic encapsulation layer 171 is arranged on the side of the light-emitting layer 16 away from the base substrate 11, the organic encapsulation layer 172 is arranged on the side of the first inorganic encapsulation layer 171 away from the base substrate 11, and the second inorganic encapsulation layer 173 is arranged on the side of the organic encapsulation layer 172 away from the base substrate 11.

[0091] The display panel also includes a touch control layer 18, which can be a mutual capacitance touch control layer. The touch control layer 18 includes a first touch control layer 182 and a second touch control layer 184. The first touch control layer 182 can be a metal mesh layer (Metal Mesh, MM), and the second touch control layer 184 can be a bridge metal layer (Bridge Metal, BM). The first touch control layer 182 can also be a bridge metal layer (Bridge Metal, BM), and the second touch control layer 184 can be a metal mesh layer (Metal Mesh, MM).

[0092] The touch control layer 18 also includes a first passivation layer 181 and a second passivation layer 183. The first passivation layer 181 is arranged on the side of the encapsulation layer 17 away from the base substrate 11. The first touch control layer 182 is arranged on the side of the first passivation layer 181 away from the base substrate 11. The second passivation layer 183 is arranged on the side of the first touch control layer 182 away from the base substrate 11. The second touch control layer 184 is arranged on the side of the second passivation layer 183 away from the base substrate 11. The covering layer 19 is arranged on the side of the second touch control layer 184 away from the base substrate 11.

[0093] The display panel also includes an opening 300 region and a transition region 200. The opening 300 is provided in the opening 300 region, and the transition region 200 is located between the edge of the opening 300 and the edge of the display area 100. Due to the flow of liquid organic encapsulating material, it is prone to overflow. To prevent this, a barrier dam 20 is provided in the transition region 200. The barrier dam 20 is located on the side of the protective layer 137 away from the base substrate 11. The barrier dam 20 surrounds the opening 300 and serves as a barrier. The cross-sectional shape of the barrier dam 20 can be rectangular or trapezoidal, and at least the side of the barrier dam 20 near the display area 100 is inclined, although this is not limited here.

[0094] The stacked pattern of the barrier dam 20 includes an insulating layer group, which is provided with the same material as one or more layers of the first planarization layer 141, the second planarization layer 142, and the pixel defining layer 15. As shown in Figure 2, the stacked pattern of the barrier dam 20 includes a first insulating layer 201, which is provided with the same layer and material as the first planarization layer 141. A second insulating layer 202 may be provided on the first insulating layer 201, and the second insulating layer 202 may be provided with the same layer and material as the second planarization layer 142. A third insulating layer 203 may be provided on the second insulating layer 202, and the third insulating layer 203 may be provided with the same layer and material as the pixel defining layer 15. The side of the barrier dam 20 away from the base substrate 11 is provided with a third light-emitting material portion 223, a third common electrode portion 233, a third encapsulation portion 1703, a first passivation layer 181, and a second passivation layer 183 in this order.

[0095] The first gate insulating layer 1321, the second gate insulating layer 1322, the third gate insulating layer 1323, and the interlayer dielectric layer all extend from the display area 100 to the first sub-transition region 2001 and the second sub-transition region 2002, and then extend from the second sub-transition region 2002 to the edge of the opening 300. A partition unit 21 is provided on the side of the interlayer dielectric layer away from the base substrate 11. In this embodiment, the partition unit 21 can be provided in the same layer and material as the second source / drain metal layer. In other embodiments, the partition unit 21 can also be provided in the same layer and material as the first source / drain metal layer.

[0096] The width of at least part of the partition unit 21 is smaller than the width of the side away from the base substrate 11. Specifically, the partition unit 21 can be set to a structure that is wide at both ends and narrow in the middle, or it can be set to an inverted trapezoidal structure in which the width gradually decreases from the end away from the base substrate 11 to the end close to the base substrate 11, or the partition unit 21 can be set to other structures that are concave (undercut) in its height direction. In this embodiment, the partition unit 21 includes a first partition structure 215, a second partition structure 214 and a third partition structure 213 connected in sequence along the direction away from the base substrate 11, and the width of the second partition structure 214 is smaller than the width of the first partition structure 215 and the third partition structure 213 on the adjacent two sides. For example, the material of the first partition structure 215 and the third partition structure 213 can be titanium, and the material of the second partition structure 214 can be aluminum.

[0097] The light-emitting material layer extends from the display area 100 to the transition area 200 and is located on the side of the partition unit 21 away from the base substrate 11. The light-emitting material layer is partitioned by the partition unit 21 to form multiple light-emitting material sections 22. The common electrode 163 located on the side of the light-emitting material layer away from the base substrate 11 is also partitioned by the partition unit 21 to form multiple common electrode sections 23.

[0098] The transition region 200 includes a first sub-transition region 2001 and a second sub-transition region 2002. The first sub-transition region 2001 is located between the edge of the blocking dam 20 and the edge of the opening 300, and the second sub-transition region 2002 is located between the edge of the blocking dam 20 and the edge of the display area 100. That is, the second sub-transition region 2002 is arranged close to the display area 100, and the first sub-transition region 2001 is arranged farther away from the display area 100 than the second sub-transition region 2002.

[0099] To improve the barrier effect, both the first sub-transition region 2001 and the second sub-transition region 2002 are provided with at least two barrier units 21. The first barrier units 211 are located in the first sub-transition region 2001, and the second barrier units 212 are located in the second sub-transition region 2002. Because the first sub-transition region 2001 is closer to the edge of the opening 300, the number of first barrier units 211 is typically greater than the number of second barrier units 212. For example, the first sub-transition region 2001 may be provided with six first barrier units 211, while the second sub-transition region 2002 may be provided with two second barrier units 212.

[0100] The luminescent material portion 22 is divided into a first luminescent material portion 221 and a second luminescent material portion 222. The first luminescent material portion 221 is located on the side of the partition unit 21 away from the base substrate 11, and the second luminescent material portion 222 is located between two adjacent partition units 21. Similarly, the common electrode portion 23 is divided into a first common electrode portion 231 and a second common electrode portion 232. The first common electrode portion 231 is located on the side of the partition unit 21 away from the base substrate 11, and the second common electrode portion 232 is located between two adjacent partition units 21. The second common electrode portion 232 connects the two adjacent partition units 21, thereby charging the common electrode portions 23 located in the transition region 200. This energizes the partition units 21, causing electrochemical corrosion of the partition units 21 under the action of water and oxygen, causing cracks to form in the encapsulation layer 17 in the transition region 200, creating a new path for water and oxygen intrusion.

[0101] As shown in Figure 3, the display panel may also include a power-off isolation unit 26, which is arranged between the two first isolation units 211 closest to the blocking dam 20. The power-off isolation unit 26 at least partially covers the side of the first isolation unit 211 away from the base substrate 11, so that the second common electrode portion 232 between the two first isolation units 211 closest to the blocking dam 20 is moved up to the side of the power-off isolation unit 26 away from the base substrate 11, and there is a second light-emitting material portion 222 between the second common electrode portion 232 and the power-off isolation unit 26. Therefore, the second common electrode portion 232 between the two first isolation units 211 closest to the blocking dam 20 is disconnected from the two second common electrode portions 232 on the side of the two first isolation units 211 closest to the blocking dam 20 away from each other, thereby avoiding electrochemical corrosion of other first isolation units 211.

[0102] The encapsulation layer 17 is disposed on the side of the common electrode 163 away from the base substrate 11. The encapsulation layer 17 includes a first encapsulation structure 1701 and a second encapsulation structure 1704. The second encapsulation structure 1704 is connected to both ends of the first encapsulation structure 1701. The orthographic projection of the first encapsulation structure 1701 on the base substrate 11 overlaps the orthographic projection of the partition unit 21 on the base substrate 11. The orthographic projection of the second encapsulation structure 1704 on the base substrate 11 overlaps the orthographic projection of the spacer unit between two adjacent partition units 21 on the base substrate 11. The first encapsulation structure 1701 includes a first encapsulation portion 1702 and a second encapsulation portion 1703. The side of the first encapsulation portion 1702 away from the base substrate 11 is higher than the side of the second encapsulation structure 1704 away from the base substrate 11. The second encapsulation portion 1703 is connected to both ends of the first encapsulation portion 1702. The second encapsulation portion 1703 is inclined toward the side closer to the base substrate 11. The two second encapsulation portions 1703 are respectively connected to the two second encapsulation structures 1704.

[0103] A spacer structure 24 is provided between the partition unit 21 and the base substrate 11. The spacer structure 24 includes multiple spacer layers sequentially arranged in a direction away from the base substrate 11, with at least one spacer layer including two or more spacer units spaced apart from each other. The encapsulation layer 17 is provided on the side of the partition unit 21 away from the base substrate 11. As shown in Figures 5 to 11, in order to reduce the step difference between the first encapsulation structure 1701 and the second encapsulation structure 1704, the spacer units of some of the spacer layers can be moved between two adjacent partition units 21, so that the orthographic projection of the second encapsulation structure 1704 on the base substrate 11 overlaps the orthographic projection of the spacer units between the two adjacent partition units 21 on the base substrate 11. In this way, the height of the second encapsulation structure 1704 can be raised, the height of the first encapsulation structure 1701 can be reduced, and the step difference between the second encapsulation structure 1704 and the first encapsulation structure 1701 can be reduced.

[0104] As shown in FIG5 , the spacer structure 24 includes a first spacer layer 241 and a second spacer layer 242. The first spacer layer 241 is disposed on one side of the base substrate 11, and the second spacer layer 242 is disposed on the side of the first spacer layer 241 closer to the base substrate 11. The first spacer layer 241 is formed of the same layer and material as the first gate electrode 1331, while the second spacer layer 242 is formed of the same layer and material as the second gate electrode 1332. The first spacer layer 241 includes a plurality of first spacer units 2411 spaced apart from each other, each spacer unit 2411 being disposed between two adjacent partition units 21. The second spacer layer 242 includes a plurality of second spacer units 2421 spaced apart from each other, with the orthographic projections of the second spacer units 2421 on the base substrate 11 overlapping with the orthographic projections of the first spacer units 2411 on the base substrate 11.

[0105] The orthographic projection of the partition unit 21 on the base substrate 11 is located between the orthographic projections of two adjacent first spacer units 2411 on the base substrate 11. Of course, the orthographic projection of the partition unit 21 on the base substrate 11 is also located between the orthographic projections of two adjacent second spacer units 2421 on the base substrate 11. The first spacer units 2411 and the second spacer units 2421 can increase the height of the second packaging structure 1704.

[0106] Because the driving circuit layer 13 typically includes multiple thin-film transistors, and different thin-film transistors may be located in different layers, the display panel may further include a third gate. A third gate insulating layer 1323 is located on the side of the second gate 1332 away from the base substrate 11, specifically between the second gate 1332 and the interlayer dielectric layer 134. The third gate may form a thin-film transistor located in another layer of the driving circuit layer 13 with other active layers. Typically, to facilitate the placement of other metal layers, a fourth gate insulating layer 1324 is also provided on the side of the third gate away from the base substrate 11.

[0107] As shown in Figure 6, in order to further reduce the step difference between the second packaging structure 1704 and the first packaging structure 1701, the display panel may also include a third spacer layer 243. The third spacer layer 243 may be set in the same layer and material as the third gate. The third spacer layer 243 includes a plurality of third spacer units 2431 arranged at intervals. The orthographic projection of the third spacer unit 2431 on the base substrate 11 overlaps with the orthographic projection of the first spacer unit 2411 and the second spacer unit 2421 on the base substrate 11, thereby further raising the height of the second packaging structure 1704.

[0108] As shown in Figures 7 and 8, in addition to raising the height of the second encapsulation structure 1704, the height difference between the first encapsulation structure 1701 and the second encapsulation structure 1704 can also be reduced by lowering the height of the first encapsulation structure 1701. Specifically, a dielectric layer opening 1341 can be provided on the interlayer dielectric layer, and the partition unit 21 is provided within the dielectric layer opening 1341. The dielectric layer opening 1341 can be a groove provided on the interlayer dielectric layer, or it can be a through hole penetrating the interlayer dielectric layer. In this embodiment, the dielectric layer opening 1341 is a through hole penetrating the interlayer dielectric layer.

[0109] Because the thickness of the interlayer dielectric layer is typically greater than that of the first gate 1331, the second gate 1332, and the third gate layer, in order to prevent the partition unit 21 from moving downward too much and affecting the isolation effect on the light-emitting material layer and the common electrode 163, as shown in FIG7 , when the partition unit 21 is disposed within the dielectric layer opening 1341, the orthographic projection of the third spacer unit 2431 on the base substrate 11 can also be positioned between two adjacent first spacer units 2411, and the orthographic projection of the partition unit 21 on the base substrate 11 can be positioned within the orthographic projection of the third spacer unit 2431 on the base substrate 11. By slightly raising the partition unit 21 with the third spacer unit 2431, cracks in the encapsulation layer 17 can be avoided while ensuring the isolation effect.

[0110] As shown in Figure 8, the third spacer layer 243 can also be set as a whole layer, so that the orthographic projections of two adjacent first spacer units 2411 on the base substrate 11 are located within the orthographic projection of the third spacer layer 243 on the base substrate 11, and the orthographic projection of the partition unit 21 on the base substrate 11 is located within the orthographic projection of the third spacer layer 243 on the base substrate 11.

[0111] As shown in Figure 9, the spacer structure 24 may also include a fourth spacer layer and a fifth spacer layer. The fourth spacer layer is provided in the same layer and material as the first source / drain metal layer, and the fifth spacer layer is provided in the same layer and material as the second source / drain metal layer. The fourth spacer layer includes a plurality of fourth spacer units 2441 spaced apart, and the fifth spacer layer includes a plurality of fifth spacer units 2451 spaced apart. The orthographic projections of the fourth spacer units 2441 and the fifth spacer units 2451 on the base substrate 11 overlap with the orthographic projection of the third spacer unit 2431 on the base substrate 11. The spacer structure 24 may include at least two layers of the first spacer layer, the second spacer layer, the third spacer layer, the fourth spacer layer, and the fifth spacer layer. In order to avoid filling the grooves formed between adjacent partitions when the planarization layer is thick, the first planarization layer may be thinned as a whole.

[0112] As shown in Figure 10, when the spacer structure includes a fourth spacer layer and a fifth spacer layer, only the first planarization layer of the barrier dam can be retained, and the first planarization layer of the remaining portion of the transition region can be directly removed. As shown in Figure 11, the portion of the first planarization layer located between two adjacent fourth spacer units 2441 can be further removed to reduce the height of the partition unit 21, while the spacer between the fourth spacer unit 2441 and the fifth spacer unit 2451 is still retained. This can further reduce the step difference between the side of the first packaging portion away from the base substrate and the side of the second packaging structure away from the base substrate, making the packaging layer in this area more flat.

[0113] As shown in Figure 12, a dielectric layer opening may be provided in the interlayer dielectric layer to further reduce the step difference between the side of the first packaging portion away from the base substrate and the side of the second packaging structure away from the base substrate. To prevent the side of the first packaging portion away from the base substrate from dropping too much, when the spacer structure includes a fourth spacer layer and a fifth spacer layer, at least one of the first spacer layer, the second spacer layer, or the third spacer layer may be provided between the partition unit and the base substrate to better adjust the step difference between the side of the first packaging portion away from the base substrate and the side of the second packaging structure away from the base substrate.

[0114] As shown in Figures 4 and 13, to prevent cracks from forming at the connection between first encapsulation structure 1701 and second encapsulation structure 1704 even after the height difference between first encapsulation structure 1701 and second encapsulation structure 1704 is reduced, a barrier layer is provided on the side of encapsulation layer 17 away from base substrate 11. The barrier layer is formed from the same layer and material as one of first touch control layer 182 and second touch control layer 184. The barrier layer includes two barrier portions 252, which form a single layer. The orthographic projections of the two barrier portions 252 on base substrate 11 cover all of first encapsulation structure 1701 and second encapsulation structure 1704 in first sub-transition region 2001 and second sub-transition region 2002, respectively. This shields locations where cracks are likely to form and prevents moisture from entering when cracks do occur.

[0115] As shown in Figures 2, 3, and 14, to avoid the serious reflection problem caused by the large-area barrier layer, the barrier layer is configured to include multiple barrier units 251. The barrier unit 251 includes two first sub-barrier units 2511. The orthographic projections of the two first sub-barrier units 2511 on the encapsulation layer 17 overlap with the second encapsulation portion 1703 and the second encapsulation structure 1704 at both ends of the first encapsulation portion 1702. As shown in Figure 15, to prevent the barrier unit 251 from leaking cracks, the barrier unit 251 further includes a second sub-barrier unit 2512. The second sub-barrier unit 2512 is connected between the two first sub-barrier units 2511. The orthographic projection of the second sub-barrier unit 2512 on the base substrate 11 covers the first encapsulation portion 1702.

[0116] As shown in Figure 16 , the partition unit 21 surrounds the opening 300, the spacer structure 24 surrounds the opening 300, and the barrier dam 20 surrounds the opening 300. As shown in Figure 17 , the first spacer units 2411 of the first spacer layer 241 are arranged around the opening 300, and the distance between two adjacent first spacer units 2411 of the first spacer layer 241 is equal. A portion of the first gate lines 1391 runs from the display area 100 on one side of the opening 300, through the upper half of the opening 300, and around to the display area 100 on the other side of the opening 300. Another portion of the first gate lines 1391 runs through the lower half of the opening 300 and around to the display area 100 on the other side of the opening 300.

[0117] As shown in Figure 18, the second spacer units 2421 of the second spacer layer 242 are arranged around the opening 300, and the distance between two adjacent second spacer units 2421 of the second spacer layer 242 is equal. The distance between two adjacent first spacer units 2411 of the first spacer layer 241 is a first distance, and the distance between two adjacent second spacer units 2421 of the second spacer layer 242 is a second distance, and the first distance is equal to the second distance. A portion of the second gate lines 1392 runs from the display area 100 on one side of the opening 300, passes through the upper half of the opening 300, and then around to the display area 100 on the other side of the opening 300. The other portion of the second gate lines 1392 passes through the lower half of the opening 300 and then around to the display area 100 on the other side of the opening 300.

[0118] As shown in Figure 19, a portion of the first data line 1393 runs from the display area 100 on one side of the opening 300, passes through the upper half of the opening 300, and then goes to the display area 100 on the other side of the opening 300. Another portion of the first data line 1393 runs from the display area 100 on one side of the opening 300, passes through the lower half of the opening 300, and then goes to the display area 100 on the other side of the opening 300.

[0119] As shown in Figure 20, a portion of the second data line 1394 runs from the display area 100 on one side of the opening 300, passes through the upper half of the opening 300, and goes around to the display area 100 on the other side of the opening 300. Another portion of the second data line 1394 runs from the display area 100 on one side of the opening 300, passes through the lower half of the opening 300, and goes around to the display area 100 on the other side of the opening 300.

[0120] As shown in Figures 20 to 23, the orthographic projections of the second spacer unit 2421 and the first spacer unit 2411 on the base substrate 11 overlap. The first partition unit 211 is located between two adjacent partition structures 24 in adjacent first sub-display areas, and the second partition unit 212 is located between two adjacent partition structures 24 in adjacent second sub-display areas. The gap between two adjacent partition structures 24 in the first sub-transition area 2001 is equal to the width of the first partition unit 211, and the gap between two adjacent partition structures 24 in the second sub-transition area 2002 is equal to the width of the second partition unit 212. Because the first distance is equal to the second distance, the width of the first partition unit 211 is equal to the width of the second partition unit 212. The orthographic projection of the first insulating layer 201 of the barrier dam on the base substrate 11 is located within the orthographic projection of the second insulating layer 202 on the base substrate.

[0121] The present disclosure also provides a display device, which may include the display panel mentioned above in the present disclosure. The specific structure and beneficial effects of the display panel have been described in detail above, so they will not be repeated here.

[0122] It should be noted that, in addition to the display panel, the display device also includes other necessary components and components, such as a housing, a circuit board, a power cord, etc. Those skilled in the art can make corresponding supplements based on the specific usage requirements of the display device, which will not be repeated here.

[0123] The display device can be a traditional electronic device, such as a mobile phone, a computer, a television, and a camcorder, or it can be an emerging wearable device, such as a virtual reality device and an augmented reality device, which are not listed here one by one.

[0124] It should be noted that the above embodiments are interconnected and can be combined with each other to form other schemes, and the scheme of the present disclosure is not limited to the schemes described in the above embodiments. After considering the specification and practicing the invention disclosed herein, those skilled in the art will easily think of other embodiments of the present disclosure. This application is intended to cover any variations, uses or adaptive changes of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not disclosed in the present disclosure. The description and examples are to be regarded as exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A display panel having an opening area, a display area, and a transition area connecting the display area and the opening area, wherein the opening area is provided with an opening, and wherein, The display panel includes: a substrate substrate; a spacer structure disposed on one side of the substrate substrate and located in the transition region, the spacer structure surrounding the opening, the spacer structure including a plurality of spacer layers sequentially arranged in a direction away from the substrate substrate, and at least one spacer layer including two or more spaced-apart spacer units; at least one partition unit disposed on a side of the spacer structure away from the substrate substrate and located in the transition region, the partition unit surrounding the opening, the partition unit being insulated from the spacer structure, and a positive projection of the partition unit on the substrate substrate being located between positive projections of two adjacent spacer units of at least one spacer layer on the substrate substrate; a packaging layer disposed on a side of the partition unit away from the substrate substrate, the packaging layer including a first packaging structure and a second packaging structure, the second packaging structure being connected to both ends of the first packaging structure, a positive projection of the first packaging structure on the substrate substrate covering the positive projection of the partition unit on the substrate substrate, and a positive projection of the second packaging structure on the substrate substrate covering the positive projection of the spacer unit between two adjacent partition units on the substrate substrate.

2. The display panel according to claim 1, wherein, The display panel further includes: a first gate insulating layer disposed on one side of the substrate substrate; a first gate electrode layer disposed on a side of the first gate insulating layer away from the substrate substrate; a second gate insulating layer disposed on a side of the first gate electrode layer close to the substrate substrate; a second gate electrode layer disposed on a side of the second gate insulating layer away from the substrate substrate, wherein the spacer structure includes a first spacer layer and a second spacer layer, the first spacer layer being provided with the same layer and the same material as the first gate electrode layer, and the second spacer layer being provided with the same layer and the same material as the second gate electrode layer.

3. The display panel according to claim 2, wherein, The display panel further includes a third gate insulating layer and a third gate electrode layer, the third gate insulating layer being disposed on a side of the second gate electrode layer close to the substrate substrate, the third gate electrode layer being disposed on a side of the third gate insulating layer close to the substrate substrate, and the spacer structure further including a third spacer layer, the third spacer layer being provided with the same layer and the same material as the third gate electrode layer.

4. The display panel according to claim 3, wherein, The first spacer layer includes a plurality of first spacer units arranged at intervals, the second spacer layer includes a plurality of second spacer units arranged at intervals, a positive projection of the first spacer unit on the substrate substrate overlaps with a positive projection of the second spacer unit on the substrate substrate, and both are covered by a positive projection of the second packaging structure on the substrate substrate.

5. The display panel according to claim 4, wherein, The third spacer layer is disposed on a side of the second spacer layer away from the substrate substrate, the third spacer layer includes a plurality of third spacer units arranged at intervals, and a positive projection of the third spacer unit on the substrate substrate overlaps with positive projections of the first spacer unit and the second spacer unit on the substrate substrate.

6. The display panel according to claim 5, wherein, The display panel further includes an interlayer dielectric layer disposed on a side of the first gate insulating layer away from the substrate substrate, the interlayer dielectric layer being provided with a dielectric layer opening, and the partition unit being disposed in the dielectric layer opening.

7. The display panel according to claim 4, wherein, The third spacer layer includes a plurality of spacer portions arranged at intervals, the orthographic projection of the spacer portion on the substrate substrate is located between two adjacent first spacer units, and the orthographic projection of the partition unit on the substrate substrate is located within the orthographic projection of the spacer portion on the substrate substrate.

8. The display panel according to claim 3, wherein, One of the first spacer layer, the second spacer layer or the third spacer layer is a whole layer structure, and the orthographic projections of the spacer units and the partition unit of the remaining two layers on the substrate substrate are located within the orthographic projection of the third spacer layer on the substrate substrate.

9. The display panel according to claim 1, wherein, The first encapsulation structure includes a first encapsulation portion and a second encapsulation portion. The second encapsulation portion is connected to both ends of the first encapsulation portion. The two second encapsulation portions are respectively connected to the two second encapsulation structures. The display panel further includes a barrier layer, and the barrier layer is disposed on a side of the encapsulation layer away from the substrate substrate. The orthographic projection of the barrier layer on the encapsulation layer at least overlaps with the second encapsulation portions and the second encapsulation structures at both ends of the first encapsulation portion.

10. The display panel according to claim 9, wherein, The barrier layer includes a plurality of barrier units, and each barrier unit includes two first sub-barrier units. The orthographic projections of the two first sub-barrier units on the encapsulation layer respectively overlap with the second encapsulation portions and the second encapsulation structures at both ends of the first encapsulation portion.

11. The display panel according to claim 10, wherein, The barrier unit further includes a second sub-barrier unit, and the second sub-barrier unit is connected between the two first sub-barrier units. The orthographic projection of the second sub-barrier unit on the substrate substrate covers the first encapsulation structure.

12. The display panel according to claim 9, wherein, The barrier layer includes a barrier portion, and the barrier portion is a whole layer structure. The orthographic projection of the barrier portion on the substrate substrate covers the first encapsulation structure and the second encapsulation structure between the two first encapsulation structures.

13. The display panel according to claim 10 or 12, wherein, The display panel further includes a touch layer group, and the touch layer group is disposed on a side of the encapsulation layer away from the substrate substrate. The touch layer group includes a first touch control layer and a second touch control layer. The barrier layer is provided with the same layer and the same material as one of the first touch control layer and the second touch control layer.

14. The display panel according to claim 1, wherein, The partition unit includes a first partition structure, a second partition structure and a third partition structure connected in sequence along a direction away from the substrate substrate. The width of the second partition structure is smaller than the widths of the first partition structure and the third partition structure on adjacent sides. The orthographic projection of the first partition structure on the substrate substrate overlaps with the orthographic projections of the spacer units on both sides of the partition unit on the substrate substrate.

15. The display panel according to claim 1, wherein, The display panel further includes a dam, the dam is disposed on one side of the substrate and is located in the transition region, the transition region includes a first sub-transition region and a second sub-transition region, the first sub-transition region is located between the edge of the dam and the edge of the opening, the second sub-transition region is located between the edge of the dam and the edge of the display region, at least one partition unit is provided in the first sub-transition region, at least one partition unit is provided in the second sub-transition region, the partition unit in the first sub-transition region is a first partition unit, the partition unit in the second sub-transition region is a second partition unit, and the number of the first partition units is greater than the number of the second partition units.

16. The display panel according to claim 15, wherein, The display panel further includes a power-off isolation unit, the power-off isolation unit is disposed between two of the first partition units closest to the dam, and the power-off isolation unit at least partially covers a side of the first partition unit away from the substrate.

17. A display device, wherein, A display panel comprising any one of claims 1 to 16.

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