Array substrate, display panel, display device and driving method

Abstract

An array substrate (001), a display panel (PNL), a display device and a driving method. The array substrate (001) comprises a base substrate (101). The base substrate (101) comprises a display area (AA) and a non-display area (BB) located on at least one side of the display area (AA). The non-display area (BB) comprises a shift register area (GOA); and a sensor circuit (103), the sensor circuit (103) being configured to monitor at least one of the temperature of the display area (AA), the temperature of the shift register area (GOA), and the ambient temperature.

Description

Array substrate, display panel, display device and driving method

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on January 25, 2024, with application number PCT / CN2024 / 074005 and invention name "Array substrate, display panel and driving method thereof, display device", the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to an array substrate, a display panel, a display device, and a driving method. Background Art

[0004] Thin Film Transistor Liquid Crystal Displays (TFT-LCDs) feature compact size, low power consumption, high image quality, zero radiation, and portability. They have experienced rapid development in recent years, gradually replacing traditional cathode ray tube (CRT) displays and dominating the current flat-panel display market. Currently, TFT-LCDs are widely used in a variety of large, medium, and small-sized products, encompassing nearly every major electronic product in today's information society, including LCD TVs, high-definition digital TVs, computers (desktop and laptop), mobile phones, tablets, navigation systems, in-car displays, projection displays, camcorders, digital cameras, electronic watches, calculators, electronic instruments, meters, public displays, and virtual displays. Summary of the Invention

[0005] The array substrate, display panel, display device, and driving method provided by the embodiments of the present disclosure are specifically described as follows:

[0006] In one aspect, an embodiment of the present disclosure provides an array substrate, comprising:

[0007] a base substrate, the base substrate comprising a display area and a non-display area located at least on one side of the display area, the non-display area comprising a shift register area;

[0008] A sensor circuit is configured to monitor at least one of a temperature of the display area, a temperature of the shift register area, and an ambient temperature.

[0009] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the sensor circuit is a temperature sensing circuit.

[0010] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a power supply line;

[0011] The sensor circuit includes a first transistor, wherein a gate of the first transistor is coupled to the power supply line, a first electrode of the first transistor is coupled to the gate of the first transistor, and a second electrode of the first transistor is coupled to a detection point.

[0012] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the non-display area also includes a virtual area, the virtual area is arranged between the display area and the shift register area, the virtual area is provided with a virtual transistor, and the first transistor is multiplexed with the virtual transistor.

[0013] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, there are multiple dummy transistors, and the multiple dummy transistors are connected in parallel as the first transistor.

[0014] In some embodiments, the above-mentioned array substrate provided in the embodiment of the present disclosure further includes a common electrode line and a connecting line located in the non-display area, the power supply line is multiplexed with the common electrode line, and the gates of multiple virtual transistors are electrically connected to the common electrode line through the connecting line.

[0015] In some embodiments, the above-mentioned array substrate provided in the embodiment of the present disclosure further includes a cascaded shift register and a virtual shift register located at at least one end of the cascade direction of the shift register, and the first transistor is multiplexed with any transistor of the virtual shift register.

[0016] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the non-display area includes a binding area, and the first transistor is multiplexed with any transistor in the virtual shift register close to the binding area.

[0017] In some embodiments, in the above-mentioned array substrate provided by an embodiment of the present disclosure, the non-display area further includes a plurality of binding areas, and the first transistor is located between adjacent binding areas.

[0018] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a switching transistor located in the display area, and the first transistor is the same as the switching transistor.

[0019] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a high-level signal line, the high-level signal line is electrically connected to the shift register, and the power supply line is multiplexed with the high-level signal line.

[0020] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a ground line, and the sensor circuit further includes a first resistor connected between the detection point and the ground line.

[0021] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the second electrodes of different first transistors are electrically connected to different first resistors.

[0022] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a common electrode line located in the non-display area, the common electrode line including a receiving groove disposed near the display area; the sensor circuit is at least partially located within the receiving groove. In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes an input signal line and a reference signal line wound around the common electrode line;

[0023] The sensor circuit includes a second transistor and a capacitor, wherein the gate of the second transistor is coupled to the input signal line, the first electrode of the second transistor is coupled to the gate of the second transistor, the second electrode of the second transistor is coupled to the first plate of the capacitor, and the second plate of the capacitor is coupled to the reference signal line.

[0024] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the capacitor is located in the receiving groove, and at least a portion of the second transistor is located in the receiving groove.

[0025] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the second transistor is located on a side of the capacitor away from the display area, or the capacitor is located on a side of the second transistor away from the display area.

[0026] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, the opening of the accommodating groove faces the side away from the display area, the input signal line extends from the side of the common electrode line away from the display area to the accommodating groove, and the reference signal line extends from the side of the input signal line away from the display area to the accommodating groove.

[0027] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a detection signal line located on a side of the reference signal line away from the common electrode line;

[0028] The sensor circuit also includes a second resistor and a third resistor, wherein the first end of the second resistor is coupled to the first plate of the capacitor, the second end of the second resistor is coupled to the detection signal line, the first end of the third resistor is coupled to the detection signal line, and the second end of the third resistor is coupled to the reference signal line.

[0029] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the third resistor is greater than the second resistor.

[0030] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the second resistor and the third resistor respectively include multiple winding repetition units, and the number of winding repetition units of the second resistor is less than the number of winding repetition units of the third resistor.

[0031] In some embodiments, the above-mentioned array substrate provided in the embodiments of the present disclosure further includes a first dummy pattern, which is located on the side of the second resistor facing the display area, the side of the second resistor away from the display area, the side of the third resistor facing the display area, and the side of the third resistor away from the display area. The structure of the first dummy pattern is substantially the same as the structure of the second resistor and the third resistor.

[0032] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the common electrode line, the input signal line, the reference signal line, the detection signal line, the second plate of the capacitor, the second resistor, the third resistor, the first dummy pattern and the gate of the transistor are arranged on the same layer, and the first plate of the capacitor and the first and second electrodes of the transistor are arranged on the same layer.

[0033] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a second dummy pattern located in the receiving groove, and the second dummy pattern is arranged in the space surrounded by the input signal line, the reference signal line, and the capacitor.

[0034] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the second dummy pattern is provided in the same layer as the gate of the transistor.

[0035] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the common electrode line, the input signal line, the reference signal line, and the second dummy pattern respectively include a plurality of hollow structures.

[0036] In some embodiments, in the array substrate provided by the embodiments of the present disclosure, the opening of the receiving groove faces the display area;

[0037] The array substrate further includes a fan-out line located between the common electrode line and the display area, and the input signal line and the reference signal line are located between the fan-out line and the common electrode line.

[0038] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a control signal line located between the input signal line and the reference signal line;

[0039] The sensor circuit also includes a third transistor, a gate of the third transistor is coupled to the control signal line, a first electrode of the third transistor is coupled to the first plate of the capacitor, a second electrode of the third transistor is coupled to the second plate of the capacitor, and a channel width-to-length ratio of the third transistor is greater than the channel width-to-length ratio of the second transistor.

[0040] In some embodiments, in the above-mentioned array substrate provided in the embodiments of the present disclosure, the sensor circuit also includes a fourth transistor, the gate of the fourth transistor is coupled to the reference signal line, the first electrode of the fourth transistor is coupled to the second plate of the capacitor, and the second electrode of the fourth transistor is coupled to the reference signal line.

[0041] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the second transistor, the third transistor, and the fourth transistor are arranged side by side on the same side of the capacitor.

[0042] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the first electrode of the second transistor, the second electrode of the second transistor, the first electrode of the third transistor, the second electrode of the third transistor, the first electrode of the fourth transistor, and the second electrode of the fourth transistor are comb electrodes or block electrodes; the gate of the second transistor, the gate of the third transistor, and the gate of the fourth transistor are block electrodes or include multiple interconnected island electrodes.

[0043] In some embodiments, the array substrate provided in the embodiments of the present disclosure further includes a switching transistor located in the display area, and the ratio of the channel width-to-length ratio of the second transistor to the channel width-to-length ratio of the switching transistor is greater than or equal to 50.

[0044] In some embodiments, in the above-mentioned array substrate provided by the embodiments of the present disclosure, the non-display area includes multiple binding areas, the sensor circuit is located between the binding area and the display area, and / or the sensor circuit is located between the gap between adjacent binding areas and the display area.

[0045] On the other hand, an embodiment of the present disclosure provides a display panel, comprising the array substrate provided in the embodiment of the present disclosure, and an opposite substrate disposed opposite to the array substrate.

[0046] On the other hand, an embodiment of the present disclosure provides a display device, including the above-mentioned display panel provided by the embodiment of the present disclosure, and a backlight module located on the light incident side of the display panel.

[0047] In some embodiments, the display device provided in the embodiments of the present disclosure further includes a microcontroller circuit, the microcontroller circuit including a storage module, a clock module, and a calculation module; wherein the storage module is configured to store a first relationship between a voltage at a detection point and a threshold voltage of the first transistor and a temperature, and to store a second relationship between a difference between the threshold voltage of the first transistor and an initial threshold voltage of the first transistor and an operating time of the first transistor;

[0048] The clock module is configured to monitor the operating time of the first transistor;

[0049] The calculation module is configured to calculate a threshold voltage of the first transistor according to the operating time of the first transistor and the second relationship, and output temperature data based on the calculated threshold voltage of the first transistor and the first relationship.

[0050] On the other hand, an embodiment of the present disclosure provides a driving method of the above-mentioned display device, including:

[0051] collecting the working time of the first transistor;

[0052] calculating the threshold voltage of the first transistor according to the operating time of the first transistor and a second relationship indicating that the difference between the threshold voltage of the first transistor and the initial threshold voltage of the first transistor varies with the operating time of the first transistor;

[0053] Temperature data is output based on the calculated threshold voltage of the first transistor and a first relationship representing a change in voltage at a detection point with the threshold voltage of the first transistor and temperature.

[0054] On the other hand, an embodiment of the present disclosure provides a method for driving the display panel, including:

[0055] Use sensor circuit to monitor panel temperature;

[0056] A driving parameter is generated according to the panel temperature, and the display panel is controlled by using the driving parameter to display an image.

[0057] In some embodiments, in the driving method provided in the embodiments of the present disclosure, a sensor circuit is used to monitor the panel temperature, specifically including:

[0058] At a fixed moment after the second transistor is turned on each time, the voltage at the connection point between the second resistor and the third resistor is collected, and the panel temperature is determined based on the collected voltage.

[0059] In some embodiments, in the driving method provided in the embodiments of the present disclosure, a sensor circuit is used to monitor the panel temperature, specifically including:

[0060] During each turn-on of the second transistor, the panel temperature is determined by monitoring the peak charging current of the capacitor.

[0061] In some embodiments, in the driving method provided by the embodiments of the present disclosure, after the sensor circuit is used to monitor the panel temperature, the method further includes: turning on the third transistor to discharge the capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] FIG1 is a schematic structural diagram of an array substrate provided in an embodiment of the present disclosure;

[0063] FIG2 is a schematic diagram of an enlarged structure of the Z1 area in FIG1 ;

[0064] FIG3 is an enlarged structural diagram of the Z2 area in FIG2 ;

[0065] FIG4 is an enlarged structural diagram of the Z3 region in FIG2 ;

[0066] FIG5 is an enlarged structural diagram of the Z4 region in FIG2 ;

[0067] FIG6 is an enlarged structural diagram of the Z5 region in FIG2 ;

[0068] FIG7 is an equivalent circuit diagram of the sensor circuit in FIG2 ;

[0069] FIG8 is a temperature monitoring schematic diagram of the sensor circuit shown in FIG7 ;

[0070] FIG9 is a schematic diagram of an enlarged structure of the Z6 region in FIG1 ;

[0071] FIG10 is an equivalent circuit diagram of the sensor circuit in FIG9 ;

[0072] FIG11 is a temperature monitoring circuit diagram of the sensor circuit shown in FIG10 ;

[0073] FIG12 is a temperature monitoring schematic diagram of the sensor circuit shown in FIG10 ;

[0074] FIG13 is another enlarged structural diagram of the Z6 region in FIG1 ;

[0075] FIG14 is an equivalent circuit diagram of the sensor circuit in FIG13 ;

[0076] FIG15 is another schematic diagram of a sensor circuit provided in an embodiment of the present disclosure;

[0077] FIG16 is a fitting curve of the threshold voltage and operating time of a transistor provided by an embodiment of the present disclosure;

[0078] FIG17a is a schematic diagram of the enlarged structure of the Z7 region in FIG1;

[0079] FIG17 b is a schematic diagram of a plurality of dummy transistors connected in parallel as a first transistor;

[0080] FIG18 is an enlarged structural diagram of the Z8 region in FIG1 ;

[0081] FIG19 is an enlarged structural diagram of the Z9 region in FIG1 ;

[0082] FIG20 is a schematic structural diagram of a transistor provided in an embodiment of the present disclosure;

[0083] FIG21 is another structural diagram of a transistor provided in an embodiment of the present disclosure;

[0084] FIG22 is a schematic structural diagram of a display panel provided in an embodiment of the present disclosure;

[0085] FIG23 is a flow chart of a method for driving a display panel according to an embodiment of the present disclosure;

[0086] FIG24 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure;

[0087] FIG25 is a schematic structural diagram of a microcontroller circuit provided in an embodiment of the present disclosure;

[0088] FIG26 is a flowchart of a method for driving a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0089] To further clarify the objectives, technical solutions, and advantages of the embodiments of the present disclosure, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below in conjunction with the accompanying drawings of the embodiments of the present disclosure. It should be noted that in the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In this disclosure, exemplary embodiments are described with reference to cross-sectional views that are schematic representations of idealized embodiments. As such, deviations from the shapes shown in the drawings are to be expected, for example, as a result of manufacturing techniques and / or tolerances. Therefore, the embodiments described in this disclosure should not be construed as limited to the specific shapes of the regions shown in this disclosure, but rather include deviations in shape resulting from, for example, manufacturing. For example, a region illustrated or described as flat may typically have rough and / or nonlinear features; a sharp angle illustrated may be rounded, etc. Therefore, the regions shown in the drawings are schematic in nature, and their sizes and shapes are not intended to illustrate the precise shapes of the regions or reflect true scale, but are intended solely to illustrate the present disclosure. Throughout, identical or similar reference numerals denote identical or similar elements or elements having identical or similar functions. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of known functions and known components.

[0090] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by persons of ordinary skill in the field to which the present disclosure belongs. The words "first", "second" and similar terms used in the present disclosure and the claims do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0091] In the following description, when an element or layer is referred to as being “on” or “connected to” another element or layer, the element or layer may be directly on, directly connected to, the other element or layer, or there may be intermediate elements or intermediate layers. When an element or layer is referred to as being “disposed on one side of” another element or layer, the element or layer may be directly on, directly connected to, the other element or layer, or there may be intermediate elements or intermediate layers. However, when an element or layer is referred to as being “directly on” or “directly connected to” another element or layer, there are no intermediate elements or intermediate layers. The term “and / or” includes any and all combinations of one or more of the associated listed items.

[0092] Competition in the TFT-LCD market is becoming increasingly fierce. As the development of high frequency, high refresh rate, and high resolution (PPI) gradually slows down, fat modules and screen empowerment are another way to enhance product competitiveness.

[0093] The present invention adds a sensor circuit within the screen to monitor the panel temperature in real time, and can adjust the panel signal on the circuit. For example, the high level (Vgh) of the gate drive circuit (GOA) in the plane. When the screen temperature increases, the transistor (TFT) driving capability will increase, and Vgh can be appropriately reduced to reduce the drift of TFT characteristics in the screen and increase the lifespan. For example, the driving strength of the line over drive (line od) in the plane controls the response time of the liquid crystal, and can be adjusted in real time according to the temperature to solve the problems such as horizontal and vertical stripes caused by the different response times of the liquid crystal at different temperatures, thereby effectively improving the display quality.

[0094] In some embodiments, FIG1 shows a schematic structural diagram of an array substrate provided in an embodiment of the present disclosure, FIG2 is an enlarged structural diagram of the Z1 region in FIG1 , and FIG3 to FIG6 are enlarged structural diagrams of the Z2 to Z6 regions in FIG2 , respectively. FIG7 is an equivalent circuit diagram of the sensor circuit in FIG2 . As can be seen from FIG1 to FIG7 , the array substrate provided in the present disclosure may include:

[0095] A base substrate 101, comprising a display area AA and a non-display area BB located on at least one side of the display area AA; optionally, the base substrate 101 is a substrate that allows visible light to pass through, such as glass, quartz, plastic, or the like;

[0096] The common electrode line 102 is located in the non-display area BB. The common electrode line 102 includes a receiving groove 1021 disposed near the display area AA.

[0097] The sensor circuit 103 is at least partially located in the receiving groove 1021. Optionally, the sensor circuit 103 is configured to monitor temperature. It should be understood that after the array substrate and the opposing substrate are assembled to form a display panel, the temperature monitored by the sensor circuit 103 may be the display panel temperature.

[0098] The array substrate provided in the embodiment of the present disclosure integrates the sensor circuit 103, which can adjust the GOA parameters according to the monitoring temperature of the sensor circuit 103 and the line in the display area AA. od parameters, etc., or optionally, the sensor circuit 103 can detect the temperature of the display panel. When the temperature is lower than the threshold temperature, the display panel can be heated. For example, a heating resistor or other structure can be set in the display area and / or the non-display area of ​​the display panel. When the display panel is lower than the threshold temperature, the heating function of the display panel is turned on to ensure normal display. The threshold temperature can be, for example, -5°C to -15°C, or set according to actual needs, which is not limited here. The setting of the sensor circuit 103 can improve the display quality; and, the present disclosure provides the common electrode line 102 with a receiving groove 1021, and at least part of the sensor circuit 103 is located in the receiving groove 1021, which is equivalent to using part of the space originally used for arranging the common electrode line 102 to set the sensor circuit 103, which is conducive to achieving a narrow frame effect; in addition, since the receiving groove 1021 is set close to the display area AA, the temperature monitored by the sensor circuit 103 can take into account the temperature of the non-display area BB and the display area AA, so that the parameters of GOA in the non-display area BB and line in the display area AA can be realized based on the monitored temperature of the sensor circuit 103. od parameters to more accurately adjust the display quality.

[0099] In some embodiments, the sensor circuit 103 of the present disclosure may be a temperature sensing circuit, and as shown in Figures 2 and 3, the array substrate of the present disclosure may further include an input signal line INL and a reference signal line LVGL wound around the common electrode line 102. The input signal line INL and the reference signal line LVGL are arranged around the common electrode line 102 to ensure that the wiring is more compact, which is conducive to reducing the wiring space and achieving a narrow bezel effect. Optionally, the reference signal line LVGL electrically connected to the sensor circuit 103 in this case can be shared with the reference signal line LVGL electrically connected to the gate drive circuit (GOA) set in the non-display area, and the two are the same signal, wherein the reference signal line LVGL is used in the gate drive circuit (GOA) to reduce noise at the pull-up node of the gate drive circuit (GOA), and / or the gate signal output end. The gate drive signal output end can be a cascade output end or an output end electrically connected to the gate line of the display area (AA). Such a shared signal can reduce the display panel bezel.

[0100] In some embodiments, as shown in Figures 1 and 2, the non-display area BB includes multiple binding areas BA (which may correspond one-to-one to the fan-out area FA, and multiple fan-out lines 106 are provided in the fan-out area FA), the sensor circuit 103 is located between the binding area BA and the display area AA, and / or the sensor circuit 103 is located between the gap between adjacent binding areas BA and the display area AA (for example, the sensor circuit 103 is located in the area between the fan-out lines 106 of two adjacent fan-out areas FA), which is not limited in the present disclosure.

[0101] It should be noted that the present disclosure uses the example of the sensor circuit 103 being arranged at the lower frame for illustration, but in some embodiments, the sensor circuit 103 of the present disclosure may also be arranged at the upper frame, left frame, right frame, etc.

[0102] In some embodiments, as shown in Figures 2, 3, and 7, the sensor circuit 103 includes a second transistor TFT2 and a capacitor C, wherein the gate of the second transistor TFT2 is coupled to the input signal line INL, the first electrode of the second transistor TFT2 is coupled to the gate of the second transistor TFT2, the second electrode of the second transistor TFT2 is coupled to the first plate of the capacitor C, and the second plate of the capacitor C is coupled to the reference signal line LVGL. The gate of the second transistor TFT2 is short-circuited to the first electrode, thereby eliminating the problem of reduced turn-on current caused by the threshold voltage (Vth) drift of the second transistor TFT2 over time. The input signal provided by the input signal line INL can be a pulse signal of a high voltage Vgh (as shown in Figure 8), or it can be a clock signal (CLK), a frame start signal (STV), etc., that is, the input signal provided by the input signal line INL can be shared with the clock signal (CLK) and the frame start signal (STV) of the gate drive circuit (GOA), etc., and this is not specifically limited in this disclosure. When the input signal line INL provides an input signal to the second transistor TFT2, the second transistor TFT2 charges the capacitor C. Because the on-state current of the second transistor TFT2 varies at different temperatures, the panel temperature can be determined based on the current or voltage of the sensor circuit. In some embodiments, the channel width-to-length ratio of the second transistor TFT2 can be at least 50 times the channel width-to-length ratio of the switching transistor (connected to the pixel electrode pixel) in the display area AA.

[0103] In some embodiments, the second transistor TFT2 in the present disclosure can be an amorphous silicon transistor (a-Si), a polycrystalline silicon (Poly) transistor, an oxide transistor, etc. In view of the high sensitivity of amorphous silicon transistors to temperature and low cost, the present disclosure preferably uses an amorphous silicon transistor as the second transistor TFT2.

[0104] In some embodiments, FIG9 shows an enlarged schematic diagram of the structure of region Z2 in FIG1 . As can be seen from FIG3 and FIG9 , capacitor C is located within receiving groove 1021, and at least a portion of second transistor TFT2 is located within receiving groove 1021. Specifically, in FIG3 , second transistor TFT2 is located within receiving groove 1021, while in FIG9 , most of second transistor TFT2 is located within receiving groove 1021, which is equivalent to second transistor TFT2 being located within receiving groove 1021. This arrangement requires very little or no additional space for second transistor TFT2 and capacitor C, which facilitates achieving a narrow bezel effect.

[0105] Alternatively, as shown in FIG3 , the second transistor TFT2 is located on the side of the capacitor C away from the display area AA; or, as shown in FIG9 , the capacitor C is located on the side of the second transistor TFT2 away from the display area AA. The on-state current of the second transistor TFT2 changes with temperature, so placing the second transistor TFT2 closer to the display area AA can more effectively take into account the temperature of the non-display area BB and the display area AA, thereby enabling precise adjustment of the parameters of GOA in the non-display area BB and the parameters of line od in the display area AA based on the monitored temperature of the sensor circuit 103, thereby effectively improving the display quality. Of course, if the space occupied by the capacitor C is small, the second transistor TFT2 is placed further away from the display area AA relative to the capacitor C, which has little impact on the monitored temperature and can still effectively improve the display quality.

[0106] In some embodiments, as shown in Figures 2 to 6, the opening of the receiving groove 1021 is arranged toward the side away from the display area AA. The input signal line INL extends from the side of the common electrode line 102 away from the display area AA into the receiving groove 1021 to be connected to the gate of the second transistor TFT2 in the receiving groove 1021. The reference signal line LVGL extends from the side of the input signal line INL away from the display area AA into the receiving groove 1021 to be connected to the second plate of the capacitor C. The input signal line INL and the reference signal line LVGL are arranged around the side of the common electrode line 102 away from the display area AA, which can fully utilize the peripheral space of the common electrode line 102 for wiring.

[0107] In some embodiments, as shown in Figures 2 to 7, a detection signal line DTL is further included on a side of the reference signal line LVGL away from the common electrode line 102; the sensor circuit 103 may further include a second resistor R2 and a third resistor R3, wherein a first end of the second resistor R2 is coupled to the first plate of the capacitor C, a second end of the second resistor R2 is coupled to the detection signal line DTL, a first end of the third resistor R3 is coupled to the detection signal line DTL, and a second end of the third resistor R3 is coupled to the reference signal line LVGL. In a specific implementation, the second resistor R2 and the third resistor R3 can achieve a voltage divider effect on the voltage across the capacitor C. Because the on-state current of the second transistor TFT2 varies at different temperatures, as shown in Figure 8, the amount of charge on the capacitor C at a fixed time (e.g., 1 second after the second transistor TFT2 is turned on) is different (equivalent to a different voltage across the capacitor C). As a result, the voltage monitored by the detection signal line DTL at a fixed time and different temperatures is different, so that the panel temperature can be determined based on the monitored voltage. In some embodiments, the detection signal line DTL can be connected to an external circuit (such as a microcontroller MCU). The external circuit can use a voltage amplifier circuit to amplify and analyze the voltage difference collected by the detection signal line DTL to more finely divide the temperature range.

[0108] In some embodiments, as shown in FIG7 , the voltage monitored by the detection signal line DTL is equivalent to the voltage divided by the third resistor R3. Therefore, if wiring space permits, the larger the third resistor R3, the easier it is to monitor the voltage. Based on this, the third resistor R3 can be set to be larger than the second resistor R2 in the present disclosure. Optionally, as shown in FIG4 to FIG6 , the second resistor R2 and the third resistor R3 of the present disclosure each include multiple winding repeating units, for example, the winding repeating units are approximately zigzag windings, and of course the winding repeating units can also be s-shaped windings, etc. Optionally, to ensure that the third resistor R3 is larger, the number of winding repeating units of the second resistor R2 can be set to be smaller than the number of winding repeating units of the third resistor R3.

[0109] In some embodiments, as shown in Figures 2 to 6 , the present disclosure may further include a first dummy pattern 104. The first dummy pattern 104 is located on the side of the second resistor R2 facing the display area AA, the side of the second resistor R2 away from the display area AA, the side of the third resistor R3 facing the display area AA, and the side of the third resistor R3 away from the display area AA. The structure of the first dummy pattern 104 is substantially the same as that of the second resistor R2 and the third resistor R3, meaning that the first dummy pattern 104 has a similar or identical winding repeating unit as the first resistor R1 and the third resistor R3. Providing the first dummy pattern 104 on both sides of the second resistor R2 and the third resistor R3 ensures uniform etching of the metal lines.

[0110] In some embodiments, as shown in Figures 2 to 6, a second dummy pattern 105 can be set in the receiving groove 1021. Optionally, the second dummy pattern 105 is set in the space surrounded by the input signal line INL, the reference signal line LVGL, and the capacitor C, so as to effectively ensure the etching uniformity of the pattern in the receiving groove 1021.

[0111] Optionally, the common electrode line 102, the input signal line INL, the reference signal line LVGL, the detection signal line DTL, the second plate of the capacitor C, the second resistor R2, the third resistor R3, the first dummy pattern 104, and the second dummy pattern 105 in the present disclosure are all arranged in the same layer and the same material as the gate of the second transistor TFT2, and the first plate of the capacitor C is arranged in the same layer and the same material as the first pole and the second pole of the second transistor TFT2. In the present disclosure, "same layer" refers to the use of the same film forming process to form a film layer for making a specific pattern, and then using the same mask to form a layer structure through a single patterning process. That is, a patterning process corresponds to a mask (mask, also known as a photomask). Depending on the specific pattern, a patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may be at the same height or have the same thickness, or may be at different heights or have different thicknesses.

[0112] In some embodiments, the sealant in the non-display area BB can be irradiated on the side of the base substrate 101 to achieve curing of the sealant. Accordingly, in order to transmit the irradiated light, the present disclosure can be configured to provide multiple hollow structures OW for all or part of the signal lines with larger line widths. For example, the common electrode line 102, the input signal line INL, the reference signal line LGVL, and the second dummy pattern 105 each include multiple hollow structures OW. Optionally, the line widths of the second resistor R2, the third resistor R3, and the first dummy pattern 104 are much smaller than the line width of the common electrode line 102, and there are gaps between adjacent lines to allow light to pass through. Therefore, there is no need to provide hollow structures OW for the windings of the second resistor R2, the third resistor R3, and the first dummy pattern 104.

[0113] In some embodiments, as shown in Figure 9, the opening of the accommodating groove 1021 faces the display area AA, and the array substrate also includes a fan-out line 106 located between the common electrode line 102 and the display area AA. The input signal line INL and the reference signal line LVGL are located between the fan-out line 106 and the common electrode line 102, so as to utilize the space between the fan-out line 106 and the common electrode line 102 for wiring, thereby maintaining the frame size unchanged.

[0114] Optionally, as shown in Figures 9 and 10, the array substrate may further include a control signal line CTL located between the input signal line INL and the reference signal line LVGL, and the sensor circuit 103 may further include a third transistor TFT3 arranged side by side with the second transistor TFT2 on the same side of the capacitor C, the gate of the third transistor TFT3 is coupled to the control signal line CTL, the first electrode of the third transistor TFT3 is coupled to the first plate of the capacitor C, and the second electrode of the third transistor TFT3 is coupled to the second plate of the capacitor C. To ensure that the monitoring current is determined by the second transistor TFT2, the present disclosure sets the channel width-to-length ratio of the second transistor TFF2 to be greater than the channel width-to-length ratio of the second transistor TFT2.

[0115] In the present disclosure, the input signal line INL provides an input signal to the second transistor TFT2, and the second transistor TFT2 charges the capacitor C. Because the on-state current of the second transistor TFT2 is different at different temperatures, the present disclosure can use an external circuit (such as a microcontroller MCU) to monitor the charging peak current of the capacitor C to monitor the temperature of the panel, as shown in Figures 11 and 12; and the external circuit can use a voltage amplifier circuit to amplify and analyze the difference in the charging peak current of the capacitor C, so as to divide the temperature range more finely. After collecting the charging peak current of the capacitor C, the third transistor TFT3 can be turned on to quickly discharge the capacitor C.

[0116] In some embodiments, as shown in Figures 13 and 14, the sensor circuit 103 may further include a fourth transistor TFT4, the gate of the fourth transistor TFT4 is coupled to the reference signal line LVGL, the first electrode of the fourth transistor TFT4 is coupled to the second plate of the capacitor C, the second electrode of the fourth transistor TFT4 is coupled to the reference signal line LVGL, and the fourth transistor TFT4 is equivalent to a resistor connected in series between the second plate of the capacitor C and the reference signal line LVGL.

[0117] In some embodiments, as shown in FIG13 , the second transistor TFT2 , the third transistor TFT3 , and the fourth transistor TFT4 are arranged side by side on the same side of the capacitor C to reduce the space occupied by the three transistors and achieve a narrow frame effect.

[0118] In some embodiments, the sensor circuit 103 disclosed herein can be configured to monitor at least one of the temperature of the display area AA, the temperature of the shift register area GOA, and the ambient temperature. For example, the sensor circuit 103 can be placed in a virtual area (Dummy Pixel) to monitor the liquid crystal temperature, the sensor circuit 103 can be placed in a virtual shift register area (Dummy GOA) to monitor the temperature of the shift register, and the sensor circuit 103 can be placed between adjacent binding areas BA to monitor the ambient temperature, thereby realizing temperature detection of different objects and improving the accuracy of temperature detection. In addition, the sensor circuit 103 does not occupy effective space such as the display area AA, the shift register area GOA, and the binding area BA, and will not affect product specifications and yield issues.

[0119] In some embodiments, FIG15 shows another schematic diagram of a sensor circuit 103 provided in an embodiment of the present disclosure. As shown in FIG15 , the sensor circuit 103 of the present disclosure includes a first transistor TFT1 and a first resistor R1. The gate of the first transistor TFT1 is coupled to a power supply line VL, the first electrode of the first transistor TFT1 is coupled to the gate of the first transistor TFT1, and the first resistor R1 is connected between the second electrode of the first transistor TFT1 and a ground line GND. In some embodiments, the first resistor R1 can be disposed on an array substrate and fabricated by film deposition, for example, by winding a source / drain metal layer and / or a gate metal layer. Alternatively, the first resistor R1 can be disposed on an external circuit such as a timing control board Tcon or a printed circuit board PCB.

[0120] In some embodiments, the connection point between the first resistor R1 and the first transistor TFT1 can serve as a detection point P. In a specific implementation, a linear equation relating the voltage Vout at detection point P and the temperature T can be obtained through pre-factory debugging of the product and written into an external circuit (e.g., a microcontroller MCU). During product use, the voltage Vout at detection point P can be monitored by the external circuit (e.g., a microcontroller MCU), and the corresponding temperature data can be output through calculation. In some embodiments, the voltage Vout at detection point P can be monitored in real time during operation, or it can be monitored at preset intervals (e.g., 1 minute), although this is not limited in this disclosure.

[0121] In some embodiments, the relationship between the current and temperature of the thin film transistor is as follows:

[0122] Among them, I DS is the drain current, that is, the current flowing from the drain to the source. DO is the saturation current, a constant related to the geometry and material properties of the device. It represents the current that will flow if the device is fully turned on and the voltage across it is zero. q is the elementary charge, which is approximately 1.6×10-19 Coulomb. V GS is the gate-source voltage, that is, the voltage difference between the gate and the source. V TH is the threshold voltage, the minimum gate-source voltage required to form a conductive path between the drain and source. It is a characteristic of thin-film transistors that depends on the design and manufacturing process of the device and changes over time. N is the subthreshold slope factor, a dimensionless parameter used to describe the degree to which the subthreshold region deviates from ideal behavior. Its value is usually between 1 and 2. k is the Boltzmann constant, which is approximately 1.38×10 -23 Joule per Kelvin. T is the absolute temperature in Kelvin. V DS is the drain-source voltage, that is, the voltage difference between the drain and the source. After a simple transformation, equation (a) can be simplified to:

[0123] Where V DS is the voltage difference between the drain and source of the transistor, which is equivalent to the voltage of the power supply line VL in Figure 15 minus the voltage Vout at the detection point P. Combined with the relationship (b), it can be seen that Vout can be considered as a linear function of the temperature T. By measuring the two sets of V at room temperature (27°C) and high temperature (60°C), DS With the data of temperature T, we can get: V DS ≈A*T+V TH (c);

[0124] Where A is a constant, V TH The threshold voltage is the minimum gate-source voltage required to form a conductive path between the drain and the source. It is a characteristic of the thin film transistor that depends on the design and manufacturing process of the device and will change over time.

[0125] V TH The measured data of the reliability time variation is shown in Figure 16. The V corresponding to different working times t is obtained by DC voltage application (the test voltage is the same as the voltage of the power supply line VL). TH Data, and through data processing, fitting to obtain △V TH The fitting formula with working time t is:

[0126] Among them, △V TH is the threshold voltage V TH The change in the threshold voltage V under specific conditions TH The change relative to the initial threshold voltage. V G is the gate voltage, the voltage applied to the gate. V TOis the initial threshold voltage, the threshold voltage when there are no other influencing factors. t is time, often used to describe time-dependent effects. DC is the DC bias or DC condition, which can represent a DC bias voltage or current. τ0 is the characteristic time constant, related to the physical and material properties of the device, and is used to describe time-dependent effects. f is the frequency, which can represent the frequency of the signal or the frequency of some periodic variation. β is an exponential factor, used to describe the degree of nonlinear effects. This fitting formula can be written into the microcontroller (MCU) to eliminate the influence of transistor reliability.

[0127] In some embodiments, FIG17a is an enlarged structural schematic diagram of the Z7 region in FIG1 . As shown in FIG17a , the virtual area DA is disposed between the display area AA and the shift register area GOA. Optionally, the virtual area DA is provided with a virtual transistor DTFT, and the display area AA is provided with a switching transistor. To improve the orientation effect of the alignment film, the virtual transistor DTFT can be identical to the switching transistor. Specifically, the virtual transistor DTFT and the switching transistor have the same film layer, channel width-to-length ratio, gate morphology, first electrode morphology, second electrode morphology, active layer morphology, gate size, first electrode size, second electrode size, and active layer size. Furthermore, it should be noted that due to limitations of process conditions or the influence of other factors such as measurement, the aforementioned “identical” may be completely identical or may have some deviations. Therefore, as long as the “identical” relationship between the aforementioned features satisfies the tolerance, it falls within the scope of protection of the present disclosure.

[0128] In some embodiments, the virtual transistor DTFT disclosed in the present invention can also be used as the first transistor TFT1 to monitor the liquid crystal temperature, thereby controlling the Line OD voltage and improving the display quality. In some embodiments, each pixel row is provided with a virtual transistor DTFT, and these virtual transistors DTFT can be connected in parallel as the first transistor TFT1, as shown in Figure 17b. For example, the common electrode line 102 can be used as the power supply line VL, and the gate of each virtual transistor DTFT is coupled to its first electrode and then connected to the common electrode line 102 through the connecting line 107. The common voltage Com of the common electrode line 102 can be provided as a driving signal to the first transistor TFT1. Since each virtual transistor DTFT can accurately reflect the liquid crystal temperature of the pixel row in which it is located, the virtual transistors DTFT of all pixel rows are connected in parallel as the first transistor TFT1, which can more accurately characterize the overall temperature of the liquid crystal, which is particularly suitable for large-size and ultra-large-size products, such as TVs.

[0129] In some embodiments, FIG18 is an enlarged structural diagram of the Z8 region in FIG1 . As shown in FIG18 , a virtual shift register DGOA is provided at at least one end of the cascade direction of the shift register GOA. The first transistor TFT1 can be reused with any transistor of the virtual shift register DGOA. That is, the present disclosure can use any transistor of the virtual shift register DGOA as the first transistor TFT1 to monitor the temperature of the shift register GOA, thereby adjusting Vgh according to the temperature to improve the life of the shift register GOA. Optionally, the present disclosure uses any transistor in the virtual shift register DGOA close to the binding area BA (equivalent to the DP side) as the first transistor TFT1. Compared with using any transistor in the virtual shift register DGOA far from the binding area BA (equivalent to the DPO side) as the first transistor TFT1, the influence of the wiring resistance can be reduced and the accuracy of temperature monitoring can be improved. In addition, the shift register GOA is typically electrically connected to a high-level signal line VDD. The high level VDD can be a signal used by the shift register GOA to control the potential of a pull-down node in a pull-down module. The pull-down node is used to reduce noise at the pull-up node of the shift register or the output of the shift register. The transistor serving as the first transistor TFT1 in the virtual shift register DGOA disclosed herein can be electrically connected to the high-level signal line VDD nearby. This is equivalent to the high-level signal line VDD electrically connected to the shift register also serving as the power supply line VL that provides the driving voltage for the first transistor TFT1. This avoids the need for an additional power supply line VL, facilitating a narrow-frame design. Optionally, any transistor in the virtual shift register DGOA, serving as the first transistor TFT1, can also be connected to the com signal, which is not limited here. Optionally, the transistors provided in the virtual shift register DGOA can be partially identical to the transistors provided in the shift register GOA (for example, the transistors have the same width-to-length ratio), meaning that the shift register GOA and the virtual shift register DGOA can be manufactured in one process. The virtual shift register DGOA can not only serve as a detection function, but also achieve uniform etching of the surrounding area.

[0130] In some embodiments, Figure 19 is an enlarged structural diagram of the Z9 area in Figure 1. Combining Figure 1 and Figure 19, it can be seen that the first transistor TFT1 can be located between adjacent binding areas BA. The temperature of the binding area BA and the area therebetween is not affected by the inside of the panel, which is conducive to accurate monitoring of the ambient temperature. Since there is almost no difference in the ambient temperature detected between different binding areas BA, in order to simplify the product structure, the present disclosure can only set the first transistor TFT1 between any two adjacent binding areas BA, without setting the first transistor TFT1 between every two binding areas BA. Optionally, the gate of the first transistor TFT1 between the binding areas BA can be electrically connected to the high-level signal line VDD, the common voltage line 102, etc., so as to utilize the high-level signal line VDD or the common voltage line 102 as the power supply line VL, avoid the additional setting of the power supply line VL, and simplify the product structure.

[0131] In some embodiments, to improve the alignment effect of the alignment film, the present disclosure may configure the first transistor TFT1 between the binding area BA to be identical to the switching transistor in the display area AA. Specifically, the first transistor TFT1 and the switching transistor may have the same film layer, channel width-to-length ratio, gate morphology, first electrode morphology, second electrode morphology, active layer morphology, gate size, first electrode size, second electrode size, and active layer size. Furthermore, it should be noted that due to limitations in process conditions or the influence of other factors such as measurement, the aforementioned "identical" may be completely identical or may have some deviations. Therefore, as long as the "identical" relationship between the aforementioned features satisfies the tolerance, it falls within the scope of protection of the present disclosure.

[0132] As can be seen from the above, the present disclosure simultaneously provides a first transistor TFT1 for monitoring the liquid crystal temperature, a first transistor TFT1 for monitoring the temperature of the shift register GOA, and a first transistor TFT1 for monitoring the ambient temperature. The first transistor TFT1 for monitoring the liquid crystal temperature can be composed of multiple virtual transistors connected in parallel. The first transistor TFT1 for monitoring the temperature of the shift register GOA can be any transistor of the virtual shift register DGOA. The first transistor TFT1 for monitoring the ambient temperature can be the same as the switching transistor of the display area AA. To accurately represent the corresponding temperature, the three first transistors TFT1 are connected in series with different first resistors R1. It is worth noting that the size of the first resistor R1 in the present disclosure is related to the channel width-to-length ratio of the first transistor TFT1. When the voltage across the first transistor TFT1 and the first resistor R1 is fixed, the larger the channel width-to-length ratio of the first transistor TFT1, the smaller the voltage divider. Accordingly, the greater the voltage divider that the first resistor R1 needs to bear, the larger the first resistor R1.

[0133] In some embodiments, in the present disclosure, the first electrode of the first transistor TFT1, the second electrode of the first transistor TFT1, the first electrode of the second transistor TFT2, the second electrode of the second transistor TFT2, the first electrode of the third transistor TFT3, the second electrode of the third transistor TFT3, the first electrode of the fourth transistor TFT4, and the second electrode of the fourth transistor TFT4 are comb-shaped electrodes or block-shaped electrodes; the gate of the first transistor TFT1, the gate of the second transistor TFT2, the gate of the third transistor TFT3, and the gate of the fourth transistor TFT4 are block-shaped electrodes or include multiple interconnected island-shaped electrodes. For example, Figure 20 shows that the first electrode S of the transistor (for example, the second transistor TFT2, the third transistor TFT3, and the fourth transistor TFT4) is comb-shaped, the second electrode D is comb-shaped, and the gate G is block-shaped; Figure 21 shows that the first electrode S of the transistor (for example, the second transistor TFT2, the third transistor TFT3, and the fourth transistor TFT4) is comb-shaped, the second electrode D is comb-shaped, and the gate G is island-shaped. A in Figures 20 and 21 represents the active layer of the transistor (for example, the second transistor TFT2, the third transistor TFT3, and the fourth transistor TFT4).

[0134] In some embodiments, as shown in Figures 17a and 18, in the array substrate provided by the embodiment of the present disclosure, the data line 108 and the gate line 109 are arranged in different layers and cross-wise. The data line 108 is electrically connected to the common electrode line 102 through the first electrostatic discharge unit 110 to discharge the static electricity of the data line 108 to the common electrode line 102, thereby realizing electrostatic protection for the data line 108. The gate line 109 is connected to the shift register GOA through the gate signal output line 111, so that the shift register GOA can provide a driving signal through the gate signal output line 111. The gate drive circuit signal line 112 can be connected to the common electrode line 102 by the second electrostatic discharge unit 113 to realize electrostatic protection for the gate drive circuit signal line 112. Optionally, the gate drive circuit signal line 112 includes a frame start signal line STV, a total reset signal line STV0, a ​​clock signal line CLK, a high level signal line VDD, a low level signal line LVGL, etc. The frame start signal line STV can be one or more, which is not limited here.

[0135] Based on the same inventive concept, an embodiment of the present disclosure provides a display panel, as shown in FIG22 , comprising the array substrate 001 provided in the embodiment of the present disclosure, and an opposing substrate 002 disposed opposite the array substrate 001. Because the principles for solving the problems solved by the display panel are similar to those solved by the array substrate, the implementation of the display panel provided in the embodiment of the present disclosure can refer to the implementation of the array substrate provided in the embodiment of the present disclosure, and any repetitions will not be repeated.

[0136] In some embodiments, as shown in FIG22 , the display panel provided by the embodiments of the present disclosure may further include a liquid crystal layer 003 between an array substrate 001 and an opposing substrate 002. In some embodiments, a first polarizer 004 may be provided on a side of the array substrate 001 away from the opposing substrate 002, and a second polarizer 005 may be provided on a side of the opposing substrate 002 away from the array substrate 001. The polarization directions of the first polarizer 004 and the second polarizer 005 are perpendicular to each other. Other essential components of the display panel are readily understood by those skilled in the art and are not described here in detail, nor should they be construed as limitations of the present disclosure.

[0137] Based on the same inventive concept, an embodiment of the present disclosure provides a driving method for the above-mentioned display panel, as shown in FIG23 , which may include the following steps:

[0138] S2301, using sensor circuit to monitor panel temperature;

[0139] S2302: Generate driving parameters according to the panel temperature, and use the driving parameters to control the display panel to display the picture.

[0140] Optionally, the above step S2301 uses a sensor circuit to monitor the panel temperature, which can be implemented in the following two ways:

[0141] The first method is: at a fixed moment after each turning on of the first transistor, the voltage at the connection point between the first resistor and the second resistor is collected, and the panel temperature is determined based on the collected voltage;

[0142] The second method is: during each turn-on of the first transistor, the panel temperature is determined by monitoring the peak charging current of the capacitor.

[0143] In some embodiments, after the sensor circuit monitors the panel temperature, a step may be performed: turning on the second transistor to discharge the capacitor. Optionally, the second transistor may be used to discharge the capacitor before the display panel is controlled to display an image using the drive parameters, or after the display panel is controlled to display an image using the drive parameters, and this is not specifically limited in this disclosure.

[0144] Based on the same inventive concept, an embodiment of the present disclosure provides a display device, as shown in FIG24 , comprising the display panel PNL provided in the embodiment of the present disclosure, and a backlight module BLU located on the light incident side of the display panel PNL. Optionally, the display device may further comprise a microcontroller MCU, as shown in FIG25 , the microcontroller MCU comprising a storage module M1, a clock module M2, and a calculation module M3; wherein the storage module M1 is configured to store the voltage Vout at the detection point P in accordance with the threshold voltage Vout of the first transistor TFT1. TH , and a first relationship of temperature T change, and storing the threshold voltage V of the first transistor TFT1 TH The difference between the initial threshold voltage of the first transistor TFT and ΔV TH The second relationship changes with the working time t of the first transistor TFT1; optionally, the first relationship is V out ≈V in -A*TV TH , the second relation is Where Vin is the voltage of the power supply line VL, A is a constant, V TH The threshold voltage is the minimum gate-source voltage required to form a conductive path between the drain and the source. It is a characteristic of the thin film transistor that depends on the design and manufacturing process of the device and will change over time. TH is the threshold voltage V TH The change in the threshold voltage V under specific conditions TH The change relative to the initial threshold voltage. V G is the gate voltage, the voltage applied to the gate. V TO is the initial threshold voltage, the threshold voltage when there are no other influencing factors. t is time, which is usually used to describe time-dependent effects. DC is a DC bias or DC condition, which can represent a certain DC bias voltage or current. τ0 is a characteristic time constant, which is related to the physical properties and material properties of the device and is used to describe time-dependent effects. f is the frequency, which can represent the frequency of the signal or the frequency of some periodic changes. β is an exponential factor, which is used to describe the degree of nonlinear effects. The clock module M2 is configured to monitor the working time t of the first transistor TFT1. The calculation module M3 is configured to calculate the threshold voltage VTH of the first transistor TFT1 based on the working time t of the first transistor TFT1 and the second relationship, and based on the calculated threshold voltage V TH The temperature data is outputted by the first relational expression. Thus, the present disclosure can also eliminate the influence of the threshold drift of the first transistor TFT1 on the temperature.

[0145] In some embodiments, in the above-mentioned display device provided by the embodiments of the present disclosure, the backlight module BLU can be a direct-type backlight module or an edge-type backlight module. Optionally, the edge-type backlight module may include a light bar, a stacked reflective sheet, a light guide plate, a diffuser, a prism group, etc., and the light bar is located on one side of the thickness direction of the light guide plate. The direct-type backlight module may include a matrix light source, a reflective sheet, a diffuser and a brightening film stacked on the light-emitting side of the matrix light source, etc., and the reflective sheet includes an opening arranged opposite to the position of each lamp bead in the matrix light source. The lamp beads in the light bar and the lamp beads in the matrix light source can be light-emitting devices (LEDs), such as quantum dot light-emitting devices.

[0146] In some embodiments, the lamp beads can also be micro light-emitting devices (such as Mini LED, Micro LED), etc. Submillimeter or even micron-scale micro light-emitting devices are self-luminous devices like organic light-emitting devices (OLED). Like organic light-emitting devices, they have a series of advantages such as high brightness, ultra-low latency, and ultra-large viewing angle. And because the light emission of inorganic light-emitting devices is based on metal semiconductors with more stable properties and lower resistance, compared with organic light-emitting devices based on organic matter, they have the advantages of lower power consumption, greater resistance to high and low temperatures, and longer service life. And when the micro light-emitting device is used as a backlight source, it can achieve a more precise dynamic backlight effect. While effectively improving the brightness and contrast of the screen, it can also solve the glare phenomenon caused by traditional dynamic backlight between the bright and dark areas of the screen, thereby optimizing the visual experience.

[0147] In some embodiments, the above-mentioned display device provided in the embodiments of the present disclosure may be: a projector, a 3D printer, a virtual reality device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or any other product or component with a display function. Optionally, the display device provided in the present disclosure includes, but is not limited to, components such as a radio frequency unit, a network module, an audio output & input unit, a sensor, a display unit, a user input unit, an interface unit, and a control chip. Optionally, the control chip is a central processing unit, a digital signal processor, a system-on-chip (SoC), etc. For example, the control chip may further include a memory, a power module, etc., and realize power supply and signal input and output functions through additionally provided wires, signal lines, etc. For example, the control chip may further include hardware circuits and computer executable code, etc. The hardware circuit may include conventional very large scale integration (VLSI) circuits or gate arrays and existing semiconductors or other discrete components such as logic chips and transistors; the hardware circuit may also include field programmable gate arrays, programmable array logic, programmable logic devices, etc. In addition, those skilled in the art will understand that the above structure does not constitute a limitation on the above display device provided in the embodiment of the present disclosure. In other words, the above display device provided in the embodiment of the present disclosure may include more or fewer of the above components, or a combination of certain components, or different component arrangements.

[0148] Based on the same inventive concept, an embodiment of the present disclosure provides a driving method for the above-mentioned display device, as shown in FIG26 , which may include the following steps:

[0149] S2601, collecting the working time of the first transistor;

[0150] S2602, calculating the threshold voltage of the first transistor according to the operating time of the first transistor and a second relationship formula showing that the difference between the threshold voltage of the first transistor and the initial threshold voltage of the first transistor varies with the operating time of the first transistor;

[0151] S2603 : Outputting temperature data based on the calculated threshold voltage of the first transistor and a first relationship representing a change in the voltage at the detection point with the threshold voltage of the first transistor and temperature.

[0152] Since the principle of solving the problem by the driving method is similar to the principle of solving the problem by the above-mentioned display device, the implementation of the driving method provided in the embodiment of the present disclosure can refer to the implementation of the above-mentioned display device provided in the embodiment of the present disclosure, and the repeated parts will not be repeated.

[0153] Although the preferred embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concepts. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present disclosure.

[0154] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present disclosure without departing from the spirit and scope of the embodiments of the present disclosure. Thus, if such changes and modifications of the embodiments of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include such changes and modifications.

Claims

1. An array substrate, wherein, Comprising: A substrate, the substrate including a display area and a non-display area located on at least one side of the display area, the non-display area including a shift register area; A sensor circuit configured to monitor at least one of the temperature of the display area, the temperature of the shift register area, and the ambient temperature.

2. The array substrate according to claim 1, wherein, The sensor circuit is a temperature sensing circuit.

3. The array substrate according to claim 2, wherein, Also including a power supply line; The sensor circuit includes a first transistor, wherein the gate of the first transistor is coupled to the power supply line, the first pole of the first transistor is coupled to the gate of the first transistor, and the second pole of the first transistor is coupled to a detection point.

4. The array substrate according to claim 3, wherein, The non-display area further includes a virtual area disposed between the display area and the shift register area, and a virtual transistor is provided in the virtual area, and the first transistor is multiplexed with the virtual transistor.

5. The array substrate according to claim 4, wherein, There are multiple virtual transistors, and the multiple virtual transistors are connected in parallel as the first transistor.

6. The array substrate according to claim 5, wherein, Also including a common electrode line and a connection line located in the non-display area, the power supply line is multiplexed with the common electrode line, and the gates of the multiple virtual transistors are electrically connected to the common electrode line through the connection line.

7. The array substrate according to claim 3, wherein, Also including a cascaded shift register and a virtual shift register located at at least one end in the cascading direction of the shift register, and the first transistor is multiplexed with any transistor of the virtual shift register.

8. The array substrate according to claim 7, wherein, The non-display area includes a bonding area, and the first transistor is multiplexed with any transistor of the virtual shift register close to the bonding area.

9. The array substrate according to claim 3, wherein, The non-display area further includes multiple bonding areas, and the first transistor is located between adjacent bonding areas.

10. The array substrate according to claim 9, wherein, Also including a switching transistor located in the display area, and the first transistor is the same as the switching transistor.

11. The array substrate according to any one of claims 7 to 10, wherein, Also including a high-level signal line electrically connected to the shift register, and the power supply line is multiplexed with the high-level signal line.

12. The array substrate according to any one of claims 3 to 11, wherein, Also including a ground wire, and the sensor circuit further includes a first resistor connected between the detection point and the ground wire.

13. The array substrate according to claim 12, wherein, The second poles of different first transistors are electrically connected to different first resistors.

14. The array substrate according to claim 1, wherein, Also including a common electrode line located in the non-display area, the common electrode line includes a receiving groove disposed close to the display area, and at least part of the sensor circuit is located in the receiving groove.

15. The array substrate according to claim 14, wherein, Also including an input signal line and a reference signal line wound around the common electrode line; The sensor circuit includes a second transistor and a capacitor, wherein the gate of the second transistor is coupled to the input signal line, the first pole of the second transistor is coupled to the gate of the second transistor, the second pole of the second transistor is coupled to the first electrode plate of the capacitor, and the second electrode plate of the capacitor is coupled to the reference signal line.

16. The array substrate according to claim 15, wherein, The capacitor is located in the receiving groove, and at least part of the second transistor is located in the receiving groove.

17. The array substrate according to claim 15 or 16, wherein, The second transistor is located on the side of the capacitor away from the display area, or the capacitor is located on the side of the second transistor away from the display area.

18. The array substrate according to any one of claims 15 to 17, wherein, The opening of the receiving groove faces away from the display area, the input signal line extends from the side of the common electrode line away from the display area into the receiving groove, and the reference signal line extends from the side of the input signal line away from the display area into the receiving groove.

19. The array substrate according to claim 18, wherein, It further includes a detection signal line located on the side of the reference signal line away from the common electrode line; The sensor circuit further includes a second resistor and a third resistor. The first end of the second resistor is coupled to the first electrode plate of the capacitor, the second end of the second resistor is coupled to the detection signal line, the first end of the third resistor is coupled to the detection signal line, and the second end of the third resistor is coupled to the reference signal line.

20. The array substrate according to claim 19, wherein, The third resistor is greater than the second resistor.

21. The array substrate according to claim 20, wherein, The second resistor and the third resistor respectively include a plurality of winding repeating units, and the number of winding repeating units of the second resistor is less than the number of winding repeating units of the third resistor.

22. The array substrate according to claim 21, wherein, It further includes a first dummy pattern, and the first dummy pattern is located on the side of the second resistor facing the display area, on the side of the second resistor away from the display area, on the side of the third resistor facing the display area, and on the side of the third resistor away from the display area. The structure of the first dummy pattern is substantially the same as the structures of the second resistor and the third resistor.

23. The array substrate according to claim 22, wherein, The common electrode line, the input signal line, the reference signal line, the detection signal line, the second electrode plate of the capacitor, the second resistor, the third resistor, the first dummy pattern are arranged on the same layer as the gate of the transistor, and the first electrode plate of the capacitor is arranged on the same layer as the first and second poles of the transistor.

24. The array substrate according to any one of claims 18 to 23, wherein, It further includes a second dummy pattern located in the receiving groove, and the second dummy pattern is arranged in the space surrounded by the input signal line, the reference signal line, and the capacitor.

25. The array substrate according to claim 24, wherein, The second dummy pattern is arranged on the same layer as the gate of the transistor.

26. The array substrate according to claim 24 or 25, wherein The common electrode line, the input signal line, the reference signal line, and the second dummy pattern respectively include a plurality of hollow structures.

27. The array substrate according to any one of claims 15 to 17, wherein, The opening of the receiving groove faces the display area; The array substrate further includes a fan-out line located between the common electrode line and the display area, and the input signal line and the reference signal line are located between the fan-out line and the common electrode line.

28. The array substrate according to claim 27, wherein, It further includes a control signal line located between the input signal line and the reference signal line; The sensor circuit further includes a third transistor. The gate of the third transistor is coupled to the control signal line, the first pole of the third transistor is coupled to the first electrode plate of the capacitor, the second pole of the third transistor is coupled to the second electrode plate of the capacitor, and the channel width-to-length ratio of the third transistor is greater than the channel width-to-length ratio of the second transistor.

29. The array substrate according to claim 28, wherein The sensor circuit further includes a fourth transistor. The gate of the fourth transistor is coupled to the reference signal line, the first pole of the fourth transistor is coupled to the second electrode plate of the capacitor, and the second pole of the fourth transistor is coupled to the reference signal line.

30. The array substrate according to claim 29, wherein, The second transistor, the third transistor, and the fourth transistor are arranged side by side on the same side of the capacitor.

31. The array substrate according to claim 29 or 30, wherein The first pole of the second transistor, the second pole of the second transistor, the first pole of the third transistor, the second pole of the third transistor, the first pole of the fourth transistor, and the second pole of the fourth transistor are comb-shaped electrodes or block electrodes; the gate of the second transistor, the gate of the third transistor, and the gate of the fourth transistor are block electrodes or include a plurality of interconnected island electrodes.

32. The array substrate according to any one of claims 14 to 31, wherein, It further includes a switching transistor located in the display area, and the ratio of the channel width-to-length ratio of the second transistor to the channel width-to-length ratio of the switching transistor is greater than or equal to 50.

33. The array substrate according to any one of claims 14 to 32, wherein, The non-display area includes a plurality of bonding areas, and the sensor circuit is located between the bonding area and the display area, and / or the sensor circuit is located between the gap adjacent to the bonding area and the display area.

34. A display panel, wherein, It includes an array substrate according to any one of claims 1 to 33, and an opposing substrate disposed opposite to the array substrate.

35. A display device, wherein, It includes a display panel according to claim 34, and a backlight module located on the light-incident side of the display panel.

36. The display device according to claim 35, wherein, It further includes a micro-control circuit, and the micro-control circuit includes a storage module, a clock module, and a calculation module; wherein, The storage module is configured to store a first relationship between the voltage of the detection point and the threshold voltage of the first transistor and the temperature change, and store a second relationship between the difference between the threshold voltage of the first transistor and the initial threshold voltage of the first transistor and the operating time of the first transistor. The clock module is configured to monitor the operating time of the first transistor. The calculation module is configured to calculate the threshold voltage of the first transistor according to the operating time of the first transistor and the second relationship, and output temperature data based on the calculated threshold voltage of the first transistor and the first relationship.

37. A driving method for a display device as described in claim 36, wherein, It includes: Collect the operating time of the first transistor; Calculate the threshold voltage of the first transistor according to the operating time of the first transistor and the second relationship between the difference between the threshold voltage of the first transistor and the initial threshold voltage of the first transistor and the operating time of the first transistor; Output temperature data based on the calculated threshold voltage of the first transistor and the first relationship between the voltage of the detection point and the threshold voltage of the first transistor and the temperature change.

38. A driving method of a display panel as described in claim 34, wherein, It includes: Monitor the panel temperature using a sensor circuit; Generate driving parameters according to the panel temperature, and use the driving parameters to control the display panel to perform screen display.

39. The driving method according to claim 38, wherein, Monitoring the panel temperature using a sensor circuit specifically includes: At a fixed moment after each turn-on of the second transistor, collect the voltage at the connection point of the second resistor and the third resistor, and judge the panel temperature according to the collected voltage.

40. The driving method according to claim 38, wherein, Monitoring the panel temperature using a sensor circuit specifically includes: During the process of each turn-on of the second transistor, judge the panel temperature by monitoring the charging peak current of the capacitor.

41. The driving method according to claim 40, wherein, After monitoring the panel temperature using the sensor circuit, it further includes: turning on the third transistor to discharge the capacitor.

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