Memory access method and apparatus

Abstract

Embodiments of the present application disclose a memory access method and apparatus, which are used for reducing the bandwidth consumption of memory access. The method in the embodiments of the present application comprises: on the basis of the state of a redo region of a second compute node, a first compute node determines that a fault has occurred in the second compute node, the redo region being used to store a data operation record of the second compute node for one or more memory nodes, and the redo region being created on the basis of a user mode library provided by the first compute node; and, on the basis of the data operation record corresponding to an instruction set recorded in the redo region of the second compute node, the first compute node continues to execute or restores an instruction already recorded by the second compute node, the instruction set comprising one or more data operation instructions of the second compute node for the one or more memory nodes, the one or more data operation instructions constituting an atomic operation of the second compute node with respect to the one or more memory nodes, and the data operation instruction comprising one or more of the following: a read operation instruction, a write operation instruction, and a lock operation instruction.

Description

Memory access method and device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on February 4, 2024, with application number 202410163243.0 and application name “A method, device and other equipment for data processing”, and claims priority to the Chinese patent application filed with the State Intellectual Property Office on April 23, 2024, with application number 202410494290.3 and application name “A memory access method and device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of cloud computing, and in particular to a memory access method and device. Background Art

[0003] With the development of remote direct memory access (RDMA) technology, split memory architectures have become popular in modern data centers. In split memory architectures, a data center's central processing unit (CPU) and memory are split into compute nodes and memory nodes, allowing applications to dynamically allocate the required compute and memory resources based on demand. Consequently, split memory systems can significantly improve data center resource utilization.

[0004] In current split-memory systems, compute nodes and memory nodes are loosely coupled. This means that compute nodes can unilaterally perform data operations such as reads and writes on memory nodes, while the memory nodes are unaware of the compute node's status. Therefore, if a compute node fails, data consistency between different memory nodes is compromised. Furthermore, the memory node's lock cannot be released, hindering access to the memory node by other healthy compute nodes.

[0005] Therefore, to ensure data consistency across different memory nodes and the atomicity of compute node-to-memory operations, current split-memory systems deploy a coordinator that periodically sends heartbeat packets to all compute nodes to detect compute node failures. Upon detecting a compute node failure, the split-memory system can recover data operations performed by the failed compute node. However, deploying an additional coordinator in the split-memory system consumes and wastes the system's computing resources.

[0006] Summary of the Invention

[0007] The present application provides an embodiment of a memory access method. In the present application, a computing node can perform data operations on a memory node through a user-state library, so that a set of atomic operations performed by the computing node on the memory node can be recorded in a redo area. When a computing node fails, other computing nodes can continue to execute or restore the computing node's memory operations based on the data operation records in the redo area, thereby improving the fault tolerance performance of the computing node's data operations on the memory node and further improving the fault handling efficiency of the computing node. The present application also provides a memory access device, computing device, computing device cluster, computer-readable storage medium, and computer program product corresponding to the memory access method.

[0008] In a first aspect, an embodiment of the present application provides a memory access method, which can be executed by a separate memory system, or by a component of the separate memory system, such as a processor, chip, or chip system of the separate memory system, or by a logic module or software that can implement all or part of the functions of the separate memory system. The first aspect provides a first computing node in one or more computing nodes of the separate memory system, the separate memory system also includes one or more memory nodes, and the one or more memory nodes are used to store data of the one or more computing nodes. The method provided in the first aspect includes: the first computing node determines that the second computing node has failed based on the state of the redo area of ​​the second computing node, the redo area is used to store the data operation record of the second computing node on the one or more memory nodes, and the redo area is created based on the user state library provided by the first computing node. The first computing node continues to execute or recover the instructions already recorded by the second computing node based on the data operation record corresponding to the instruction set recorded in the redo area of ​​the second computing node, the instruction set including one or more data operation instructions of the second computing node on the one or more memory nodes, the one or more data operation instructions constituting the atomic operation of the second computing node on the one or more memory nodes, and the data operation instruction including one or more of the following: read operation instruction, write operation instruction, and lock operation instruction.

[0009] In the embodiment of the present application, the separated memory system can provide a redo area for computing nodes to perform data operations on memory nodes, so that a group of atomic operations of computing nodes on memory nodes can be recorded in the redo area. When a computing node fails, other computing nodes can continue to execute or restore the computing node's data on the memory node based on the data operation records in the redo area. Compared with the existing memory system that monitors computing node failures based on heartbeat packets and restores computing node operations based on logs, the memory access method provided in the embodiment of the present application improves the fault tolerance performance of computing nodes performing data operations on memory nodes, as well as the efficiency of computing node failure handling.

[0010] In one possible implementation, a first compute node accesses a memory node based on an interface in a user-state library. The user-state library is used to create and manage data operation records in a redo area. A set of atomic operations performed by the first compute node on the memory node based on the interface in the user-state library is recorded in the redo area of ​​the first compute node. When the set of atomic operations performed by the compute node on the memory node is confirmed, the data operation records in the redo area are committed, indicating that the set of atomic operations is executed on the memory node.

[0011] In the embodiment of the present application, when a computing node accesses a memory node based on an interface in a user-state library, the computing node will record its data operations on the memory node in a redo area, so that the separated memory system provides fault-tolerant support for the computing node, and separates the concurrent access control and fault-tolerant phases of multiple computing nodes to the memory node, thereby improving the access efficiency of the computing node to the memory node.

[0012] In one possible implementation, when it is determined that the first computing node obtains the lock corresponding to the memory node, that is, the data operation instructions in the redo area of ​​the first computing node are submitted, the first computing node executes the instruction set in the redo area on the memory node. After the first computing node completes execution of the instruction set, the first computing node releases the lock corresponding to the memory node.

[0013] In the embodiment of the present application, the computing node can submit the data operation instructions in the redo area only after obtaining the lock of the memory node, thereby ensuring the atomicity of the computing node's execution of the instruction set.

[0014] In one possible implementation, when each data manipulation instruction in the instruction set obtains a lock on the corresponding operation object in the memory node, the first compute node is determined to have obtained the corresponding lock on the memory node. Because the one or more data manipulation instructions included in the instruction set constitute an atomic operation by the compute node on the memory node, the first compute node is considered to have obtained the lock on the memory node only after each data manipulation instruction in the instruction set obtains a lock on the corresponding operation object in the memory node, and the data manipulation record in the redo area is committed.

[0015] In the embodiment of the present application, each data operation instruction in the redo area obtains the lock of the corresponding operation object in the memory node, so as to determine that the first computing node obtains the lock corresponding to the memory node, thereby ensuring the atomicity of the computing node execution instruction set and further improving the concurrency performance of the separated memory system.

[0016] In one possible implementation, upon determining that the first computing node has not obtained the lock corresponding to the memory node within a predetermined time, the first computing node restores the instructions already recorded by the first computing node based on the operation record in the redo area of ​​the first computing node. The first computing node clears the record and area context in the redo area.

[0017] In an embodiment of the present application, when the first computing node fails to obtain the lock corresponding to the memory node within a predetermined time, the first computing node restores the data operation record in the redo area, that is, the data operation record in the redo area of ​​the first computing node will not be executed on the memory node, thereby improving the fault tolerance performance of the separated memory system for computing node operations.

[0018] In one possible implementation, after a data operation instruction in a redo area of ​​a first computing node is committed, the first computing node executes a set of instructions in the redo area on a memory node. After the first computing node completes execution of the set of instructions, the first computing node releases a lock corresponding to the memory node. After releasing the lock corresponding to the memory node, the first computing node changes the status of the redo area to a committed state.

[0019] In the embodiment of the present application, after the data operation instructions of the redo area of ​​the first computing node are submitted, the data operation records of the redo area of ​​the first computing node will be applied to the memory node, and the first computing node will modify the status of the redo area to a submitted state, thereby improving the integrity of the memory access method.

[0020] In one possible implementation, the first computing node continues to execute or recover the instructions already recorded by the second computing node based on the data operation record corresponding to the instruction set recorded in the redo area of ​​the second computing node. Then, the first computing node releases the lock obtained by the second computing node, and the second computing node is the failed computing node.

[0021] In the embodiment of the present application, after the first computing node is able to continue executing or recover the instructions already recorded by the second computing node, the first computing node releases the lock obtained by the second computing node, thereby improving the fault handling efficiency of the split memory system.

[0022] In one possible implementation, the lock corresponding to the memory node includes an expiration time. When the first computing node determines that the second computing node has not released the lock corresponding to the memory node within the expiration time, it is determined that the second computing node has failed.

[0023] In the embodiment of the present application, a computing node can detect whether other computing nodes have failed based on the expiration time in the lock structure of the memory node, thereby improving the fault handling efficiency of the split memory system.

[0024] In one possible implementation, the instruction set includes a read operation instruction. When it is determined that data corresponding to the read operation instruction exists in the region context of the redo area, the data corresponding to the read operation instruction is read from the region context of the redo area.

[0025] In an embodiment of the present application, when a computing node performs a data reading operation on a memory node, it can first read the required data from the regional context of the redo area. When the data to be read does not exist in the regional context, the computing node reads the data from the memory node, thereby improving the data reading efficiency of the calculation.

[0026] In one possible implementation, when it is determined that the data corresponding to the read operation instruction does not exist in the area context of the redo area, the data corresponding to the read operation instruction is read from the memory node based on the indirect pointer and the data pointer, the indirect pointer is used to point to the data pointer, and the data pointer is used to point to the storage location of the data corresponding to the read operation instruction in the memory node.

[0027] In the embodiment of the present application, the computing node can determine the location of the data to be operated in the memory node based on the intermediate pointer and the data pointer, thereby improving the feasibility of the internal method. At the same time, the log area of ​​the memory node only needs to store the data pointer without having to store the data to be operated by the computing node, thereby reducing the storage space occupied by the log area of ​​the memory node.

[0028] In a second aspect, an embodiment of the present application provides a memory access device, which includes a determination unit and a processing unit, wherein the determination unit is used to determine that a second computing node has failed based on the state of the redo area of ​​the second computing node, the redo area is used to store the data operation records of the second computing node on one or more memory nodes, and the redo area is created based on the user state library provided by the first computing node. The processing unit is used to continue executing or recovering the instructions already recorded by the second computing node based on the data operation records corresponding to the instruction set recorded in the redo area of ​​the second computing node, the instruction set including one or more data operation instructions of the second computing node on one or more memory nodes, the one or more data operation instructions constituting the atomic operation of the second computing node on the one or more memory nodes, and the data operation instructions including one or more of the following: read operation instructions, write operation instructions, and lock operation instructions.

[0029] In a possible implementation, the processing unit is further configured to access the memory node based on an interface in a user state library, and the user state library is configured to create and manage data operation records in the redo area.

[0030] In a possible implementation, the processing unit is further configured to, when determining that the first computing node obtains the lock corresponding to the memory node, execute an instruction set in the redo area on the memory node to release the lock corresponding to the memory node.

[0031] In a possible implementation, the processing unit is specifically configured to determine that the first computing node obtains the lock corresponding to the memory node when each data operation instruction in the instruction set obtains the lock of the corresponding operation object in the memory node.

[0032] In one possible implementation, the processing unit is further configured to restore the instructions recorded by the first computing node based on the operation records in the redo area of ​​the first computing node when it is determined that the first computing node has not obtained the lock corresponding to the memory node within a predetermined time.

[0033] In a possible implementation, the processing unit is further configured to modify the status of the redo area to a committed status.

[0034] In a possible implementation, the processing unit is further configured to release the lock acquired by the second computing node.

[0035] In one possible implementation, the lock corresponding to the memory node includes an expiration time, and the determination unit is further configured to determine that if the second computing node does not release the lock corresponding to the memory node within the expiration time, then determine that the second computing node has failed.

[0036] In one possible implementation, the instruction set includes a read operation instruction, and the processing unit is further configured to read the data corresponding to the read operation instruction from the regional context of the redo area when determining that data corresponding to the read operation instruction exists in the regional context of the redo area.

[0037] In one possible embodiment, the processing unit is also used to read the data corresponding to the read operation instruction from the memory node based on the indirect pointer and the data pointer when it is determined that the data corresponding to the read operation instruction does not exist in the area context of the redo area, the indirect pointer is used to point to the data pointer, and the data pointer is used to point to the storage location of the data corresponding to the read operation instruction in the memory node.

[0038] In a third aspect, an embodiment of the present application provides a computing device, comprising a processor coupled to a memory, the processor being used to store instructions. When the instructions are executed by the processor, the computing device executes the method described in the first aspect or any possible implementation of the first aspect.

[0039] In a fourth aspect, an embodiment of the present application provides a computing device cluster, which includes one or more computing devices, each of which includes a processor coupled to a memory, and the processor is used to store instructions. When the instructions are executed by the processor, the computing device cluster executes the method described in the first aspect or any possible implementation method of the first aspect.

[0040] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium having instructions stored thereon. When the instructions are executed, the computer executes the method described in the first aspect or any possible implementation method of the first aspect.

[0041] In a sixth aspect, an embodiment of the present application provides a computer program product, which includes instructions. When the instructions are executed, the computer implements the method described in the first aspect or any possible implementation method of the first aspect.

[0042] It can be understood that the beneficial effects that can be achieved by any of the memory access devices, computing devices, computing device clusters, computer-readable media or computer program products provided above can be referred to the beneficial effects in the corresponding methods and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] FIG1 is a schematic diagram of the system architecture of a separate memory system provided in an embodiment of the present application;

[0044] FIG2 is a flow chart of a memory access method provided in an embodiment of the present application;

[0045] FIG3 is a schematic diagram of a memory access method provided in an embodiment of the present application;

[0046] FIG4 is a schematic diagram of the structure of a lock code provided in an embodiment of the present application;

[0047] FIG5 is a flow chart of another memory access method provided in an embodiment of the present application;

[0048] FIG6 is a schematic diagram of a flow chart of a computing node performing a read operation instruction according to an embodiment of the present application;

[0049] FIG7 is a schematic diagram of a flow chart of a lock operation instruction performed by a computing node according to an embodiment of the present application;

[0050] FIG8 is a schematic diagram of a process for a computing node to submit a redo area according to an embodiment of the present application;

[0051] FIG9 is a schematic diagram of a process for a computing node to recover a redo area according to an embodiment of the present application;

[0052] FIG10 is a schematic structural diagram of a memory access device provided in an embodiment of the present application;

[0053] FIG11 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0054] FIG12 is a schematic diagram of the structure of a computing device cluster provided in an embodiment of the present application;

[0055] FIG13 is a schematic diagram of the structure of another computing device cluster provided in an embodiment of the present application. DETAILED DESCRIPTION

[0056] Embodiments of the present application provide a memory access method and apparatus for reducing the resource overhead required for fault recovery in a separate memory system, thereby improving the recovery efficiency of computing node faults in the separate memory system.

[0057] The terms "first," "second," "third," "fourth," and the like (if any) in the specification and claims of this application and in the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or sequential sequence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions, e.g., a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0058] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0059] First, some terms involved in the embodiments of the present application are introduced to facilitate those skilled in the art to understand the technical solutions.

[0060] Disaggregated memory (DM) is a memory architecture that dynamically adjusts node memory resources. A disaggregated memory system consists of compute nodes (CN) and memory nodes (MN). Memory nodes MN provide data storage services to compute nodes CN. Compute nodes CN can access memory nodes MN through read and write operations.

[0061] The user state library is a user interface library for high-performance computing and big data processing. For example, the PhoenixCN user state library provides a set of user state interfaces for handling communication and data transmission between computing nodes and memory nodes, enabling computing nodes to interact with memory nodes based on user state interfaces.

[0062] In order to make the technical solution of the present application clearer and easier to understand, the system architecture of the present application is introduced below with reference to the accompanying drawings.

[0063] Please refer to Figure 1, which is a schematic diagram of the system architecture of a separate memory system provided as an example in this application. In the example shown in Figure 1, separate system 10 includes a computing node 101 and a memory node 102, wherein computing node 101 also includes a user state library 1011. Applications running on computing node 101 can access memory node 102 through the operation interface in user state library 1011. In separate memory system 10, computing node 101 and memory node 102 work together to achieve dynamic configuration and sharing of memory resources. The specific functions of each part of separate system 10 are described below.

[0064] Compute node 101 is used to run user applications and access data from memory node 102. In a split memory system, compute node 101 does not directly contain memory resources. Instead, it communicates with memory node 102 via a high-speed network to obtain the memory required by compute node 101. For example, the compute node communicates with memory node 102 via remote direct memory access (RDMA) to perform operations such as reading and writing data.

[0065] Compute node 101 includes a user state library 1011. Applications running on compute node 101 can access memory node 102 through an operation interface in user state library 1011. User state library 1011, for example, is a Phoenix CN user state library. When compute node 101 accesses memory node 102 through user state library 1011, user state library 1011 provides a redoable region for access operations. The redo region is used to store records of data operations performed by compute node 101 on memory node 102. Data operations include read operations, write operations, and lock operations.

[0066] Memory node 102 is used to store and manage the data stored by compute node 101 and provide an interface for compute node 101 to access the stored data. For example, memory node 102 can communicate with compute node 101 over a network, transmitting stored data to compute node 101. Furthermore, memory node 102 can receive and store computation results sent by compute node 101. Memory node 101 is also used to back up, restore, and protect data to ensure data integrity and reliability.

[0067] It can be understood that in the embodiment of the present application, the number of computing nodes 101 and memory nodes 102 in the separate system 10 can be multiple nodes, such as a first computing node and a second computing node. Multiple computing nodes 101 can constitute a computing pool (computing pool) of the separate memory system 10, and multiple memory nodes 102 can constitute a memory pool (memory pool) of the separate memory system 10.

[0068] Based on the memory access system 10 shown in Figure 1, the present application further provides a memory access method. The memory access method provided by the embodiment of the present application is introduced below in conjunction with an embodiment.

[0069] Please refer to Figure 2, which is a flow chart of a memory access method provided in an embodiment of the present application. In the example shown in Figure 2, the method includes the following steps:

[0070] Step 201. The separated storage system provides a user state library, which is used to create a redo area for computing nodes to access memory nodes. The redo area is used to store instructions that the computing nodes are operating on the memory nodes but have not yet submitted.

[0071] In the embodiment of the present application, the separated storage system 10 provides a user state library 1011, and the computing node 101 accesses the memory node 102 through the user state library 1011, which can ensure the atomicity of the data operations performed by the computing node 101 on the memory node 102. Atomicity means that when the computing node 101 crashes, a group of atomic operations are either all executed successfully or not executed at all.

[0072] In an embodiment of the present application, the user state library 101 is used to provide the computing node 101 with access to the redo area of ​​the memory node 102. The redo area is used to store the operation records of the computing node 101 on the memory node 102. These operation records are instructions that the computing node 101 is performing on the memory node 102 but has not yet been submitted. The computing node 101 ensures the atomicity of a set of data operations based on the data operation records in the redo area. Only when the data operations in the redo area are submitted can the computing node 101 execute these data operations in the memory node 102.

[0073] The following describes in detail the user state library 1011 in the embodiment of the present application. The user state library 1011 can provide one or more interface functions for creating and operating redo areas. The user state library 1011 can be called a user interface library. The computing node 101 can create and manage redo areas by calling these interface functions.

[0074] It should be noted that user state library 1011 does not directly operate the underlying implementation of the redo area, but rather simplifies the application's use of the redo area by encapsulating and providing a high-level interface. Therefore, in the embodiment of the present application, user state library 1011 provides a more user-friendly operation interface to the application in computing node 101 by encapsulating the underlying redo area functionality, allowing the application in computing node 101 to more conveniently use the redo area to achieve atomicity and recoverability of data operations.

[0075] In the embodiment of the present application, the operation records stored in the redo region can also be regarded as the operation intention of the computing node 101 on the memory node 102. The redo region also includes a region context. The region context is located in the computing node 101 and is used to store metadata and status information related to the redo region, including region identification information, permission information, and data structure information.

[0076] The region identification information is used to identify the redo region. For example, the region identification information is a 16-bit integer that uniquely identifies a redo region. The permission information is used to record the access rights and operation permissions for the redo region. The data structure information is used to indicate the data and data structure information associated with the operation instructions in the redo region. The data structure information includes data types, field definitions, and index structures.

[0077] In the embodiment of the present application, the separated storage system also provides a log space (log space), wherein the log space is located in the memory node 102, and the log space is used to persistently store the operation records of the computing node 101 on the memory node 102 in the redo area. For example, when the computing node 101 wants to write data in the memory node 102, the computing node 101 will first initialize the area context and mark the redo area. The computing node 102 will record the contents of the redo area in the log space of the memory node 102 to ensure that the write operation is persistently recorded. When the computing node 101 fails or data recovery is required, the memory node 102 will re-execute the operation of the computing node 101 according to the records in the log space, thereby recovering the data and ensuring the consistency and reliability of the data.

[0078] It should be noted that when computing node 101 operates on data in memory node 102 based on user-state library 1011, user-state library 1011 provides data operations at an object-level. That is, computing node 101 implements data operations on memory node 102 based on pointers corresponding to data operation objects. For example, computing node 101 can use an indirect pointer to the data object to point to a data pointer in memory node 102, and further use the data pointer to point to the actual location where the data object in memory node 102 is stored.

[0079] Please refer to Figure 3, which is a schematic diagram of a computing node providing memory access at an object granularity according to an embodiment of the present application. In the example shown in Figure 3, computing node 101 performs data operations at an object granularity based on the operation interface of user state library 101, where each object is a 64-bit pointer, which is called an indirect pointer. The indirect pointer points to an area in memory node 102, which stores a 64-bit data pointer. The data pointer points to the data in memory node 102 that computing node 101 actually wants to perform data operations on.

[0080] Step 202: The first computing node determines that the second computing node has failed based on a status of a redo area of ​​the second computing node, where the redo area is used to store data operation records of the second computing node on one or more memory nodes.

[0081] When a split memory system includes multiple compute nodes, for example, a first compute node and a second compute node, the first compute node determines that the second compute node has failed based on the status of the second compute node's redo area, where the redo area is used to store records of data operations performed by the second compute node on one or more memory nodes. For example, if the first compute node determines that the redo area of ​​the second compute node is in the "commit" state and the second compute node has not released the lock corresponding to the memory node, the first compute node determines that the second compute node has failed.

[0082] It should be noted that the separate memory system 10 in the embodiment of the present application needs to control the concurrent access of multiple computing nodes 101 to the data of the memory node 102 through a lock. When the computing node 101 needs to access the data in the memory node 102, it needs to first obtain the lock corresponding to the access data. The lock in the embodiment of the present application has a specified lock coding structure, which includes a lock identifier and an expiration time, wherein the lock identifier is used to identify the uniqueness of the lock, and the lock identifier is, for example, a 16-bit integer. The expiration time is used to indicate the validity period of the lock, and the expiration time is, for example, a 48-bit integer.

[0083] Please refer to Figure 4, which is a schematic diagram of a lock code structure provided in an embodiment of the present application. In the example shown in Figure 4, the lock code structure consists of two parts: a lock ID and an expiration time. The lock ID is 16 bits and the expiration time is 48 bits. In the example shown in Figure 4, since each redo region has a unique region ID, the lock ID can be consistent with the region ID of the redo region.

[0084] In an embodiment of the present application, the computing node 101 executes an instruction set based on the operation interface in the user state library 1011. The instruction set includes one or more data operation instructions of the computing node 101 to the memory node 102. The data operation instructions include one or more of the following: read operation instructions, write operation instructions and lock operation instructions. The one or more data operation instructions in the instruction set constitute the atomic operation of the computing node 101 to the memory node 102.

[0085] In the process of computing node 101 executing an instruction set based on the operation interface in the user state library 1011, different data operation instructions can be executed based on different operation interfaces. For example, the operation interface in the user state library includes a read operation interface, a write operation interface and a lock operation interface. Computing node 101 can execute a read operation instruction based on the read operation interface, execute a write operation instruction based on the write operation interface, and execute a lock operation instruction based on the lock operation interface.

[0086] Please refer to Figure 5, which is a flow chart of another memory access method provided by an embodiment of the present application. In steps a to b of the example shown in Figure 5, during the process of computing node 101 accessing memory node 102 based on the operation interface in user state library 1011, computing node 101 first initializes the region context of the redo area, and the initialization includes allocating space for the redo area, etc., wherein each operation interface in user state library 101 has a corresponding region context, for example, the region context includes Read-Set, Write-Set and Lock-Set, etc.

[0087] In steps c to e of the example shown in FIG5 , after the region context is initialized, computing node 101 executes an instruction set based on the operation interface in user state library 1011. During the execution of the instruction set, since computing node 101 needs to obtain a lock on the corresponding data of memory node 102 to execute the data operation instructions in the instruction set, when the instruction set contains data operation instructions for computing node 101 on different data in memory node 102, computing node 101 needs to obtain the locks corresponding to the different data. If all lock operations are successful, then after the data operations in the instruction set are completed in the redo region, computing node 101 commits the instruction set. Otherwise, computing node 101 recovers the instruction set. Committing refers to applying the instruction set to memory node 102, that is, executing the data operation instructions in the instruction set in memory node 102, and recovering refers to clearing the instruction set in the redo region and releasing the lock of memory node 102.

[0088] It should be noted that, in the example shown in FIG3 , the recovery (recovery) of the data operation instructions in the instruction set by the computing node 101 can be the recovery of the redo area by the computing node 101 itself, or the recovery of the failed computing node by other computing nodes, without specific limitation.

[0089] The following uses the read operation of the computing node 101 on the memory node 102 as an example to further describe an example of the computing node 101 executing an instruction set based on the operation interface in the user state library 1011:

[0090] In one possible implementation, when computing node 101 executes a read operation instruction based on the read operation interface in user state library 1011, if computing node 101 determines that the data corresponding to the read operation instruction exists in the region context of the redo area, computing node 101 reads the data corresponding to the read operation instruction from the region context of the redo area. If computing node 101 determines that the data corresponding to the read operation instruction does not exist in the region context of the redo area, computing node 101 reads the data corresponding to the read operation instruction from memory node 102 based on an indirect pointer and a data pointer. The indirect pointer is used to point to the data pointer, and the data pointer is used to point to the storage location of the data corresponding to the read operation instruction in memory node 102.

[0091] Please refer to Figure 6, which is a schematic diagram of a computing node executing a read operation instruction provided by an embodiment of the present application. In steps a to c of the example shown in Figure 6, when computing node 101 reads data from memory node 102 based on the read operation interface in data interface library 101, if the data to be read by computing node 101 is already write-set in the region context of the redo area, that is, the data to be read by computing node 101 is data that is being written but has not yet been committed to memory node 102, computing node 101 reads the data from the region context of the redo area.

[0092] In steps b through e of the example shown in FIG6 , if the data to be read by compute node 101 is not in the region context of the redo region, compute node 101 reads the data from memory node 102 based on the indirect pointer and the data pointer. Specifically, during the process of computing node 101 reading data from memory node 102 based on the indirect pointer and the data pointer, compute node 101 reads the data pointer based on the indirect pointer, and then reads the data corresponding to the data read operation in memory node 101 based on the data pointer.

[0093] The following continues to use the lock operation of the computing node 101 on the memory node 102 as an example to introduce an example in which the computing node 101 executes an instruction set based on the operation interface in the user state library 1011:

[0094] In one possible implementation, when computing node 101 executes a lock operation instruction based on the lock operation interface in user state library 1011, computing node 101 first determines in the region context of the redo region whether the data corresponding to the lock operation instruction has been locked, that is, whether computing node 101 has obtained the lock corresponding to the data. If computing node 101 has obtained the lock corresponding to the data, then a message indicating that the lock operation was successful is returned. If the data corresponding to the lock operation instruction in the region context of the redo region is not locked, that is, computing node 101 has not obtained the lock corresponding to the data, computing node 101 performs a lock operation on the data in the redo region.

[0095] Please refer to Figure 7, which is a schematic diagram of a process flow for a computing node to perform a lock operation according to an embodiment of the present application. In steps a to c of the example shown in Figure 7, when computing node 101 executes a lock operation instruction, computing node 101 first determines whether the data corresponding to the lock operation instruction has been locked in the region context lock-set of the redo region. If the data corresponding to the lock operation instruction has been locked, a message indicating that the lock operation is successful is returned. If the data corresponding to the lock operation instruction in the redo region is not locked, computing node 101 performs a lock operation on the data in the redo region.

[0096] In steps e through h of the example shown in FIG7 , after computing node 101 successfully executes the lock operation instruction, computing node 101 updates the region context lock-set of the redo region and returns a message indicating that the lock operation was successful. If computing node 101 fails to execute the lock operation instruction, computing node 101 may retry the lock operation. If computing node 101 fails to successfully execute the lock operation within a predetermined time period corresponding to the lock, computing node 101 may resume the lock operation on the redo region.

[0097] In one possible implementation, when separate memory system 10 determines that compute node 101 has acquired the lock corresponding to memory node 102, separate memory system 10 applies the instruction set in the redo region to memory node 102. Computing node 101 then releases the lock corresponding to memory node 102. Determining that compute node 101 has acquired the lock corresponding to memory node 102 by separate memory system 10 means that all lock operations in the instruction set executed by compute node 101 have succeeded.

[0098] It should be noted that the above-mentioned application of the instruction set in the redo area to the memory node 102, that is, the computing node 101 commits the instruction set of the redo area. Commit means that after the computing node 101 completes all data operation instructions of the instruction set, it saves the data operations it has performed to the memory node 102.

[0099] Please refer to Figure 8, which is a schematic diagram of a process for a computing node to submit an instruction set provided by an embodiment of the present application. In steps a to c of the example shown in Figure 8, in the process of the computing node submitting the instructions of the redo area, when the computing node 101 obtains the lock corresponding to the memory node 102, the computing node 101 applies the data operation instructions in the redo area to the memory node 102. For example, the computing node 101 writes data in the memory node 102 based on the write operation instructions in the redo area. Afterwards, the computing node 101 writes the instruction record of the redo area to the log space of the memory node 102, and switches the status of the redo area in the log space to committing. If the status switch of the redo area in the log space fails, the computing node 101 clears the area context and returns.

[0100] In the example steps e to g shown in FIG8 , after computing node 101 applies the data operation instructions in the redo region to memory node 102, if the state of the redo region in the log space is successfully switched, computing node 101 updates the data in the region context write-set of the redo region to memory node 102 and releases the lock corresponding to memory node 102 in the region context. After computing node 101 releases the lock corresponding to memory node 102, it switches the state of the redo region in the log space to committed.

[0101] Step 203. The first computing node continues to execute or recover the instructions already recorded by the second computing node based on the data operation record corresponding to the instruction set recorded in the redo area of ​​the second computing node, where the instruction set includes one or more data operation instructions of the second computing node on one or more memory nodes, and the one or more data operation instructions constitute the atomic operation of the second computing node on the one or more memory nodes.

[0102] The computing nodes include a first computing node and a second computing node. When the second computing node fails, the first computing node continues to execute or recover instructions in an instruction set recorded by the second computing node based on the redo area of ​​the second computing node. The instruction set includes one or more data operation instructions of the second computing node on one or more memory nodes, and the one or more data operation instructions constitute an atomic operation of the second computing node on the one or more memory nodes. The first computing node then releases the lock obtained by the second computing node, allowing the first computing node to obtain the lock corresponding to the memory node.

[0103] In one possible implementation, when separate storage system 10 determines that computing node 101 has failed, computing node 101 recovers the instructions recorded in the instruction set based on the redo area. Computing node 101 performs a recovery operation based on the redo area, which means undoing the data operation instructions in the redo area, restoring memory node 102 to the last committed state.

[0104] Please refer to Figure 9, which is a schematic diagram of a process flow for performing execution recovery on a computing node according to an embodiment of the present application. In steps a and b of the example shown in Figure 9, when computing node 2 determines that computing node 1 has failed, computing node 2 reads the data operation instructions in the redo area of ​​computing node 1. Based on the data operation instructions in the redo area of ​​computing node 1, computing node 2 recovers the instructions in the instruction set that computing node 1 has recorded.

[0105] In steps c through g of the example shown in FIG9 , when compute node 2 recovers instructions already recorded in the redo area of ​​compute node 1, if compute node 2 determines that compute node 1 has failed, compute node 2 first switches the node state of compute node 1 from the initial (INIT) state to the aborted (ABORT) state. Compute node 2 then checks the state of compute node 1's redo area. If the redo area is in the committing state, compute node 2 reads the region context write-set for compute node 1's redo area from compute node 1's log space. Based on the region context read from the log space, compute node 2 executes the unfinished operations of compute node 1 and then changes the state of compute node 1's redo area to committed. Simultaneously, the lock acquired by compute node 1 is released.

[0106] In one possible implementation, the lock corresponding to the memory node includes an expiration time. When the first computing node determines that the second computing node has not released the lock corresponding to the memory node within the expiration time, the first computing node determines that the second computing node has failed. After the second computing node fails, the first computing node recovers the instructions in the instruction set that the second computing node has recorded based on the redo area of ​​the second computing node.

[0107] Continuing with Figure 9, in the example shown in Figure 9, after compute node 2 determines that compute node 1 has failed, compute node 2 checks the status of compute node 1's redo region. If the redo region status is uncommitted, compute node 2 clears the redo region and region context for compute node 1 and releases the lock acquired by compute node 1. During the process of determining that compute node 1 has failed, if compute node 1 does not release the lock corresponding to the memory node within the expiration time, compute node 2 determines that compute node 1 has failed.

[0108] It can be seen from the above embodiments that the separated memory system in the embodiments of the present application can provide a redo area for the computing node to perform data operations on the memory node, so that a group of atomic operations of the computing node on the memory node can be recorded in the redo area. When a computing node fails, other computing nodes can continue to execute or restore the computing node's memory node data based on the data operation records in the redo area, thereby improving the fault tolerance performance of the computing node's data operations on the memory node and the efficiency of computing node fault handling.

[0109] Based on the above method embodiment, the embodiment of the present application further provides a memory access device. The memory access device provided by the embodiment of the present application is described in detail below.

[0110] Please refer to Figure 10, which is a schematic diagram of the structure of a memory access device provided in an embodiment of the present application. In the example shown in Figure 10, the memory access device 1000 is used to implement the various steps performed by the separate memory system in the above embodiments. The memory access device 1000 includes a determination unit 1001 and a processing unit 1002.

[0111] Determining unit 1001 is configured to determine, based on the state of a redo area of ​​the second computing node, that a fault has occurred in the second computing node. The redo area is configured to store data operation records of the second computing node on one or more memory nodes. The redo area is created based on a user state library provided by the first computing node. Processing unit 1002 is configured to continue executing or recovering instructions already recorded by the second computing node based on data operation records corresponding to an instruction set recorded in the redo area of ​​the second computing node. The instruction set includes one or more data operation instructions of the second computing node on the one or more memory nodes. The one or more data operation instructions constitute an atomic operation of the second computing node on the one or more memory nodes. The data operation instructions include one or more of the following: a read operation instruction, a write operation instruction, and a lock operation instruction.

[0112] In a possible implementation, the processing unit 1002 is further configured to access a memory node based on an interface in a user state library, and the user state library is configured to create and manage data operation records in a redo area.

[0113] In a possible implementation, the processing unit 1002 is further configured to, when determining that the first computing node obtains the lock corresponding to the memory node, execute an instruction set in the redo area on the memory node to release the lock corresponding to the memory node.

[0114] In a possible implementation, the processing unit 1002 is specifically configured to determine that the first computing node obtains the lock corresponding to the memory node when each data operation instruction in the instruction set obtains the lock of the corresponding operation object in the memory node.

[0115] In one possible implementation, the processing unit 1002 is further configured to restore the instructions recorded by the first computing node based on the operation records in the redo area of ​​the first computing node when it is determined that the first computing node has not obtained the lock corresponding to the memory node within a predetermined time.

[0116] In a possible implementation, the processing unit 1002 is further configured to modify the status of the redo area to a committed status.

[0117] In a possible implementation, the processing unit 1002 is further configured to release the lock obtained by the second computing node.

[0118] In one possible implementation, the lock corresponding to the memory node includes an expiration time, and the determination unit 1001 is further configured to determine that if the second computing node does not release the lock corresponding to the memory node within the expiration time, then determine that the second computing node has failed.

[0119] In one possible implementation, the instruction set includes a read operation instruction, and the processing unit 1002 is further configured to read the data corresponding to the read operation instruction from the regional context of the redo area when it is determined that data corresponding to the read operation instruction exists in the regional context of the redo area.

[0120] In one possible embodiment, the processing unit 1002 is also used to read the data corresponding to the read operation instruction from the memory node based on the indirect pointer and the data pointer when it is determined that the data corresponding to the read operation instruction does not exist in the area context of the redo area, and the indirect pointer is used to point to the data pointer, and the data pointer is used to point to the storage location of the data corresponding to the read operation instruction in the memory node.

[0121] It is understandable that the determining unit 1001 and the processing unit 1002 in the memory access device 1000 can be mapped as functional modules to the modules in the separate memory system 10 in FIG. 1 , thereby realizing the functions of the modules in the separate system 10 .

[0122] It should be understood that the division of units in the above device is merely a division of logical functions. In actual implementation, they can be fully or partially integrated into one physical entity, or they can be physically separated. Moreover, the units in the device can all be implemented in the form of software called through processing elements; or they can all be implemented in the form of hardware; or some units can be implemented in the form of software called through processing elements, and some units can be implemented in the form of hardware. For example, each unit can be a separately established processing element, or it can be integrated into a certain chip of the device. In addition, it can also be stored in the memory in the form of a program, called by a certain processing element of the device and perform the function of the unit. In addition, all or part of these units can be integrated together, or they can be implemented independently. The processing element described here can also be a processor, which can be an integrated circuit with signal processing capabilities. In the implementation process, each step of the above method or each unit above can be implemented by the integrated logic circuit of the hardware in the processor element or in the form of software called through the processing element.

[0123] It is worth noting that, for the sake of simplicity of description, the above method embodiments are all expressed as a series of action combinations. However, those skilled in the art should know that this application is not limited to the order of the actions described. Secondly, those skilled in the art should also know that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required for this application.

[0124] Other reasonable step combinations that can be thought of by those skilled in the art based on the above description also fall within the scope of protection of this application. Secondly, those skilled in the art should also be familiar with that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by this application.

[0125] Please refer to Figure 11, which is a schematic diagram of the structure of a computing device provided in an embodiment of the present application. As shown in Figure 11, computing device 1100 includes: a processor 1101, a memory 1102, a communication interface 1103, and a bus 1104. Processor 1101, memory 1102, and communication interface 1103 are coupled via a bus (not labeled in the figure). Memory 1102 stores instructions. When the execution instructions in memory 1102 are executed, computing device 1100 executes the method performed by the computing node of the separate internal memory system in the above method embodiment.

[0126] The computing device 1100 may be one or more integrated circuits configured to implement the above method, such as one or more application specific integrated circuits (ASICs), one or more digital signal processors (DSPs), one or more field programmable gate arrays (FPGAs), or a combination of at least two of these integrated circuit forms. For example, when a unit in the device can be implemented in the form of a processing element scheduler, the processing element can be a general-purpose processor, such as a central processing unit (CPU) or other processor that can call a program. For example, these units can be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0127] The processor 1101 may be a central processing unit (CPU), other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA), other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. The general-purpose processor may be a microprocessor or any conventional processor.

[0128] Memory 1102 may be volatile memory or nonvolatile memory, or may include both volatile and nonvolatile memory. Nonvolatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link DRAM (SLDRAM), and direct rambus RAM (DR RAM).

[0129] The memory 1102 stores executable program codes, and the processor 1101 executes the executable program codes to respectively implement the functions of the aforementioned units or modules, thereby implementing the aforementioned memory access method.

[0130] The communication interface 1103 uses a transceiver module such as, but not limited to, a network interface card or a transceiver to implement communication between the computing device 1100 and other devices or a communication network.

[0131] In addition to the data bus, bus 1104 may also include a power bus, a control bus, and a status signal bus. The bus may be a Peripheral Component Interconnect Express (PCIe) bus, an Extended Industry Standard Architecture (EISA) bus, a unified bus (Ubus or UB), a Compute Express Link (CXL), or a Cache Coherent Interconnect for Accelerators (CCIX). Buses can be categorized as address buses, data buses, and control buses.

[0132] Please refer to Figure 12, which is a schematic diagram of a computing device cluster provided in an embodiment of the present application. As shown in Figure 12, the computing device cluster 1200 includes at least one computing device 1100.

[0133] As shown in Figure 12, the computing device cluster 1200 includes at least one computing device 1100. The memory 1102 in one or more computing devices 1100 in the computing device cluster 1200 may store the same instructions for executing the above memory access method.

[0134] In some possible implementations, the memory 1102 of one or more computing devices 1100 in the computing device cluster 1200 may also store some instructions for executing the above-mentioned memory access method. In other words, the combination of one or more computing devices 1100 can jointly execute the instructions for executing the above-mentioned memory access method.

[0135] It should be noted that the memory 1102 in different computing devices 1100 in the computing device cluster 1200 may store different instructions, each for executing a portion of the functions of the aforementioned memory access device. In other words, the instructions stored in the memory 1102 in different computing devices 1100 may implement the functions of one or more modules in the processing unit and the determination unit.

[0136] In some possible implementations, one or more computing devices 1100 in the computing device cluster 1200 may be connected via a network, which may be a wide area network or a local area network.

[0137] Please refer to Figure 13, which is a schematic diagram of computer devices in a computer cluster 1300 provided in an embodiment of the present application connected via a network. As shown in Figure 13, two computing devices 1100A and 1100B are connected via a network. Specifically, the connection to the network is achieved through a communication interface in each computing device.

[0138] In one possible implementation, the memory of the computing device 1100A stores instructions for executing the function of the determination unit, and the memory of the computing device 1100B stores instructions for executing the function of the processing unit.

[0139] It should be understood that the functions of the computing device 1100A shown in Figure 13 may also be completed by multiple computing devices. Similarly, the functions of the computing device 1100B may also be completed by multiple computing devices.

[0140] In another embodiment of the present application, a computer-readable storage medium is provided, in which computer-executable instructions are stored. When the processor of the device executes the computer-executable instructions, the device executes the method executed by the separate memory system in the above method embodiment.

[0141] In another embodiment of the present application, a computer program product is provided, comprising computer-executable instructions stored in a computer-readable storage medium. When a processor of a device executes the computer-executable instructions, the device performs the method performed by the split memory system in the above method embodiment.

[0142] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0143] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0144] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0145] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0146] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

Claims

1. A memory access method, characterized in that: The method is applied to a first computing node among one or more computing nodes of a separate memory system, wherein the separate memory system further includes one or more memory nodes, wherein the one or more memory nodes are used to store data of the one or more computing nodes, and includes: The first computing node determines, based on a status of a redo area of the second computing node, that the second computing node has failed, where the redo area is used to store a record of data operations performed by the second computing node on the one or more memory nodes, and is created based on a user state library provided by the first computing node. The first computing node continues to execute or recover instructions already recorded by the second computing node based on the data operation record corresponding to the instruction set recorded in the redo area of the second computing node, the instruction set including one or more data operation instructions of the second computing node on the one or more memory nodes, the one or more data operation instructions constituting an atomic operation of the second computing node on the one or more memory nodes, the data operation instructions including one or more of the following: read operation instructions, write operation instructions and lock operation instructions.

2. The method according to claim 1, characterized in that The method further comprises: The first computing node accesses the memory node based on an interface in the user state library, and the user state library is used to create and manage data operation records of the redo area.

3. The method according to claim 1 or 2, characterized in that The method further comprises: Determining that the first computing node obtains the lock corresponding to the memory node, the first computing node executes the instruction set in the redo area on the memory node; The first computing node releases the lock corresponding to the memory node.

4. The method according to claim 3, characterized in that Determining that the first computing node obtains the lock corresponding to the memory node includes: When each data operation instruction in the instruction set obtains the lock of the corresponding operation object in the memory node, it is determined that the first computing node obtains the lock corresponding to the memory node.

5. The method according to claim 1 or 2, characterized in that The method further comprises: If it is determined that the first computing node has not obtained the lock corresponding to the memory node within a predetermined time, the instructions recorded by the first computing node are restored based on the operation record in the redo area of the first computing node.

6. The method according to claim 3 or 4, characterized in that After releasing the lock corresponding to the memory node, the method further includes: The first computing node changes the state of the redo area to a committed state.

7. The method according to any one of claims 1 to 6, characterized in that After the first computing node continues to execute or recover the instructions already recorded by the second computing node based on the data operation record corresponding to the instruction set recorded in the redo area of the second computing node, the method further includes: The first computing node releases the lock acquired by the second computing node.

8. The method according to any one of claims 1 to 7, characterized in that The lock corresponding to the memory node includes an expiration time, and the method further includes: When the first computing node determines that the second computing node has not released the lock corresponding to the memory node within the expiration time, it is determined that the second computing node has failed.

9. The method according to any one of claims 1 to 8, characterized in that The instruction set includes a read operation instruction, and the method further includes: When it is determined that the data corresponding to the read operation instruction exists in the area context of the redo area, the data corresponding to the read operation instruction is read from the area context of the redo area.

10. The method according to claims 1 to 9, characterized in that The method further comprises: When it is determined that the data corresponding to the read operation instruction does not exist in the area context of the redo area, the data corresponding to the read operation instruction is read from the memory node based on an indirect pointer and a data pointer, where the indirect pointer is used to point to the data pointer, and the data pointer is used to point to the storage location of the data corresponding to the read operation instruction in the memory node.

11. A memory access device, characterized in that: The device comprises: A determining unit is configured to determine that a fault has occurred in the second computing node based on a state of a redo area of the second computing node, wherein the redo area is configured to store data operation records of the second computing node on the one or more memory nodes, and the redo area is configured to determine that a fault has occurred in the second computing node based on a state of a redo area of the second computing node. The user state library provided by the first computing node is created; A processing unit is used to continue executing or recovering instructions already recorded by the second computing node based on the data operation record corresponding to the instruction set recorded in the redo area of the second computing node, the instruction set including one or more data operation instructions of the second computing node on the one or more memory nodes, the one or more data operation instructions constituting an atomic operation of the second computing node on the one or more memory nodes, and the data operation instructions including one or more of the following: read operation instructions, write operation instructions and lock operation instructions.

12. The device according to claim 11, characterized in that The processing unit is further configured to: The memory node is accessed based on an interface in the user state library, and the user state library is used to create and manage data operation records of the redo area.

13. The device according to claim 11 or 12, characterized in that The processing unit is further configured to: Determining that the first computing node obtains the lock corresponding to the memory node, executing the instruction set in the redo area on the memory node; Release the lock corresponding to the memory node.

14. The device according to claim 13, characterized in that The processing unit is specifically configured to: When each data operation instruction in the instruction set obtains the lock of the corresponding operation object in the memory node, it is determined that the first computing node obtains the lock corresponding to the memory node.

15. The device according to claim 11 or 12, characterized in that The processing unit is further configured to: If it is determined that the first computing node has not obtained the lock corresponding to the memory node within a predetermined time, the instructions recorded by the first computing node are restored based on the operation record in the redo area of the first computing node.

16. The device according to claim 13 or 14, characterized in that The processing unit is further configured to: The state of the redo area is changed to a committed state.

17. The device according to any one of claims 11 to 16, characterized in that The processing unit is further configured to: Release the lock acquired by the second computing node.

18. The device according to any one of claims 11 to 17, characterized in that The lock corresponding to the memory node includes an expiration time, and the determining unit is further configured to: If it is determined that the second computing node has not released the lock corresponding to the memory node within the expiration time, it is determined that the second computing node has failed.

19. The device according to any one of claims 11 to 18, characterized in that The instruction set includes a read operation instruction, and the processing unit is further configured to: When it is determined that the data corresponding to the read operation instruction exists in the area context of the redo area, the data corresponding to the read operation instruction is read from the area context of the redo area.

20. The device according to claims 11 to 19, characterized in that The processing unit is further configured to: When it is determined that the data corresponding to the read operation instruction does not exist in the area context of the redo area, the data corresponding to the read operation instruction is read from the memory node based on an indirect pointer and a data pointer, where the indirect pointer is used to point to the data pointer, and the data pointer is used to point to the storage location of the data corresponding to the read operation instruction in the memory node.

21. A computing device, characterized in that The computer comprises a processor coupled to a memory, wherein the processor is configured to store instructions. When the instructions are executed by the processor, the computer causes the computing device to perform the method according to any one of claims 1 to 10.

22. A computing device cluster, characterized in that: The system comprises at least one computing device, wherein the computing device comprises a processor coupled to a memory, and the processor is configured to store instructions. When the instructions are executed by the processor, the computing device cluster performs the method according to any one of claims 1 to 10.

23. A computer-readable storage medium having instructions stored thereon, characterized in that: When the instructions are executed, the computer is caused to perform the method according to any one of claims 1 to 10.

24. A computer program product comprising instructions, characterized in that: When the instructions are executed, the computer is caused to implement the method according to any one of claims 1 to 10.

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