Simplified implementation method for NR polar coding, and computer-readable storage medium

Abstract

A simplified implementation method for NR Polar coding and a computer-readable storage medium, relating to the field of communications. The method comprises: acquiring original information to be transmitted; on the basis of the original information, determining a bit sequence to be coded; storing said bit sequence according to a data type having a set bit length, so as to form a first array; and using a coding matrix to code said bit sequence so as to determine a code output sequence, comprising: acquiring each column vector in the coding matrix, and storing said column vectors according to the data type having the set bit length, so as to correspondingly form second arrays; storing the second arrays in a row sequence of the coding matrix so as to form a third array; and performing bit operation on the first array and the third array to determine the code output sequence, so as to perform corresponding processing prescribed by a protocol. Therefore, the present application reduces the complexity of coding operation, improves the coding efficiency and reduces memory resources required for coding.

Description

A simplified implementation method of NR Polar coding and computer-readable storage medium Technical Field

[0001] The present application relates to the field of communications, and in particular to a simplified implementation method of NR Polar coding and a computer-readable storage medium. Background Art

[0002] According to Section 5.3.1.2 of the 3GPP TS 38.212 standard, in the Polar coding process, information bits and check bits are filled into the selected subchannel according to the characteristic rules to generate the bit sequence u to be coded. The bit sequence u to be coded is a row vector with a maximum order of 1024. This row vector contains the information and check bit data and is the input vector for the coding operation. The coding matrix G N It is generated by the Kronecker product operation of the base matrix G2 and is a matrix of order 1024 at most. The bit sequence u to be encoded and the encoding matrix G N Multiply to get the encoded output sequence d.

[0003] When simulating NR Polar coding in software, the original solution to implement the above coding matrix operation is to use a two-dimensional array to store the coding matrix G N Considering that each element in can reach a maximum order of 1024, at least 1024 × 1024 elements must be stored. According to the matrix multiplication rules, the encoding matrix is ​​column-by-column multiplied by the row vector of the bit sequence to be encoded, u, and the remainder is calculated. The values ​​of each column element of the encoded output sequence d are calculated separately. According to the above calculation method, if a 1024-order encoding matrix is ​​used, 1024 integer arithmetic operations and 1024 integer additions are required for each column, resulting in 1024 × 1024 integer multiplications and additions required for the entire encoding calculation. This entire calculation consumes a large amount of memory and processor resources, resulting in low encoding efficiency. Summary of the Invention

[0004] The main technical problem solved by this application is to provide a simplified implementation method and computer-readable storage medium for NR Polar coding that does not require excessive consumption of memory and operator resources during the calculation process.

[0005] According to the first aspect, an embodiment provides a simplified implementation method of NR Polar coding, including:

[0006] Obtaining original information to be transmitted, determining a bit sequence to be encoded based on the original information, and storing the bit sequence to be encoded according to a data type with a set bit length to form a first array;

[0007] Encoding the to-be-encoded bit sequence using a coding matrix to determine a coded output sequence includes:

[0008] Obtain each column vector in the encoding matrix, and store each column vector according to the data type of the set bit length to form a corresponding second array;

[0009] storing each of the second arrays in the order of rows of the encoding matrix to form a third array;

[0010] A bit operation is performed on the first array and the third array to determine the coded output sequence, so as to perform corresponding processing specified by the protocol.

[0011] In one embodiment, storing the to-be-encoded bit sequence according to a data type of a set bit length to form a first array includes:

[0012] Get the number of bits of the data type with set bit length;

[0013] Extracting elements of the number of bits from the to-be-encoded bit sequence in sequence to form a plurality of first sequences;

[0014] The plurality of first sequences are stored in order to form a first array.

[0015] In one embodiment, storing each of the column vectors according to the data type of the set bit length to form a corresponding second array includes:

[0016] Obtain the number of bits of the data type with the set bit length;

[0017] extracting elements of the bit number from each column vector in the encoding matrix in sequence to form a plurality of second sequences;

[0018] The plurality of second sequences are stored in order to form a corresponding second array.

[0019] In one embodiment, the third array is a two-dimensional array;

[0020] The storing each of the second arrays in the order of rows of the encoding matrix to form a third array includes:

[0021] Get the second array corresponding to each column;

[0022] Each second array is stored in the order of rows of the encoding matrix to form the two-dimensional array.

[0023] In one embodiment, performing a bitwise operation on the first array and the third array to determine the coded output sequence includes:

[0024] Performing AND operations on a plurality of first sequences of the first array and a plurality of second sequences of the second array, respectively, to obtain a plurality of corresponding AND operation values;

[0025] Performing an exclusive-OR operation on the plurality of AND operation values ​​to correspondingly determine an inner product operation result between the to-be-encoded bit sequence and each column vector of the encoding matrix;

[0026] The coded output sequence is determined according to the inner product operation result.

[0027] In one embodiment, performing an exclusive-OR operation on the plurality of AND operation values ​​to correspondingly determine an inner product operation result between the to-be-encoded bit sequence and each column vector of the encoding matrix includes:

[0028] performing an XOR operation on the plurality of AND operation values ​​to determine a first XOR result;

[0029] Starting from the first XOR result, right shifting one bit at a time to determine a first right-shifted value; performing an XOR operation on the first right-shifted value and the first XOR result to update the first XOR result;

[0030] Each time the first XOR result is updated, the first right-shifted value is right-shifted by one bit to update the first right-shifted value, until each bit in the first XOR result participates in the XOR operation on the lowest bit, then the calculation is stopped and the XOR operation is completed;

[0031] The value of the least significant bit of the first XOR result after the XOR operation is completed is obtained, where the value of the least significant bit is the result of the inner product operation of the to-be-encoded bit sequence and the corresponding encoding matrix column vector.

[0032] In one embodiment, performing an exclusive-OR operation on the plurality of AND operation values ​​to correspondingly determine an inner product operation result between the to-be-encoded bit sequence and each column vector of the encoding matrix includes:

[0033] performing an XOR operation on the plurality of operation values ​​to determine a second XOR result;

[0034] Starting from the second XOR result, left shifting one bit at a time to determine a first left-shifted value; performing an XOR operation on the first left-shifted value and the second XOR result to update the second XOR result;

[0035] Each time the second XOR result is updated, the first left shift value is shifted left by one bit to update the first left shift value, until each bit in the second XOR result participates in the XOR operation on the highest bit, then the calculation is stopped and the XOR operation is completed;

[0036] The value of the most significant bit of the second XOR result of the XOR operation is obtained, where the most significant bit data is the result of the inner product operation of the to-be-encoded bit sequence and the corresponding encoding matrix column vector.

[0037] In one embodiment, the data type of the set bit length includes a 1-byte character type, a 2-byte short integer type, a 4-byte integer type, or a 4-byte long integer type.

[0038] In one embodiment, the number is a value obtained by dividing the order of the encoding matrix by the number of bits.

[0039] According to a second aspect, an embodiment provides a computer-readable storage medium, on which a program is stored. The program can be executed by a processor to implement the method described in any one of the above embodiments.

[0040] According to a simplified implementation method of NR Polar coding and a computer-readable storage medium of the above embodiment, in this method, the original information to be transmitted is obtained, the bit sequence to be encoded is determined based on the original information, and the bit sequence to be encoded is stored according to the data of the set bit length to form a first array. The coding matrix is ​​used to encode the bit sequence to determine the coding output sequence, wherein each column vector in the coding matrix is ​​stored according to the data type of the set bit length, thereby correspondingly forming a second array, and each second array is stored in the order of the rows of the coding matrix to form a third array. Finally, bit operations are performed on the first array and the third array. The coding matrix and the bit sequence to be encoded of the present application are stored in a bit manner, and the coding matrix and the bit sequence to be encoded are stored using the data type of the set bit length, which can make full use of memory resources and reduce the memory resources required for encoding. At the same time, the present application uses bit operations to replace arithmetic operations in coding matrix operations, which reduces the complexity of coding operations and improves coding efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] FIG1 is a schematic diagram of an existing Polar coding matrix storage mode;

[0042] FIG2 is a schematic diagram of a single multiplication operation of an existing Polar coding matrix;

[0043] FIG3 is a general flow chart of a simplified implementation method of NR Polar coding according to an embodiment;

[0044] FIG4 is a flowchart of step S100 of a simplified implementation method of NR Polar coding according to an embodiment;

[0045] FIG5 is a flowchart of step S200 of a simplified implementation method of NR Polar coding according to an embodiment;

[0046] FIG6 is a flowchart of step S210 of a simplified implementation method of NR Polar coding according to an embodiment;

[0047] FIG7 is a schematic diagram of a Polar coding matrix storage mode according to an embodiment;

[0048] FIG8 is a flowchart of step S230 of a simplified implementation method of NR Polar coding according to an embodiment;

[0049] FIG9 is a flowchart of step S232 of a simplified implementation method of NR Polar coding according to an embodiment;

[0050] FIG10 is a flowchart of step S232 of a simplified implementation method of NR Polar coding according to another embodiment;

[0051] FIG11 is a schematic diagram of an assembly implementation of a simplified implementation method of NR Polar coding according to an embodiment. DETAILED DESCRIPTION

[0052] The present application is further described in detail below by means of specific embodiments in conjunction with the accompanying drawings. Similar elements in different embodiments are numbered with associated similar elements. In the following embodiments, many detailed descriptions are provided to enable the present application to be better understood. However, those skilled in the art will readily appreciate that some of the features may be omitted in different circumstances, or may be replaced by other elements, materials, or methods. In some cases, some operations related to the present application are not shown or described in the specification. This is to avoid the core portion of the present application being overwhelmed by excessive descriptions. For those skilled in the art, it is not necessary to describe these related operations in detail. They can fully understand the related operations based on the description in the specification and the general technical knowledge in the art.

[0053] In addition, the features, operations, or characteristics described in the specification may be combined in any appropriate manner to form various embodiments. Furthermore, the steps or actions in the method description may be reordered or adjusted in a manner readily apparent to those skilled in the art. Therefore, the various sequences in the specification and drawings are provided solely for the purpose of clearly describing a particular embodiment and are not intended to be mandatory, unless otherwise specified.

[0054] Component numbers used herein, such as "first" and "second," are used solely to distinguish the components being described and do not convey any sequential or technical meaning. References to "connection" and "coupling" herein, unless otherwise specified, include both direct and indirect connections (couplings).

[0055] To improve communication reliability, the NR protocol introduces Polar coding as a coding method for some physical layer channels. According to Section 5.3.1.2 of the 3GPP TS 38.212 standard, the Polar coding used in the NR protocol uses a base matrix generated by a Kronecker Power operation to perform coding calculations on the coding matrix. The coding matrix can be up to a 1024-order square matrix. However, when using software simulation to analyze the NR physical layer link, the Polar coding matrix operation requires calculating up to 1024-order matrix multiplication operations, which consumes more memory and operator resources, and the coding operation efficiency is low.

[0056] When the above method is specifically applied to memory resource usage, the Polar coding matrix storage mode under the original scheme is shown in Figure 1. Assuming that a 4-byte (32-bit) integer is used to store matrix operations, since Section 5.3.1.2 of the 3GPP TS 38.212 standard stipulates that Polar coding matrix operations are defined in the GF(2) valid domain, this means that the data reference range is binary, 0 or 1. Therefore, each integer actually has only one bit to store valid data, resulting in obvious waste of storage resources.

[0057] When the above method is applied to the encoding operation process, only a single bit in the register is effectively operated each time an arithmetic operation is performed. As shown in Figure 2, there is also obvious waste of computing resources in each arithmetic multiplication operation. In Figure 2, x is used to represent the encoding matrix G. N , y represents the element data in the encoded bit sequence u, and z represents the element data in the encoded output sequence d. If we quantitatively analyze the arithmetic multiplication in the original scheme, a typical assembly implementation for a single arithmetic multiplication is as follows: First, read the specific element in the to-be-encoded bit sequence u from the memory into the accumulator EAX; then, read the encoding matrix G from the memory N The characteristic elements in are read into the general register EDX; finally, the arithmetic logic unit ALU performs arithmetic multiplication and the result is stored in the accumulator EAX: Z0Z1Z2……Z 31 Without considering efficiency optimization such as pipelining technology, a single arithmetic multiplication may require three CPU instruction cycles to complete. In this case, the operation consumes more memory and operator resources, resulting in low coding efficiency.

[0058] Based on the above, this application provides a simplified implementation method for NR Polar coding. This method utilizes the characteristics of computer memory to store the Polar matrix bit by bit. Compared to the original solution of storing the coding matrix element individually, this method saves a large amount of memory resources. Furthermore, this application utilizes the characteristics of computer operators to convert Polar coding matrix operations from arithmetic operations to bit operations, reducing the computational complexity of coding matrix operations. This is explained in detail below.

[0059] Referring to FIG3 , an embodiment provides a simplified method for NR Polar encoding, including the following steps.

[0060] Step S100: obtaining original information to be transmitted, determining a bit sequence u to be encoded according to the original information, and storing the bit sequence u to be encoded according to a data type with a set bit length to form a first array.

[0061] In one embodiment, raw information refers to unencoded data or messages to be transmitted in a communication system. This data may be user-generated information, sensor-collected data, or other raw information generated by applications. In a communication system, raw information is typically a bit sequence in digital or binary form, representing the content that a specific application or user wants to convey. Raw information may include voice, images, text, sensor measurement data, etc. The bit sequence u to be encoded is determined based on this raw information to be transmitted.

[0062] In one embodiment, Section 5.3.1.2 of the 3GPP TS 38.212 standard specifies that the Polar coding matrix operation is defined in the GF(2) valid domain, and the bit sequence u to be coded and the coding matrix G N The elements of G have only two possibilities (0 or 1), so a single bit can be used to store the encoded bit sequence u and the encoding matrix G N At the same time, in order to facilitate the description and implementation of bit operations using high-level computer languages, it is necessary to treat the encoding bit sequence u and the encoding matrix G N Each element value in is packaged as a certain data type.

[0063] Referring to FIG. 4 , in one embodiment, when the bit sequence u to be encoded is stored according to a data type of a set bit length to form a first array in step S100 , the following steps are also included.

[0064] Step S110: Obtain the number of bits of the data type with a set bit length.

[0065] In one embodiment, the number of CPU register bits in different computers is different, and a data type with a set bit length is used to store the bit sequence u to be encoded and the encoding matrix G according to the number of bits of the data type. N The bit length of the data type can be selected from the typical CPU register bit number and its factors. In a 32-bit register, you can choose a 1-byte character type (char), a 2-byte short integer type (short), a 4-byte integer type (int), or a 4-byte long integer type (long). A 1-byte character type includes 8 bits, a 2-byte short integer type includes 16 bits, a 4-byte integer type (int) includes 32 bits, and a 4-byte long integer type (long) includes 32 bits. Considering the encoding matrix G specified by the protocol, N The minimum is a 32-order square matrix, so the bit sequence u to be encoded and the encoding matrix G in this application are N A 4-byte integer (int), occupying 32 bits, is selected as the storage unit. Since 1 byte of storage space is equivalent to 8 bits, using a 1-byte character type reduces the required storage space by at least 1 / 8. The specific amount of storage space saved varies depending on the data type. In actual implementation, any of the above data types can be used as the storage unit.

[0066] Step S120: extracting bit elements from the bit sequence u to be encoded in sequence to form a plurality of first sequences.

[0067] In one embodiment, the bit sequence u to be encoded is a row vector. Taking a byte integer data type with 32 bits as an example, every 32 elements in the bit sequence u to be encoded are packed as a first sequence. Since the bit sequence u to be encoded includes at most 1024 orders, the bit sequence u to be encoded includes 1024 / 32=32 first sequences.

[0068] Step S130: Store a plurality of first sequences in order to form a first array.

[0069] In one embodiment, taking a 128-order to-be-encoded bit sequence u, with an integer data type as an example, the elements in columns 1-32 of the to-be-encoded bit sequence u are packed to form a first first sequence, the elements in columns 33-64 of the to-be-encoded bit sequence u are packed to form a second first sequence, the elements in columns 65-96 of the to-be-encoded bit sequence u are packed to form a third first sequence, and the elements in columns 97-128 of the to-be-encoded bit sequence u are packed to form a fourth first sequence. These four sequences are stored in ascending order according to the column number of the to-be-encoded bit sequence u, thereby forming a first array with one row and four columns. Similar packaging is used for to-be-encoded bit sequences u of different orders.

[0070] Step S200: Using the encoding matrix G N The bit sequence u to be encoded is encoded to determine the encoded output sequence d.

[0071] Please refer to FIG5 , in one embodiment, in step S200, the encoding matrix G is used. N When encoding the to-be-encoded bit sequence u to determine the encoded output sequence d, the following steps are also included.

[0072] Step S210: Obtain each column vector in the encoding matrix, and store each column vector according to a data type of a set bit length to form a corresponding second array.

[0073] Please refer to Figure 6. In one embodiment, when executing step S210 to obtain each column vector in the encoding matrix and storing each column vector according to a data type with a set bit length to form a corresponding second array, the following steps are also included.

[0074] Step S211: Obtain the number of bits of the data type with a set bit length.

[0075] In one embodiment, the encoding matrix G N The data type in adopts the same data type as the bit sequence u to be encoded.

[0076] Step S212: extracting the elements of the bit number from each column vector in sequence to form a plurality of second sequences.

[0077] In one embodiment, the encoding matrix G N Is a square matrix of set order, encoding matrix G N The maximum order is 1024, that is, the maximum matrix is ​​1024 rows × 1024 columns. N Is a square matrix of set order, then the square matrix includes row vectors of set order and column vectors of set order. Taking the 4-byte integer data type of 32 bits as an example, first encode the matrix G N Each column vector in the sequence packs 32 elements as a second sequence, since the encoding matrix G N At most, it includes 1024 orders, so each column vector includes 1024 / 32=32 second sequences. N Each integer stores 32 consecutive elements in a single column, thereby realizing the encoding matrix G N Each element value in occupies only 1 bit of storage space.

[0078] Step S213: Store the plurality of second sequences in order to form a corresponding second array.

[0079] In one embodiment, the second sequence in each column vector is stored sequentially to form a second array. When storing using a data type with a set bit length, the storage is sequential, so when storing using a data type with a set bit length, the row and column information in the matrix is ​​naturally included.

[0080] Step S220: Each second array is encoded according to the encoding matrix G N The rows are stored sequentially to form a third array.

[0081] In one embodiment, please refer to FIG7 , after each column vector is stored in a second sequence to form a second array, each second array is then stored in a second sequence according to the encoding matrix G N The rows are stored in order, thereby forming a third array, which is a two-dimensional array.

[0082] Similarly, the encoding matrix G N For example, the 128-order encoding matrix includes 128 rows of row vectors and 128 columns of column vectors. The elements of the 1st to 32nd rows of the 1st column are packed to form the first second sequence, the elements of the 33rd to 64th rows of the 1st column are packed to form the second second sequence, the elements of the 65th to 96th rows of the 1st column are packed to form the third second sequence, and the elements of the 97th to 128th rows of the 1st column are packed to form the fourth second sequence. The four sequences are stored in ascending order according to the row number of the encoding matrix to form the first second array. Similarly, the column vectors of each column are packed to form the second array corresponding to each column vector. After each column is packed and stored, the second array corresponding to each column is stored according to the encoding matrix G. N The rows of the vectors are stored sequentially, thus forming a two-dimensional array of 4 rows and 128 columns. After packing each column vector (the 128 elements of each column vector are packed into 4 packages in groups of 32), the encoding matrix G N The number of columns remains unchanged, while the number of rows is reduced to 1 / 32 of the original number. However, the data is stored in a column-first manner, i.e., column 0 and row 0 are stored sequentially (column number first, row number last), recorded as [0, 0], [0, 1], [0, 2], [0, 3], [1, 0], [1, 1], [1, 2], [1, 3], [2, 0]... Those skilled in the art will clearly understand that this two-dimensional array is not stored in a matrix in a computer, but rather is stored with each second sequence placed in the corresponding order.

[0083] Step S230: performing bitwise operations on the first array and the third array to determine the coded output sequence d, so as to perform corresponding processing specified by the protocol.

[0084] In one embodiment, the present application performs encoding matrix G N When performing operations, bit operations are used instead of arithmetic operations, where bitwise AND operations are used instead of integer multiplications. The encoding matrix G N The summation of the multiplication results is replaced by a shift operation and a bitwise XOR operation.

[0085] Referring to FIG. 8 , in one embodiment, when performing step S230 to perform bitwise operation on the first array and the third array to determine the coded output sequence d for channel transmission, the following steps are also included.

[0086] Step S231 : performing an AND operation on a plurality of first sequences of the first array and a plurality of second sequences of the second array respectively, to obtain a plurality of corresponding AND operation values.

[0087] In one embodiment, the first sequence of the first array and the second sequence of the second array have the same number of elements, and the first sequence of the first array is ANDed with each second sequence of the second array one by one.

[0088] In the case of a 128-order bit sequence u to be encoded and a coding matrix G N , when the data type is set to integer, for example, the 128-order bit sequence to be encoded u and the 128-order encoding matrix G N Corresponding to the first array of 1 row and 4 columns and the third array of 4 rows and 128 columns, the first array and the third array are ANDed according to the matrix multiplication operation rule, that is, the first sequence in the first array of 1 row and 4 columns is ANDed with the second sequence in the third array of 4 rows and 128 columns in a bitwise manner to obtain a number of corresponding ANDed values.

[0089] It should be noted that, since the third data is composed of the second data, and the second data is composed of the second sequence, the first sequences of the first array are respectively ANDed with the second sequences of the second array, that is, the first sequences in the first array are ANDed with the second sequences in the third array. N In the example where the data type is set to integer, there are 128 second arrays in the third array, corresponding to 128 columns, and there are 4 second sequences in the second array, corresponding to 4 rows, so the third array corresponds to 4 rows and 128 columns. The 4 first sequences in the first array are each bitwise ANDed with the 4 second sequences in the second array, resulting in 4 AND results. Since the third array contains 128 second sequences, the same bitwise AND operation is performed on all 128 second sequences in the third array, resulting in a total of 128×4 AND results.

[0090] Step S232: Perform an XOR operation on several AND operation values ​​to determine the corresponding bit sequence u to be encoded and the encoding matrix G N The result of the inner product operation of each column vector.

[0091] 9, in one embodiment, in step S232, an XOR operation is performed on a plurality of AND operation values ​​to determine the corresponding bit sequence u to be encoded and the encoding matrix G N The inner product calculation results of each column vector also include the following steps.

[0092] Step S232a: Perform an XOR operation on a plurality of AND operation values ​​to determine a first XOR result.

[0093] In one embodiment, each first sequence is subjected to a bitwise AND operation with the corresponding second sequence, and the result of the AND operation is XORed, thereby obtaining a corresponding first XOR result.

[0094] It should be noted that the XOR operation here refers to performing a bitwise AND operation on the second sequence corresponding to each column in the third array and each first sequence in the first array to obtain an AND operation value whose length is equal to the length of the first sequence.

[0095] In the 128-order bit sequence u to be encoded, the encoding matrix G N In the example of a 4-byte integer with an order of 128 and a set data type of 32 bits, the first array is an array of 1 row and 4 columns, a row includes 4 first sequences, each first sequence includes 32 elements, the third array is an array of 4 rows and 128 columns, a column includes 4 second sequences, each second sequence also includes 32 elements, and the first sequence of a row in the first array is bitwise ANDed with the second sequence of a column in the third array to obtain the AND operation value corresponding to each column, that is, 4 32-bit AND operation values.

[0096] The exclusive OR operation refers to sequentially performing exclusive OR operations on the four 32-bit AND operation values ​​in each column of the third array. That is, the 0th bit of the first 32-bit AND operation value in each column is exclusive ORed with the 0th bit of the second AND operation value. The obtained result is exclusive ORed with the 0th bit of the third 32-bit AND operation value. The obtained result is exclusive ORed with the 0th bit of the fourth 32-bit AND operation value, thereby obtaining the result corresponding to the 0th bit of the first exclusive OR result. This process is repeated in this way to calculate the first exclusive OR result for each column.

[0097] Step S232b: Update the first XOR result.

[0098] In one embodiment, after determining the first XOR result, the first XOR result is right-shifted one bit at a time. The first right-shift value is determined during the first right shift, and the first right-shift value is XORed with the first XOR result again to update the first XOR result. After each update of the first XOR result, the first right-shift value is right-shifted one bit to update the first right-shift value, until each bit in the first XOR result participates in the XOR operation on the lowest bit, then the calculation is stopped to complete the XOR operation.

[0099] Step S232c: Obtain the value of the least significant bit of the first XOR result after the XOR operation is completed.

[0100] In one embodiment, the value of the lowest bit is the value of the bit sequence to be encoded u and the corresponding encoding matrix G N The result of the inner product operation of column vectors.

[0101] For example, if the first XOR result of the XOR operation of the bitwise AND operation on each first sequence and the corresponding second sequence is 1010, then 1010 is first right-shifted by one position to obtain a first right-shifted value of 0101, and 1010 and 0101 are XORed again to obtain 1111, and 1111 is updated as the first XOR result; at this time, the first right-shifted value is right-shifted again to 0010, and 1111 and 0010 are XORed again to obtain 1101, and 1101 is updated as the first XOR result again; at this time, the first right-shifted value is right-shifted again by 0001, and 1101 and 0001 are XORed again to obtain 1100. At this time, each bit in the first right-shifted value 0101 participates in the XOR operation, and the calculation is stopped. At this time, the lowest bit 0 in 1100 is the bit sequence u to be encoded and the corresponding encoding matrix G N The result of the inner product operation of column vectors.

[0102] Please refer to FIG10 , in another embodiment, in step S232 , an XOR operation is performed on a plurality of AND operation values ​​to determine the corresponding bit sequence u to be encoded and the encoding matrix G N The inner product calculation results of each column vector also include the following steps.

[0103] Step S232A: Perform an XOR operation on a plurality of AND operation values ​​to determine a second XOR result.

[0104] In one embodiment, each first sequence is subjected to a bitwise AND operation with the corresponding second sequence, and the result of the AND operation is XORed, thereby obtaining a corresponding second XOR result.

[0105] It should be noted that the AND operation value and the second XOR result in step S232A are calculated in the same manner as in step S232a, and are not described again here.

[0106] Step S232B: Update the second XOR result.

[0107] In one embodiment, after determining the second XOR result, the second XOR result begins to be left-shifted, one bit at a time. During the first left shift, a first left-shift value is determined, and the first left-shift value is XORed with the second XOR result again, thereby updating the second XOR result. After each update of the second XOR result, the first left-shift value is left-shifted one bit, thereby updating the first left-shift value, until each bit in the second XOR result participates in the XOR operation on the highest bit, then the calculation is stopped and the XOR operation is completed.

[0108] Step S232C: Obtain the value of the most significant bit of the second XOR result of the XOR operation.

[0109] In one embodiment, the value of the highest bit is the value of the bit sequence to be encoded u and the corresponding encoding matrix G N The result of the inner product operation of column vectors.

[0110] For example, if the second XOR result of the XOR operation value of the bitwise AND operation on each first sequence and the corresponding second sequence is 1010, then 1010 is first shifted left by one bit to obtain a first left-shifted value of 0100, and 1010 and 0100 are XORed again to obtain 1110, and 1110 is updated as the second XOR result; at this time, the first left-shifted value is left-shifted to 1000, and 1110 and 1000 are XORed again to obtain 0110, and 0110 is updated as the second XOR result again; at this time, the first left-shifted value is left-shifted again by 0000, and 0110 and 0000 are XORed again to obtain 0110. At this time, each bit in the first left-shifted value 0100 participates in the XOR operation, and the calculation is stopped. At this time, the highest bit 0 in 0110 is the bit sequence u to be encoded and the corresponding encoding matrix G N The result of the inner product operation of column vectors.

[0111] Step S233: Determine the coded output sequence according to each inner product operation result.

[0112] In one embodiment, in the case of a 128-order bit sequence u to be encoded and a coding matrix G N In the example of order 128, there are 128 first XOR results calculated. After updating these 128 XOR results, 128 inner product operation results are obtained. These 128 inner product operation results are arranged in the column order of the third array to obtain a 128-order encoding output sequence.

[0113] In one embodiment, the original information is the starting point of communication in the communication system. Through encoding and transmission, it is ensured that the information can be effectively transmitted in the communication system. The bit sequence u to be encoded corresponding to the original information to be transmitted passes through the encoding matrix GN After encoding, the coded output sequence d is formed. The coded output sequence d undergoes a series of processing such as rate matching according to the NR protocol, and then is modulated and transmitted. The receiving end performs decoding operations to restore the original information.

[0114] A specific embodiment uses a 32-bit integer as a storage unit and uses a 1024-order coding matrix G N Encoding is taken as an example to illustrate the specific implementation method of encoding matrix operation.

[0115] The bit sequence u to be encoded and the encoding matrix G N Each column element is stored in 32 integer variables, and these integer variables are bitwise ANDed one by one, and all the integer variables obtained by the bitwise ANDed operation of the column are extracted through arithmetic shifting, and the bitwise XOR operation is performed on the above-extracted bit data. The result of this operation is used as the column element data corresponding to the encoding output sequence. Its possible assembly implementation is shown in Figure 11. This application implements arithmetic multiplication with bitwise AND operation, making full use of the CPU's computing resources, reducing the complexity of encoding operations, and improving encoding efficiency. For a computer system with a 32-bit processor, if a 32-bit integer is used as a storage unit, this application combines 32 arithmetic multiplications into a single bitwise AND operation. Taking into account the consumption of fetching data from the memory, it can be completed in only 3 CPU instruction cycles, reducing the computing time consumption to at least 1 / 32 of the original.

[0116] Those skilled in the art will appreciate that all or part of the functions of the various methods in the above embodiments can be implemented by hardware or by computer program. When all or part of the functions in the above embodiments are implemented by computer program, the program can be stored in a computer-readable storage medium, and the storage medium can include: read-only memory, random access memory, disk, optical disk, hard disk, etc., and the program is executed by a computer to implement the above functions. For example, the program is stored in the memory of the device, and when the program in the memory is executed by the processor, all or part of the above functions can be implemented. In addition, when all or part of the functions in the above embodiments are implemented by computer program, the program can also be stored in a storage medium such as a server, another computer, disk, optical disk, flash disk or mobile hard disk, and saved in the memory of the local device by downloading or copying, or the system of the local device is updated. When the program in the memory is executed by the processor, all or part of the functions in the above embodiments can be implemented.

[0117] The above specific examples are used to illustrate the present application, which is only used to help understand the present application and is not intended to limit the present application. For those skilled in the art of the present application, based on the concept of the present application, they can also make some simple deductions, modifications or substitutions.

Claims

1. A simplified implementation method for NR Polar coding, characterized in that: include: Obtaining original information to be transmitted, determining a bit sequence to be encoded based on the original information, and storing the bit sequence to be encoded according to a data type with a set bit length to form a first array; wherein the data type with the set bit length is determined based on the number of register bits; Encoding the to-be-encoded bit sequence using a coding matrix to determine a coded output sequence includes: Obtain each column vector in the encoding matrix, and store each column vector according to the data type of the set bit length to form a corresponding second array; storing each of the second arrays in the order of rows of the encoding matrix to form a third array; A bit operation is performed on the first array and the third array to determine the coded output sequence, so as to perform corresponding processing specified by the protocol.

2. The simplified implementation method for NR Polar coding according to claim 1, wherein: The step of storing the to-be-encoded bit sequence according to a data type having a set bit length to form a first array includes: Get the number of bits of the data type with set bit length; Extracting elements of the number of bits from the to-be-encoded bit sequence in sequence to form a plurality of first sequences; The plurality of first sequences are stored in order to form a first array.

3. The simplified implementation method for NR Polar coding according to claim 2, wherein: The step of storing each of the column vectors according to the data type of the set bit length to form a corresponding second array includes: Obtain the number of bits of the data type with the set bit length; extracting elements of the bit number from each column vector in the encoding matrix in sequence to form a plurality of second sequences; The plurality of second sequences are stored in order to form a corresponding second array.

4. The simplified implementation method for NR Polar coding according to claim 3, wherein: The third array is a two-dimensional array; The storing each of the second arrays in the order of rows of the encoding matrix to form a third array includes: Get the second array corresponding to each column; Each second array is stored in the order of rows of the encoding matrix to form the two-dimensional array.

5. The simplified implementation method of NR Polar coding according to claim 4, characterized in that The performing bitwise operation on the first array and the third array to determine the coded output sequence includes: Performing AND operations on a plurality of first sequences of the first array and a plurality of second sequences of the second array, respectively, to obtain a plurality of corresponding AND operation values; Performing an exclusive-OR operation on the plurality of AND operation values to correspondingly determine an inner product operation result between the to-be-encoded bit sequence and each column vector of the encoding matrix; The coded output sequence is determined according to the inner product operation result.

6. The simplified implementation method for NR Polar coding according to claim 5, wherein: The performing an exclusive OR operation on the plurality of AND operation values to correspondingly determine an inner product operation result between the to-be-encoded bit sequence and each column vector of the encoding matrix includes: performing an XOR operation on the plurality of AND operation values to determine a first XOR result; Starting from the first XOR result, right shifting one bit at a time to determine a first right-shifted value; performing an XOR operation on the first right-shifted value and the first XOR result to update the first XOR result; Each time the first XOR result is updated, the first right-shifted value is right-shifted by one bit to update the first right-shifted value, until each bit in the first XOR result participates in the XOR operation on the lowest bit, then the calculation is stopped and the XOR operation is completed; The value of the least significant bit of the first XOR result after the XOR operation is completed is obtained, where the value of the least significant bit is the result of the inner product operation of the to-be-encoded bit sequence and the corresponding encoding matrix column vector.

7. The simplified implementation method for NR Polar coding according to claim 5, wherein: The performing an exclusive OR operation on the plurality of AND operation values to correspondingly determine an inner product operation result between the to-be-encoded bit sequence and each column vector of the encoding matrix includes: performing an XOR operation on the plurality of operation values to determine a second XOR result; Starting from the second XOR result, left shifting one bit at a time to determine a first left-shifted value; performing an XOR operation on the first left-shifted value and the second XOR result to update the second XOR result; Each time the second XOR result is updated, the first left shift value is shifted left by one bit to update the first left shift value, until each bit in the second XOR result participates in the XOR operation on the highest bit, then the calculation is stopped and the XOR operation is completed; The value of the most significant bit of the second XOR result of the XOR operation is obtained, where the most significant bit data is the result of the inner product operation of the to-be-encoded bit sequence and the corresponding encoding matrix column vector.

8. The simplified implementation method of NR Polar coding according to any one of claims 1 to 3, wherein: The data type of the set bit length includes a 1-byte character type, a 2-byte short integer type, a 4-byte integer type or a 4-byte long integer type.

9. The simplified implementation method for NR Polar coding according to any one of claims 2 to 7, wherein: The number is a value obtained by dividing the order of the encoding matrix by the number of bits.

10. A computer-readable storage medium, characterized in that: The medium stores a program, which can be executed by a processor to implement the method according to any one of claims 1 to 9.

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