Imaging circuitry and method for operating an imaging circuitry

Abstract

The present disclosure generally pertains to imaging circuitry including: a first semiconductor layer including: a photodiode; a global shutter memory node for a global shutter mode; and a first transfer gate coupled between the photodiode and the global shutter memory node; and a second transfer gate coupled between the global shutter memory node and a pixel amplifier in a second semiconductor layer; the second semiconductor layer including the pixel amplifier; and a third semiconductor layer including analog to digital conversion circuitry.

Description

[0001] IMAGING CIRCUITRY AND METHOD FOR OPERATING AN

[0002] IMAGING CIRCUITRY

[0003] TECHNICAL FIELD

[0004] The present disclosure generally pertains to imaging circuitry and a method for operating imaging circuitry in the field of charge domain global / rolling shutter operation.

[0005] TECHNICAL BACKGROUND

[0006] Generally, global shutter operation for image sensors is known. In such an operation, an exposure of each pixel row is kept (roughly) identical for each pixel row and a readout for each row is delayed following a rolling readout where a pixel amplifier acts as a buffer of charge before readout is carried out in voltage domain.

[0007] A distinction may be drawn between charge domain global shutter (CD-GS; also called floating diffusion global shutter, FD-GS), and voltage domain global shutter (VD-GS). In charge domain global shutter, readout may happen in charges domain. In voltage domain global shutter, readout may happen in voltage domain.

[0008] Also, correlated double sampling (CDS) is known as sampling a signal two times for a differential measurement and, by subtracting the two measurements, remove all correlated noises that appear in the same fashion in each measurement.

[0009] Although there exist techniques for global shutter operation, it is generally desirable to provide imaging circuitry and a method for operating imaging circuitry.

[0010] SUMMARY

[0011] According to a first aspect, the disclosure provides imaging circuitry comprising: a first semiconductor layer including: a photodiode; a global shutter memory node for a global shutter mode; and a first transfer gate coupled between the photodiode and the global shutter memory node; and a second transfer gate coupled between the global shutter memory node and a pixel amplifier in a second semiconductor layer; the second semiconductor layer including the pixel amplifier; and a third semiconductor layer including analog to digital conversion circuitry. According to a second aspect, the disclosure provides a method for operating imaging circuitry, the imaging circuitry comprising: a first semiconductor layer including: a photodiode; a global shutter memory node for a global shutter mode; and a first transfer gate coupled between the photodiode and the global shutter memory node; and a second transfer gate coupled between the global shutter memory node and a pixel amplifier in a second semiconductor layer; the second semiconductor layer including the pixel amplifier; and a third semiconductor layer including analog to digital conversion circuitry, the method comprising: carrying out the global shutter mode or a rolling shutter mode based on a predetermined signaling sequence.

[0012] Further aspects are set forth in the dependent claims, the drawings and the following description.

[0013] BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Embodiments are explained by way of example with respect to the accompanying drawings, in which:

[0015] Fig. 1 depicts an image sensor configured for rolling shutter and that can also be configured for charge domain global shutter (without capability of correlated double sampling, in some embodiments), wherein Fig. la depicts the sensor as a circuit diagram and Fig. lb depicts how the sensor is stacked;

[0016] Fig. 2 depicts a pixel circuit configured for charge domain global shutter which has also capabilities for correlated double sampling;

[0017] Fig. 3 depicts an image sensor configured for voltage domain global shutter, wherein Fig. 3a depicts the sensor as a circuit diagram and Fig. 3b depicts how the sensor is stacked;

[0018] Fig. 4 depicts imaging circuitry according to the present disclosure for charge domain global shutter with capabilities for correlated double sampling (and high dynamic range, in some embodiments), wherein Fig. 4a depicts the sensor as a circuit diagram and Fig. 4b depicts how the sensor is stacked;

[0019] Fig. 5 depicts timing diagrams (Fig. 5a, 5b, 5c) for controlling the imaging circuitry of Fig. 4 to carry out a global shutter mode; Fig. 6 depicts timing diagrams (Fig. 6a, 6b, 6c) for controlling the imaging circuitry of Fig. 4 to carry out a rolling shutter mode;

[0020] Fig. 7 depicts a method for controlling an imaging circuitry according to the present disclosure;

[0021] Fig. 8 depicts a further method for controlling an imaging circuitry according to the present disclosure to carry out a rolling shutter mode; and

[0022] Fig. 9 depicts a further method for controlling an imaging circuitry according to the present disclosure to carry out correlated double sampling during a global shutter mode.

[0023] DETAILED DESCRIPTION OF EMBODIMENTS

[0024] Before a detailed description of the embodiments starting with Fig. 4 is given, general explanations are made.

[0025] Fig. 1 depicts an image sensor. In Fig. la, a circuit diagram of the image sensor is shown for a pixel 1. The image sensor includes a first wafer 2 and a second wafer 3 which are stacked (see also Fig. lb). The first wafer 2 includes a pixel circuit. It should be noted that a pinned photodiode PPD generates electric charges that are transferred, via a transfer gate TRG / Mr- into a memory node (floating diffusion) FDi. TRG and MTXrefer to the same device, wherein TRG stands for transfer gate and refers to a signal and Mrs stands for a mosfet transistor that is activated when TRG is high. A floating diffusion FDI holds charges for a readout. MFDG is configured to short FDI with FD2 when FDG is turned high. RST is a reset transistor configured to flush charges from PPD, FDI and FD2. MSF is a source follower configured as an amplifier in the pixel. MSEL is a selection transistor configured to connect the pixel to the readout circuitry when SEL is turned high.

[0026] The second wafer 3 includes an analog to digital conversion (ADC) circuit including a ramp generator and a comparator. Moreover, the second wafer 3 includes digital image signal processing (ISP) circuitry. The image sensor 1 is configured such that it can operate in a global shutter (GS) mode, i.e., bias each pixel row with the same value during readout.

[0027] As can be taken from Fig. lb., the wafers 2 and 3 are stacked, such that the pixels are provided on the first wafer 2 and such that they can be read out based on the ADC and ISP circuitry of the second wafer 3.

[0028] However, in the image sensor 1, no correlated double sampling (CDS) is possible in the global shutter mode, such that the pixel of the image sensor 1 has a high readout noise. This may be because, if there is no memory node, it may be impossible to have a global exposure (global shutter) while reading sequentially row by row and cancelling the noise coming from the reset phase per pixel. Also, pixel performance optimization may be limited due to other pixel transistors since if many transistors are too close to each other, they may add impurity to the silicon and limit a performance of the photodiode.

[0029] However, the image sensor 1 provides enough space on the second wafer, such that ISP circuitry can be implemented on the chip (instead of on another chip).

[0030] To allow for charge domain global shutter and CDS, an additional transfer gate and an additional memory node may be needed, whereas the additional memory node may be roughly as large as the PPD. Such a known pixel circuit 10 is shown in Fig. 2.

[0031] The pixel circuit 10 includes an additional memory node FDGS and an additional transfer gate Mrxi before the memory node FDi, thereby enabling CDS.

[0032] However, such a pixel has been recognized to be rather large and thus, not suitable for small pitch production.

[0033] In contrast to the charge domain approach discussed under reference of Figs. 1 and 2, a voltage domain approach is shown in Fig. 3. Fig. 3a depicts a circuit diagram of a pixel provided on a first wafer 20 and of a readout circuit provided on a second wafer 21.

[0034] As can be taken from Fig. 3b, the second wafer 21 includes a CDS circuit and an ADC circuit. Hence, such an implementation leaves no space for ISP (Image Signal Processing) circuitry. Also, a readout noise depends on a capacitor size, such that such an implementation is challenging to scale.

[0035] When enabling voltage domain GS with CDS, the readout noise may depend on the capacitor size. Also CDS capacitors may be directly exposed to light which has been recognized as not desirable. Some embodiments of the disclosure may solve or alleviate these problems.

[0036] Generally, for a charge domain global shutter (CD-GS; also known as floating diffusion global shutter), noise expressed in electrons may be determined as follows:

[0037] On the other hand, for voltage domain global shutter (VD-GS), noise expressed in Volts may be determined as follows:

[0038] In these equations, k refers to Boltzman’s constant, T is the temperature in Kelvin, C is the capacitance at the node where the noise is calculated, q is the electron charge. While in the charge domain, the capacitance is in the numerator of the above expression, it is in the denominator of the voltage domain expression. Accordingly, in the charge domain, the smaller the capacitor, the smaller the noise. The noise may be fully cancelled or almost fully cancelled with CDS. On the other hand, in the voltage domain, the smaller the capacitor, the higher the noise. Also, the noise may not be fully cancelled since sampling may introduce a new noise which may be uncorrelated.

[0039] Hence, it has been recognized that it is desirable to provide charge-domain global shutter imaging circuitry that is capable of CDS and which also gives the possibility to implement an on-chip image signal processing circuitry.

[0040] Therefore, some embodiments pertain to imaging circuitry comprising: a first semiconductor layer including: a photodiode; a global shutter memory node for a global shutter mode; and a first transfer gate coupled between the photodiode and the global shutter memory node; and a second transfer gate coupled between the global shutter memory node and a pixel amplifier in a second semiconductor layer; the second semiconductor layer including the pixel amplifier; and a third semiconductor layer including analog to digital conversion circuitry.

[0041] The imaging circuitry may include a single pixel or a pixel array and may thus be suitable as an image sensor. The respective semiconductor layers (e.g., wafers) may include any type of semiconductor, e.g., based on CMOS (complementary metal oxide semiconductor) technology, NMOS (n-type metal oxide semiconductor) technology, or the like. In some embodiments, a mixture of different semiconductor types may be used. For example, the first semiconductor layer may be based on CMOS technology and the second semiconductor layer may be based on NMOS technology. The present disclosure is not limited to any type of semiconductor layer. For example, a wafer may be such a layer, as stated above, the present disclosure is not limited in that regard. The semiconductor layers may be bonded together with electrical coupling, interconnections in or between the layer, or the like.

[0042] In the first semiconductor layer, a pixel circuit may be provided including a photodiode, a global shutter memory node, and two transfer gates. The first transfer gate may be coupled between the photodiode and the global shutter memory node. The second transfer gate may be coupled between the global shutter memory node and an amplifier in the second semiconductor layer.

[0043] For example, the circuit depicted in Fig. 2 may be distributed among the first and the second semiconductor layer, such that the second semiconductor layer may include a high dynamic range (HDR) circuit. Hence, the second semiconductor layer may include a pixel amplifier, as will be further discussed below.

[0044] Moreover, the third semiconductor layer may include an ADC for reading out the signal. As indicated above, in some embodiments, the first semiconductor layer is configured for correlated double sampling, as will be discussed below.

[0045] In some embodiments, the correlated double sampling is carried out based on the global shutter memory node and the photodiode, as will be discussed further below.

[0046] In some embodiments, the second semiconductor layer further includes a reset transistor and, optionally, a gain stage

[0047] In some embodiments, the third semiconductor layer further includes image signal processing circuitry. Hence, the ISP circuitry may be provided on the same chip as the pixel.

[0048] In some embodiments, the imaging circuitry is further configured to switch between the global shutter mode and a rolling shutter mode based on switching the first transfer gate.

[0049] For example, if the first transfer gate is kept high during an acquisition period, rolling shutter may be enabled, as will be discussed further below.

[0050] In some embodiments, the imaging circuitry is further configured to activate the global shutter mode by activating the first transfer gate with a predetermined signaling sequence, as will be discussed further below.

[0051] In some embodiments, the second semiconductor layer is configured for high dynamic range operation, as discussed herein.

[0052] In some embodiments the second semiconductor layer further includes at least one conversion gain stage.

[0053] In some embodiments, the second semiconductor layer is an NMOS semiconductor.

[0054] For example, only NMOS technology may be applied (and no PMOS technology), such that leakage may be reduced in the second semiconductor layer.

[0055] In some embodiments, the first semiconductor layer further includes optically sensitive devices. Thereby, the optically sensitive devices may be exposed to light and the other devices in the second and third semiconductor layer may be shielded from light.

[0056] In some embodiments, the rolling shutter mode is activated out based on switching on the first transfer gate for one acquisition period, as discussed herein.

[0057] Some embodiments pertain to a method for operating imaging circuitry, the imaging circuitry comprising: a first semiconductor layer including: a photodiode; a global shutter memory node for a global shutter mode; and a first transfer gate coupled between the photodiode and the global shutter memory node; and a second transfer gate coupled between the global shutter memory node and a pixel amplifier in a second semiconductor layer; the second semiconductor layer including the pixel amplifier; and a third semiconductor layer including analog to digital conversion circuitry, the method comprising: carrying out the global shutter mode or a rolling shutter mode based on a predetermined signaling sequence, as discussed herein.

[0058] In some embodiments, the rolling shutter mode is activated out based on switching on the first transfer gate for one acquisition period, as discussed herein. In some embodiments, the method further includes: carrying out correlated double sampling in the global shutter mode, as discussed herein. In some embodiments, correlated double sampling is carried out based on the global shutter memory node and the photodiode, as discussed herein. In some embodiments, the third semiconductor layer further includes image signal processing circuitry, as discussed herein. In some embodiments, the second semiconductor layer is configured for high dynamic range operation, as discussed herein. In some embodiments, the second semiconductor layer further includes at least one conversion gain stage, as discussed herein. In some embodiments, the second semiconductor layer is an NMOS semiconductor, as discussed herein. In some embodiments, the first semiconductor layer further includes optically sensitive devices, as discussed herein.

[0059] The methods as described herein are also implemented in some embodiments as a computer program causing a computer and / or a processor to perform the method, when being carried out on the computer and / or processor. In some embodiments, also a non-transitory computer-readable recording medium is provided that stores therein a computer program product, which, when executed by a processor, such as the processor described above, causes the methods described herein to be performed.

[0060] Returning to Fig. 4, there is depicted a schematic diagram of imaging circuitry 30 according to the present disclosure. The imaging circuitry 30 includes three semiconductor layers (wafers) 31, 32 and 33.

[0061] The first semiconductor layer 31 includes a pixel circuit including a photodiode PPD that is coupled to a first transfer gate TRG1 and to an overflow gate OFG, wherein the overflow gate OFG is further supplied with a pixel voltage PIX_VDD. The transfer gate TRG1 is coupled to a global shutter memory node FDGS and to a second transfer gate TRG2.

[0062] In particular, the source of the first transfer gate TRG1 is coupled with the output of the photodiode PPD and the drain is coupled with the global shutter memory node FDGS- The source of the overflow gate OFG is coupled with the output of the photodiode PPD and the drain is coupled with the pixel voltage PIX_VDD. Accordingly, the global shutter memory node FDGS is placed between the drain of the first transfer gate TRG1 and the source of the second transfer gate TRG2. The drain of the second transfer gate TRG2 is coupled to a pixel amplifier provided in the second semiconductor layer 32. It should be noted that any type of amplifier circuit may be used and that the amplifier depicted in Fig. 4a has only exemplary character.

[0063] The gate of a transistor MSF in the amplifier is coupled with the drain of the second transfer gate TRG2. Moreover, the drain of MSF is supplied with the pixel voltage PIX_VDD. The source is coupled with a selection transistor SEL.

[0064] Moreover, the second semiconductor layer 32 includes a plurality of conversion gain stages each including a transistor (FDG1, FDG2) and a capacitance. Moreover, a reset transistor RST is provided that is supplied with the pixel voltage PIX_VDD.

[0065] The source of the selection transistor SEL is coupled with a capacitance provided in the third semiconductor layer 33 that is, in turn coupled with a comparator configured to compare the output of the selection transistor against a ramp signal generated in a ramp generator (coupled via a capacitance to the comparator) provided in the third semiconductor layer 33. Moreover, a counter CN is provided after the comparator that is coupled with ISP circuitry .

[0066] Fig. 4b depicts an exemplary diagram of the stacked imaging circuitry 30 depicting that pixel circuit in the first semiconductor layer 31 stacked on the second semiconductor layer 32 including the HDR circuit stacked on the third semiconductor layer 33 including the ADC circuit and the ISP circuitry , as discussed above. It should be noted that the present disclosure is not limited to stacked image sensors, since any type of interconnected image circuitry may be envisaged by the skilled person according to the present disclosure.

[0067] Thereby, a global shutter operation while providing CDS is possible. Moreover, ISP circuitry can be provided on-chip. Also, rolling shutter may be possible by shorting the photodiode PPD and the global shutter memory node FDGS via the first transfer gate TRG1, as discussed herein.

[0068] It should be noted that some embodiments pertain to a global shutter (GS) and / or rolling shutter (RS) pixel including: a photodiode (PPD); a circuitry configured for Correlated Double Sampling (CDS) in case of global shutter; circuitry comprising the pixel amplifier and a multiple conversion gain stage; and circuitry configured to convert the analog pixel information to digital and on chip signal processing. Embodiments also include corresponding methods of operating circuitry to provide GS and / or RS modes.

[0069] In a user device such as a camera or a mobile phone, an image sensor comprising the above described pixel may provide a user interface enabling selection of global shutter or rolling shutter modes. A global shutter mode may be preferable for quality of imaging whereas a rolling shutter mode may be preferable to save battery power. Global shutter mode or rolling shutter mode may be selected by a user or be algorithmically selected by the device according to one or more of (i) energy in the battery (ii) the field of view of the camera of the device (iii) ambient lighting (iv) whether a flash is used. More generally the algorithm may determine whether conditions or current operating settings of the device will benefit from using the global shutter over using the rolling shutter to provide a higher quality or less noisy output image, wherein the present disclosure is not limited to that. It should further be noted that global shutter according to the present disclosure may additionally or alternatively be useful for obtaining a no-motion-artifact image and / or an image synchronized with an external light source. Rolling shutter according to the present disclosure may be used for imaging with a fast frame rate. Both rolling shutter and global shutter according to the present disclosure may be used for high dynamic range and low noise imaging.

[0070] Embodiments of the disclosure provide a hybrid global shutter / rolling shutter circuitry.

[0071] In some embodiments, the CDS function is located on a different wafer than the pixel amplifier and the multiple conversion gain stage (FDG1, FDG2, FD2, FD3). It should be noted that the conversion gain stage may be based on FD2 and FD3, but the present disclosure is not limited in that regard as it may only be based on FD2 or based on more floating diffusions than FD2 and FD3.

[0072] In some embodiments, the global shutter with CDS (GS) or rolling shutter (RS) is selected by switching the TRG1. In some embodiments, switching the transistor TRG1 shorts the transistor TRG1 (i.e., PPD with FDGS). In some embodiments, switching or shorting TRG1 maximizes or combines the capacitance across PDD and FDGS and enables the use of a rolling shutter mode with larger capacity than in global shutter mode, such that dynamic range may be further enhanced.

[0073] In some embodiments, the global shutter (GS) and / or rolling shutter (RS) pixel includes circuitries located on two or three distinct wafer layers.

[0074] In some embodiments, the global shutter mode is activated by activating TRG1 with a predetermined sequence.

[0075] In some embodiments, the first wafer includes a photodiode, a memory node, a first transfer gate between the photodiode and the memory node, and a second transfer gate between the memory node and the second wafer.

[0076] In some embodiments, the first wafer further includes silicon, implants, trench isolation, color filters, and only one metal level.

[0077] In some embodiments, the pixel amplifier and multiple conversion gain stage are delocalized from the first wafer, on a second wafer, thereby optimizing the photodiode’s performance. In some embodiments, the second wafer includes the pixel amplifier and the multiple conversion gain stage.

[0078] In some embodiments, the second wafer includes only NMOS (but no PMOS).

[0079] In some embodiments, the third wafer is a CMOS wafer.

[0080] Some embodiments pertain to a method for controlling imaging circuitry as discussed herein.

[0081] In some embodiments, the method includes carrying out a global shutter mode.

[0082] In some embodiments, the global shutter mode is carried out based on activating the first and second transfer gates with a predetermined timing. This will also be discussed under reference of Fig. 5a.

[0083] In some embodiments, the predetermined timing includes controlling the first transfer gate as a global shutter and the second transfer gate as a rolling shutter.

[0084] In some embodiments, the first transfer gate is set high (and then low again), at the end of an exposure phase, and the second transfer gate is set high during a readout phase after the exposure phase.

[0085] Fig. 5a depicts a timing diagram 40 according to the present disclosure for a global shutter mode.

[0086] During a reset / shutter mode 41, a pulse is applied to the (base of) the transistors RST, FDG, TRG1, and TRG2. Then, at an end of an exposure phase 42, a further pulse is applied to (the base of) TRG1, such that after that, a readout phase 43 starts.

[0087] In the readout phase, first, a pulse is applied to the reset transistor while FDG is set high for a predetermined time. Also, shortly after that, the signal on SEL is set high for a predetermined time (longer than the signal FDG). When SEL is set low again, a pulse is applied to TRG2. After that, SEL is set high again and when it is set low again, at the same time, FDG is set high and shortly after that, a further pulse is applied to TRG2.

[0088] Thereby, a readout according to Fig. 5b can be achieved. The black line depicts that the exposure is constant for the first cycle and the second cycle while a buffer time (dotted line) increases in each cycle and a readout (hatched line) is thereby delayed for each cycle, such that each pixel row can be read after one another. Similarly, Fig. 5c depicts a constant exposure and delayed readout for five exemplary pixel row, without limiting the present disclosure in that regard.

[0089] Fig. 6a depicts a timing diagram 50 for a rolling shutter mode according to the present disclosure which is different from the timing diagram 40 in that the signal TRG1 is set high during one cycle. Thereby, as can be taken from Figs. 6b and 6c, the exposure and the readout for each row is delayed without using a buffer. Fig. 7 depicts a method 70 for operating imaging circuitry according to the present disclosure. The method includes, at 71, carrying out global shutter mode or rolling shutter mode based on a predetermined signaling sequence, as discussed herein.

[0090] Fig. 8 depicts a method 80 for operating imaging circuitry according to the present disclosure. At 81, a transfer gate is switched on, thereby shorting a photodiode with a global shutter memory node, for one acquisition period, such that, at 82, an RS mode is carried out.

[0091] Fig. 9 depicts a method 90 for operating imaging circuitry according to the present disclosure. At 91, global shutter mode is carried out. At the same time, at 92, CDS is carried out, as discussed herein.

[0092] It should be recognized that the embodiments describe methods with an exemplary ordering of method steps. The specific ordering of method steps is however given for illustrative purposes only and should not be construed as binding. For example, the ordering of 91 and 92 in the embodiment of Fig. 9 may be exchanged. Other changes of the ordering of method steps may be apparent to the skilled person.

[0093] Please note that the division of the ADC circuit and the ISP circuitry of the third semiconductor layer is only made for illustration purposes and that the present disclosure is not limited to any specific division of functions in specific units. For instance, the units of the third semiconductor layer could be implemented by a respective programmed processor, field programmable gate array (FPGA) and the like.

[0094] In some embodiments, also a non-transitory computer-readable recording medium is provided that stores therein a computer program product, which, when executed by a processor, such as the processor described above, causes the method described to be performed.

[0095] All units and entities described in this specification and claimed in the appended claims can, if not stated otherwise, be implemented as integrated circuit logic, for example on a chip, and functionality provided by such units and entities can, if not stated otherwise, be implemented by software.

[0096] In so far as the embodiments of the disclosure described above are implemented, at least in part, using software-controlled data processing apparatus, it will be appreciated that a computer program providing such software control and a transmission, storage or other medium by which such a computer program is provided are envisaged as aspects of the present disclosure.

[0097] It will be appreciated that the above description for clarity has described embodiments with reference to different functional units, circuitry and / or processors. However, it will be apparent that any suitable distribution of functionality between different functional units, circuitry and / or processors may be used without detracting from the embodiments. Described embodiments may be implemented in any suitable form including hardware, software, firmware or any combination of these. Described embodiments may optionally be implemented at least partly as computer software running on one or more data processors and / or digital signal processors. The elements and components of any embodiment may be physically, functionally, and logically implemented in any suitable way. Indeed the functionality may be implemented in a single unit, in a plurality of units or as part of other functional units. As such, the disclosed embodiments may be implemented in a single unit or may be physically and functionally distributed between different units, circuitry and / or processors.

[0098] Although the present disclosure has been described in connection with some embodiments, it is not intended to be limited to the specific form set forth herein. Additionally, although a feature may appear to be described in connection with particular embodiments, one skilled in the art would recognize that various features of the described embodiments may be combined in any manner suitable to implement the technique.

[0099] Note that the present technology can also be configured as described below.

[0100] (1) Imaging circuitry comprising: a first semiconductor layer including: a photodiode; a global shutter memory node for a global shutter mode; and a first transfer gate coupled between the photodiode and the global shutter memory node; and a second transfer gate coupled between the global shutter memory node and a pixel amplifier in a second semiconductor layer; the second semiconductor layer including the pixel amplifier; and a third semiconductor layer including analog to digital conversion circuitry.

[0101] (2) The imaging circuitry of (1), wherein the first semiconductor layer is configured for correlated double sampling.

[0102] (3) The imaging circuitry of (2), wherein the correlated double sampling is carried out based on the global shutter memory node and the photodiode.

[0103] (4) The imaging circuitry of anyone of (1) to (3), wherein the third semiconductor layer further includes image signal processing circuitry.

[0104] (5) The imaging circuitry of anyone of (1) to (4), further configured to switch between the global shutter mode and a rolling shutter mode based on switching the first transfer gate. (6) The imaging circuitry of anyone of (1) to (5), further configured to activate the global shutter mode by activating the first transfer gate with a predetermined signaling sequence.

[0105] (7) The imaging circuitry of anyone of (1) to (6), wherein the second semiconductor layer is configured for high dynamic range operation.

[0106] (8) The imaging circuitry of anyone of (1) to (7), wherein the second semiconductor layer further includes at least one conversion gain stage.

[0107] (9) The imaging circuitry of anyone of (1) to (8), wherein the second semiconductor layer is an NMOS semiconductor.

[0108] (10) The imaging circuitry of anyone of (1) to (9), wherein the first semiconductor layer further includes optically sensitive devices.

[0109] (11) The imaging circuitry of anyone of (1) to (10), wherein the rolling shutter mode is activated out based on switching on the first transfer gate for one acquisition period.

[0110] (12) A method for operating imaging circuitry, the imaging circuitry comprising: a first semiconductor layer including: a photodiode; a global shutter memory node for a global shutter mode; and a first transfer gate coupled between the photodiode and the global shutter memory node; and a second transfer gate coupled between the global shutter memory node and a pixel amplifier in a second semiconductor layer; the second semiconductor layer including the pixel amplifier; and a third semiconductor layer including analog to digital conversion circuitry, the method comprising: carrying out the global shutter mode or a rolling shutter mode based on a predetermined signaling sequence.

[0111] (13) The method of (12), wherein the rolling shutter mode is activated out based on switching on the first transfer gate for one acquisition period.

[0112] (14) The method of (12) or (13), further comprising: carrying out correlated double sampling in the global shutter mode.

[0113] (15) The method of (14), wherein correlated double sampling is carried out based on the global shutter memory node and the photodiode. (16) The method of anyone of (12) to (15), wherein the third semiconductor layer further includes an image signal processing circuitry.

[0114] (17) The method of anyone of (12) to (16), wherein the second semiconductor layer is configured for high dynamic range operation. (18) The method of anyone of (12) to (17), wherein the second semiconductor layer further includes at least one conversion gain stage.

[0115] (19) The method of anyone of (12) to (18), wherein the second semiconductor layer is an NMOS semiconductor.

[0116] (20) The method of anyone of (12) to (19), wherein the first semiconductor layer further includes optically sensitive devices.

[0117] (21) A computer program comprising program code causing a computer to perform the method according to anyone of (11) to (20), when being carried out on a computer.

[0118] (22) A non-transitory computer-readable recording medium that stores therein a computer program product, which, when executed by a processor, causes the method according to anyone of (11) to (20) to be performed.

Claims

CLAIMS1. Imaging circuitry comprising: a first semiconductor layer including: a photodiode; a global shutter memory node for a global shutter mode; and a first transfer gate coupled between the photodiode and the global shutter memory node; and a second transfer gate coupled between the global shutter memory node and a pixel amplifier in a second semiconductor layer; the second semiconductor layer including the pixel amplifier; and a third semiconductor layer including analog to digital conversion circuitry.

2. The imaging circuitry of claim 1, wherein the first semiconductor layer is configured for correlated double sampling.

3. The imaging circuitry of claim 2, wherein the correlated double sampling is carried out based on the global shutter memory node and the photodiode.

4. The imaging circuitry of claim 1, wherein the third semiconductor layer further includes a image signal processing circuitry.

5. The imaging circuitry of claim 1, further configured to switch between the global shutter mode and a rolling shutter mode based on switching the first transfer gate.

6. The imaging circuitry of claim 1, further configured to activate the global shutter mode by activating the first transfer gate with a predetermined signaling sequence.

7. The imaging circuitry of claim 1, wherein the second semiconductor layer is configured for high dynamic range operation.

8. The imaging circuitry of claim 1, wherein the second semiconductor layer further includes at least one conversion gain stage.

9. The imaging circuitry of claim 1, wherein the second semiconductor layer is an NMOS semiconductor.

10. The imaging circuitry of claim 1, wherein the first semiconductor layer further includes optically sensitive devices.

11. The imaging circuitry of claim 1, wherein the rolling shutter mode is activated out based on switching on the first transfer gate for one acquisition period.

12. A method for operating imaging circuitry, the imaging circuitry comprising: a first semiconductor layer including: a photodiode; a global shutter memory node for a global shutter mode; and a first transfer gate coupled between the photodiode and the global shutter memory node; and a second transfer gate coupled between the global shutter memory node and a pixel amplifier in a second semiconductor layer; the second semiconductor layer including the pixel amplifier; and a third semiconductor layer including analog to digital conversion circuitry, the method comprising: carrying out the global shutter mode or a rolling shutter mode based on a predetermined signaling sequence.

13. The method of claim 12, wherein the rolling shutter mode is activated out based on switching on the first transfer gate for one acquisition period.

14. The method of claim 12, further comprising: carrying out correlated double sampling in the global shutter mode.

15. The method of claim 14, wherein correlated double sampling is carried out based on the global shutter memory node and the photodiode.

16. The method of claim 12, wherein the third semiconductor layer further includes an image signal processing circuitry.

17. The method of claim 12, wherein the second semiconductor layer is configured for high dynamic range operation.

18. The method of claim 12, wherein the second semiconductor layer further includes at least one conversion gain stage.

19. The method of claim 12, wherein the second semiconductor layer is an NMOS semiconductor.

20. The method of claim 12, wherein the first semiconductor layer further includes optically sensitive devices.

Images