Apparatus and method for controlling processor cluster, and device

Abstract

The present application relates to the technical field of electronics. Provided are apparatus and method for controlling a processor cluster, and a device, which are used for improving the energy efficiency of a processor cluster while ensuring that the overall performance of the processor cluster remains unchanged. The apparatus comprises: a plurality of processors located in the same voltage domain and / or clock domain, and a detector and a controller, which are coupled to a first processor among the plurality of processors, the detector being configured to detect performance parameters of the first processor, the controller being configured to control the first processor to switch from a normal operating mode to a performance degradation mode when the load of the first processor is lower than the load of a second processor, and the second processor being a processor with the highest load among the plurality of processors, wherein a first performance parameter, which is detected by the detector when the first processor is in the normal operating mode, is greater than a second performance parameter, which is detected by the detector when the first processor is in the performance degradation mode.

Description

A control device, method and apparatus for a processor cluster

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on February 19, 2024, with application number 202410185827.8 and application name “A control device, method and apparatus for a processor cluster”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of electronic technology, and in particular to a control device, method, and equipment for a processor cluster. Background Art

[0003] Multiple processors are typically integrated into a system on a chip (SoC) to maximize the computing power of the SoC. Given the complexity of power distribution network design, these processors are grouped together to form a processor cluster, sharing the same voltage domain and / or clock domain. This means that the processors in the cluster share the same operating voltage and / or operating frequency, making it impossible for any of the processors to independently perform dynamic voltage and frequency scaling (DVFS).

[0004] When multiple processors in the processor cluster are used to process business, the load on these multiple processors may be unbalanced due to various reasons. The above-mentioned operating voltage and / or operating frequency are usually determined based on the computing power requirements of the processor with the heaviest load. At this time, the processor with a lighter load may have excess computing power when using this operating voltage and / or operating frequency, thereby reducing the energy efficiency of the system. Summary of the Invention

[0005] This application provides a control device, method, and apparatus for a processor cluster, which are used to improve the energy efficiency of the processor cluster while ensuring that the overall performance of the processor cluster remains unchanged. To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, a control device for a processor cluster is provided, the device comprising: multiple processors located in the same voltage domain and / or clock domain (i.e., the multiple processors use the same operating voltage and / or operating frequency), and a controller coupled to a first processor among the multiple processors; the controller is configured to control the first processor to switch from a normal operating mode to a performance degradation mode (i.e., reduce the performance parameters of the first processor) when the load of the first processor is less than the load of any processor among the multiple processors, the operating voltage and / or operating frequency provided by the above-mentioned voltage domain and / or clock domain being determined based on the computing power requirement of the processor with the heaviest load; wherein a first performance parameter of the first processor in the normal operating mode is greater than a second performance parameter of the first processor in the performance degradation mode.

[0007] In the above technical solution, for the first processor with a smaller load in the processor cluster, the controller can be used to control the first processor to switch from a normal operating mode to a performance degradation mode to reduce the performance of the first processor, so that different processors in the processor cluster can complete load processing in the same or similar time. In this way, the energy efficiency of the processor cluster can be improved while ensuring that the overall performance of the processor cluster remains unchanged.

[0008] In one possible implementation of the first aspect, the apparatus further includes a detector coupled to the first processor; the detector is configured to detect a performance parameter of the first processor, such as a number of instructions executed per unit time. In this possible implementation, detecting the performance parameter of the first processor by the detector enables the controller to precisely control the performance of the first processor based on the performance parameter.

[0009] In a possible implementation of the first aspect, the device further includes: a configuration interface coupled to the first processor; the configuration interface is configured to receive configuration information, the configuration information is used to indicate whether to enable the performance degradation mode, and the configuration information may be configured for the first processor by software; the controller is further configured to control the first processor to switch from the normal operating mode to the performance degradation mode when the configuration information is used to indicate enabling the performance degradation mode. In the above possible implementation, when the configuration information of the first processor is used to indicate enabling the performance degradation mode of the first processor, the controller controls the first processor to switch from the normal operating mode to the performance degradation mode, thereby achieving flexible control of the first processor and avoiding erroneous triggering of the performance degradation mode of the first processor.

[0010] In a possible implementation of the first aspect, the controller is further configured to: when the first processor is in the performance degradation mode, control the first processor to perform a performance degradation operation according to a preset control strategy and / or a preset degradation intensity. In this possible implementation, the controller controls the first processor to perform a performance degradation operation according to the preset control strategy and / or the preset degradation intensity, thereby achieving flexible control over the performance degradation operation of the first processor, thereby improving the effectiveness and accuracy of the control over the performance degradation operation.

[0011] In a possible implementation of the first aspect, the configuration information is also used to indicate a target degradation intensity; the controller is further used to: determine a target performance parameter based on the target degradation intensity and a first performance parameter; and adjust the preset control strategy and / or preset degradation intensity when the absolute value of the difference between the target performance parameter and the second performance parameter is greater than a preset threshold. In the above possible implementation, the controller can implement closed-loop control of the performance parameters of the first processor, thereby achieving a balance between energy efficiency gains and performance losses, and ultimately achieving that different processors in the processor cluster complete load processing in the same or similar time, thereby improving the energy efficiency of the processor cluster while ensuring that the overall performance of the processor cluster remains unchanged.

[0012] In a possible implementation of the first aspect, the performance degradation operations corresponding to the preset control strategy and / or preset degradation intensity include at least one of the following: intermittently shutting down the clock, reducing the intensity of branch instruction prediction, reducing the prefetch intensity of the hardware prefetcher, stopping access to at least one level of branch target buffer, stopping use of a specified branch prediction algorithm, stopping speculative optimization functions related to latency, stopping speculative optimization functions related to wakeup, and shutting down preset physical resources. The above possible implementation provides a variety of performance degradation operations corresponding to the preset control strategy and / or preset degradation intensity, as well as flexibility in selection. This allows, when the performance of the first processor is degraded, to select an appropriate performance degradation operation based on actual conditions, thereby precisely controlling the performance parameters of the first processor.

[0013] In a second aspect, a control method for a processor cluster is provided, which is applied to a control device of the processor cluster, the device including multiple processors located in the same voltage domain and / or clock domain, and a controller coupled to a first processor among the multiple processors; the method including: when the load of the first processor is less than the load of any processor among the multiple processors, the controller controls the first processor to switch from a normal operating mode to a performance degradation mode; wherein a first performance parameter of the first processor in the normal operating mode is greater than a second performance parameter of the first processor in the performance degradation mode.

[0014] In a possible implementation of the second aspect, the device further includes a detector coupled to the first processor; the method further includes: the detector detecting a performance parameter of the first processor, for example, the performance parameter includes the number of instructions executed per unit time.

[0015] In a possible implementation of the second aspect, the device also includes a configuration interface coupled to the first processor; the method also includes: the configuration interface receives configuration information, the configuration information is used to indicate whether to turn on the performance degradation mode; the controller controls the first processor to switch from the normal working mode to the performance degradation mode, including: when the configuration information is used to indicate to turn on the performance degradation mode, the controller controls the first processor to switch from the normal working mode to the performance degradation mode.

[0016] In a possible implementation manner of the second aspect, the method further includes: when the first processor is in the performance degradation mode, the controller controls the first processor to perform a performance degradation operation according to a preset control strategy and / or a preset degradation intensity.

[0017] In a possible implementation of the second aspect, the configuration information is also used to indicate a target degradation intensity; the method also includes: the controller determines a target performance parameter based on the target degradation intensity and a first performance parameter; and when the absolute value of the difference between the target performance parameter and the second performance parameter is greater than a preset threshold, adjusts the preset control strategy and / or preset degradation intensity.

[0018] In a possible implementation of the second aspect, the performance degradation operations corresponding to the preset control strategy and / or preset degradation intensity include at least one of the following: intermittently shutting down the clock, reducing the intensity of branch instruction prediction, reducing the prefetch intensity of the hardware prefetcher, stopping access to at least one level of branch target buffer, stopping the use of a specified branch prediction algorithm, stopping speculative optimization functions regarding delays, stopping speculative optimization functions regarding wake-up, and shutting down preset physical resources.

[0019] In a possible implementation manner of the second aspect, the performance parameter includes the number of instructions executed per unit time.

[0020] In another aspect of the present application, an electronic device is provided, comprising a memory and a control device for a processor cluster, the control device comprising multiple processors located in the same voltage domain and / or clock domain, and a detector and a controller coupled to each of the multiple processors, the memory being used to store computer instructions, and the control device being used to execute the computer instructions so that the electronic device implements the method for controlling the processor cluster provided in the second aspect or any possible implementation of the second aspect. Optionally, the control device for the processor cluster is the control device for the processor cluster provided in the first aspect or any possible implementation of the first aspect.

[0021] In another aspect of the present application, a computer-readable storage medium is provided, in which a computer program or instruction is stored. When the computer program or instruction is executed, a control method for a processor cluster as provided in the second aspect or any possible implementation of the second aspect is implemented.

[0022] In another aspect of the present application, a computer program product is provided, which includes: a computer program (also referred to as code, or instructions), which, when executed, enables a computer to execute a method for controlling a processor cluster as provided in the second aspect or any possible implementation of the second aspect.

[0023] It can be understood that the beneficial effects achieved by any of the above-mentioned processor cluster control methods, electronic devices, computer-readable storage media, and computer program products can correspond to the beneficial effects of the processor cluster control device provided above. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] FIG1 is a schematic diagram of the structure of a SoC provided in an embodiment of the present application;

[0025] FIG2 is a schematic diagram of load balancing for multiple processors in a processor cluster according to an embodiment of the present application;

[0026] FIG3 is a schematic diagram illustrating the performance of a processor in a processor cluster under different control scenarios provided by an embodiment of the present application;

[0027] FIG4 is a schematic structural diagram of a control device for a processor cluster provided in an embodiment of the present application;

[0028] FIG5 is a schematic structural diagram of another control device for a processor cluster provided in an embodiment of the present application;

[0029] FIG6 is a schematic diagram of a control processor switching between different states provided by an embodiment of the present application;

[0030] FIG7 is a schematic flow chart of a method for controlling a processor cluster according to an embodiment of the present application;

[0031] FIG8 is a schematic structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0032] The following will discuss in detail the making and use of various embodiments. However, it should be understood that many applicable inventive concepts provided herein can be implemented in a variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to implement and use the present application and technology and do not limit the scope of this application.

[0033] Unless defined otherwise, all technical and scientific terms used herein have the same meanings as commonly understood by one of ordinary skill in the art.

[0034] Various circuits or other components may be described or referred to as being "configured to" perform one or more tasks. In this case, "configured to" is used to imply structure by indicating that the circuit / component includes structure (e.g., circuitry) that performs the one or more tasks during operation. Thus, even when a specified circuit / component is not currently operational (e.g., not turned on), the circuit / component may be referred to as being configured to perform the task. Circuits / components used with the phrase "configured to" include hardware, such as circuitry that performs an operation, etc.

[0035] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application. In the present application, "at least one" refers to one or more, and "more" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can represent: a, b, c, a and b, a and c, b and c, a, b and c; where a, b and c can be single or multiple.

[0036] The embodiments of this application use terms such as "first" and "second" to distinguish objects with similar names, functions, or effects. Those skilled in the art will understand that terms such as "first" and "second" do not limit the quantity or order of execution. The term "coupled" is used to indicate an electrical connection, including direct connection via wires or connectors or indirect connection via other devices. Therefore, "coupling" should be considered a broadly defined electronic communication connection.

[0037] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0038] Before introducing the embodiments of the present application, the application scenarios involved in the embodiments of the present application are first introduced and explained.

[0039] Multiple processors are typically integrated into a system on a chip (SoC) to maximize computing power. Given the complexity of power distribution network design, multiple processors within the SoC are grouped together to form a processor cluster, sharing the same voltage domain and / or clock domain. This means that multiple processors within a cluster share the same operating voltage and / or operating frequency, making it impossible for any of these processors to independently perform dynamic voltage and frequency scaling (DVFS).

[0040] Exemplarily, Figure 1 shows a schematic structural diagram of a SoC. The SoC includes at least one processor cluster, each processor cluster in the at least one processor cluster includes multiple processors and a shared cache, and multiple processors in the same processor cluster and the shared cache share the same voltage domain. Optionally, each processor may include a processing core (or kernel, also called a processor core) and a private cache. In Figure 1, the at least one processor cluster includes a first processor cluster 11 and a second processor cluster 12, the first processor cluster 11 is in a first voltage domain V1, and the second processor cluster 12 is in a second voltage domain V2. Optionally, the SoC may also include a third-level (level 3, L3) cache that is accessible to the at least one processor cluster, and the third-level cache may be in a third voltage domain V3.

[0041] When multiple processors in the same processor cluster process business, the load on these multiple processors may be unbalanced due to various reasons. The above-mentioned operating voltage and / or operating frequency are usually determined based on the computing power requirements of the processor with the largest load (or the heaviest load). At this time, the processor with a lighter load (or a smaller load) will have an excess computing power problem when using this operating voltage and / or operating frequency, thereby reducing the energy efficiency of the system.

[0042] In one embodiment, the SoC's operating system typically uses a scheduling algorithm to balance the loads of the processors in the same processor cluster as much as possible to ensure that the loads on most processors are moderate. However, when the number of processors in the same processor cluster is large, such as when evolving from a dual-core to a quad-core architecture, it is difficult for the operating system to achieve ideal load balancing as the load scenario changes. Figure 2 shows a schematic diagram of load balancing for different processors in the same processor cluster. For example, as shown in Figure 2, a processor cluster includes four processors. When the operating system performs load balancing, the load (or task) distributed to each processor can be placed in the task queue corresponding to each processor. Since overloaded threads and underloaded threads often occur during the load balancing process, the loads in the task queues corresponding to the four processors are uneven. In the figure, the four processors are represented as C1 to C4, and the task queues corresponding to the four processors are represented as T1 to T4. For example, the loads of the four processors are arranged in descending order as C1, C4, C3, and C2. At this time, the operating system determines the operating voltage and operating frequency of the processor cluster based on the load of processor C1 to meet the computing power requirements of processor C1. However, processors C2 to C4, which have a lighter load, have a problem of excess computing power.

[0043] Based on this, an embodiment of the present application provides a control device for a processor cluster, which can be used to degrade the performance of a processor with a smaller load in the processor cluster to reduce the performance of the processor with a smaller load, so that different processors in the processor cluster complete the load processing in the same or similar time, so that the energy efficiency of the processor cluster can be improved while ensuring that the overall performance of the processor cluster remains unchanged. For example, as shown in (a) and (b) in Figure 3, schematic diagrams of the performance of the processors with a smaller load in the same processor cluster are shown respectively without and after performance degradation. In the figure, the processor cluster includes 4 processors and is represented as C1 to C4. The load of processor C1 is the largest, and the load of processors C1 to C4 is relatively small. Figure 3 (b) uses the performance degradation of processors C2 and C4 as an example for explanation. The horizontal axis represents the scheduling period, and the two rectangles corresponding to the same processor in the vertical axis represent the processor in the running state and the idle state respectively. The performance of the processor when it is in the running state can be represented by the width of the corresponding rectangle, and the duration of the processor in the running state can be represented by the length of the corresponding rectangle.

[0044] The control device of the processor cluster can be applied to an electronic device, or to an SoC of an electronic device, or a chipset comprising multiple chips, or a module comprising the SoC or chipset. The electronic device can be used as a server or a terminal device. Optionally, the electronic device includes but is not limited to: mobile phones, tablet computers, laptops, desktop computers, PDAs, ultra-mobile personal computers (umPCs), mobile internet devices (MIDs), netbooks, camcorders, cameras, wearable devices (such as smart watches and smart bracelets, etc.), vehicle-mounted equipment (such as cars, bicycles, electric vehicles, airplanes, ships, trains, high-speed railways, etc.), virtual reality (VR) equipment, augmented reality (AR) equipment, wireless terminals in industrial control, smart home devices (such as refrigerators, televisions, air conditioners, electric meters, etc.), intelligent robots, workshop equipment, wireless terminals in self-driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, or wireless terminals in smart homes, flying equipment (such as intelligent robots, hot air balloons, drones, airplanes), etc.

[0045] Figure 4 is a schematic diagram of the structure of a processor cluster control device provided in an embodiment of the present application. The device includes: multiple processors located in the same voltage domain and / or clock domain; and a controller coupled to any of the multiple processors; optionally, the device also includes a detector coupled to the processor. For ease of description, the following example uses the multiple processors including a first processor 21, which is coupled to a first detector 31 and a first controller 41.

[0046] The first detector 31 is used to detect the performance parameters of the first processor 21. The performance parameters of the first processor 21 include one or more parameters that can characterize the performance of the first processor 21. In one example, the performance parameters of the first processor 21 include the number of instructions executed per unit time. For example, the number of instructions executed per unit time is instruction number / clock cycle (instruction per clock, IPC), that is, the number of instructions executed per clock cycle. Optionally, the first detector 31 can be used to periodically or non-periodically detect the performance parameters of the first processor 21; further, the first detector 31 can also be used to send the detected performance parameters to the first controller 41.

[0047] The first controller 41 is configured to control the first processor 21 to switch from a normal operating mode to a degraded performance mode when the load of the first processor 21 is less than the load of any of the multiple processors. For example, the load of the first processor 21 is less than the load of the second processor 22, which is the most heavily loaded processor among the multiple processors. Furthermore, the first performance parameter detected by the first detector 31 of the first processor 21 in the normal operating mode is greater than the second performance parameter detected by the first detector 31 of the first processor 21 in the degraded performance mode.

[0048] The first processor 21 being in the normal operating mode (or referred to as the first processor 21 being in the normal operating mode) may specifically mean that the first processor 21 does not experience performance degradation when processing a load, that is, the first processor 21 operates normally according to the prior art. The first processor 21 being in the performance degradation mode (or referred to as the first processor 21 being in the performance degradation mode) may specifically mean that the first processor 21 experiences performance degradation when processing a load, and the operation of the first processor 21 at this time is different from the normal operation described above, and the second performance parameter detected by the first detector 31 when the first processor 21 is in the performance degradation mode is less than the first performance parameter detected when the first processor 21 is in the normal operating mode.

[0049] In addition, the load of the first processor 21 is less than the load of the second processor 22, and the second processor 22 is the processor with the largest load among the multiple processors. In one example, the difference between the load of the second processor 22 and the load of the first processor 21 can be greater than a preset threshold; the preset threshold can be set in advance, and the specific value can be fixed or dynamically changing, and this embodiment of the application does not impose any specific limitation on this.

[0050] In one possible embodiment, when the load of the first processor 21 is less than the load of the second processor 22, and the difference between the load of the second processor 22 and the load of the first processor 21 is greater than a preset threshold, the first controller 41 can be used to control the first processor 21 to switch from a normal working mode to a performance degradation mode to reduce the performance parameters of the first processor 21, so that the first processor 21 and the second processor 22 can complete the processing of the load in the same or similar time, thereby improving the energy efficiency of the processor cluster while ensuring that the overall performance of the processor cluster remains unchanged. Optionally, when the load of the first processor 21 is less than the load of the second processor 22, and the difference between the load of the second processor 22 and the load of the first processor 21 is not greater than the preset threshold, it indicates that the first processor 21 and the second processor 22 can complete the processing of the load in a similar time, and at this time, the first processor 21 can process the load in this normal working mode.

[0051] Optionally, the multiple processors further include a third processor 23 and a fourth processor 24, etc., that is, the multiple processors may include a larger number of processors. In this case, the processor with the heaviest load among the multiple processors may serve as the second processor 22, and any processor among the multiple processors except the processor with the heaviest load may serve as the first processor 21. In one possible embodiment, each processor in the multiple processors is coupled to a detector and a controller, and the detector and controller corresponding to the same processor may also be coupled.

[0052] 4 , the plurality of processors include a first processor 21, a second processor 22, a third processor 23, and a fourth processor 24. The first processor 21 is coupled to a first detector 31 and a first controller 41, the second processor 22 is coupled to a second detector 32 and a second controller 42, the third processor 23 is coupled to a third detector 33 and a third controller 43, and the fourth processor 24 is coupled to a fourth detector 34 and a fourth controller 44. Optionally, the control device may further include a shared cache 10, and the first processor 21, the second processor 22, the third processor 23, and the fourth processor 24 may all access the shared cache 10.

[0053] Furthermore, as shown in FIG5 , each of the multiple processors may be coupled to a configuration interface, for example, the first processor 21 is coupled to the first configuration interface 51, the second processor 22 is coupled to the second configuration interface 52, the third processor 23 is coupled to the third configuration interface 53, and the fourth processor 24 is coupled to the fourth configuration interface 54. Each of the multiple processors may be directly or indirectly coupled to the corresponding configuration interface, and the configuration interface may also be coupled to the controller corresponding to the processor. Optionally, as shown in FIG5 , each of the multiple processors may include a processing core and a private cache.

[0054] For any processor among the multiple processors, the configuration interface coupled to the processor can be used to receive configuration information of the processor, and the controller coupled to the processor can be used to control the processor according to the configuration information. The following description takes the first configuration interface 51 and the first controller 41 coupled to the first processor 21 as an example.

[0055] The first configuration interface 51 is used to receive configuration information of the first processor 21, where the configuration information indicates whether to enable the performance degradation mode of the first processor 21. The configuration information may be configured for the first processor 21 by software (e.g., an operating system) running on the processor cluster through the first configuration interface 51. The performance degradation mode may be disabled by default.

[0056] The first controller 41 is further configured to control the first processor 21 to switch from the normal operating mode to the performance-degraded mode when the configuration information indicates that the performance-degraded mode is enabled. For example, when the configuration information indicates that the performance-degraded mode is enabled, the first controller 41 may send a control signal to the first processor 21. When the first processor 21 receives the control signal, the first processor 21 switches from the normal operating mode to the performance-degraded mode.

[0057] Furthermore, when the first processor 21 is in the performance degradation mode, the first processor 21 may perform performance degradation to reduce the performance of the first processor 21. The process of the first processor 21 performing performance degradation is described in detail below.

[0058] In a possible embodiment, the first controller 41 is further configured to: when the first processor 21 is in the performance degradation mode, control the first processor 21 to perform a performance degradation operation according to a preset control strategy and / or a preset degradation intensity.

[0059] The preset control strategy and the preset degradation intensity may be preconfigured, and the performance degradation operation corresponding to the preset control strategy and the performance degradation operation corresponding to the preset degradation intensity may also be preconfigured. Optionally, the preset control strategy may include at least one control strategy, and each of the at least one control strategy may correspond to one or more performance degradation operations. Similarly, the preset degradation intensity may also include at least one degradation intensity, and each of the at least one degradation intensity may include one or more performance degradation operations.

[0060] Optionally, the performance degradation operations corresponding to the preset control strategy and / or preset degradation intensity include at least one of the following: intermittently shutting down the (processor's) clock, reducing the intensity of branch instruction prediction, reducing the prefetch intensity of the hardware prefetcher, stopping access to at least one level of branch target buffer (for example, a first-level branch target buffer, a second-level branch target buffer), stopping the use of a specified branch prediction algorithm, stopping speculative optimization functions regarding delays, stopping speculative optimization functions regarding wake-up, and shutting down preset physical resources (for example, shutting down the physical register stack, shutting down the transmit queue, and shutting down the sequential submission queue, etc.).

[0061] Among them, the degradation intensity corresponding to each of the above-mentioned performance degradation operations may be related to the execution time, execution intensity, and / or execution quantity corresponding to the performance degradation operation. For example, taking the intermittent clock shutdown as an example, the longer the duration of the clock shutdown is, the greater the corresponding degradation intensity, and the shorter the duration of the clock shutdown is, the smaller the corresponding degradation intensity. For another example, taking the reduction of the intensity of branch instruction prediction as an example, the greater the reduced intensity value is, the greater the corresponding degradation intensity is, and the smaller the reduced intensity value is, the smaller the corresponding degradation intensity is. For another example, taking the closing of physical register stacks as an example, the more physical register stacks are closed, the greater the corresponding degradation intensity is, and the fewer physical register stacks are closed, the smaller the corresponding degradation intensity is.

[0062] In addition, the execution time, execution intensity, and / or execution quantity corresponding to each of the above-mentioned performance degradation operations can be fixed, or can be dynamically adjusted according to needs in actual application. The embodiments of the present application do not impose specific restrictions on this.

[0063] In one possible example, the preset control strategy includes multiple control strategies, and the performance degradation operations corresponding to any two control strategies within the multiple control strategies may be completely different, partially different, or the same but with different corresponding execution times, execution intensities, and / or execution quantities. For example, assuming that the performance degradation operations corresponding to the multiple control strategies are at least partially the same, the performance degradation operations corresponding to each control strategy within the multiple control strategies may be shown in Table 1 below.

[0064] Table 1

[0065] In another possible example, the preset degradation intensity includes multiple degradation intensities, and the performance degradation operations corresponding to any two degradation intensities within the multiple degradation intensities may be completely different, partially different, or the same but with different corresponding execution times, execution intensities, and / or execution quantities. For example, assuming that the performance degradation operations corresponding to the multiple degradation intensities are at least partially the same, the performance degradation operations corresponding to each degradation intensity within the multiple degradation intensities may be shown in Table 2 below.

[0066] Table 2

[0067] In addition, the following Table 3 shows the energy efficiency benefits corresponding to each performance degradation operation listed above, which may include: reducing the power consumption of the clock tree, reducing the power consumption of some instructions lost due to speculation failures, reducing the power consumption caused by hardware speculation operations, reducing the power consumption of the branch target buffer, reducing the energy consumption of resources that need to be accessed by complex branch prediction algorithms, reducing the power consumption loss caused by speculation errors, and reducing the power consumption of preset physical resources.

[0068] Table 3

[0069] It will be understood that the performance degradation operations listed above are merely exemplary. In practical applications, other performance degradation operations that can reduce the performance parameters of the processor may also be used, and the embodiments of the present application do not impose any specific limitations on this.

[0070] In another possible embodiment, when the first processor 21 is in the performance degradation mode, the first processor 21 may also perform a performance degradation operation according to a preset control strategy and / or a preset degradation intensity. For a detailed description of the preset control strategy, the preset degradation intensity, and the performance degradation operation, reference may be made to the above description, and the embodiments of the present application will not be repeated here.

[0071] Furthermore, the configuration information is also used to indicate the target degradation intensity; the first controller 41 is also used to: determine the target performance parameter based on the target degradation intensity and the first performance parameter; when the absolute value of the difference between the target performance parameter and the second performance parameter is greater than a preset threshold, adjust the preset control strategy and / or preset degradation intensity.

[0072] In one possible example, the target degradation intensity may refer to the intensity after degradation, and the product of the target degradation intensity and the first performance parameter may be the target performance parameter. For example, if the target degradation intensity is 80% and the first performance parameter is A, then the target performance parameter is equal to 0.8×A. In another possible example, the target degradation intensity may refer to the intensity to be reduced, and the product of the first performance parameter and the first difference may be the target performance parameter, where the first difference is one minus the difference from the target degradation intensity. For example, if the target degradation intensity is 20% and the first performance parameter is A, then the target performance parameter is equal to (1-0.2)×A.

[0073] Optionally, the configuration information may also be used to indicate the target performance parameter. In this case, the first controller 41 may directly obtain the target performance parameter from the configuration information without determining the target performance parameter through calculation.

[0074] After determining the target performance parameter, the first controller 41 may adjust the preset control strategy and / or preset degradation intensity based on the magnitude relationship between the absolute value of the difference between the target performance parameter and the second performance parameter and a preset threshold value (or, alternatively, based on the magnitude relationship between the target performance parameter and the second performance parameter). The preset threshold value may be set in advance, and the specific value of the preset threshold value is not limited in this embodiment of the application.

[0075] In one possible example, when the target performance parameter is greater than the second performance parameter, and the difference between the target performance parameter and the second performance parameter is greater than the preset threshold, it means that the current performance parameter of the first processor 21 is still large. At this time: the first controller 41 can adopt a control strategy with faster degradation, or increase the degradation intensity, so that the first processor 21 performs a more aggressive performance degradation operation to further reduce the performance parameter of the first processor 21, until the difference between the target performance parameter and the second performance parameter detected by the first detector 31 is less than or equal to the preset threshold, or the second performance parameter detected by the first detector 31 is close to the target performance parameter.

[0076] In one possible example, when the target performance parameter is less than the second performance parameter, and the difference between the second performance parameter and the target performance parameter is greater than the preset threshold, it means that the current performance parameter of the first processor 21 is too small. At this time: the first controller 41 can adopt a slower degradation control strategy, or reduce the degradation intensity, so that the first processor 21 performs a more conservative performance degradation operation to gradually increase the performance parameter of the first processor 21 until the difference between the target performance parameter and the second performance parameter detected by the first detector 31 is less than or equal to the preset threshold.

[0077] Optionally, when the load of the first processor 21 is less than the load of the second processor 22, the first controller 41 can also be used to intermittently (e.g., periodically or aperiodically) control the first processor 21 to switch between the normal operating mode and the performance degradation mode, and compare the first performance parameter and the second performance parameter of the first processor 21 detected by the first detector 31 within the same time period (e.g., from time 0 to t2, or from time t1 to t3 in FIG. 6 below) to monitor whether the performance parameter of the first processor 21 is within the configured range. For example, FIG. 6 shows a schematic diagram of the first controller 41 intermittently controlling the first processor 21 to switch between the normal operating mode and the performance degradation mode. The figure illustrates an example in which the first processor 21 is in the performance degradation mode from time 0 to t1 and from time t2 to t3, and in the normal operating mode from time t1 to t2 and from time t3 to t4, and the first controller 41 controls the first processor 21 to switch between the normal operating mode and the performance degradation mode at time t1, time t2, and time t3, respectively.

[0078] For ease of understanding, the following takes the performance parameter of the first processor 21 as IPC, and the control device controls the first processor 21 through the flowchart shown in the following Figure 6 as an example to illustrate the solution provided in the embodiment of the present application.

[0079] Exemplarily, as shown in FIG7 , the method includes: S1. The first controller 41 detects the configuration information obtained by the first configuration interface 51, and exits (i.e., ends) if the configuration information is used to indicate turning off the performance degradation mode; and executes S2 if the configuration information is used to indicate turning on the performance degradation mode; S2. The first controller 41 controls the first processor 21 to enter the normal working mode; S3. The first IPC of the first processor 21 under the normal working mode detected by the first detector 31; S4. The first controller 41 determines whether the first time window is over, and the first time window is the time window for detecting the first IPC. If not, it returns to S3, and if so, it executes S5; S5. The first controller 41 determines the target IPC based on the target degradation intensity in the configuration information and the first IPC. The target IPC can also be called the IPC lower bound; S6. The first controller 41 controls the first processor 21 to enter the performance degradation mode; S7. The first detector 31 detects the first The processor 21 detects the second IPC of the performance degradation mode; S8. The first controller 41 determines whether the second time window is over, and the second time window is the time window for detecting the second IPC. If not, it returns to S7, and if so, it executes S9; S9. The first controller 41 determines the second IPC after degradation based on the second IPC detected by the first detector 31 in the second time window; S10. The first controller 41 determines whether the sampling time is over, and if so, it returns to S2, and if otherwise, it executes S11; S11. The first controller 41 compares the size relationship between the second IPC and the target IPC. If the second IPC is greater than the target IPC (that is, higher than the IPC lower limit), it executes S12, and if the second IPC is less than the target IPC (that is, lower than the IPC lower limit), it executes S13; S12. The first controller 41 adopts a control strategy with faster degradation or increases the degradation intensity; S13. The first controller 41 adopts a control strategy with slower degradation or reduces the degradation intensity.

[0080] In an embodiment of the present application, the first controller 41 can intermittently control the first processor 21 to switch between the normal operating mode and the performance degradation mode, and adjust the control strategy or degradation intensity corresponding to the performance degradation operation of the first processor 21 according to the first performance parameter and the second performance parameter of the first processor 21 detected by the first detector 31 within the same time period, thereby achieving closed-loop control of the performance parameters of the first processor 21, and then achieving a balance between energy efficiency gains and performance losses. Ultimately, different processors in the processor cluster can complete load processing in the same or similar time, which can improve the energy efficiency of the processor cluster while ensuring that the overall performance of the processor cluster remains unchanged.

[0081] Based on this, an embodiment of the present application also provides a method for controlling a processor cluster, which can be applied to a control device for a processor cluster. For a description of the control device, please refer to the explanation above. The method includes, when the load of the first processor is less than the load of any processor among the multiple processors, a first controller controlling the first processor to switch from a normal operating mode to a performance degradation mode; wherein the first performance parameter of the first processor in the normal operating mode is greater than the second performance parameter of the first processor in the performance degradation mode. Optionally, the method also includes: a first detector detecting the performance parameter of the first processor.

[0082] The performance parameter of the first processor may include the number of instructions executed per unit time. For example, the number of instructions executed per unit time is the number of instructions / clock cycle IPC, that is, the number of instructions executed per clock cycle.

[0083] Optionally, the method further includes: receiving, by the first configuration interface, configuration information indicating whether to enable the performance degradation mode. Accordingly, the first controller controls the first processor to switch from the normal operating mode to the performance degradation mode, including: when the configuration information indicates enabling the performance degradation mode, controlling, by the controller, the first processor to switch from the normal operating mode to the performance degradation mode.

[0084] In a possible embodiment, the method further includes: when the first processor is in the performance degradation mode, the first controller controls the first processor to perform a performance degradation operation according to a preset control strategy and / or a preset degradation intensity.

[0085] Furthermore, the configuration information is also used to indicate the target degradation intensity; the method also includes: the first controller determines the target performance parameter based on the target degradation intensity and the first performance parameter; and when the absolute value of the difference between the target performance parameter and the second performance parameter is greater than a preset threshold, adjusts the preset control strategy and / or preset degradation intensity.

[0086] Optionally, the performance degradation operations corresponding to the preset control strategy and / or preset degradation intensity include at least one of the following: intermittently shutting down the clock, reducing the intensity of branch instruction prediction, reducing the prefetch intensity of the hardware prefetcher, stopping access to at least one level of branch target buffer, stopping the use of a specified branch prediction algorithm, stopping speculative optimization functions regarding delays, stopping speculative optimization functions regarding wake-up, and shutting down preset physical resources.

[0087] In an embodiment of the present application, the control device downgrades the performance of the processor with a smaller load in the processor cluster to reduce the performance of the processor with a smaller load, so that different processors in the processor cluster complete the load processing in the same or similar time. This can improve the energy efficiency of the processor cluster while ensuring that the overall performance of the processor cluster remains unchanged.

[0088] In another aspect of the present application, an electronic device is provided, as shown in FIG8 , comprising a memory and a control device for a processor cluster, the control device comprising multiple processors located in the same voltage domain and / or clock domain, and a detector and a controller coupled to each of the multiple processors. The memory is configured to store computer instructions, and the control device is configured to execute the computer instructions so that the electronic device implements any of the processor cluster control methods provided above. A detailed description of the control device can be found in the previous embodiments.

[0089] It can be understood that all relevant contents of each step involved in the above-mentioned device embodiment can be referred to the embodiment of the control method and the embodiment of the electronic device, and the embodiments of the present application will not be repeated here.

[0090] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules or units is merely a logical functional division. In actual implementation, other division methods may be used, such as combining or integrating multiple units or components into another device, or ignoring or not implementing certain features.

[0091] The units described as separate components may or may not be physically separate, and the components shown as units may be one physical unit or multiple physical units, that is, they may be located in one place or distributed in multiple places. Some or all of the units may be selected according to actual needs to achieve the purpose of the present embodiment.

[0092] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a readable storage medium. The readable storage medium may include: a USB flash drive, a mobile hard drive, a read-only memory, a random access memory, a magnetic disk, or an optical disk, etc., which can store program code. Based on this understanding, the technical solution of the embodiment of the present application, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product.

[0093] In another embodiment of the present application, a readable storage medium is also provided, which stores computer execution instructions. When a device (which may be a single-chip microcomputer, chip, etc.) or a processor executes the steps in the above method embodiment.

[0094] In another embodiment of the present application, a computer program product is provided, which includes computer instructions stored in a readable storage medium; at least one processor of the device can read the computer instructions from the readable storage medium, and at least one processor executes the computer instructions so that the device performs the steps in the above method embodiment.

[0095] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A control device for a processor cluster, characterized in that: The apparatus includes: a plurality of processors located in the same voltage domain and / or clock domain, and a controller coupled to a first processor of the plurality of processors; The controller is configured to control the first processor to switch from a normal operating mode to a performance degradation mode when the load of the first processor is less than the load of any processor among the multiple processors; The first performance parameter of the first processor in the normal working mode is greater than the second performance parameter of the first processor in the performance degradation mode.

2. The device according to claim 1, characterized in that The apparatus further includes: a detector coupled to the first processor; The detector is used to detect performance parameters of the first processor.

3. The device according to claim 1 or 2, characterized in that The apparatus further comprises: a configuration interface coupled to the first processor; The configuration interface is used to receive configuration information, where the configuration information is used to indicate whether to enable the performance degradation mode; The controller is further configured to control the first processor to switch from the normal operating mode to the performance degradation mode when the configuration information is used to instruct to enable the performance degradation mode.

4. The device according to any one of claims 1 to 3, characterized in that The controller is further configured to control the first processor to perform a performance degradation operation according to a preset control strategy and / or a preset degradation intensity when the first processor is in the performance degradation mode.

5. The device according to claim 4, characterized in that The configuration information is also used to indicate the target degradation intensity; The controller is further configured to: determine a target performance parameter based on the target degradation intensity and the first performance parameter; and adjust the preset control strategy and / or preset degradation intensity when the absolute value of the difference between the target performance parameter and the second performance parameter is greater than a preset threshold.

6. The device according to claim 4 or 5, characterized in that The performance degradation operations corresponding to the preset control strategy and / or preset degradation intensity include at least one of the following: intermittently shutting down the clock, reducing the intensity of branch instruction prediction, reducing the prefetch intensity of the hardware prefetcher, stopping access to at least one level of branch target buffer, stopping the use of a specified branch prediction algorithm, stopping the speculative optimization function regarding delay, stopping the speculative optimization function regarding wake-up, and shutting down preset physical resources.

7. The device according to any one of claims 1 to 6, characterized in that The performance parameter includes the number of instructions executed per unit time.

8. A method for controlling a processor cluster, characterized in that: A control device for a processor cluster, the device comprising multiple processors located in the same voltage domain and / or clock domain, and a controller coupled to a first processor of the multiple processors; the method comprising: When the load of the first processor is less than the load of any processor among the multiple processors, the controller controls the first processor to switch from a normal operating mode to a performance degradation mode; The first performance parameter of the first processor in the normal working mode is greater than the second performance parameter of the first processor in the performance degradation mode.

9. The method according to claim 8, characterized in that The apparatus further includes: a detector coupled to the first processor; and the method further includes: The detector is used to detect performance parameters of the first processor.

10. The method according to claim 8 or 9, characterized in that The apparatus further includes a configuration interface coupled to the first processor; the method further including: The configuration interface receives configuration information, where the configuration information is used to indicate whether to enable the performance degradation mode; The controller controls the first processor to switch from a normal operating mode to a performance degradation mode, including: when the configuration information is used to instruct to enable the performance degradation mode, the controller controls the first processor to switch from the normal operating mode to the performance degradation mode.

11. The method according to any one of claims 8 to 10, characterized in that: The method further comprises: When the first processor is in the performance degradation mode, the controller controls the first processor to perform a performance degradation operation according to a preset control strategy and / or a preset degradation intensity.

12. The method according to claim 11, characterized in that The configuration information is further used to indicate a target degradation intensity; and the method further includes: The controller determines a target performance parameter based on the target degradation intensity and the first performance parameter; and adjusts the preset control strategy and / or preset degradation intensity when the absolute value of the difference between the target performance parameter and the second performance parameter is greater than a preset threshold.

13. The method according to claim 11 or 12, characterized in that The performance degradation operations corresponding to the preset control strategy and / or preset degradation intensity include at least one of the following: intermittently shutting down the clock, reducing the intensity of branch instruction prediction, reducing the prefetch intensity of the hardware prefetcher, stopping access to at least one level of branch target buffer, stopping the use of a specified branch prediction algorithm, stopping the speculative optimization function regarding delay, stopping the speculative optimization function regarding wake-up, and shutting down preset physical resources.

14. The method according to any one of claims 8 to 13, characterized in that: The performance parameter includes the number of instructions executed per unit time.

15. An electronic device, characterized in that: The electronic device comprises a memory and a control device of the processor cluster according to any one of claims 1 to 7, wherein the memory is used to store instructions and / or data required by the device.

16. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and when the computer instructions are executed on a device, the device executes the method for controlling a processor cluster according to any one of claims 8 to 14.

Images