Level conversion circuit, driving chip, display module, and display apparatus

Abstract

A level conversion circuit (100), a driving chip (10), a display module, and a display apparatus. The level conversion circuit (100) comprises a conversion unit (110), an inverting unit (120) and a delay unit (130), wherein the conversion unit (110) is electrically connected to the inverting unit (120), and the conversion unit (110) is configured to, under the action of a first bias signal (Bias1), generate a switch signal on the basis of a first power source voltage (AVDD1) and transmit the switch signal to the inverting unit (120); the inverting unit (120) is configured to, under the action of a second bias signal (Bias2), generate a driving voltage (VDD) on the basis of a second power source voltage (AVDD2), and invert the switch signal on the basis of the driving voltage (VDD) and transmit same to a load (140'); the delay unit (130) is electrically connected to the inverting unit (120), and the delay unit (130) is configured to transmit the second bias signal (Bias2) to the inverting unit (120); and the time when the conversion unit (110) receives the first bias signal (Bias1) is earlier than the time when the inverting unit (120) receives the second bias signal (Bias2).

Description

Level conversion circuit, driver chip, display module and display device CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to the Chinese patent application filed on February 22, 2024, with application number 202410197503.6 and entitled “Level conversion circuit, driver chip, display module and display device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a level conversion circuit, a driver chip, a display module, and a display device. Background Art

[0003] Currently, various electronic devices are equipped with chips or circuits with unified power management functions, which can extend battery life, improve power efficiency and protect devices from problems such as overvoltage, overcurrent and overheating to support the normal operation of electronic devices.

[0004] However, in some cases, such as low temperatures or power failure, the power output voltage of electronic devices may become unstable, resulting in excessive inrush current in some internal circuits. Excessive inrush current can easily cause the power management chip or circuit to shut down, resulting in the electronic device failing to start normally. Summary of the Invention

[0005] The present disclosure provides a level conversion circuit, a driver chip, a display module, and a display device, which can reduce the surge current generated by an electronic device so that the electronic device can start normally when the power supply is unstable.

[0006] A first aspect of the present disclosure provides a level conversion circuit, comprising a conversion unit, a flip unit, and a delay unit, wherein the conversion unit is electrically connected to the flip unit, and is configured to generate a switching signal according to a first power supply voltage under the action of a first bias signal and transmit the switching signal to the flip unit; the delay unit is electrically connected to the flip unit, and is configured to transmit a second bias signal to the flip unit; wherein the time when the conversion unit receives the first bias signal is earlier than the time when the flip unit receives the second bias signal.

[0007] In some embodiments, the flip unit includes an inverter, an input end of the inverter is used to receive the switching signal, an output end of the inverter is electrically connected to the load, and a power supply end of the inverter is used to receive the driving voltage.

[0008] In some embodiments, the delay unit includes a first transistor, the flip unit includes a second transistor, and the first transistor and the second transistor are used to form a current mirror circuit, wherein the first electrode of the second transistor is used to receive the second power supply voltage, the second electrode of the second transistor is electrically connected to the power supply end of the inverter, the reference current of the current mirror circuit passes through the first transistor, and the output current of the current mirror circuit flows through the second transistor.

[0009] In some embodiments, the gate of the first transistor is electrically connected to the gate of the second transistor, the first electrode of the first transistor is used to receive the reference current, the second electrode of the first transistor is used to be grounded, and the gate of the first transistor is electrically connected to the first electrode of the first transistor.

[0010] In some embodiments, the channel width-to-length ratios of the first transistor and the second transistor are equal.

[0011] In some embodiments, the delay unit includes a capacitor, one end of the capacitor is electrically connected to the flip unit, and the other end of the capacitor is used to receive the second bias signal.

[0012] In some embodiments, the number of the capacitors is at least two, wherein at least two of the capacitors are connected in series.

[0013] In some embodiments, the inverter includes a pull-up transistor and a pull-down transistor, wherein absolute values ​​of a threshold voltage of the pull-up transistor and a threshold voltage of the pull-down transistor are equal.

[0014] In some embodiments, the pull-up transistor is a P-type transistor, and the pull-down transistor is an N-type transistor.

[0015] In some embodiments, the number of the flipping units and the number of the delay units are both two, and the flipping units are electrically connected to the delay units in a one-to-one correspondence; wherein, the potential of one of the switching signals received at the input ends of the inverters in the two flipping units is a high potential, and the other is a low potential.

[0016] In some embodiments, the first power supply voltage and the second power supply voltage are the same.

[0017] A second aspect of the present disclosure provides a driver chip, comprising the level conversion circuit as described in any one of the first aspects.

[0018] A third aspect of the present disclosure provides a display module, comprising: a display panel; and a driving chip as described in the second aspect; wherein the display panel comprises a pixel circuit, and the driving chip is electrically connected to the pixel circuit.

[0019] In some embodiments, the display module further includes: a power management integrated circuit electrically connected to the driver chip, the power management integrated circuit being configured to provide power supply to the driver chip, the power supply including the first power supply voltage and the second power supply voltage.

[0020] In some embodiments, the display module further includes: a timing controller, electrically connected to the driver chip and the power management integrated circuit, respectively, and the timing controller is used to transmit a reset signal and a power start signal to the driver chip and the power management integrated circuit, respectively; wherein, the driver chip is used to generate a driving instruction after receiving the reset signal for a preset time, so as to transmit the first bias signal and the second bias signal to the conversion unit and the flipping unit, respectively.

[0021] In some embodiments, the display module further includes: a system on chip electrically connected to the timing controller and the power management integrated circuit respectively.

[0022] A fourth aspect of the present disclosure provides a display device, comprising the display module as described in any one of the third aspects. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] FIG1 shows a schematic structural block diagram of a level conversion circuit according to an embodiment of the present disclosure;

[0024] FIG2 shows a schematic structural block diagram of another level conversion circuit according to an embodiment of the present disclosure;

[0025] FIG3 shows a schematic structural block diagram of a flip unit according to an embodiment of the present disclosure;

[0026] FIG4 shows a schematic circuit structure diagram of a level conversion circuit according to an embodiment of the present disclosure;

[0027] FIG5 shows a schematic circuit structure diagram of another level conversion circuit according to an embodiment of the present disclosure;

[0028] FIG6 shows a schematic structural block diagram of a display module according to an embodiment of the present disclosure;

[0029] FIG7 shows a comparison diagram of current simulation according to an embodiment of the present disclosure;

[0030] FIG8 shows a schematic structural block diagram of a display device according to an embodiment of the present disclosure.

[0031] The corresponding component names and reference numerals in Figures 1 to 6 are as follows:

[0032] 10 driver chips, 20 pixel circuits, 30 power management integrated circuits, 40 timing controllers, 50 systems on chips;

[0033] 100 level conversion circuit;

[0034] 110 conversion unit, 120 flip unit, 130 delay unit, load 140′;

[0035] 121 inverter;

[0036] AVDD1 is the first power supply voltage, AVDD2 is the second power supply voltage, Bias1 is the first bias signal, Bias2 is the second bias signal, and the driving voltage is VDD. DETAILED DESCRIPTION

[0037] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or that are inherent to these processes, methods, products or devices. The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments.

[0038] Level shifting circuits are widely used in various electronic devices. They convert the level of an electrical signal from one logic level to another. They are typically used to interconnect signals of different levels. Because level shifting circuits directly interact with other loads, excessive inrush currents can be generated within these circuits when powering on some electronic devices. If the power supply is unstable at this time, this can easily cause the power management chip or power supply circuit within the electronic device to unexpectedly shut down, rendering the device inoperable.

[0039] In view of the above-mentioned deficiencies in the related art, a first aspect of the present disclosure provides a level conversion circuit. The level conversion circuit provided by the present disclosure is introduced below with reference to the accompanying drawings.

[0040] FIG1 shows a schematic block diagram of a level shifter circuit according to an embodiment of the present disclosure. As shown in FIG1 , the level shifter circuit 100 includes a shifter unit 110, a flipping unit 120, and a delay unit 130. The shifter unit 110 is electrically connected to the flipping unit 120. Under the action of a first bias signal Bias1, the shifter unit 110 is configured to generate a switching signal based on a first power supply voltage AVDD1 and transmit the switching signal to the flipping unit 120. Under the action of a second bias signal Bias2, the flipping unit 120 is configured to generate a driving voltage based on a second power supply voltage AVDD2 and flip the switching signal based on the driving voltage and transmit the signal to a load 140′. The delay unit 130 is electrically connected to the flipping unit 120 and transmits the second bias signal Bias2 to the flipping unit 120. The shifter unit 110 receives the first bias signal Bias1 earlier than the flipping unit 120 receives the second bias signal Bias2. The load 140′ may include a circuit or functional element, such as a pixel circuit or a chip.

[0041] It should be noted that the conversion unit 110 in the level conversion circuit 100 provided in the embodiment of the present disclosure is used to convert a stable voltage into a digital signal, namely the aforementioned switching signal. The flipping unit 120, based on the requirements of the load 140′ connected to the level conversion circuit 100 and the potential of the switching signal, flips the switching signal and outputs it to the load 140′. The aforementioned level conversion circuit 100 can be connected to more than one flipping unit 120, and each flipping unit 120 can be connected to a different load 140′. FIG2 shows a schematic structural block diagram of another level conversion circuit according to an embodiment of the present disclosure. As shown in FIG2 , the conversion unit 110 is connected to two flipping units 120. However, the present disclosure does not specifically limit the number of flipping units 120 connected to the conversion unit 110 or other structural relationships, and such a limitation does not deviate from the scope of protection and inventive concept of the present disclosure.

[0042] The level conversion circuits of various current electronic devices are filled with a large number of capacitive devices. Therefore, there may be residual charges in many connection nodes. This residual charge will cause the on or off state of the switching devices in the circuit to be uncertain. In addition, the operating state of the circuit switches frequently. In some cases, the power supply voltage will be directly connected to the ground terminal, resulting in a large inrush current. If the power supply voltage is unstable, it will cause a huge voltage drop, affecting the normal operation of the electronic equipment. When the level conversion circuit 100 provided in the embodiment of the present disclosure is turned on, the conversion unit 110 is turned on after receiving the first bias signal Bias1 and outputs a switching signal to the flip unit 120. The flip unit 120 is turned on after receiving the second bias signal Bias2 and flips the switching signal to output to the load 140′. The above-mentioned second bias signal Bias2 is transmitted by the delay unit to control the time when the conversion unit 110 receives the first bias signal Bias1 to be earlier than the time when the flip unit 120 receives the second bias signal Bias2. In this way, when the flip unit 120 is turned on, the conversion unit 110 has already been turned on, and the potential of the output switching signal is determined. Therefore, when the flip unit 120 is turned on, the second power supply voltage AVDD2 will not be directly grounded due to the uncertain potential state of the switching signal, causing a large inrush current. Since the level conversion circuit 100 provided by the present disclosure does not generate a large inrush current when turned on, and thus does not generate an excessive voltage drop, when the voltage of the power supply is unstable, it will not affect the stability of the power supply, thereby enabling the electronic device to which the level conversion circuit 100 belongs to start normally even when the power supply voltage is unstable. According to some embodiments, in the embodiments of Figures 1 and 2, the flip unit may include an inverter. Figure 3 shows a schematic structural block diagram of a flip unit according to an embodiment of the present disclosure. As shown in Figure 3, the input end of the inverter 121 is used to receive a switching signal, the output end of the inverter 121 is electrically connected to the load 140', and the power supply end of the inverter 121 is used to receive the driving voltage VDD.

[0043] Exemplarily, the conversion unit 110 is used to generate a switching signal according to the first power supply voltage AVDD1 under the action of the first bias signal Bias1 and transmit the switching signal to the flip unit 120. The input end of the inverter 121 inside the flip unit 120 is used to receive the switching signal, and under the action of the driving voltage VDD, the above-mentioned inverter 121 flips the switching signal and outputs it to the output end. The output end is connected to the load 140′. The above-mentioned driving voltage VDD is generated by the flip unit 120 according to the second power supply voltage AVDD2 under the action of the second bias signal Bias2.

[0044] It should be noted that, since the flip unit 120 receives the switching signal output by the conversion unit 110 through the input end of the inverter 121, in some cases, such as when the electronic device is just turned on, the flip unit 120 first receives the second bias signal Bias2, and the conversion unit 110 then receives the first bias signal Bias1. That is, the flip unit 120 first generates the driving voltage VDD, and since the conversion unit 110 does not generate a switching signal, the output end of the conversion unit 110 that outputs the switching signal, that is, the potential of the input end of the inverter 121 is in a floating state, then the pull-up transistor and the pull-down transistor inside the inverter 121 may be turned on at the same time, that is, a large surge current is generated between the power supply end and the ground end of the inverter 121, and if the flip unit 120 is turned on at this time, The second power supply voltage AVDD2 received by the unit 120 is unstable. For example, if the power supply of the current electronic device is in a low-temperature and power-deficient situation, the flip unit 120 will have an excessively large instantaneous surge current, which is equivalent to a short-term excessive voltage drop inside the flip unit 120. Since the power supply end of the flip unit 120 (i.e., the second power supply voltage AVDD2) is unstable, the voltage drop can easily cause a sudden drop in the potential of the power supply end of the flip unit 120, which will have an adverse effect on the power supply of the electronic device. If the power supply voltage is provided by a power management integrated chip or circuit, since the power management integrated chip or circuit usually has a protection value, the excessive voltage drop will directly cause it to shut down. In this way, the power supply of the electronic device cannot provide power to the various internal working circuits, resulting in the electronic device being unable to start normally.

[0045] In view of this, the presently disclosed embodiment includes a delay unit 130. Delay unit 130 may include a nonlinear element. Because the voltage and current of a nonlinear element have a nonlinear relationship, compared to a circuit without a nonlinear element, it takes longer to reach the same current value under a certain voltage. Therefore, it can delay the output current. Delay unit 130 is electrically connected to flip unit 120 and is configured to transmit the second bias signal Bias2 to flip unit 120, so that conversion unit 110 receives first bias signal Bias1 earlier than flip unit 120 receives second bias signal Bias2. The conversion unit 110 first receives the first bias signal Bias1 and thereby generates a switching signal. The flipping unit 120 then receives the second bias signal Bias2. Thus, the potential of the switching signal received at the input of the inverter 121 within the flipping unit 120 is clear, i.e., it is not in a floating state. Therefore, the pull-up transistor and the pull-down transistor of the inverter 121 are not simultaneously on. Consequently, excessive inrush current and thus excessive voltage drop are prevented within the flipping unit 120. Therefore, even if the power supply of the electronic device is at low temperature or low power, making it difficult to provide a stable voltage, the potential of the power supply terminal of the flipping unit 120 will not suddenly drop, thereby preventing any adverse effects on the power supply of the electronic device. Furthermore, when a power management integrated circuit or circuit is connected, the load 140' will not suddenly shut down due to unstable power supply or excessive power.

[0046] According to some embodiments, in the embodiments of Figures 1 and 2 , the delay unit 130 includes a first transistor, the flip unit 120 includes a second transistor, and the first transistor and the second transistor are used to form a current mirror circuit. A first electrode of the second transistor is used to receive a second power supply voltage AVDD2, and a second electrode of the second transistor is electrically connected to a power supply terminal of the inverter 121. A reference current of the current mirror circuit passes through the first transistor, and an output current of the current mirror circuit flows through the second transistor.

[0047] Exemplarily, the delay unit 130 includes a first transistor, and the flip unit 120 includes a second transistor. A first electrode of the second transistor receives the second power supply voltage AVDD2, and a second electrode is electrically connected to the power supply terminal of the inverter 121. The first transistor and the second transistor form a current mirror circuit. The current flowing through the first transistor is a reference current of the current mirror circuit, and the current flowing through the second transistor is an output current of the current mirror. Since the delay unit 130 is configured to receive the second bias signal Bias2, the reference current is generated based on the second bias signal Bias2. Based on the above-described current mirror circuit, when the second bias signal Bias2 enters the delay unit 130, the second transistor in the flip unit 120 needs to mirror the current of the first transistor. Therefore, the speed at which the current flowing through the second transistor is generated is reduced. This is equivalent to a time delay before the flip unit 120 receives the second bias signal Bias2, allowing the conversion unit 110 to receive the first bias signal Bias1 first. When the power supply terminal of the inverter 121 within the flip unit 120 receives the driving voltage VDD, the potential of the switching signal is not left floating, and the state of the inverter 121 is determined. Therefore, excessive inrush current is not generated within the flip unit 120.

[0048] According to some embodiments, the gate of the first transistor is electrically connected to the gate of the second transistor, the first electrode of the first transistor is used to receive a reference current, the second electrode of the first transistor is used to be grounded, and the gate of the first transistor is electrically connected to the first electrode of the first transistor.

[0049] It should be noted that in the present disclosure, the transistors used can all be thin film transistors or field effect transistors or other switching devices with the same characteristics. The source and drain of the transistors used here can be symmetrical in structure. The first electrode is used to represent one of the source and the drain, and the second electrode is used to represent the other of the source and the drain. In addition, according to the characteristics of the transistor, it is divided into N-type and P-type transistors. The turn-on voltage of the P-type transistor is a low-level voltage, and the turn-on voltage of the N-type transistor is a high-level voltage. However, whether it is an N-type or P-type transistor, it does not deviate from the scope and spirit of the technical solution provided by the present disclosure. The following is an example provided in conjunction with the accompanying drawings to illustrate an embodiment of the present disclosure.

[0050] For example, FIG4 shows a schematic circuit structure diagram of a level conversion circuit according to an embodiment of the present disclosure. The circuit structure of FIG4 may correspond to the structural block diagram of FIG2. As shown in FIG4:

[0051] The conversion unit 110 includes a P-type third transistor MP5 , a fourth transistor MP6 , and a fifth transistor MP7 , an N-type sixth transistor MN3 , a seventh transistor MN4 , and a built-in inverter INV1 .

[0052] Among them, a first electrode of the third transistor MP5 receives the first power supply voltage AVDD1, a gate receives the first bias signal Bias1, a second electrode is electrically connected to the first electrodes of the fourth transistor MP6 and the fifth transistor MP7, respectively, and the gates of the fourth transistor MP6 and the fifth transistor MP7 are respectively connected to the second electrodes of each other. The first electrodes of the sixth transistor MN3 and the seventh transistor MN4 are electrically connected to the second electrodes of the fourth transistor MP6 and the fifth transistor MP7, respectively. The gates of the sixth transistor MN3 and the seventh transistor MN4 are electrically connected via the built-in inverter INV1. The gate IN of the transistor NN3 is connected to the input terminal of the built-in inverter INV1, and the gate INB of the seventh transistor MN4 is connected to the output terminal of the built-in inverter INV1. One terminal of the built-in inverter INV1 is connected to the voltage DVDD, and the other terminal is grounded. The connection point between the second electrode of the fifth transistor MP7 and the first electrode of the seventh transistor MN4 forms a first output node OUT1, and the connection point between the second electrode of the fourth transistor MP6 and the first electrode of the sixth transistor MN3 forms a second output node OUT1B.

[0053] Taking the delay unit 130 on the right side of Figure 4 as an example, the delay unit 130 includes a P-type first transistor MP8, the first transistor MP8 is electrically connected to the gate of the second transistor MP2, the gate of the first transistor MP8 is electrically connected to the first electrode, the first electrode of the first transistor MP8 receives the first bias signal Bias1, and the second electrode is grounded.

[0054] It should be noted that in the flip unit 120 on the left side of FIG4 , the connection relationship between the P-type transistor MP9 and the first transistor MP8 corresponds to that between the P-type transistor MP1 and the second transistor MP2, the connection relationship between the P-type transistor MP4 and the transistor MP3 corresponds to that between the N-type transistor MN2 and the transistor MN1, and the connection relationship between the fourth output ground OUT and the third output node OUTB corresponds to that between the P-type transistor MP9 and the first transistor MP8. In the delay unit 130 on the left side of FIG4 , the connection relationship between the P-type transistor MP9 and the first transistor MP8 corresponds to that between the P-type transistor MP1 and the second transistor MP2.

[0055] According to some embodiments, the channel width-to-length ratios of the first transistor and the second transistor are equal.

[0056] Exemplarily, the channel width-to-length ratio of the first transistor in the delay unit 130 is equal to that of the second transistor in the flip unit 120. Since the first transistor and the second transistor form a current mirror circuit, and the current flowing through the second transistor mirrors the current flowing through the first transistor, when the channel width-to-length ratios of the first transistor and the second transistor are equal, the current flowing through the second transistor is equal to the current flowing through the first transistor. This ensures that the added delay unit 130 structure will not affect the original current flowing through the flip unit 120. The driving voltage VDD received by the power supply terminal of the inverter 121 inside the flip unit 120 will not change compared to the case without the delay unit 130, thereby not affecting the output of the flip unit 120 and, subsequently, the working state of the load 140′.

[0057] According to some embodiments, in the embodiments of FIG. 1 and FIG. 2 , the delay unit 130 includes a capacitor, one end of the capacitor is electrically connected to the flip unit 120 , and the other end of the capacitor is used to receive the second bias signal Bias2 .

[0058] It should be noted that the capacitor is a capacitive element that has the function of storing charge and releasing the charge when it is fully charged. Therefore, when one end of the capacitor receives the second bias signal Bias2, it takes some time for the charge at the other end to accumulate. This can limit the time when the flip unit 120 receives the second bias signal Bias2, so that the conversion unit 110 receives the first bias signal Bias1 earlier than the flip unit 120 receives the second bias signal Bias2.

[0059] For example, Figure 5 shows a schematic circuit structure diagram of another level conversion circuit according to an embodiment of the present disclosure. As shown in Figure 5, compared with the embodiment of Figure 4, the right delay unit 130 includes a capacitor C1, and the left delay unit 130 includes a capacitor C2. The capacitor C1 and the capacitor C2 are both connected to the second bias signal Bias2 at one end, and the other end is connected to the gate of the second transistor MP2 and the gate of the transistor MP1, respectively.

[0060] It should be noted that, since the plates at both ends of the capacitor carry opposite charges, that is, if one end is positively charged, the other end is negatively charged, taking the right delay unit 130 and the flip unit 120 in the embodiments of Figures 4 and 5 as an example, if the second bias signal Bias2 is positively charged, the second transistor MP2 is a P-type transistor, and conversely, if the second bias signal Bias2 is negatively charged, the second transistor MP2 is an N-type transistor.

[0061] According to some embodiments, the number of the capacitors is at least two, wherein at least two capacitors are connected in series.

[0062] It should be noted that the capacitor in the delay unit 130 includes a series structure of at least two capacitors. The series structure can increase the capacitance of the capacitor. Compared with a single capacitor structure, the flip unit 120 receives the second bias signal Bias2 later.

[0063] According to some embodiments, the inverter 121 in the embodiments of FIG. 1 to FIG. 5 includes a pull-up transistor and a pull-down transistor, wherein the absolute values ​​of the threshold voltage of the pull-up transistor and the threshold voltage of the pull-down transistor are equal.

[0064] It should be noted that, since under normal operation, only one of the pull-up transistor and the pull-down transistor of the inverter 121 is in the on state, and the absolute values ​​of the threshold voltages of the two are equal, the internal voltage drops of the pull-up transistor and the pull-down transistor are equal, so that the internal loss of the inverter 121 is consistent under normal operation, thereby improving the accuracy of the output to the load 140′.

[0065] According to some embodiments, the pull-up transistor is a P-type transistor, and the pull-down transistor is an N-type transistor.

[0066] Exemplarily, as shown in the embodiments of FIG. 4 and FIG. 5 , the inverter 121 of the flip unit 120 includes P-type pull-up transistors MP3 / MP4 and N-type pull-down transistors MN1 / MN2 .

[0067] It should be noted that, since the voltage loss is smaller when a high voltage flows through the source and drain of the P-type transistor, and the voltage loss is smaller when a low voltage flows through the source and drain of the N-type transistor, the first electrode of the P-type transistor is used to receive the driving voltage VDD, and the second electrode of the N-type transistor is grounded, which can reduce the internal loss of the inverter 121.

[0068] According to some embodiments, the number of the flipping units 120 and the number of the delay units 130 are both two, and the flipping units 120 and the delay units 130 are electrically connected in a one-to-one correspondence;

[0069] Among the switching signals received at the input terminals of the inverters 121 in the two flip units 120 , one has a high potential and the other has a low potential.

[0070] For example, as shown in the embodiments of Figures 2, 4 and 5, two flipping units 120 are connected to the conversion unit 110, each flipping unit 120 is connected to a delay unit 130, and the potentials of the switching signals received at the input ends of the inverters 121 in the two flipping units 120 are one high potential and one low potential, that is, the first output node OUT1 and the second output node OUT1B are in opposite potential states.

[0071] It should be noted that both flip units 120 include an inverter 121, and the potentials received at the input ends of the inverter 121 are opposite, so that the outputs of the two flip units 120 are opposite. Therefore, one conversion unit 110 can control the two flip units 120 to output different control logics, thereby improving the adaptability of the level conversion circuit 100 proposed in the embodiment of the present disclosure.

[0072] According to some embodiments, in the embodiments of FIG. 1 , FIG. 2 , FIG. 4 , and FIG. 5 , the first power supply voltage AVDD1 and the second power supply voltage AVDD2 are the same.

[0073] It should be noted that the flip unit 120 and the conversion unit 110 receive the same power supply voltage, that is, both receive the power supply voltage at the same time. The startup order depends entirely on the time of receiving the first bias signal Bias1 and the second bias signal Bias2. Only the first bias signal Bias1 and the second bias signal Bias2 need to be controlled, that is, the output of the level conversion circuit 100 can be accurately controlled.

[0074] A second aspect of an embodiment of the present disclosure provides a driver chip, comprising the level conversion circuit 100 as described in any one of the first aspects.

[0075] It should be noted that a driver chip is a chip used to control other chips or components in electronic devices. It converts control signals into specific signals required by other chips or components to ensure normal device operation. It is widely used in display devices, communication devices, storage devices, and the like. The driver chip includes the level conversion circuit 100 provided by the present disclosure. In devices that require frequent power on and off and are prone to unstable power supply voltage, it can reduce the inrush current generated during power on, thereby protecting the chip and extending its service life.

[0076] A third aspect of the present disclosure provides a display module. FIG6 shows a schematic structural block diagram of a display module according to an embodiment of the present disclosure. As shown in FIG6 , the display module includes: a display panel; and a driver chip 10 as in the second aspect.

[0077] The display panel includes a pixel circuit 20 , and the driving chip 10 is electrically connected to the pixel circuit 20 .

[0078] Exemplarily, the driver chip 10 can be a source driver chip, which drives the pixel circuit 20 to emit light through GOA (Gate Driven on Array). The pixel circuit 20 is connected to the output of the flip unit 120 in the embodiment of the present disclosure. Since the pixel circuit 20 is mostly a light-emitting pixel, the current that each light-emitting pixel can withstand is relatively small. A large surge current can easily break down the light-emitting pixels in the pixel circuit 20. The level conversion circuit 100 provided in the embodiment of the present disclosure can reduce the surge current, thereby preventing the light-emitting pixels in the pixel current from being broken down.

[0079] According to some embodiments, as shown in FIG6 , the display module further includes: a power management integrated circuit 30 electrically connected to the driver chip 10 , the power management integrated circuit 30 being configured to provide power to the driver chip 10 , the power supply including a first power supply voltage AVDD1 and a second power supply voltage AVDD2 .

[0080] Exemplarily, the PMIC (Power Management Integrated Circuit, power management integrated circuit 30) is used to provide power supply AVDD to the driver chip 10. The power supply includes a first power supply voltage AVDD1 and a second power supply voltage AVDD2. In some examples, the first power supply voltage AVDD1 and the second power supply voltage AVDD2 are the same.

[0081] According to some embodiments, as shown in FIG6 , the display module further includes a timing controller 40 , which is electrically connected to the driver chip 10 and the power management integrated circuit 30 , and is configured to transmit a reset signal and a power start signal to the driver chip 10 and the power management integrated circuit 30 , respectively.

[0082] The driver chip 10 is configured to generate a driving instruction after receiving a reset signal for a preset time, so as to transmit a first bias signal Bias1 and a second bias signal Bias2 to the conversion unit 110 and the flip unit 120 respectively.

[0083] Exemplarily, a TCON (Timing Controller) is electrically connected to the driver chip 10 and the power management integrated circuit 30 , and is used to transmit a reset signal and a power start signal to the driver chip 10 and the power management integrated circuit 30 , respectively.

[0084] It should be noted that, after receiving the reset signal, the driver chip 10 generates a driving instruction to control the level conversion circuit 100 to operate.

[0085] The power startup signal is used to control the power management integrated circuit 30 . After receiving the power startup signal, the power management integrated circuit 30 provides the power supply AVDD to the driver chip 10 .

[0086] According to some embodiments, the display module further includes a system on chip 50 electrically connected to the timing controller 40 and the power management integrated circuit 30 .

[0087] For example, a SoC (System-on-Chip) typically includes a processor, memory, input / output interfaces, analog circuits, and other necessary components, all integrated on a single chip. This integration approach offers advantages such as reduced size and cost. In the disclosed embodiment, the SoC 50 is electrically connected to the timing controller 40 and the power management integrated circuit 30. The power supply in the electronic device can provide the input voltage Vin to the power management integrated circuit 30 via the SoC 50, rather than directly from the power supply, thereby ensuring the controllability of the input voltage Vin.

[0088] In order to better illustrate the technical effects of the embodiments of the present disclosure, a set of simulation comparison diagrams are provided below. FIG7 shows a comparison diagram of current simulation according to an embodiment of the present disclosure, based on an OLED (Organic Light-Emitting Diode) notebook display module, as shown in FIG7 :

[0089] In FIG7 , Reset represents the reset signal, SD_EN represents the driving instruction, Bias1 represents the first bias signal, Bias2 represents the second bias signal, and AVDD represents the first power supply voltage AVDD1 and the second power supply voltage AVDD2.

[0090] In FIG7 , the drive instruction SD_EN in the driver chip 10 is generated 30 μs after receiving the reset signal Reset from the timing controller 40. As can be seen from the current simulation diagram before improvement, the second bias signal Bias2 is written earlier than the first bias signal Bias1. At this time, when the second bias signal Bias2 is written, the AVDD current and AVDD voltage have a larger value, namely 850 mA.

[0091] After adopting the level conversion circuit 100 provided by the embodiment of the present disclosure, it can be seen from the improved current simulation diagram that the states of the reset signal Reset and the drive instruction SD_EN have not changed, but the second bias signal Bias2 is written later than before the improvement, and the second bias signal Bias2 decreases more gently, and the maximum AVDD current also becomes 50mA.

[0092] It can be seen that the display module using the level conversion circuit 100 provided by the embodiment of the present disclosure can effectively reduce the surge current generated when it is turned on.

[0093] A fourth aspect of an embodiment of the present disclosure provides a display device. FIG8 shows a schematic structural block diagram of a display device according to an embodiment of the present disclosure. As shown in FIG8 , the display device includes a display module as described in any one of the third aspects.

[0094] For example, the display device provided by the embodiments of the present disclosure can be applied to scenarios such as vehicle-mounted displays, smart phones, computers, medical displays, televisions, smart wearable displays, etc., and the embodiments of the present disclosure do not make specific limitations.

[0095] It should be noted that since the display device proposed in the embodiment of the present disclosure includes the above-mentioned level conversion circuit 100, in some devices that often work in a low-temperature environment, causing the power supply to be easily depleted, and need to be frequently started, since no excessive surge current will be generated during startup, it is less likely that the device will fail to start.

[0096] The above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present disclosure.

Claims

1. A level conversion circuit, comprising a conversion unit, a flip unit and a delay unit, wherein: The conversion unit is electrically connected to the flip unit, and the conversion unit is used to generate a switching signal according to the first power supply voltage under the action of the first bias signal and transmit the switching signal to the flip unit; The flip unit is configured to generate a driving voltage according to the second power supply voltage under the action of the second bias signal, and flip the switching signal according to the driving voltage and transmit the flip signal to the load; The delay unit is electrically connected to the flip unit, and the delay unit is used to transmit the second bias signal to the flip unit; The conversion unit receives the first bias signal earlier than the flip unit receives the second bias signal.

2. The level conversion circuit according to claim 1, wherein: The flip unit includes an inverter, an input end of the inverter is used to receive the switching signal, an output end of the inverter is electrically connected to the load, and a power supply end of the inverter is used to receive the driving voltage.

3. The level conversion circuit according to claim 2, wherein: The delay unit includes a first transistor, and the flip unit includes a second transistor; The first transistor and the second transistor are used to form a current mirror circuit; The first electrode of the second transistor is used to receive the second power supply voltage, the second electrode of the second transistor is electrically connected to the power supply end of the inverter, the reference current of the current mirror circuit passes through the first transistor, and the output current of the current mirror circuit flows through the second transistor.

4. The level conversion circuit according to claim 3, wherein: The gate of the first transistor is electrically connected to the gate of the second transistor, the first electrode of the first transistor is used to receive the reference current, the second electrode of the first transistor is used to be grounded, and the gate of the first transistor is electrically connected to the first electrode of the first transistor.

5. The level conversion circuit according to claim 4, wherein: The channel width-to-length ratios of the first transistor and the second transistor are equal.

6. The level conversion circuit according to claim 2, wherein: The delay unit includes a capacitor, one end of the capacitor is electrically connected to the flip unit, and the other end of the capacitor is used to receive the second bias signal.

7. The level conversion circuit according to claim 6, wherein: The number of the capacitors is at least two, and at least two of the capacitors are connected in series.

8. The level conversion circuit according to any one of claims 2 to 7, wherein: The inverter includes a pull-up transistor and a pull-down transistor, and the absolute values ​​of the threshold voltage of the pull-up transistor and the threshold voltage of the pull-down transistor are equal.

9. The level conversion circuit according to claim 8, wherein: The pull-up transistor is a P-type transistor, and the pull-down transistor is an N-type transistor.

10. The level conversion circuit according to any one of claims 2 to 7, wherein: The number of the flip units and the number of the delay units are both two, and the flip units are electrically connected to the delay units in a one-to-one correspondence; One of the switching signals received by the input terminals of the inverters in the two flip units has a high potential and the other has a low potential.

11. The level conversion circuit according to any one of claims 2 to 7, wherein: The first power supply voltage and the second power supply voltage are the same. 12 . A driver chip comprising the level conversion circuit according to claim 1 .

13. A display module comprising: Display panel; The driver chip according to claim 12; The display panel includes a pixel circuit, and the driving chip is electrically connected to the pixel circuit.

14. The display module according to claim 13, further comprising: A power management integrated circuit is electrically connected to the driver chip, and is used to provide power supply to the driver chip, where the power supply includes the first power supply voltage and the second power supply voltage.

15. The display module according to claim 14, further comprising: a timing controller, electrically connected to the driver chip and the power management integrated circuit, respectively, and configured to transmit a reset signal and a power start signal to the driver chip and the power management integrated circuit, respectively; The driver chip is configured to generate a driving instruction after receiving the reset signal for a preset time, so as to transmit the first bias signal and the second bias signal to the conversion unit and the flip unit respectively.

16. The display module according to claim 15, further comprising: The system on chip is electrically connected to the timing controller and the power management integrated circuit respectively.

17. A display device comprising the display module according to any one of claims 13 to 16.

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