Imaging device and imaging method

Abstract

The present invention allows improvement in dynamic range while suppressing a decrease in frame rate.　This imaging device comprises: pixels for which conversion efficiency can be switched; comparison units for comparing a pixel signal, which is read out from a pixel, with a first reference signal and a second reference signal; and a switching control unit for switching the conversion efficiency of the pixel on the basis of comparison results of the comparison units. On the basis of the comparison results of the comparison units, the switching control unit may control switching between an output of the comparison result between the pixel signal and the first reference signal, and an output of the comparison result between the pixel signal and the second reference signal.

Description

Imaging device and imaging method

[0001] The present technology relates to an imaging device and an imaging method, and more particularly, to an imaging device and an imaging method capable of switching conversion efficiency of pixels.

[0002] There is a DCG (Dual Conversion Gain)-HDR technology that switches pixel conversion efficiencies to achieve high dynamic range (HDR). For example, a technology has been disclosed that achieves HDR by using data read with high conversion efficiency in dark areas of the screen to reduce noise, and by using data read with low conversion efficiency in bright areas to prevent signal saturation (see, for example, Patent Document 1).

[0003] US Patent Application Publication No. 2022 / 060647

[0004] However, in the above-mentioned conventional technology, four A / D conversions (P phase → P phase → D phase → D phase) are required when reading from one pixel, which may result in a decrease in frame rate.

[0005] This technology was developed in light of these circumstances, and aims to improve the dynamic range while suppressing a decrease in frame rate.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is an imaging device including a pixel capable of switching conversion efficiency, a comparator that compares a pixel signal read from the pixel with a first reference signal and a second reference signal, and a switching control unit that switches the conversion efficiency of the pixel based on a comparison result of the comparator, thereby providing an effect that the pixel signal is read out with different conversion efficiencies according to the level of the pixel signal.

[0007] In the first aspect, the digital signal processing device may further include a reference signal generating unit that generates the first reference signal and the second reference signal. This brings about an effect that a plurality of reference signals having different analog gains are input to the comparing unit.

[0008] In addition, in the first aspect, the digital signal processing device may further include a reference signal generator that generates the first reference signal, and an attenuator that attenuates the first reference signal to generate the second reference signal, thereby eliminating the need for a signal line that distributes the second reference signal to the comparator, and providing an effect that multiple reference signals with different analog gains are input to the comparator.

[0009] In addition, in the first aspect, the comparison unit may include a two-input first comparator and a two-input second comparator, the first reference signal being input to a first input of the two-input first comparator, the pixel signal being input to a second input of the two-input first comparator, the second reference signal being input to a first input of the two-input second comparator, and the pixel signal being input to a second input of the two-input second comparator. This brings about an effect that pixel signals read out at different conversion efficiencies are compared with a plurality of reference signals while enabling auto-zero.

[0010] In addition, in the first aspect, the two-input first comparator may include a first input transistor to which the first reference signal is input, a second input transistor to which the pixel signal is input, a first load transistor connected in series to the first input transistor, and a second load transistor connected in series to the second input transistor, and the two-input second comparator may include a third input transistor to which the second reference signal is input, a fourth input transistor to which the pixel signal is input, a third load transistor connected in series to the third input transistor, and a fourth load transistor connected in series to the fourth input transistor. This brings about an effect of configuring a comparison unit that compares pixel signals read out at different conversion efficiencies with a plurality of reference signals while enabling auto-zero.

[0011] In the first aspect, the comparison unit may include a four-input comparator, the pixel signal being input to a first input of the four-input comparator, the pixel signal being input to a second input of the four-input comparator, the first reference signal being input to a third input of the four-input comparator, and the second reference signal being input to a fourth input of the four-input comparator. This provides an effect that pixel signals read out at different conversion efficiencies are compared with a plurality of reference signals while enabling auto-zero by providing a single comparator.

[0012] In addition, in the first aspect, the four-input comparator may include a first input transistor to which the pixel signal is input, a second input transistor to which the pixel signal is input, a third input transistor to which the first reference signal is input, a fourth input transistor to which the second reference signal is input, a first load transistor connectable in series to the first input transistor and the second input transistor, and a second load transistor connectable in series to the third input transistor and the fourth input transistor. Thus, by providing four input transistors and two load transistors, an effect is achieved in which a comparison unit is configured that compares pixel signals read out at different conversion efficiencies with a plurality of reference signals while enabling auto-zero.

[0013] In addition, in the first aspect, the switching control unit may control switching between outputting a comparison result between the pixel signal and the first reference signal and outputting a comparison result between the pixel signal and the second reference signal, based on a comparison result of the comparator, thereby achieving switching of analog gain during comparison of pixel signals, in addition to switching of pixel conversion efficiency.

[0014] In the first aspect, the image sensor may further include a switch that switches between outputting a comparison result between the pixel signal and the first reference signal and outputting a comparison result between the pixel signal and the second reference signal, based on control by the switching control unit, thereby providing an effect that an analog gain for comparing pixel signals can be switched when the pixel conversion efficiency is switched.

[0015] In addition, in the first aspect, the first reset level may be AD converted based on a comparison result between a first reset level read from the pixel at a first conversion efficiency and the first reference signal, the second reset level may be AD converted based on a comparison result between a second reset level read from the pixel at a second conversion efficiency higher than the first conversion efficiency and the second reference signal, a determination may be made as to whether to switch between the first conversion efficiency and the second conversion efficiency based on the signal level read from the pixel at the second conversion efficiency, and the signal level read from the pixel at the first conversion efficiency or the second conversion efficiency switched based on the determination result may be AD converted. This brings about an effect that HDR is enabled with three A / D conversions (P phase → P phase → D phase) when reading from one pixel, while achieving CDS (Correlated Double Sampling) of pixel signals read at mutually different conversion efficiencies.

[0016] In the first aspect, the first reference signal may be selected when the signal level is AD converted at the first conversion efficiency, and the second reference signal may be selected when the signal level is AD converted at the second conversion efficiency, thereby providing an effect of switching the conversion efficiency when reading out the signal level and switching the analog gain when AD converting the signal level.

[0017] According to a second aspect, there is provided an imaging device including effective pixels having switchable conversion efficiencies, light-shielded pixels having switchable conversion efficiencies, a comparator that compares effective pixel signals read from the effective pixels and light-shielded pixel signals read from the light-shielded pixels with reference signals, respectively, and a switch control unit that switches the conversion efficiencies of the effective pixels based on the comparison result between the effective pixel signals and the reference signals, thereby providing the effect of reading out pixel signals with different conversion efficiencies according to the levels of the pixel signals.

[0018] In the second aspect, the image sensor may further include a correction unit that corrects the effective pixel signal based on a correction value calculated with reference to a comparison result between the light-shielded pixel signal and the reference signal, thereby achieving the effect of correcting the effective pixel signal while eliminating the need to read out the P-phase level of the effective pixel signal at a low conversion efficiency.

[0019] In addition, in the second aspect, the effective pixels may be arranged in a matrix in row and column directions, and the light-shielded pixels may be arranged in the row direction, thereby providing an effect that readout from the effective pixels and readout from the light-shielded pixels are performed sequentially for each row.

[0020] In the second aspect, the effective pixels may be arranged in a matrix in row and column directions, and the light-shielded pixels may be arranged in the column direction, thereby achieving the effect of reading out from the effective pixels and reading out from the light-shielded pixels in parallel for each row.

[0021] A third aspect is an imaging method that performs A / D conversion on a first reset level read out from an effective pixel at a first conversion efficiency, A / D converts a second reset level read out from the effective pixel at a second conversion efficiency higher than the first conversion efficiency, determines whether to switch between the first conversion efficiency and the second conversion efficiency based on the signal level read out from the effective pixel at the second conversion efficiency, and A / D converts the signal level read out from the effective pixel at the first conversion efficiency or the second conversion efficiency switched based on the determination result. This provides the effect of enabling HDR with three A / D conversions (P phase → P phase → D phase) when reading out from one pixel, while realizing correction of pixel signals read out at mutually different conversion efficiencies.

[0022] A fourth aspect is an imaging method including: AD converting a first reset level read from a first light-shielding pixel at a first conversion efficiency, AD converting a first signal level read from the first light-shielding pixel at the first conversion efficiency, AD converting a second reset level read from a second light-shielding pixel at the first conversion efficiency, AD converting a second signal level read from the second light-shielding pixel at a second conversion efficiency lower than the first conversion efficiency, and calculating a correction value for an effective pixel signal read from an effective pixel at the second conversion efficiency based on the AD conversion results of the first reset level, the first signal level, the second reset level, and the second signal level. This brings about an effect that the effective pixel signal is corrected based on the light-shielding signal read from the light-shielding pixel.

[0023] In addition, in the fourth aspect, a reset level read out from the effective pixel at the first conversion efficiency may be AD converted, a determination may be made as to whether to switch between the first conversion efficiency and the second conversion efficiency based on the signal level read out from the effective pixel at the first conversion efficiency, and the signal level read out from the effective pixel at the first conversion efficiency or the second conversion efficiency switched based on the determination result may be AD converted. This brings about an effect that HDR is enabled by two A / D conversions (P phase → D phase) when reading out from one pixel, while correction of pixel signals read out at mutually different conversion efficiencies is realized.

[0024] In a fourth aspect, the effective pixels may be arranged in a matrix in row and column directions, the first light-shielding pixels and the second light-shielding pixels may be arranged in the column direction, and reading from the first light-shielding pixels, reading from the second light-shielding pixels, and reading from the effective pixels may be performed sequentially, thereby providing an effect that the effective pixel signals are corrected based on the light-shielding pixels read out from two rows of light-shielding pixels.

[0025] In addition, in a fourth aspect, the effective pixels may be arranged in a matrix in row and column directions, the light-shielded pixels may be arranged in the row direction, and readout from the first light-shielded pixels, readout from the second light-shielded pixels, and readout from the effective pixels may be performed in parallel, thereby providing an effect that the effective pixel signals are corrected based on the light-shielded pixel signals read out from two columns of light-shielded pixels.

[0026] 1 is a block diagram showing an example of the configuration of an imaging device according to a first embodiment. FIG. 2 is a block diagram showing an example of the configuration of a solid-state imaging device according to the first embodiment. FIG. 3 is a diagram showing an example of the circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment. FIG. 4 is a block diagram showing an example of the configuration of an AD conversion unit according to the first embodiment. FIG. 5 is a diagram showing an example of the circuit configuration of a comparator according to the first embodiment. FIG. 6 is a diagram showing an example of the circuit configuration of a post-stage amplifier according to the first embodiment. FIG. 7 is a timing chart showing waveforms of each unit in a signal readout process according to the first embodiment. FIG. 8 is a block diagram showing an example of the configuration of an AD conversion unit according to the second embodiment. FIG. 9 is a diagram showing an example of the circuit configuration of a comparator according to the second embodiment. FIG. 10 is a block diagram showing an example of the configuration of a solid-state imaging device according to a third embodiment. FIG. 11 is a block diagram showing an example of the configuration of an AD conversion unit according to the third embodiment. FIG. 12 is a diagram showing an example of the circuit configuration of a comparator according to the third embodiment. FIG. 13 is a timing chart showing waveforms of each unit in a signal readout process according to the third embodiment. FIG. 14 is a block diagram showing an example of the configuration of a solid-state imaging device according to a fourth embodiment. FIG. 15 is a block diagram showing an example of the configuration of an AD conversion unit according to the fourth embodiment. FIG. 16 is a diagram showing an example of the circuit configuration of a comparator according to the fourth embodiment. FIG. 17 is a diagram showing an example of the circuit configuration of a comparator according to the fourth embodiment. FIG. 18 is a timing chart showing waveforms of each unit in a signal readout process according to the fourth embodiment. FIG. 10 is a timing chart showing waveforms of each part of a signal readout process according to a fourth embodiment. FIG. 11 is a block diagram showing a configuration example of a solid-state imaging device according to a fifth embodiment. FIG. 12 is a timing chart showing waveforms of each part of a signal readout process according to the fifth embodiment. FIG. 13 is a perspective view showing an example of a stack of a solid-state imaging device according to a sixth embodiment. FIG. 14 is a block diagram showing a schematic configuration example of a vehicle control system. FIG. 15 is an explanatory diagram showing an example of an installation position of an imaging unit.

[0027] Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described. The descriptions will be made in the following order: 1. First embodiment (an example in which two two-input comparators are provided for each column, reference signals having different slopes are input, and the conversion efficiency and analog gain of the AD conversion are switched based on the level of the pixel signal after AD conversion of the P-phase level read out at low conversion efficiency and AD conversion of the P-phase level read out at high conversion efficiency) 2. Second embodiment (an example in which one four-input comparator is provided for each column, reference signals having different slopes are input, and the conversion efficiency and analog gain of the AD conversion are switched based on the level of the pixel signal after AD conversion of the P-phase level read out at low conversion efficiency and AD conversion of the P-phase level read out at high conversion efficiency) 3. 3. Third Embodiment (an example in which one four-input comparator is provided for each column, and an attenuator that attenuates a reference signal is provided, and the conversion efficiency and analog gain of the AD conversion are switched based on the level of a pixel signal after AD conversion of a P-phase level read out at low conversion efficiency and AD conversion of a P-phase level read out at high conversion efficiency) 4. Fourth Embodiment (an example in which the conversion efficiency is switched based on the level of a pixel signal after AD conversion of a P-phase level read out at high conversion efficiency, and effective pixel signals read out at low conversion efficiency are corrected based on vertical light-shielded pixel signals read out from vertical light-shielded pixels) 5. Fifth Embodiment (an example in which the conversion efficiency is switched based on the level of a pixel signal after AD conversion of a P-phase level read out at high conversion efficiency, and effective pixel signals read out at low conversion efficiency are corrected based on horizontal light-shielded pixel signals read out from horizontal light-shielded pixels) 6. Sixth Embodiment (an example in which pixel array units are stacked) 7. Application to a Mobile Body

[0028] 1. First Embodiment FIG. 1 is a block diagram showing an example of the configuration of an imaging device according to a first embodiment.

[0029] In the figure, the imaging device 100 includes an optical system 101, a solid-state imaging device 102, an imaging control unit 103, an image processing unit 104, a storage unit 105, a display unit 106, and an operation unit 107. The imaging control unit 103, the image processing unit 104, the storage unit 105, the display unit 106, and the operation unit 107 are connected to one another via a bus 108. The imaging device 100 may be used as a standalone device, or may be incorporated into a mobile terminal such as a smartphone, an authentication device, a monitoring device, a vehicle, or a drone.

[0030] The optical system 101 causes light from a subject to be incident on the solid-state imaging device 102, and forms an optical image on the light-receiving surface of the solid-state imaging device 102. The optical system 101 may include, for example, a focus lens, a zoom lens, and an aperture. The optical system 101 may also include multiple lenses, such as a wide-angle lens, a standard lens, and a telephoto lens.

[0031] The solid-state imaging device 102 converts an optical image formed on the light-receiving surface into an electrical signal for each pixel, digitizes the electrical signal, and outputs it. At this time, the solid-state imaging device 102 can perform HDR by switching the pixel conversion efficiency. For example, the solid-state imaging device 102 can use pixel signals read with high conversion efficiency for dark areas of the screen and pixel signals read with low conversion efficiency for bright areas. Here, the solid-state imaging device 102 can read pixel signals by switching the conversion efficiency based on the level of the pixel signal. The solid-state imaging device 102 is, for example, a CMOS (Complementary Metal Oxide Semiconductor) image sensor. The CMOS image sensor may be a back-illuminated image sensor or a front-illuminated image sensor.

[0032] The imaging control unit 103 controls imaging by the solid-state imaging device 102 based on instructions from the operation unit 107. At this time, the imaging control unit 103 can control the exposure time, exposure amount, imaging timing, etc. of the solid-state imaging device 102.

[0033] The image processing unit 104 performs image processing based on the output from the solid-state imaging device 102. The image processing includes, for example, gamma correction, white balance processing, sharpness processing, and tone conversion processing. The image processing unit 104 may include a processor that executes processing based on software.

[0034] The storage unit 105 stores images captured by the solid-state imaging device 102 and stores imaging parameters of the solid-state imaging device 102. The storage unit 105 can also store a program that operates the imaging device 100 based on software. The storage unit 105 may include a read-only memory (ROM), a random access memory (RAM), and a memory card.

[0035] The display unit 106 displays captured images and various information that supports the image capturing operation. The display unit 106 may be a liquid crystal display, an organic EL (Electro Luminescence) display, or a micro LED display.

[0036] The operation unit 107 provides a user interface for operating the imaging device 100. The operation unit 107 may include, for example, buttons, dials, and switches provided on the imaging device 100. The operation unit 107 may be configured as a touch panel together with the display unit 106.

[0037] Depending on the configuration of the imaging device 100, some of the above functions may not be present, or conversely, the imaging device 100 may further include functions that are not disclosed.

[0038] FIG. 2 is a block diagram showing an example of the configuration of the solid-state imaging device according to the first embodiment.

[0039] In the figure, the solid-state imaging device 102 includes a pixel array section 111, a vertical scanning circuit 112, a column readout circuit 113, a column signal processing section 114, a horizontal scanning circuit 115, and a control circuit 116.

[0040] The pixel array unit 111 includes a plurality of cells 120. The cells 120 are arranged in a matrix along the row direction (also referred to as the horizontal direction) and the column direction (also referred to as the vertical direction). For example, four pixels may share one floating diffusion for each cell 120. Alternatively, eight pixels may share one floating diffusion for each cell 120, or each cell 120 may be composed of a single pixel. The cells 120 may form a source follower with the column readout circuit 113 during signal readout. Each cell 120 is connected to a horizontal drive line 131 in the row direction and to a vertical signal line 132 and a conversion efficiency switching line 133 in the column direction. The horizontal drive line 131 drives each cell 120 horizontally during signal readout from the cell 120. The vertical signal line 132 vertically transmits a potential based on the current flowing during signal readout from the cell 120 to the column signal processing unit 114. The conversion efficiency switching line 133 vertically transmits a switching signal for switching the conversion efficiency of each pixel included in the cell 120 to each cell 120. The switching signal can switch the conversion efficiency of the cell 120 between low conversion efficiency and high conversion efficiency.

[0041] The pixels included in the cell 120 may form a Bayer array or a quad-Bayer array. The light received by each pixel included in each cell 120 may be visible light, near infrared light (NIR), short wavelength infrared light (SWIR), ultraviolet light, X-rays, or the like.

[0042] The vertical scanning circuit 112 vertically scans each pixel included in the cell 120 to be read. The vertical scanning circuit 112 may be configured using a vertical register. The vertical scanning circuit 112 may include an address decoder or a driver that drives the horizontal drive line 131 selected via the address decoder for each row.

[0043] The column readout circuit 113 can form a source follower with each cell 120 when reading out a signal from the cell 120. At this time, the column readout circuit 113 can change the potential of the vertical signal line 132 based on the charge held in the cell 120.

[0044] The column signal processing unit 114 processes signals transmitted in the vertical direction from the cells 120. For example, the column signal processing unit 114 can perform correlated double sampling (CDS) processing based on the signals transmitted in the vertical direction from the cells 120. The column signal processing unit 114 can also perform AD (Analog to Digital) conversion processing based on the signals transmitted in the vertical direction from each cell 120, and output an imaging signal Gout.

[0045] The column signal processing unit 114 includes a column ADC unit 114A and a reference signal generation unit 114B. The reference signal generation unit 114B generates reference signals RH and RL and supplies them to the column ADC unit 114A. Each of the reference signals RH and RL may include a ramp wave for each of the P phase and the D phase. The slope of the ramp wave of the reference signal RH may be smaller than the slope of the ramp wave of the reference signal RL. In this case, when the reference signal RH is selected for AD conversion of the pixel signal, the analog gain can be higher than when the reference signal RL is selected. Furthermore, a threshold level for determining the magnitude of the pixel signal level can be set for the reference signal RH between the P phase and the D phase. Note that the P phase is the period during which the reset level is AD converted, and the D phase is the period during which the reset level and the pixel signal are AD converted.

[0046] The column ADC unit 114A can perform AD conversion processing in parallel for each column. At this time, the column ADC unit 114A can perform AD conversion for each column based on the comparison result between the pixel signal read from the cell 120 and the reference signals RH and RL. Here, the column ADC unit 114A can switch the conversion efficiency of the cell 120 to high conversion efficiency in dark areas of the screen and to low conversion efficiency in bright areas of the screen. Furthermore, a column including a cell 120 for which high conversion efficiency is selected can select the reference signal RL, and a column including a cell 120 for which low conversion efficiency is selected can select the reference signal RH. Furthermore, the column ADC unit 114A can determine the brightness of the screen based on the comparison result between the D-phase level of the pixel signal and the threshold level included in the reference signal RH.

[0047] The horizontal scanning circuit 115 scans, in the row direction, each pixel included in the cell 120 to be read out. The horizontal scanning circuit 115 may be configured using a horizontal register.

[0048] The control circuit 116 controls the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115. For example, the control circuit 116 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing unit 114. At this time, the control circuit 116 can coordinate the vertical scanning circuit 112, the column readout circuit 113, the column signal processing unit 114, and the horizontal scanning circuit 115 so that the accumulation operation, the shutter operation, and the read operation are performed for each row in each frame.

[0049] 3 is a diagram showing an example of the circuit configuration of a pixel provided in the solid-state imaging device according to the first embodiment, taking a four-pixel shared cell as an example.

[0050] In the figure, the cell 120 includes photodiodes PD1 to PD4, transfer transistors 121 to 124, a reset transistor 141, an amplifier transistor 142, a selection transistor 143, a switching transistor 144, a capacitor 145, and a floating diffusion FD. The transfer transistors 121 to 124, the reset transistor 141, the amplifier transistor 142, the selection transistor 143, and the switching transistor 144 may be MOS (Metal Oxide Semiconductor) transistors. The capacitor 145 may be a MOM (Metal Oxide Metal) capacitor or a MIM (Metal Insulation Metal) capacitor.

[0051] Each of the photodiodes PD1 to PD4 performs photoelectric conversion and accumulates the photoelectrically converted charges. Each of the transfer transistors 121 to 124 transfers the charges accumulated in each of the photodiodes PD1 to PD4 to the floating diffusion FD. The reset transistor 141 resets the floating diffusion FD. The amplification transistor 142 outputs a signal according to the potential of the floating diffusion FD. The selection transistor 143 selects the output of the amplification transistor 142. The switching transistor 144 switches the conversion efficiency of the amplification transistor 142. The capacitor 145 adjusts the conversion efficiency of the amplification transistor 142.

[0052] Each of the transfer transistors 121 to 124 is connected between the cathode of each of the photodiodes PD1 to PD4 and the floating diffusion FD. At this time, the floating diffusion FD is shared by the photodiodes PD1 to PD4. The amplification transistor 142 and the selection transistor 143 are connected in series. The drain of the amplification transistor 142 is connected to the power supply voltage VDD. The gate of the amplification transistor 142 is connected to the floating diffusion FD. The source of the selection transistor 143 is connected to the vertical signal line 132.

[0053] The switching transistor 144 is connected between the floating diffusion FD and the capacitor 145. The reset transistor 141 is connected between the floating diffusion FD and the power supply voltage VDD. The capacitor 145 is connected between the switching transistor 144 and the ground potential.

[0054] Transfer signals TGL1 to TGL4 are applied to the gates of the transfer transistors 121 to 124. A reset signal RST is applied to the gate of the reset transistor 141. A selection signal SEL is applied to the gate of the selection transistor 143. A switching signal FDG is applied to the gate of the switching transistor 144. The transfer signals TGL1 to TGL4, the reset signal RST, and the selection signal SEL can be transmitted to the cell 120 via a horizontal drive line 131. The switching signal FDG can be transmitted to the cell 120 via a conversion efficiency switching line 133.

[0055] 4 is a block diagram showing an example of the configuration of an AD conversion unit according to the first embodiment, which shows an example of the configuration of an AD conversion unit for one column.

[0056] In the figure, the column ADC unit 114A includes comparators CML1 and CMH1, a post-stage amplifier CM2, switches SWL and SWH, a latch circuit 151, a multiplexer 152, a counter 153, and a switching control unit 154 for each column. Each comparator CML1 and CMH1 can be configured as a two-input comparator. In this case, the non-inverting inputs of the comparators CML1 and CMH1 are connected to a vertical signal line 132 via input capacitors CL2 and CH2, respectively. A reference signal RL is applied to the inverting input of the comparator CML1 via an input capacitor CL1. A reference signal RH is applied to the inverting input of the comparator CMH1 via an input capacitor CH1. A vertical signal line 132 and a conversion efficiency switching line 133 are provided for each column.

[0057] The comparator CML1 compares the pixel signal transmitted via the vertical signal line 132 with the reference signal RL. At this time, the pixel signal is read out from the cell 120 with low conversion efficiency. The comparator CMH1 compares the pixel signal transmitted via the vertical signal line 132 with the reference signal RH. At this time, the pixel signal is read out from the cell 120 with high conversion efficiency.

[0058] Additionally, auto-zero signals AZL and AZH are input to the comparators CML1 and CMH1, respectively. The auto-zero signal AZL activates the auto-zero operation of the comparator CML1 during the auto-zero period. The auto-zero signal AZH activates the auto-zero operation of the comparator CMH1 during the auto-zero period. During the auto-zero operation, charges that balance the non-inverting and inverting inputs of the comparators CML1 and CMH1 can be accumulated in the input capacitors CL1, CH1, CL2, and CH2, respectively.

[0059] The switches SWL and SWH switch the outputs of the comparators CML1 and CMH1 to input them to the post-stage amplifier CM2.

[0060] The post-amplifier CM 2 amplifies the outputs of the comparators CML 1 and CMH 1 and inputs the amplified outputs to the latch circuit 151 and the multiplexer 152 .

[0061] The latch circuit 151 latches the output of the post-stage amplifier CM2 and inputs it to the multiplexer 152 and the switching control unit 154. The latch circuit 151 can latch the result of determining whether the D-phase level of the pixel signal is large or small.

[0062] The multiplexer 152 combines the output of the post-stage amplifier CM2 and the output of the latch circuit 151 into a single signal and inputs it to the counter 153.

[0063] The switching control unit 154 switches the switching signal FDG based on the result of determining whether the D-phase level of the pixel signal latched in the latch circuit 151 is large or small. Furthermore, the switching control unit 154 exclusively switches the switches SWL and SWH and exclusively activates the comparators CML1 and CMH1 based on the result of determining whether the D-phase level of the pixel signal latched in the latch circuit 151 is large or small. At this time, when the D-phase level of the pixel signal read out at the high conversion efficiency is equal to or higher than a threshold level, the switching control unit 154 switches the conversion efficiency of each pixel included in the cell 120 to low conversion efficiency and activates the comparator CML1. On the other hand, when the D-phase level of the pixel signal read out at the high conversion efficiency is lower than the threshold level, the switching control unit 154 switches the conversion efficiency of each pixel included in the cell 120 to high conversion efficiency and activates the comparator CMH1.

[0064] The counter 153 performs a counting operation based on the output timing of the comparison results of the comparators CML1 and CMH1. The counter 153 then digitizes the pixel signals transmitted via the vertical signal line 132 based on the count value generated by the counting operation, and outputs the digitized digital signal ADO.

[0065] 5 is a diagram showing an example of the circuit configuration of a comparator according to the first embodiment. Note that, in the diagram, the circuit configuration of the comparator CMH1 is taken as an example, but the comparator CML1 can also be configured in the same way.

[0066] In the figure, comparator CMH1 balances comparator inputs DVH1 and DVH2 based on auto-zero operation, and then outputs a voltage VCH corresponding to the difference between comparator inputs DVH1 and DVH2. Comparator CMH1 includes PMOS transistors 231 and 232, NMOS transistors 233, 234, 241, and 242, a capacitor 238, and switches 236 and 237. Note that PMOS transistors 231 and 232 are examples of load transistors recited in the claims. NMOS transistors 233 and 234 are examples of input transistors recited in the claims.

[0067] The PMOS transistor 231 and the NMOS transistor 233 are connected in series to each other. The PMOS transistor 232 and the NMOS transistor 234 are connected in series to each other. The sources of the PMOS transistors 231 and 232 are connected to the power supply potential VDD, and the gates of the PMOS transistors 231 and 232 are connected to the drain of the PMOS transistor 231. In this case, the PMOS transistors 231 and 232 can form a current mirror.

[0068] A reference signal RH is input via an input capacitor CH1 to the gate of the NMOS transistor 233. A potential VSL of the vertical signal line 132 is connected to the gate of the NMOS transistor 234 for each column via an input capacitor CH2.

[0069] A switch 236 is connected between the gate and drain of the NMOS transistor 233, and a switch 237 is connected between the gate and drain of the NMOS transistor 234. The sources of the NMOS transistors 233 and 234 are connected to the ground potential via NMOS transistors 241 and 242 in this order.

[0070] The switches 236 and 237 are opened and closed based on the auto-zero signal AZH. During the auto-zero period, the switches 236 and 237 are turned on based on the auto-zero signal AZH. At this time, current flows through the PMOS transistors 231 and 232 based on the current mirror operation of the PMOS transistors 231 and 232. Charge is then accumulated in the input capacitors CH1 and CH2 so that the non-inverting input and inverting input of the comparator CMH1 are balanced.

[0071] The capacitor 238 is connected in parallel to the PMOS transistor 232. The capacitor 238 can limit the band.

[0072] A switching signal SCM is applied to the gate of the NMOS transistor 241 from the switching control unit 154. At this time, the NMOS transistor 241 is turned on based on the switching signal SCM, thereby activating the comparator CMH1. Note that when the switching signal SCM is applied to the comparator CMH1, an inverted signal of the switching signal SCM can be applied to the comparator CML1.

[0073] A bias voltage VBN is applied to the gate of the NMOS transistor 242. The NMOS transistor 242 can operate as a constant current source based on the bias voltage VBN.

[0074] FIG. 6 is a diagram illustrating an example of a circuit configuration of a post-stage amplifier according to the first embodiment.

[0075] In the figure, the post-amplifier CM 2 includes a PMOS transistor 251 , an NMOS transistor 252 , a switch 253 , and a capacitor 254 .

[0076] The PMOS transistor 251 and the NMOS transistor 252 are connected in series. The source of the PMOS transistor 251 is connected to the power supply potential VDD. A switch 253 is connected between the gate and drain of the NMOS transistor 252. A capacitor 254 is connected between the gate of the NMOS transistor 252 and the ground potential. An input voltage VI is input to the gate of the PMOS transistor 251, and an output voltage VO is output from the drain of the NMOS transistor 252.

[0077] 7 is a timing chart showing waveforms of various parts of the signal readout process according to the first embodiment. Note that the diagram shows an example of waveforms for a 1H period (one horizontal synchronization period). The transfer signal TGL is one of the transfer signals TGL1 to TGL4.

[0078] In the figure, in this signal readout process, a low conversion efficiency P-phase readout period T1, a high conversion efficiency P-phase readout period T2, a level determination period T3, and a selective conversion efficiency D-phase readout period T4 are provided in a 1H period. In the reference signal RH, a ramp wave RPH is provided in the high conversion efficiency P-phase readout period T2, a threshold level RSH is provided in the level determination period T3, and a ramp wave RDH is provided in the selective conversion efficiency D-phase readout period T4. In the reference signal RL, a ramp wave RPL is provided in the low conversion efficiency P-phase readout period T1, and a ramp wave RDL is provided in the selective conversion efficiency D-phase readout period T4.

[0079] Before the low conversion efficiency P-phase read period T1, the reset signal RST rises, turning on the reset transistor 123 and resetting the floating diffusion FD. Also, before the low conversion efficiency P-phase read period T1, the auto-zero signal AZL rises, and charges are accumulated in the input capacitors CL1 and CL2 so that the non-inverting input and the inverting input of the comparator CML1 are balanced.

[0080] Next, during the low conversion efficiency P-phase read period T1, the switching signal FDG is set to a high level. At this time, the switching transistor 144 is turned on, and the conversion efficiency of the cell 120 is set to a low conversion efficiency. The switching signal SCM is also set to a high level, and the comparator CML1 is activated. At this time, the switch SWL is turned on, the switch SWH is turned off, and the comparator CML1 is connected to the post-amplifier CM2, while the comparator CMH1 is disconnected from the post-amplifier CM2.

[0081] Next, the reset signal RST falls, turning off the reset transistor 123, and then the auto-zero signal AZL falls. At this time, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the low conversion efficiency P-phase level of the floating diffusion FD is applied to the gate of the amplification transistor 142.

[0082] Next, in the comparator CML1, the potential VSL of the vertical signal line 132 corresponding to the low conversion efficiency P-phase level is compared with the ramp wave RPL, and the comparison result is output as the timing when the level of the ramp wave RPL matches the potential VSL of the vertical signal line 132. At this time, the low conversion efficiency P-phase level read out from the cell 120 is AD converted for each column based on the count operation until the level of the ramp wave RPL matches the potential VSL of the vertical signal line 132.

[0083] Next, during the high-conversion-efficiency P-phase readout period T2, the switching signal FDG is set to a low level. At this time, the switching transistor 144 is turned off, and the conversion efficiency of the cell 120 is set to high conversion efficiency. The switching signal SCM is also set to a low level, activating the comparator CMH1. At this time, the switch SWL is turned off and the switch SWH is turned on, connecting the comparator CMH1 to the post-amplifier CM2 and disconnecting the comparator CML1 from the post-amplifier CM2. The auto-zero signal AZH rises, and charge is accumulated in the input capacitors CH1 and CH2 so that the non-inverting and inverting inputs of the comparator CMH1 are balanced. The auto-zero signal AZH then falls. The potential VSL of the vertical signal line 132 is then set based on the source-follower operation when the high-conversion-efficiency P-phase level of the floating diffusion FD is applied to the gate of the amplifier transistor 142.

[0084] Next, in the comparator CMH1, the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency P-phase level is compared with the ramp wave RPH, and the comparison result is output as the timing when the level of the ramp wave RPH matches the potential VSL of the vertical signal line 132. At this time, the high conversion efficiency P-phase level read out from the cell 120 is AD converted for each column based on the count operation until the level of the ramp wave RPH matches the potential VSL of the vertical signal line 132.

[0085] Next, in the level determination period T3, when the transfer signal TGL rises, one of the transfer transistors 121 to 124 is turned on, and the charge accumulated in one of the photodiodes PD1 to PD4 is transferred to the floating diffusion FD.

[0086] Next, when the transfer signal TGL falls, the transfer transistors 121 to 124 are turned off. At this time, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency D-phase level of the floating diffusion FD is applied to the gate of the amplification transistor 142. Then, the comparator CMH1 compares the high conversion efficiency D-phase level with a threshold level RSH, and the comparison result is input to the switching control unit 154 via the latch circuit 151. Then, when the high conversion efficiency D-phase level is equal to or higher than the threshold level RSH, the switching control unit 154 switches the conversion efficiency of the cell 120 to low conversion efficiency, activates the comparator CML1, and turns on the switch SWL. On the other hand, when the high conversion efficiency D-phase level is lower than the threshold level, the switching control unit 154 activates the comparator CMH1 and turns on the switch SWH while keeping the conversion efficiency of each pixel included in the cell 120 at high conversion efficiency.

[0087] Next, in a selective conversion efficiency D-phase readout period T4, when the comparator CMH1 is activated, the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency D-phase level is compared with the ramp wave RDH, and the comparison result is output as the timing when the level of the ramp wave RDH matches the potential VSL of the vertical signal line 132. At this time, the high conversion efficiency D-phase level read out from the cell 120 is AD converted for each column based on the count operation until the level of the ramp wave RDH matches the potential VSL of the vertical signal line 132.

[0088] On the other hand, when the comparator CML1 is activated, the potential VSL of the vertical signal line 132 corresponding to the low conversion efficiency D phase level is compared with the ramp wave RDL, and the comparison result is output as the timing when the level of the ramp wave RDL matches the potential VSL of the vertical signal line 132. At this time, the low conversion efficiency D phase level read out from the cell 120 is AD converted for each column based on the count operation until the level of the ramp wave RDL matches the potential VSL of the vertical signal line 132.

[0089] As described above, in the first embodiment, two comparators CML1 and CMH1 are provided for each column, and a reference signal RL is input to comparator CML1, and a reference signal RH is input to comparator CMH1. Then, after AD conversion at the low-conversion-efficiency P-phase level and AD conversion at the high-conversion-efficiency P-phase level, the conversion efficiency and the analog gain of the AD conversion are switched based on the high-conversion-efficiency P-phase level. This enables HDR with three A / D conversions (P-phase → P-phase → D-phase) when reading from one pixel, while achieving CDS and auto-zero for pixel signals read at low and high conversion efficiencies. This allows for improved dynamic range and reduced power consumption while suppressing degradation in frame rate and image quality.

[0090] 2. Second Embodiment In the first embodiment described above, two comparators CML1 and CMH1 are provided for each column, and a reference signal RL is input to the comparator CML1, and a reference signal RH is input to the comparator CMH1. In this second embodiment, one four-input comparator is provided for each column, and the reference signals RL and RH are input to the four-input comparator.

[0091] 8 is a block diagram showing an example of the configuration of an AD conversion unit according to the second embodiment, which shows an example of the configuration of an AD conversion unit for one column.

[0092] In the figure, the column ADC unit 114A of the second embodiment includes a comparator CM1 instead of the comparators CML1 and CMH1 of the first embodiment. The rest of the configuration of the column ADC unit 114A of the second embodiment is the same as the configuration of the column ADC unit 114A of the first embodiment.

[0093] The comparator CM1 can be configured as a four-input comparator. In this case, the two non-inverting inputs of the comparator CM1 are connected to the vertical signal line 132 via input capacitors CL2 and CH2, respectively. A reference signal RL is applied to a first inverting input of the comparator CM1 via an input capacitor CL1. A reference signal RH is applied to a second inverting input of the comparator CM1 via an input capacitor CH1.

[0094] The comparator CM1 compares the pixel signal transmitted via the vertical signal line 132 with the reference signal RL. At this time, the pixel signal is read out from the cell 120 with high conversion efficiency. The comparator CM1 also compares the pixel signal transmitted via the vertical signal line 132 with the reference signal RH. At this time, the pixel signal is read out from the cell 120 with low conversion efficiency.

[0095] Additionally, auto-zero signals AZL and AZH are input to comparator CM1. The auto-zero signal AZL activates auto-zero operation during the auto-zero period for low conversion efficiency readout. The auto-zero signal AZH activates auto-zero operation during the auto-zero period for high conversion efficiency readout. In auto-zero operation, charges that balance the non-inverting and inverting inputs of comparator CM1 can be accumulated in the input capacitors CL1, CH1, CL2, and CH2, respectively.

[0096] FIG. 9 is a diagram illustrating an example of a circuit configuration of a comparator according to the second embodiment.

[0097] In the figure, comparator CM1 balances comparator inputs DVH1 and DVH2 based on auto-zero operation and outputs voltage VCH corresponding to the difference between comparator inputs DVH1 and DVH2. Also, comparator CM1 balances comparator inputs DVL1 and DVL2 based on auto-zero operation and outputs voltage VCL corresponding to the difference between comparator inputs DVL1 and DVL2. Comparator CM1 includes PMOS transistors 261 and 262, NMOS transistors 263, 264, 269, 273, and 274, a capacitor 268, and switches 271, 272, 281, and 282.

[0098] The PMOS transistor 261 and the NMOS transistor 263 are connected in series to each other. The PMOS transistor 262 and the NMOS transistor 264 are connected in series to each other. The sources of the PMOS transistors 261 and 262 are connected to the power supply potential VDD, and the gates of the PMOS transistors 261 and 262 are connected to the drain of the PMOS transistor 261. In this case, the PMOS transistors 261 and 262 can form a current mirror.

[0099] The PMOS transistor 261 and the NMOS transistor 263 are connected in series to each other. The PMOS transistor 262 and the NMOS transistor 264 are connected in series to each other. The NMOS transistor 273 is connected to the NMOS transistor 263 and the NMOS transistor 269. The NMOS transistor 274 is connected to the NMOS transistor 264 and the NMOS transistor 269. The sources of the PMOS transistors 261 and 262 are connected to the power supply potential VDD, and the gates of the PMOS transistors 261 and 262 are connected to the drain of the PMOS transistor 261. In this case, the PMOS transistors 261 and 262 can form a current mirror.

[0100] A reference signal RL is input to the gate of the NMOS transistor 263 via an input capacitor CL1. A reference signal RH is input to the gate of the NMOS transistor 273 via an input capacitor CH1. A potential VSL of the vertical signal line 132 is connected to the gate of the NMOS transistor 264 via an input capacitor CL2 for each column. A potential VSL of the vertical signal line 132 is connected to the gate of the NMOS transistor 274 via an input capacitor CH2 for each column.

[0101] A switch 266 is connected between the gate and drain of NMOS transistor 263, and a switch 267 is connected between the gate and drain of NMOS transistor 264. A switch 276 is connected between the gate and drain of NMOS transistor 273, and a switch 277 is connected between the gate and drain of NMOS transistor 274. The sources of NMOS transistors 263, 264, 273, and 274 are connected to the ground potential via NMOS transistor 269.

[0102] The switches 266 and 267 are opened and closed based on the auto-zero signal AZL. During the auto-zero period of low conversion efficiency readout, the switches 266 and 267 are turned on based on the auto-zero signal AZL. The switches 276 and 277 are opened and closed based on the auto-zero signal AZH. During the auto-zero period of high conversion efficiency readout, the switches 276 and 277 are turned on based on the auto-zero signal AZH. At this time, current flows through the PMOS transistors 261 and 262 based on the current mirror operation of the PMOS transistors 261 and 262. During both low conversion efficiency readout and high conversion efficiency readout, charge is accumulated in the input capacitors CH1, CH2, CL1, and CL2 so that the non-inverting input and the inverting input of the comparator CM1 are balanced.

[0103] A capacitor 268 is connected in parallel to the PMOS transistor 262. The capacitor 268 can limit the band.

[0104] A switching signal SCM is applied to the switches 281 and 282. At this time, the switches 281 and 282 are turned on based on the switching signal SCM, thereby activating the input of the reference signal RL and the potential VSL of the vertical signal line 132. A switching inversion signal SCB is applied to the switches 271 and 272. At this time, the switches 271 and 272 are turned on based on the switching inversion signal SCB, thereby activating the input of the reference signal RHL and the potential VSL of the vertical signal line 132. The switching inversion signal SCB is a signal obtained by inverting the switching signal SCM.

[0105] A bias voltage VBN is applied to the gate of the NMOS transistor 269. The NMOS transistor 269 can operate as a constant current source based on the bias voltage VBN.

[0106] The column ADC unit 114A of the second embodiment can operate in the same manner as the column ADC unit 114A of the first embodiment described above, and can perform AD conversion operations in accordance with the timing chart of FIG.

[0107] As described above, in the second embodiment, one comparator CM1 is provided for each column, and reference signals RL and RH are input to the comparator CM1. Then, after AD conversion at the low-conversion-efficiency P-phase level and AD conversion at the high-conversion-efficiency P-phase level, the conversion efficiency and the analog gain of the AD conversion are switched based on the high-conversion-efficiency P-phase level. This enables HDR with three A / D conversions (P-phase → P-phase → D-phase) when reading from one pixel, while achieving CDS and auto-zero for pixel signals read at low and high conversion efficiencies. This allows for improved dynamic range and reduced power consumption while suppressing degradation in frame rate and image quality.

[0108] Furthermore, compared to a configuration in which two comparators CML1 and CMH1 are provided for each column, the number of transistors can be reduced, making it possible to reduce the chip size and further reduce power consumption.

[0109] 3. Third Embodiment In the second embodiment described above, one comparator CM1 is provided for each column, and reference signals RL and RH are input to the comparator CM1. In this third embodiment, one comparator CM1 is provided for each column, and a reference signal RF is input to the comparator CM1, and the reference signal RF is attenuated and then input to the comparator CM1 via a separate system.

[0110] FIG. 10 is a block diagram showing an example of the configuration of a solid-state imaging device according to the third embodiment.

[0111] In the figure, this solid-state imaging device 302 includes a column signal processing unit 314 instead of the column signal processing unit 114 of the first embodiment described above. Other configurations of this solid-state imaging device 302 are similar to the configuration of the solid-state imaging device 102 of the first embodiment described above.

[0112] The column signal processing unit 314 includes a column ADC unit 314A and a reference signal generation unit 314B. The reference signal generation unit 314B generates a reference signal RA and supplies it to the column ADC unit 314A. Each reference signal RA may include a ramp wave for each of the P phase and the D phase. Furthermore, a threshold level for determining whether the D phase level of the pixel signal is large or small can be set between the P phase and the D phase for the reference signal RA.

[0113] The column ADC unit 314A can perform AD conversion processing in parallel for each column. At this time, the column ADC unit 314A can attenuate the reference signal RA for each column. The column ADC unit 314A can then perform AD conversion for each column based on the comparison result between the pixel signal read from each pixel included in the cell 120 and the reference signal RA or the comparison result between the pixel signal and the attenuated reference signal RA. Here, the column ADC unit 314A can switch the conversion efficiency of each pixel included in the cell 120 to high conversion efficiency in dark areas of the screen, and switch the conversion efficiency of each pixel included in the cell 120 to low conversion efficiency in bright areas of the screen. Furthermore, a column including a cell 120 for which high conversion efficiency is selected can select an attenuated reference signal RA, and a column including a cell 120 for which low conversion efficiency is selected can select the reference signal RA. The column ADC unit 314A can also determine the brightness or darkness of the screen based on the comparison result between the D-phase level of the pixel signal and the threshold level included in the reference signal RA.

[0114] 11 is a block diagram showing an example of the configuration of an AD conversion unit according to the third embodiment. Note that the diagram shows an example of the configuration of an AD conversion unit for one column.

[0115] In the figure, the column ADC unit 114A of the third embodiment includes a comparator CM1' and an attenuator 155 instead of the comparator CM1 and the input capacitor CH1 of the second embodiment. Other configurations of the column ADC unit 114A of the third embodiment are similar to the configuration of the column ADC unit 114A of the second embodiment.

[0116] The attenuator 155 attenuates the reference signal RA before applying it to the inverting input of the comparator CM1'. The attenuator 155 includes input capacitors CH11 and CH12. The input capacitor CH12 is connected in parallel to the input capacitor CH11. For example, if the capacitance of the input capacitor CL1 is 4 C, the capacitance of the input capacitor CH11 can be set to C, and the capacitance of the input capacitor CH12 can be set to 3 C. Here, the attenuator 155 can attenuate the reference signal RA by 1 / 4 before applying it to the inverting input of the comparator CM1'.

[0117] The comparator CM1' can be configured as a four-input comparator. In this case, the two non-inverting inputs of the comparator CM1' are connected to the vertical signal line 132 via input capacitors CL2 and CH2, respectively. The reference signal RA is applied to the first inverting input of the comparator CM1' via an input capacitor CL1. The reference signal RA is applied to the second inverting input of the comparator CM1' via an input capacitor CH11.

[0118] The comparator CM1' compares the pixel signal transmitted via the vertical signal line 132 with the attenuated reference signal RA. At this time, the pixel signal is read out from the cell 120 with high conversion efficiency. The comparator CM1' also compares the pixel signal transmitted via the vertical signal line 132 with the unattenuated reference signal RA. At this time, the pixel signal is read out from the cell 120 with low conversion efficiency.

[0119] Additionally, auto-zero signals AZL and AZH are input to the comparator CM1'. The auto-zero signal AZL activates the auto-zero operation during the auto-zero period for low conversion efficiency readout. The auto-zero signal AZH activates the auto-zero operation during the auto-zero period for high conversion efficiency readout. In the auto-zero operation, charges that balance the non-inverting and inverting inputs of the comparator CM1' can be accumulated in the input capacitors CL1, CL2, CH2, CH11, and CH12, respectively.

[0120] FIG. 12 is a diagram illustrating an example of a circuit configuration of a comparator according to the third embodiment.

[0121] In the figure, this comparator CM1' has input capacitors CH11 and CH12 instead of the input capacitor CH1 of the comparator CM1 of the second embodiment described above. Also, this comparator CM1' has switches 321, 322, and 331 to 336 added to the comparator CM1 of the second embodiment described above. Other configurations of the comparator CM1' of the third embodiment are similar to the configuration of the comparator CM1 of the second embodiment described above.

[0122] The reference signal RA is input to the gate of the NMOS transistor 263 via the switch 322 and the input capacitor CL1 in this order. The reference signal RA is also input to the gate of the NMOS transistor 273 via the switch 321 and the input capacitor CH11 in this order. The reference signal RA is also input to the gate of the NMOS transistor 273 via the switch 321, the input capacitor CH12, and the switch 330 in this order.

[0123] The connection point of the switch 321 and the input capacitor CH11 is grounded via a switch 331. The connection point of the switch 322 and the input capacitor CL1 is grounded via a switch 332. The connection point of the input capacitor CH11 and the gate of the NMOS transistor 273 is grounded via a switch 333. The connection point of the input capacitor CH12 and the switch 330 is grounded via a switch 334.

[0124] A switching signal SCM is input to the switches 322 and 331. An inverted switching signal SCB is input to the switches 321 and 332. Furthermore, by switching the switches 333 to 336, it is possible to switch the input capacitances CH11 and CH12 connected to the gate of the NMOS transistor 273. By switching the input capacitances CH11 and CH12 connected to the gate of the NMOS transistor 273, it is possible to switch the attenuation rate of the reference signal RA input to the gate of the NMOS transistor 273.

[0125] Here, when the conversion efficiency of cell 120 is set to low conversion efficiency, switches 322 and 331 are turned on and switches 321 and 332 are turned off, and reference signal RA is input to the gate of NMOS transistor 273 via input capacitor CL1. When the conversion efficiency of cell 120 is set to high conversion efficiency, switches 321 and 332 are turned on and switches 322 and 331 are turned off, and attenuated reference signal RA is input to the gate of NMOS transistor 273 via input capacitors CH11 and CH12.

[0126] FIG. 13 is a timing chart showing waveforms at various parts of the signal readout process according to the third embodiment.

[0127] 1, in this signal readout process, a high conversion efficiency P-phase readout period T2' is provided instead of the high conversion efficiency P-phase readout period T2. In the reference signal RA, a ramp wave RP1 is provided in the low conversion efficiency P-phase readout period T1, a ramp wave RP2 is provided in the high conversion efficiency P-phase readout period T2', a threshold level RSH is provided in the level determination period T3, and a ramp wave RD is provided in the selective conversion efficiency D-phase readout period T4.

[0128] During the low conversion efficiency P-phase read period T1, the comparator CM1′ compares the potential VSL of the vertical signal line 132 corresponding to the low conversion efficiency P-phase level with the ramp wave RP1, and outputs as a comparison result the timing when the level of the ramp wave RP1 matches the potential VSL of the vertical signal line 132. At this time, the low conversion efficiency P-phase level read from the cell 120 is AD converted for each column based on the count operation until the level of the ramp wave RP1 matches the potential VSL of the vertical signal line 132.

[0129] During the high conversion efficiency P-phase read period T2', the comparator CM1' compares the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency P-phase level with the ramp wave RP2, and outputs as a comparison result the timing when the level of the ramp wave RP2 matches the potential VSL of the vertical signal line 132. At this time, the high conversion efficiency P-phase level read from the cell 120 is AD converted for each column based on the count operation until the level of the ramp wave RP2 matches the potential VSL of the vertical signal line 132.

[0130] During the level determination period T3, the comparator CM1' compares the high conversion efficiency D-phase level with a threshold level RSH, and the comparison result is input to the switching control unit 154 via the latch circuit 151. When the high conversion efficiency D-phase level is equal to or higher than the threshold level RSH, the switching control unit 154 switches the conversion efficiency of each pixel included in the cell 120 to low conversion efficiency and turns on the switches 281, 282, 322, and 331. At this time, the comparator CM1' compares the low conversion efficiency D-phase level with the unattenuated reference signal RA input via the input capacitor CL1. On the other hand, when the high conversion efficiency D-phase level is lower than the threshold level, the switching control unit 154 switches the conversion efficiency of each pixel included in the cell 120 to high conversion efficiency and turns on the switches 271, 272, 321, and 332. At this time, in the comparator CM1', the high conversion efficiency D-phase level is compared with the reference signal RA attenuated via the input capacitors CH11 and CH12.

[0131] During the selective conversion efficiency D-phase readout period T4, when the switches 271, 272, 321, and 332 are turned on, the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency D-phase level is compared with the ramp wave RD attenuated via the input capacitances CH11 and CH12. The timing at which the level of the ramp wave RD attenuated via the input capacitances CH11 and CH12 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, the high conversion efficiency D-phase level read out from the cell 120 is AD-converted for each column based on the count operation until the level of the ramp wave RD attenuated via the input capacitances CH11 and CH12 matches the potential VSL of the vertical signal line 132.

[0132] On the other hand, when the switches 281, 282, 322, and 331 are turned on, the potential VSL of the vertical signal line 132 corresponding to the low conversion efficiency D-phase level is compared with the unattenuated ramp wave RD input via the input capacitance CL1. The timing at which the level of the unattenuated ramp wave RD input via the input capacitance CL1 matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, the low conversion efficiency D-phase level read from the cell 120 is AD converted for each column based on the count operation until the level of the unattenuated ramp wave RD input via the input capacitance CL1 matches the potential VSL of the vertical signal line 132.

[0133] As described above, in the third embodiment, one comparator CM1' is provided for each column, and an unattenuated reference signal RF is input to the comparator CM1. The reference signal RF is attenuated and then input to the comparator CM1 via a separate system. After AD conversion at the low-conversion-efficiency P-phase level and AD conversion at the high-conversion-efficiency P-phase level, the conversion efficiency and the analog gain of the AD conversion are switched based on the high-conversion-efficiency P-phase level. This enables HDR with three A / D conversions (P-phase → P-phase → D-phase) when reading from one pixel, while achieving CDS and auto-zero for pixel signals read at low and high conversion efficiencies. This allows for improved dynamic range and reduced power consumption while suppressing degradation in frame rate and image quality.

[0134] Furthermore, by attenuating the reference signal RF and then inputting it to the comparator CM1 via a separate system, the analog gain of the AD conversion can be changed based on the distribution of one reference signal RF. Therefore, compared to when two reference signals RL and RH are input to each comparator CM1, the wiring space used for distributing the reference signal RF can be reduced, and the chip size can be reduced.

[0135] 4. Fourth Embodiment In the first embodiment described above, two comparators CML1 and CMH1 are provided for each column, and a reference signal RL is input to the comparator CML1, and a reference signal RH is input to the comparator CMH1. In this fourth embodiment, effective pixel signals read out at low conversion efficiency are corrected based on vertical light-shielded pixel signals read out from vertical light-shielded pixels (light-shielded pixels provided by expanding the pixel area in the vertical direction).

[0136] FIG. 14 is a block diagram showing an example of the configuration of a solid-state imaging device according to the fourth embodiment.

[0137] In the figure, the solid-state imaging device 402 includes a pixel array section 411 , a vertical scanning circuit 412 , a column readout circuit 113 , a column signal processing section 414 , a horizontal scanning circuit 115 , a control circuit 416 , and a correction section 417 .

[0138] The pixel array section 411 includes a plurality of cells 120 and light-shielding cells 420. The cells 120 are arranged in a matrix along the row and column directions. The light-shielding cells 420 are arranged along the row direction. In this case, two rows of light-shielding cells 420 may be provided. The light-shielding cells 420 may be arranged at the upper end of the pixel array section 411. In this case, the pixel array section 411 may be provided with a plurality of effective rows in which the cells 120 are arranged and first and second light-shielding rows in which the light-shielding cells 420 are arranged. The cells 120 may be provided with effective pixels, and the light-shielding cells 420 may be provided with vertical light-shielding pixels. The effective pixels can receive incident light. The vertical light-shielding pixels are shielded from incident light. The light-shielding cells 420 may be configured similarly to the cells 120, except that the effective pixels are provided in the cells 120 and the vertical light-shielding pixels are provided in the light-shielding cells 420.

[0139] Each cell 120 and each light-shielding cell 420 is connected to a horizontal drive line 431 in the row direction. Furthermore, each cell 120 and each light-shielding cell 420 is connected to a vertical signal line 432 and a conversion efficiency switching line 433 in the column direction. The horizontal drive line 431 drives each cell 120 horizontally when reading out a signal from the cell 120, and drives each light-shielding cell 420 horizontally when reading out a signal from the light-shielding cell 420. The vertical signal line 432 vertically transmits a potential based on a current flowing when reading out a signal from the cell 120 to the column signal processing unit 414, and vertically transmits a potential based on a current flowing when reading out a signal from the light-shielding cell 420 to the column signal processing unit 414. The conversion efficiency switching line 433 vertically transmits a switching signal for switching the conversion efficiency of the cell 120 to each cell 120, and vertically transmits a switching signal for switching the conversion efficiency of the light-shielding cell 420 to each light-shielding cell 420. The switching signal can switch the conversion efficiency of the cell 120 and the conversion efficiency of the light-shielding cell 420 between low conversion efficiency and high conversion efficiency.

[0140] The vertical scanning circuit 412 vertically scans each effective pixel included in the cell 120 to be read and each light-shielded pixel included in the light-shielded cell 420. The vertical scanning circuit 412 may be configured using a vertical register. The vertical scanning circuit 412 may include an address decoder, or may include a driver that drives the horizontal drive line 431 selected via the address decoder for each row.

[0141] The column signal processing unit 414 processes signals transmitted in the vertical direction from the cells 120 and the light-shielding cells 420. For example, the column signal processing unit 414 can perform correlated double sampling based on the signals transmitted in the vertical direction from the cells 120. The column signal processing unit 414 can also perform AD conversion based on the signals transmitted in the vertical direction from each cell 120 and output an image pickup signal Gout. The column signal processing unit 414 can also output an AD conversion result Aout of the vertical light-shielding pixel signals transmitted in the vertical direction from the light-shielding cells 420.

[0142] The column signal processing unit 414 includes a column ADC unit 414A and a reference signal generating unit 414B. The reference signal generating unit 414B generates a reference signal RF and supplies it to the column ADC unit 414A. The reference signal RF can include a ramp wave referenced for AD conversion of the effective pixel signals read out from the cells 120 and a ramp wave referenced for AD conversion of the vertical light-shielded pixel signals read out from the light-shielded cells 420.

[0143] The column ADC unit 414A can perform AD conversion processing for each column on the effective pixel signals read out from the cells 120 and the vertical light-shielded pixel signals read out from the light-shielded cells 420. At this time, the column ADC unit 414A can perform AD conversion for each column based on the comparison result between the effective pixel signals read out from each effective pixel included in the cells 120 and the reference signal RF, or can perform AD conversion for each column based on the comparison result between the vertical light-shielded pixel signals read out from each vertical light-shielded pixel included in the light-shielded cells 420 and the reference signal RF. Here, the column ADC unit 414A can switch the conversion efficiency of each effective pixel included in the cells 120 to high conversion efficiency in dark areas of the screen and switch the conversion efficiency of each effective pixel included in the cells 120 to low conversion efficiency in bright areas of the screen. Furthermore, the column ADC unit 414A can determine the brightness or darkness of the screen based on the comparison result between the D-phase level of the effective pixel signal and the threshold level included in the reference signal RF.

[0144] The control circuit 416 controls the vertical scanning circuit 412, the column readout circuit 113, the column signal processing unit 414, and the horizontal scanning circuit 115. For example, the control circuit 416 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 113, and the processing timing of the column signal processing unit 414. In this case, the control circuit 416 can coordinate the vertical scanning circuit 412, the column readout circuit 113, the column signal processing unit 414, and the horizontal scanning circuit 115 so that the accumulation operation, the shutter operation, and the read operation are performed for each row in each frame.

[0145] The correction unit 417 calculates a correction value based on the AD conversion result Aout of the vertical light-shielded pixel signal, and can correct the effective pixel signal based on the correction value. The correction based on this correction value can be applied to the effective pixel signal read out with low conversion efficiency. For the effective pixel signal read out with high conversion efficiency, CDS can be applied.

[0146] 15 is a block diagram showing an example of the configuration of an AD conversion unit according to the fourth embodiment. Note that the diagram shows an example of the configuration of an AD conversion unit for one column.

[0147] In the figure, the column ADC unit 414A includes a comparator CM11 and a switching control unit 454 instead of the comparators CML1 and CMH1 and the switching control unit 154 of the first embodiment described above. Furthermore, the column ADC unit 414A is configured by removing the switches SWL and SWH from the column ADC unit 114A of the first embodiment described above. The comparator CM11 can be configured as a two-input comparator. In this case, the non-inverting input of the comparator CM11 is connected to the vertical signal line 132 via an input capacitor C2. A reference signal RF is applied to the inverting input of the comparator CM11 via an input capacitor C1. The rest of the configuration of the column ADC unit 414A is the same as the configuration of the column ADC unit 114A of the first embodiment described above.

[0148] The comparator CM11 compares the effective pixel signal and the vertical light-shielded pixel signal transmitted via the vertical signal line 132 with a reference signal RF. The effective pixel signal is a signal read out from the effective pixel included in the cell 120. The vertical light-shielded pixel signal is a signal read out from the vertical light-shielded pixel included in the light-shielded cell 420.

[0149] The comparator CM11 also receives an auto-zero signal AZ, which activates an auto-zero operation during an auto-zero period. During the auto-zero operation, charges can be accumulated in the input capacitors C1 and C2, which balance the non-inverting and inverting inputs of the comparator CM11, respectively.

[0150] The switching control unit 454 switches the switching signal FDG based on the result of determining whether the D-phase level of the effective pixel signal latched in the latch circuit 151 is large or small. At this time, when the D-phase level of the effective pixel signal read out at the high conversion efficiency is equal to or higher than a threshold level, the switching control unit 454 switches the conversion efficiency of each pixel included in the cell 120 to low conversion efficiency. On the other hand, when the D-phase level of the effective pixel signal read out at the high conversion efficiency is lower than the threshold level, the switching control unit 454 switches the conversion efficiency of each pixel included in the cell 120 to high conversion efficiency.

[0151] FIG. 16 is a diagram illustrating an example of a circuit configuration of a comparator according to the fourth embodiment.

[0152] In the figure, the comparator CM11 is the same as the comparator CMH1 of the first embodiment described above, except that the NMOS transistor 241 is removed. In this case, the sources of the NMOS transistors 233 and 234 are connected to the ground potential via an NMOS transistor 242. The rest of the configuration of the comparator CM11 is the same as the configuration of the comparator CMH1 of the first embodiment described above.

[0153] 17 and 18 are timing charts showing waveforms at various parts of a signal readout process according to the fourth embodiment. FIG. 17 shows waveforms at various parts of a readout process of vertical shaded pixel signals read out from shaded cells 420. FIG. 17 shows an example of waveforms over a 2H period. FIG. 18 shows waveforms at various parts of a readout process of effective pixel signals read out from cells 120. FIG. 18 shows an example of waveforms over a 1H period.

[0154] 17, the readout process of vertical shaded pixel signals includes a first shaded row readout period P1 and a second shaded row readout period P2. In the first shaded row readout period P1 and the second shaded row readout period P2, vertical shaded pixel signals are read out from vertical shaded pixels in different rows.

[0155] The first light-shielded LOW readout period P1 includes a 1H period including a high conversion efficiency P-phase readout period T11, a settling period T12, and a high conversion efficiency D-phase readout period T13. The second light-shielded LOW readout period P2 includes a 1H period including a high conversion efficiency P-phase readout period T14, a settling period T15, and a low conversion efficiency D-phase readout period T16. For the reference signal RF, a ramp wave RPH1 is provided in the high conversion efficiency P-phase readout period T11, a ramp wave RDH is provided in the high conversion efficiency D-phase readout period T13, a ramp wave RPH2 is provided in the high conversion efficiency P-phase readout period T14, and a ramp wave RDL is provided in the low conversion efficiency D-phase readout period T16.

[0156] Before the high conversion efficiency P-phase read period T11, the reset signal RST of the light-shielding cells 420 of the first light-shielding row rises, the reset transistor 123 of the light-shielding cells 420 of the first light-shielding row turns on, and the floating diffusion FD is reset.

[0157] Next, in the high conversion efficiency P-phase read period T11, the switching signal FDG of the light-shielding cells 420 of the first light-shielding row is set to low level, at which point the switching transistors 144 of the light-shielding cells 420 of the first light-shielding row are turned off, and the conversion efficiency of the light-shielding cells 420 of the first light-shielding row is set to high conversion efficiency.

[0158] Next, the reset signal RST of the light-shielding cells 420 of the first light-shielding row falls, turning off the reset transistors 123 of the light-shielding cells 420 of the first light-shielding row. At this time, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high-conversion-efficiency P-phase level of the floating diffusion FD of the light-shielding cells 420 of the first light-shielding row is applied to the gate of the amplification transistor 142.

[0159] Next, in the comparator CM11, the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency P-phase level of the light-shielded cells 420 of the first light-shielded row is compared with the ramp wave RPH1, and the comparison result is output as the timing when the level of the ramp wave RPH1 matches the potential VSL of the vertical signal line 132. At this time, the high conversion efficiency P-phase level read out from the light-shielded cells 420 of the first light-shielded row is AD-converted for each column based on the count operation until the level of the ramp wave RPH1 matches the potential VSL of the vertical signal line 132.

[0160] Next, in a settling period T12, when the transfer signal TGL of the light-shielding cells 420 of the first light-shielding row rises, one of the transfer transistors 121 to 124 of the light-shielding cells 420 of the first light-shielding row turns on, and the charge accumulated in one of the photodiodes PD1 to PD4 is transferred to the floating diffusion FD. After that, the transfer signal TGL of the light-shielding cells 420 of the first light-shielding row falls, and the transfer transistors 121 to 124 of the light-shielding cells 420 of the first light-shielding row turn off. Then, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high-conversion-efficiency D-phase level of the floating diffusion FD of the light-shielding cells 420 of the first light-shielding row is applied to the gate of the amplification transistor 142.

[0161] Next, in a high conversion efficiency D-phase readout period T13, the comparator CM11 compares the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency D-phase level of the light-shielded cells 420 of the first light-shielded row with the ramp wave RDH, and outputs as a comparison result the timing when the level of the ramp wave RDH matches the potential VSL of the vertical signal line 132. At this time, the high conversion efficiency D-phase level read out from the light-shielded cells 420 of the first light-shielded row is AD-converted for each column based on the count operation until the level of the ramp wave RDH matches the potential VSL of the vertical signal line 132.

[0162] Next, before the high conversion efficiency P-phase read period T14, the reset signal RST of the light-shielding cells 420 of the second light-shielding row rises, the reset transistor 123 of the light-shielding cells 420 of the second light-shielding row is turned on, and the floating diffusion FD is reset.

[0163] Next, in the high conversion efficiency P-phase read period T14, the switching signal FDG of the light-shielding cells 420 of the second light-shielding row is set to low level, and the switching transistors 144 of the light-shielding cells 420 of the second light-shielding row are turned off, and the conversion efficiency of the light-shielding cells 420 of the second light-shielding row is set to high conversion efficiency.

[0164] Next, the reset signal RST of the light-shielding cells 420 of the second light-shielding row falls, turning off the reset transistors 123 of the light-shielding cells 420 of the second light-shielding row. At this time, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high-conversion-efficiency P-phase level of the floating diffusion FD of the light-shielding cells 420 of the second light-shielding row is applied to the gate of the amplification transistor 142.

[0165] Next, in the comparator CM11, the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency P-phase level of the light-shielded cells 420 of the second light-shielding row is compared with the ramp wave RPH2, and the comparison result is output as the timing when the level of the ramp wave RPH2 matches the potential VSL of the vertical signal line 132. At this time, the high conversion efficiency P-phase level read out from the light-shielded cells 420 of the second light-shielding row is AD-converted for each column based on the count operation until the level of the ramp wave RPH2 matches the potential VSL of the vertical signal line 132.

[0166] Next, during the settling period T15, when the transfer signal TGL of the light-shielding cells 420 of the second light-shielding row rises, one of the transfer transistors 121 to 124 of the light-shielding cells 420 of the second light-shielding row turns on, and the charge accumulated in one of the photodiodes PD1 to PD4 is transferred to the floating diffusion FD. Then, the transfer signal TGL of the light-shielding cells 420 of the second light-shielding row falls, and the transfer transistors 121 to 124 of the light-shielding cells 420 of the second light-shielding row turn off. Furthermore, the switching signal FDG of the light-shielding cells 420 of the second light-shielding row is set to a high level. At this time, the switching transistor 144 of the light-shielding cells 420 of the second light-shielding row turns on, and the conversion efficiency of the light-shielding cells 420 of the second light-shielding row is set to a low conversion efficiency. The potential VSL of the vertical signal line 132 is set based on the source follower operation when the low conversion efficiency D-phase level of the floating diffusion FD of the light-shielded cell 420 of the second light-shielded row is applied to the gate of the amplifying transistor 142 .

[0167] Next, in a low conversion efficiency D-phase readout period T16, the comparator CM11 compares the potential VSL of the vertical signal line 132 corresponding to the low conversion efficiency D-phase level of the light-shielded cells 420 of the second light-shielding row with the ramp wave RDL, and outputs as a comparison result the timing when the level of the ramp wave RDL matches the potential VSL of the vertical signal line 132. At this time, the low conversion efficiency D-phase level read out from the light-shielded cells 420 of the second light-shielding row is AD-converted for each column based on the count operation until the level of the ramp wave RDL matches the potential VSL of the vertical signal line 132.

[0168] 18 , in the readout process of the effective pixel signal, a high conversion efficiency P-phase readout period T17, a level determination period T18, and a selective conversion efficiency D-phase readout period T19 are provided in a 1H period. For the reference signal RF, a ramp wave RPH is provided in the high conversion efficiency P-phase readout period T17, a threshold level RSH is provided in the level determination period T18, and a ramp wave RD is provided in the selective conversion efficiency D-phase readout period T19.

[0169] Before the high conversion efficiency P-phase read period T17, the reset signal RST of the cell 120 rises, the reset transistor 123 of the cell 120 is turned on, and the floating diffusion FD is reset.

[0170] Next, in a high conversion efficiency P-phase read period T17, the switching signal FDG of the cell 120 is set to low level. At this time, the switching transistor 144 of the cell 120 is turned off, and the conversion efficiency of the cell 120 is set to high conversion efficiency.

[0171] Next, the reset signal RST of the cell 120 falls, turning off the reset transistor 123 of the cell 120. At this time, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency P-phase level of the floating diffusion FD of the cell 120 is applied to the gate of the amplification transistor 142.

[0172] Next, in the comparator CM11, the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency P-phase level of the cell 120 is compared with the ramp wave RPH, and the comparison result is output as the timing when the level of the ramp wave RPH matches the potential VSL of the vertical signal line 132. At this time, the high conversion efficiency P-phase level read out from the cell 120 is AD converted for each column based on the count operation until the level of the ramp wave RPH matches the potential VSL of the vertical signal line 132.

[0173] Next, in the level determination period T18, when the transfer signal TGL of the cell 120 rises, one of the transfer transistors 121 to 124 of the cell 120 turns on, and the charge accumulated in one of the photodiodes PD1 to PD4 is transferred to the floating diffusion FD.

[0174] Next, when the transfer signal TGL of the cell 120 falls, the transfer transistors 121 to 124 of the cell 120 are turned off. At this time, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency D-phase level of the floating diffusion FD of the cell 120 is applied to the gate of the amplification transistor 142. Then, the comparator CM11 compares the high conversion efficiency D-phase level of the cell 120 with a threshold level RSH, and the comparison result is input to the switching control unit 454 via the latch circuit 151. Then, when the high conversion efficiency D-phase level is equal to or higher than the threshold level RSH, the switching control unit 454 switches the conversion efficiency of the cell 120 to low conversion efficiency. On the other hand, when the high conversion efficiency D-phase level is lower than the threshold level, the switching control unit 454 switches the conversion efficiency of the cell 120 to high conversion efficiency.

[0175] Next, in a selective conversion efficiency D-phase readout period T19, when the conversion efficiency of the cell 120 is switched to high conversion efficiency, the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency D-phase level of the cell 120 is compared with the ramp wave RD, and the timing when the level of the ramp wave RD matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, the high conversion efficiency D-phase level read out from the cell 120 is AD converted for each column based on the count operation until the level of the ramp wave RD matches the potential VSL of the vertical signal line 132.

[0176] On the other hand, when the conversion efficiency of the cell 120 is switched to low conversion efficiency, the potential VSL of the vertical signal line 132 corresponding to the low conversion efficiency D phase level of the cell 120 is compared with the ramp wave RD, and the timing when the level of the ramp wave RD matches the potential VSL of the vertical signal line 132 is output as the comparison result. At this time, the low conversion efficiency D phase level read out from the cell 120 is AD converted for each column based on the count operation until the level of the ramp wave RD matches the potential VSL of the vertical signal line 132.

[0177] Here, for the effective pixel signals read out from the cells 120 with high conversion efficiency, CDS can be performed based on the high conversion efficiency P-phase level and the high conversion efficiency D-phase level, thereby improving the image quality.

[0178] On the other hand, for the effective pixel signals read out from the cells 120 at low conversion efficiency, CDS cannot be performed because the low conversion efficiency P-phase level is not read out. At this time, the correction unit 417 can calculate a correction value HOS based on the vertical light-shielded pixel signals read out from the light-shielded cells 420 in order to correct the effective pixel signals read out from the cells 120 at low conversion efficiency. This correction value HOS can be given by the following equation (1).

[0179] HOS={D(HCG)-P(HCG)}-{D(LCG)-P(HCG)} =DK(HCG)-DK(LCG)≒P(HCG)-P(LCG)...(1)

[0180] where D(HCG) is a high-conversion-efficiency D-phase effective pixel signal. P(HCG) is a high-conversion-efficiency P-phase effective pixel signal. D(LCG) is a low-conversion-efficiency D-phase effective pixel signal. P(LCG) is a low-conversion-efficiency P-phase effective pixel signal. DK(HCG) is a high-conversion-efficiency D-phase vertical light-shielded pixel signal. DK(LCG) is a high-conversion-efficiency D-phase vertical light-shielded pixel signal. At this time, the correction unit 417 can store D(HCG), P(HCG), D(LCG), P(LCG), DK(HCG), and DK(LCG).

[0181] The correction unit 417 can correct the effective pixel signal read from the cell 120 with low conversion efficiency based on the following equation (2) by referring to the correction value HOS: D(LCG)-P(HCG)+HOS≈D(LCG)-P(LCG) (2)

[0182] As described above, in the fourth embodiment, after AD conversion of the P-phase level read out at high conversion efficiency, the conversion efficiency is switched based on the D-phase level of the pixel signal. At this time, the effective pixel signal read out at low conversion efficiency is corrected based on the vertical light-shielded pixel signal read out from the vertical light-shielded pixel. This enables HDR with two A / D conversions (P-phase → D-phase) when reading out from one pixel, while also achieving correction of pixel signals read out at low and high conversion efficiencies. This makes it possible to improve the dynamic range while suppressing degradation in frame rate and image quality, and also achieve low power consumption.

[0183] Furthermore, since only one comparator CM11 is required for each column, the number of transistors can be reduced compared to a configuration in which two comparators CML1 and CMH1 are provided for each column, which allows for a reduction in chip size and further reduction in power consumption.

[0184] 5. Fifth Embodiment In the above-described fourth embodiment, effective pixel signals read out at low conversion efficiency are corrected based on vertical light-shielded pixel signals read out from vertical light-shielded pixels. In this fifth embodiment, effective pixel signals read out at low conversion efficiency are corrected based on horizontal light-shielded pixel signals read out from horizontal light-shielded pixels (light-shielded pixels provided by expanding the pixel area in the horizontal direction).

[0185] FIG. 19 is a block diagram showing an example of the configuration of a solid-state imaging device according to the fifth embodiment.

[0186] In the figure, the solid-state imaging device 502 includes a pixel array unit 511 , a vertical scanning circuit 112 , a column readout circuit 513 , a column signal processing unit 514 , a horizontal scanning circuit 515 , a control circuit 516 , and a correction unit 417 .

[0187] The pixel array section 511 includes a plurality of cells 120 and light-shielding cells 520. The light-shielding cells 520 are arranged in the column direction. In this case, two columns of light-shielding cells 520 can be provided. The light-shielding cells 520 may be arranged at both ends of the pixel array section 511. In this case, the pixel array section 511 can be provided with a plurality of active columns in which the cells 120 are arranged, and first and second light-shielding columns in which the light-shielding cells 520 are arranged. The light-shielding cells 520 can be provided with horizontal light-shielding pixels. The horizontal light-shielding pixels are shielded from incident light. The light-shielding cells 520 can be configured similarly to the light-shielding cells 420, except that their arrangement within the pixel array section 511 is different.

[0188] Each cell 120 and each light-shielding cell 520 is connected to a horizontal drive line 531 in the row direction. Furthermore, each cell 120 and each light-shielding cell 520 is connected to a vertical signal line 532 and a conversion efficiency switching line 533 in the column direction. The horizontal drive line 531 drives each cell 120 and each light-shielding cell 520 horizontally when reading out an effective pixel signal from each cell 120 and a horizontal light-shielding pixel signal from each light-shielding cell 520. The vertical signal line 532 vertically transmits, to the column signal processing unit 514, a potential based on a current flowing when a signal is read out from the cell 120 and a potential based on a current flowing when a signal is read out from the light-shielding cell 520. The conversion efficiency switching line 533 vertically transmits a switching signal for switching the conversion efficiency of the cell 120 and the conversion efficiency of the light-shielding cell 520 to each cell 120 and each light-shielding cell 520. The switching signal can switch the conversion efficiency of the cell 120 and the conversion efficiency of the light-shielding cell 520 between low conversion efficiency and high conversion efficiency.

[0189] The column readout circuit 513 can form a source follower between each cell 120 and each light-shielded cell 520 when reading out the effective pixel signal from the cell 120 and the horizontal light-shielded pixel signal from the light-shielded cell 520. At this time, the column readout circuit 513 can change the potential of the vertical signal line 532 based on the charge held in the cell 120, and can also change the potential of the vertical signal line 532 based on the charge held in the light-shielded cell 520.

[0190] The column signal processing unit 514 processes the effective pixel signals transmitted vertically from the cells 120 and the horizontal light-shielded pixel signals transmitted vertically from the light-shielded cells 520. For example, the column signal processing unit 514 can perform correlated double sampling based on the effective pixel signals transmitted vertically from the cells 120. The column signal processing unit 514 can also perform AD conversion based on the effective pixel signals transmitted vertically from each cell 120 and output an image pickup signal Gout. The column signal processing unit 514 can also output an AD conversion result Aout of the horizontal light-shielded pixel signals transmitted vertically from the light-shielded cells 520.

[0191] The column signal processing unit 514 includes a column ADC unit 514A and a reference signal generating unit 514B. The reference signal generating unit 514B generates a reference signal RB and supplies it to the column ADC unit 514A. The reference signal RB is referenced for AD conversion of the effective pixel signals read out from the cells 120 and can include a ramp wave referenced for AD conversion of the horizontal light-shielded pixel signals read out from the light-shielded cells 520.

[0192] The column ADC unit 514A can perform AD conversion processing in parallel for each column on the effective pixel signals read from the cells 120 and the horizontal light-shielded pixel signals read from the light-shielded cells 520. The column ADC unit 514A can perform AD conversion for each column based on the comparison result between the effective pixel signals read from the cells 120 and the reference signal RB, or can perform AD conversion for each column based on the comparison result between the horizontal light-shielded pixel signals read from the light-shielded cells 520 and the reference signal RB. The column ADC unit 514A can switch the conversion efficiency of the cells 120 to high conversion efficiency in dark areas of the screen and to low conversion efficiency in bright areas of the screen. The column ADC unit 514A can also determine the brightness or darkness of the screen based on the comparison result between the D-phase level of the effective pixel signal and the threshold level included in the reference signal RB. The column ADC unit 514A can be provided with the AD conversion unit shown in FIG. 15 for each column.

[0193] The horizontal scanning circuit 515 scans, in the row direction, each effective pixel included in the cell 120 to be read and each horizontal light-shielded pixel included in the light-shielded cell 520. The horizontal scanning circuit 515 may be configured using a horizontal register.

[0194] The control circuit 516 controls the vertical scanning circuit 112, the column readout circuit 513, the column signal processing unit 514, and the horizontal scanning circuit 515. For example, the control circuit 516 can control the scanning timing in the column direction, the scanning timing in the row direction, the operation timing of the column readout circuit 513, and the processing timing of the column signal processing unit 514. In this case, the control circuit 516 can coordinate the vertical scanning circuit 112, the column readout circuit 513, the column signal processing unit 514, and the horizontal scanning circuit 515 so that the accumulation operation, the shutter operation, and the read operation are performed for each row in each frame.

[0195] FIG. 20 is a timing chart showing waveforms at various parts of the signal readout process according to the fifth embodiment.

[0196] 1, in the readout process of this signal, a high conversion efficiency P-phase readout period T21, a level determination period T23, and a selective conversion efficiency D-phase readout period T24 are set up in one H period. For the reference signal RB, a ramp wave RPH is set up in the high conversion efficiency P-phase readout period T21, a threshold level RSH is set up in the level determination period T23, and a ramp wave RD is set up in the selective conversion efficiency D-phase readout period T24. In the readout process of this signal, readout processes of effective pixel signals, horizontal light-shielded pixel signals of the first light-shielded column, and horizontal light-shielded pixel signals of the second light-shielded column are performed in parallel.

[0197] Note that VSL is the potential of the vertical signal line 132 of the active column, VSL1 is the potential of the vertical signal line 132 of the first light-shielding column, and VSL2 is the potential of the vertical signal line 132 of the second light-shielding column. FDG is a switching signal for the conversion efficiency of the active column, FDG1 is a switching signal for the conversion efficiency of the first light-shielding column, and FDG2 is a switching signal for the conversion efficiency of the second light-shielding column. ADO is a digital signal for the active column, ADO1 is a digital signal for the first light-shielding column, and ADO2 is a digital signal for the second light-shielding column.

[0198] Before the high conversion efficiency P-phase read period T21, the reset signal RST rises, the reset transistor 123 is turned on, and the floating diffusion FD is reset.

[0199] Next, in a high conversion efficiency P-phase read period T21, the switching signals FDG, FDG1, and FDG2 are set to a low level, and the switching transistors 144 are turned off for the active column, the first light-shielded column, and the second light-shielded column, and the conversion efficiencies of the cells 120 and the light-shielded cells 520 are set to the high conversion efficiency.

[0200] Next, the reset signal RST falls, turning off the reset transistor 123. At this time, for the active column, the potential VSL of the vertical signal line 132 is set based on the source follower operation when the high conversion efficiency P-phase level of the floating diffusion FD of the cell 120 is applied to the gate of the amplifier transistor 142. Furthermore, for each of the first and second light-shielded columns, the potentials VSL1 and VSL2 of the vertical signal line 132 are set based on the source follower operation when the high conversion efficiency P-phase level of the floating diffusion FD of the light-shielded cell 520 is applied to the gate of the amplifier transistor 142.

[0201] Next, in the comparator CM11, the potentials VSL, VSL1, and VSL2 of the vertical signal line 132 corresponding to the high conversion efficiency P-phase level are compared in parallel with the ramp wave RPH, and the comparison result is output as the timing when the level of the ramp wave RPH matches the potentials VSL, VSL1, and VSL2 of the vertical signal line 132. At this time, the high conversion efficiency P-phase levels read out from the cells 120 and the light-shielded cells 520 are AD-converted for each column based on the counting operation until the level of the ramp wave RPH matches the potentials VSL, VSL1, and VSL2 of the vertical signal line 132.

[0202] Next, in the level determination period T23, when the transfer signal TGL rises for each of the active column, the first light-shielded column, and the second light-shielded column, one of the transfer transistors 121 to 124 of the cell 120 and the light-shielded cell 520 is turned on, and the charge accumulated in one of the photodiodes PD1 to PD4 is transferred to the floating diffusion FD.

[0203] Next, when the transfer signal TGL falls, the transfer transistors 121 to 124 of the cell 120 and the light-shielding cell 520 are turned off. Thereafter, the switching signal FDG2 for the second light-shielding column is set to a high level. At this time, the switching transistor 144 of the light-shielding cell 520 in the second light-shielding column is turned on, and the conversion efficiency of the light-shielding cell 520 in the second light-shielding column is set to a low conversion efficiency. At this time, the potential VSL of the vertical signal line 132 is set based on the source-follower operation when the high-conversion-efficiency D-phase level of the floating diffusion FD of the cell 120 is applied to the gate of the amplifier transistor 142. Furthermore, for each of the first and second light-shielding columns, the potentials VSL1 and VSL2 of the vertical signal line 132 are set based on the source-follower operation when the high-conversion-efficiency D-phase level of the floating diffusion FD of the light-shielding cell 520 is applied to the gate of the amplifier transistor 142.

[0204] Then, in the comparator CM11, the high conversion efficiency D phase level of the cell 120 is compared with the threshold level RSH, and the comparison result is input to the switching control unit 454 via the latch circuit 151. Then, when the high conversion efficiency D phase level of the cell 120 is equal to or higher than the threshold level RSH, the switching control unit 454 switches the conversion efficiency of the cell 120 to low conversion efficiency. On the other hand, when the high conversion efficiency D phase level of the cell 120 is lower than the threshold level, the switching control unit 454 switches the conversion efficiency of the cell 120 to high conversion efficiency.

[0205] Next, in a selective conversion efficiency D-phase readout period T24, the comparator CM11 compares the potential VSL1 of the vertical signal line 132 corresponding to the high conversion efficiency D-phase level of the light-shielded cell 520 of the first light-shielded column with the ramp wave RD, and outputs as a comparison result the timing when the level of the ramp wave RD matches the potential VSL1 of the vertical signal line 132. At this time, the high conversion efficiency D-phase level of the first light-shielded column read out from the light-shielded cell 520 is AD-converted based on the counting operation until the level of the ramp wave RD matches the potential VSL1 of the vertical signal line 132.

[0206] Furthermore, in the comparator CM11, the potential VSL2 of the vertical signal line 132 corresponding to the low conversion efficiency D-phase level of the light-shielded cell 520 of the second light-shielded column is compared with the ramp wave RD, and the comparison result is output as the timing when the level of the ramp wave RD matches the potential VSL2 of the vertical signal line 132. At this time, the low conversion efficiency D-phase level of the second light-shielded column read out from the light-shielded cell 520 is AD-converted based on the counting operation until the level of the ramp wave RD matches the potential VSL2 of the vertical signal line 132.

[0207] Furthermore, when the conversion efficiency of the cell 120 is switched to high conversion efficiency, the comparator CM11 compares the potential VSL of the vertical signal line 132 corresponding to the high conversion efficiency D-phase level of the cell 120 with the ramp wave RD, and outputs as a comparison result the timing when the level of the ramp wave RD matches the potential VSL of the vertical signal line 132. At this time, the high conversion efficiency D-phase level read out from the cell 120 is AD converted for each column based on the count operation until the level of the ramp wave RD matches the potential VSL of the vertical signal line 132.

[0208] On the other hand, when the conversion efficiency of the cell 120 is switched to low conversion efficiency, the comparator CM11 compares the potential VSL of the vertical signal line 132 corresponding to the low conversion efficiency D phase level of the cell 120 with the ramp wave RD, and outputs as a comparison result the timing when the level of the ramp wave RD matches the potential VSL of the vertical signal line 132. At this time, the low conversion efficiency D phase level read out from the cell 120 is AD converted for each column based on the count operation until the level of the ramp wave RD matches the potential VSL of the vertical signal line 132.

[0209] At this time, the correction unit 417 can store D(HCG), P(HCG), D(LCG), P(LCG), DK(HCG), and DK(LCG). Then, the correction unit 417 can correct the effective pixel signal read out from the cell 120 with low conversion efficiency based on the above-mentioned equations (1) and (2).

[0210] As described above, in the fifth embodiment, after AD conversion of the P-phase level read out at high conversion efficiency, the conversion efficiency is switched based on the D-phase level of the pixel signal. At this time, the effective pixel signal read out at low conversion efficiency is corrected based on the horizontal light-shielded pixel signal read out from the horizontal light-shielded pixel. This enables HDR with two A / D conversions (P-phase → D-phase) when reading out from one pixel, while also achieving correction of pixel signals read out at low and high conversion efficiencies. This makes it possible to improve the dynamic range while suppressing degradation of frame rate and image quality, and also achieve low power consumption.

[0211] Furthermore, since only one comparator CM11 is required for each column, the number of transistors can be reduced compared to a configuration in which two comparators CML1 and CMH1 are provided for each column, which allows for a reduction in chip size and further reduction in power consumption.

[0212] 6. Sixth Embodiment In the first embodiment described above, two comparators CML1 and CMH1 are provided for each column, and a reference signal RL is input to the comparator CML1, and a reference signal RH is input to the comparator CMH1. In this sixth embodiment, semiconductor chips each having a pixel array portion in which pixels are arranged in a matrix are stacked.

[0213] FIG. 21 is a perspective view showing an example of a stack of pixel array units according to the sixth embodiment.

[0214] In the figure, the solid-state imaging device includes semiconductor chips 921 and 922. The semiconductor chip 922 is stacked on the semiconductor chip 921.

[0215] A pixel array section 923 is formed in the semiconductor chip 922. In the pixel array section 923, pixels 931 are arranged in a matrix in the row and column directions. Pad electrodes 932 and via electrodes 933 are formed around the pixel array section 923. The via electrodes 933 penetrate the semiconductor chip 922 and can electrically connect the semiconductor chips 921 and 922 to each other.

[0216] A peripheral circuit 924 is formed on the semiconductor chip 921. A column readout circuit 925, a column ADC 926, a communication interface 927, and an oscillator circuit 928 are formed on the peripheral circuit 924. The column readout circuit 925 and the column ADC 926 may be formed so as to correspond to positions on both sides of the pixel array unit 923 in the column direction. The solid-state imaging device according to any one of the first to fifth embodiments described above can be formed on the semiconductor chips 921 and 922.

[0217] The semiconductor chips 921 and 922 may be directly bonded to each other. Hybrid bonding can be used for directly bonding the semiconductor chips 921 and 922. In this case, the semiconductor chips 921 and 922 may be electrically connected based on Cu-Cu bonding. The material of the semiconductor substrate used for the semiconductor chips 921 and 922 may be Si, InGaAs, or InP.

[0218] As described above, in the sixth embodiment, the semiconductor chip 922 on which the pixel array unit 923 is formed is stacked on the semiconductor chip 921 on which the peripheral circuit 924 is formed. This makes it possible to increase the sensitivity of the solid-state imaging device while suppressing an increase in the mounting area of ​​the semiconductor chip on which the solid-state imaging device is formed.

[0219] 7. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0220] FIG. 22 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0221] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 22, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (interface) 12053.

[0222] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0223] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0224] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0225] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0226] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0227] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0228] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0229] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0230] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 22, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0231] FIG. 23 is a diagram showing an example of the installation position of the imaging unit 12031.

[0232] In FIG. 23, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0233] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0234] 23 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0235] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0236] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which runs autonomously without relying on driver operation.

[0237] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0238] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0239] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 of the above-described configuration. Specifically, for example, the imaging devices according to the first to sixth embodiments described above can be applied to the imaging unit 12031. By applying the technology according to the present disclosure to the vehicle control system 12000, it is possible to improve the dynamic range while suppressing a decrease in frame rate.

[0240] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology with the same title correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist. Furthermore, the effects described in this specification are merely examples and are not limited, and other effects may also be present.

[0241] The present technology may also have the following configurations: (1) An imaging device comprising: a pixel capable of switching conversion efficiency; a comparator that compares a pixel signal read from the pixel with a first reference signal and a second reference signal; and a switching control unit that switches the conversion efficiency of the pixel based on a comparison result of the comparator. (2) The imaging device described in (1), further comprising: a reference signal generator that generates the first reference signal and the second reference signal. (3) The imaging device described in (1), further comprising: a reference signal generator that generates the first reference signal; and an attenuator that attenuates the first reference signal to generate the second reference signal. (4) The imaging device according to any one of (1) to (3), wherein the comparison unit includes a two-input first comparator and a two-input second comparator, wherein the first reference signal is input to a first input of the two-input first comparator, the pixel signal is input to a second input of the two-input first comparator, the second reference signal is input to a first input of the two-input second comparator, and the pixel signal is input to a second input of the two-input second comparator. (5) The imaging device according to (4), wherein the two-input first comparator comprises: a first input transistor to which the first reference signal is input, a second input transistor to which the pixel signal is input, a first load transistor connected in series to the first input transistor, and a second load transistor connected in series to the second input transistor, and the two-input second comparator comprises: a third input transistor to which the second reference signal is input, a fourth input transistor to which the pixel signal is input, a third load transistor connected in series to the third input transistor, and a fourth load transistor connected in series to the fourth input transistor. (6) The imaging device according to any of (1) to (3), wherein the comparison unit comprises a four-input comparator, wherein the pixel signal is input to a first input of the four-input comparator, the pixel signal is input to a second input of the four-input comparator, the first reference signal is input to a third input of the four-input comparator, and the second reference signal is input to a fourth input of the four-input comparator.(7) The imaging device according to (6), wherein the four-input comparator comprises: a first input transistor to which the pixel signal is input, a second input transistor to which the pixel signal is input, a third input transistor to which the first reference signal is input, a fourth input transistor to which the second reference signal is input, a first load transistor connectable in series to the first input transistor and the second input transistor, and a second load transistor connectable in series to the third input transistor and the fourth input transistor. (8) The imaging device according to any of (1) to (7), wherein the switching control unit controls switching between outputting a comparison result between the pixel signal and the first reference signal and outputting a comparison result between the pixel signal and the second reference signal based on a comparison result of the comparator. (9) The imaging device according to any of (1) to (8), further comprising: a switch that switches between outputting a comparison result between the pixel signal and the first reference signal and outputting a comparison result between the pixel signal and the second reference signal based on control of the switching control unit. (10) The imaging device according to any one of (1) to (9), which performs AD conversion on a first reset level read out from the pixel at a first conversion efficiency based on a comparison result between the first reference signal and the first reset level, performs AD conversion on a second reset level read out from the pixel at a second conversion efficiency higher than the first conversion efficiency based on a comparison result between the second reference signal and the second reset level, determines whether to switch between the first conversion efficiency and the second conversion efficiency based on the signal level read out from the pixel at the second conversion efficiency, and performs AD conversion on the signal level read out from the pixel at the first conversion efficiency or the second conversion efficiency switched based on the determination result. (11) The imaging device according to (10), which selects the first reference signal when AD converting the signal level at the first conversion efficiency, and selects the second reference signal when AD converting the signal level at the second conversion efficiency.(12) An imaging device comprising: effective pixels capable of switching conversion efficiency; light-shielded pixels capable of switching conversion efficiency; a comparison unit that compares each of effective pixel signals read from the effective pixels and light-shielded pixel signals read from the light-shielded pixels with a reference signal; and a switching control unit that switches the conversion efficiency of the effective pixels based on a comparison result between the effective pixel signal and the reference signal. (13) The imaging device according to (12), further comprising: a correction unit that corrects the effective pixel signal based on a correction value calculated with reference to a comparison result between the light-shielded pixel signal and the reference signal. (14) The imaging device according to (12) or (13), wherein the effective pixels are arranged in a matrix in row and column directions, and the light-shielded pixels are arranged in the row direction. (15) The imaging device according to (12) or (13), wherein the effective pixels are arranged in a matrix in row and column directions, and the light-shielded pixels are arranged in the column direction. (16) An imaging method comprising: A / D converting a first reset level read out from an effective pixel at a first conversion efficiency; A / D converting a second reset level read out from the effective pixel at a second conversion efficiency higher than the first conversion efficiency; determining whether to switch between the first conversion efficiency and the second conversion efficiency based on the signal level read out from the effective pixel at the second conversion efficiency; and A / D converting the signal level read out from the effective pixel at the first conversion efficiency or the second conversion efficiency switched based on the determination result. (17) An imaging method comprising: AD converting a first reset level read out from a first light-shielding pixel at a first conversion efficiency; AD converting a first signal level read out from the first light-shielding pixel at the first conversion efficiency; AD converting a second reset level read out from a second light-shielding pixel at the first conversion efficiency; AD converting a second signal level read out from the second light-shielding pixel at a second conversion efficiency lower than the first conversion efficiency; and calculating a correction value for an effective pixel signal read out from an effective pixel at the second conversion efficiency based on a result of the AD conversion of the first reset level, a result of the AD conversion of the first signal level, a result of the AD conversion of the second reset level, and a result of the AD conversion of the second signal level.(18) The imaging method according to (17), comprising: A / D converting a reset level read out from the effective pixels at the first conversion efficiency; determining whether to switch between the first conversion efficiency and the second conversion efficiency based on the signal level read out from the effective pixels at the first conversion efficiency; and A / D converting the signal level read out from the effective pixels at the first conversion efficiency or the second conversion efficiency switched based on the determination result. (19) The imaging method according to (17) or (18), wherein the effective pixels are arranged in a matrix in row and column directions, the first light-shielding pixels and the second light-shielding pixels are arranged in the column direction, and readout from the first light-shielding pixels, readout from the second light-shielding pixels, and readout from the effective pixels are performed sequentially. (20) The imaging method described in (17) or (18), wherein the effective pixels are arranged in a matrix in row and column directions, the light-shielding pixels are arranged in the row direction, and readout from the first light-shielding pixels, readout from the second light-shielding pixels, and readout from the effective pixels are performed in parallel.

[0242] REFERENCE SIGNS LIST 100 Imaging device 101 Optical system 102 Solid-state imaging device 103 Imaging control unit 104 Image processing unit 105 Memory unit 106 Display unit 107 Operation unit 108 Bus 111 Pixel array unit 112 Vertical scanning circuit 113 Column readout circuit 114 Column signal processing unit 115 Horizontal scanning circuit 116 Control circuit 120 Cell 131 Horizontal drive line 132 Vertical signal line 133 Conversion efficiency switching line CL1, CL2, CH1, CH2 Input capacitance CML1, CMH1 Comparator CM2 Post-stage amplifier SWL, SWH Switch 151 Latch circuit 152 Multiplexer 153 Counter 154 Switching control unit

Claims

1. An imaging device comprising: a pixel capable of switching conversion efficiency; a comparison unit that compares a pixel signal read from the pixel with a first reference signal and a second reference signal; and a switching control unit that switches the conversion efficiency of the pixel based on the comparison result of the comparison unit.

2. The imaging device according to claim 1, further comprising a reference signal generating unit that generates the first reference signal and the second reference signal.

3. The imaging device according to claim 1, further comprising: a reference signal generating unit that generates the first reference signal; and an attenuator that attenuates the first reference signal to generate the second reference signal.

4. The imaging device of claim 1, wherein the comparison unit comprises a two-input first comparator and a two-input second comparator, the first reference signal is input to a first input of the two-input first comparator, the pixel signal is input to a second input of the two-input first comparator, the second reference signal is input to a first input of the two-input second comparator, and the pixel signal is input to a second input of the two-input second comparator.

5. The imaging device described in claim 4, wherein the two-input first comparator comprises: a first input transistor to which the first reference signal is input; a second input transistor to which the pixel signal is input; a first load transistor connected in series to the first input transistor; and a second load transistor connected in series to the second input transistor; and the two-input second comparator comprises: a third input transistor to which the second reference signal is input; a fourth input transistor to which the pixel signal is input; a third load transistor connected in series to the third input transistor; and a fourth load transistor connected in series to the fourth input transistor.

6. The imaging device according to claim 1, wherein the comparison unit comprises a four-input comparator, the pixel signal being input to a first input of the four-input comparator, the pixel signal being input to a second input of the four-input comparator, the first reference signal being input to a third input of the four-input comparator, and the second reference signal being input to a fourth input of the four-input comparator.

7. The imaging device described in claim 6, wherein the four-input comparator comprises: a first input transistor to which the pixel signal is input; a second input transistor to which the pixel signal is input; a third input transistor to which the first reference signal is input; a fourth input transistor to which the second reference signal is input; a first load transistor connectable in series to the first input transistor and the second input transistor; and a second load transistor connectable in series to the third input transistor and the fourth input transistor.

8. The imaging device according to claim 1, wherein the switching control unit controls switching between outputting the comparison result between the pixel signal and the first reference signal and outputting the comparison result between the pixel signal and the second reference signal based on the comparison result of the comparison unit.

9. The imaging device according to claim 1, further comprising a switch that switches between outputting the result of the comparison between the pixel signal and the first reference signal and outputting the result of the comparison between the pixel signal and the second reference signal based on the control of the switching control unit.

10. The imaging device of claim 1, further comprising: A / D converting a first reset level read from the pixel at a first conversion efficiency based on a comparison result between the first reference signal and the first reset level; A / D converting a second reset level read from the pixel at a second conversion efficiency higher than the first conversion efficiency based on a comparison result between the second reference signal and the second reset level; determining whether to switch between the first conversion efficiency and the second conversion efficiency based on the signal level read from the pixel at the second conversion efficiency; and A / D converting a signal level read from the pixel at the first conversion efficiency or the second conversion efficiency switched based on the determination result.

11. The imaging device according to claim 10, wherein the first reference signal is selected when the signal level is AD converted at the first conversion efficiency, and the second reference signal is selected when the signal level is AD converted at the second conversion efficiency.

12. An imaging device comprising: effective pixels capable of switching conversion efficiency; light-shielded pixels capable of switching conversion efficiency; a comparison unit that compares effective pixel signals read from the effective pixels and light-shielded pixel signals read from the light-shielded pixels with reference signals; and a switching control unit that switches the conversion efficiency of the effective pixels based on the comparison result between the effective pixel signals and the reference signals.

13. The imaging device according to claim 12, further comprising a correction unit that corrects the effective pixel signal based on a correction value calculated by referring to a comparison result between the light-shielded pixel signal and the reference signal.

14. The imaging device according to claim 12, wherein the effective pixels are arranged in a matrix in row and column directions, and the light-shielding pixels are arranged in the row direction.

15. The imaging device according to claim 12, wherein the effective pixels are arranged in a matrix in row and column directions, and the light-shielding pixels are arranged in the column direction.

16. An imaging method comprising: AD converting a first reset level read out from an effective pixel at a first conversion efficiency; AD converting a second reset level read out from the effective pixel at a second conversion efficiency higher than the first conversion efficiency; determining whether to switch between the first conversion efficiency and the second conversion efficiency based on the signal level read out from the effective pixel at the second conversion efficiency; and AD converting the signal level read out from the effective pixel at the first conversion efficiency or the second conversion efficiency switched based on the determination result.

17. An imaging method comprising: AD converting a first reset level read from a first light-shielding pixel at a first conversion efficiency; AD converting a first signal level read from the first light-shielding pixel at the first conversion efficiency; AD converting a second reset level read from a second light-shielding pixel at the first conversion efficiency; AD converting a second signal level read from the second light-shielding pixel at a second conversion efficiency lower than the first conversion efficiency; and calculating a correction value for an effective pixel signal read from an effective pixel at the second conversion efficiency based on the AD conversion result of the first reset level, the AD conversion result of the first signal level, the AD conversion result of the second reset level, and the AD conversion result of the second signal level.

18. The imaging method according to claim 17, further comprising: A / D converting a reset level read out from the effective pixel at the first conversion efficiency; determining whether to switch between the first conversion efficiency and the second conversion efficiency based on the signal level read out from the effective pixel at the first conversion efficiency; and A / D converting the signal level read out from the effective pixel at the first conversion efficiency or the second conversion efficiency switched out based on the determination result.

19. The imaging method according to claim 17, wherein the effective pixels are arranged in a matrix in row and column directions, the first light-shielding pixels and the second light-shielding pixels are arranged in the column direction, and readout from the first light-shielding pixels, readout from the second light-shielding pixels, and readout from the effective pixels are performed sequentially.

20. The imaging method according to claim 17, wherein the effective pixels are arranged in a matrix in row and column directions, the light-shielding pixels are arranged in the row direction, and readout from the first light-shielding pixels, readout from the second light-shielding pixels, and readout from the effective pixels are performed in parallel.

Images