Display backplane and display apparatus

Abstract

A display backplane and a display apparatus. The display backplane comprises: a plurality of first signal lines (1), which extend in a first direction and are sequentially arranged in a second direction, wherein the first direction intersects with the second direction; a plurality of second signal lines (2), which extend in the second direction and are sequentially arranged in the first direction, wherein each first signal line (1) is connected to at least one second signal line (2), and in a direction perpendicular to the display backplane, the second signal lines (2) and the first signal lines (1) overlap with each other; and a plurality of electrostatic protection units (601), which are electrically connected to the first signal lines (1), wherein in the direction perpendicular to the display backplane, each electrostatic protection unit (601) is located between two adjacent second signal lines (2), and the electrostatic protection unit (601) overlaps with the two adjacent second signal lines (2), respectively.

Description

Display back panel and display device

[0001] This application claims priority to the Chinese patent application filed on March 4, 2024, with application number 202410245478.4 and invention name “Display backplane and display device”, the content of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to but is not limited to display technology, and in particular to a display backplane and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, and extremely fast response times. With the continuous advancement of display technology, display devices using OLEDs as light-emitting elements and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0004] However, static electricity exists during the preparation of the display backplane, which is not conducive to the yield of the display backplane. Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] In a first aspect, an embodiment of the present disclosure provides a display backplane, comprising: a plurality of first signal lines extending along a first direction, the plurality of first signal lines being arranged in sequence along a second direction, and the first direction and the second direction intersecting; a plurality of second signal lines extending along the second direction, the plurality of second signal lines being arranged in sequence along the first direction; the first signal line being connected to at least one second signal line, and the second signal line and the first signal line overlapping with each other in a direction perpendicular to the display backplane; a plurality of electrostatic protection units, the electrostatic protection units being electrically connected to the first signal line; the electrostatic protection units being located between two adjacent second signal lines in a direction perpendicular to the display backplane, and the electrostatic protection units respectively overlapping with two adjacent second signal lines.

[0007] In an exemplary embodiment, the display backplane includes a display area and a border area surrounding the display area; the border area includes a binding area located on one side of the display area along the second direction; the border area includes a gate drive circuit, and the binding area includes a plurality of binding pins; the second signal line is connected to the gate drive circuit, one end of the first signal line is connected to at least one second signal line, and the other end of the first signal line is connected to the binding pin.

[0008] In an exemplary embodiment, a minimum overlap dimension between the electrostatic protection unit and the second signal line is greater than or equal to 0.9 micrometers.

[0009] In an exemplary embodiment, overlapping areas between the static electricity protection unit and different second signal lines are equal.

[0010] In an exemplary embodiment, a single electrostatic protection unit overlaps with a single first signal line, and overlapping areas between different electrostatic protection units and the first signal lines are equal.

[0011] In an exemplary embodiment, an orthographic projection of the electrostatic protection unit on the display back panel is axially symmetrical, and the symmetry axis of the electrostatic protection unit extends along the second direction.

[0012] In an exemplary embodiment, the electrostatic protection unit is made of a semiconductor material.

[0013] In an exemplary embodiment, the display backplane includes a substrate and a first semiconductor layer, a first metal layer, and a second metal layer sequentially arranged on the substrate; the electrostatic protection unit is located in the first semiconductor layer, the second signal line is located in the first metal layer, and the first signal line is located in the second metal layer; a single electrostatic protection unit is provided between two adjacent second signal lines, and the electrostatic protection unit is in the shape of a line; in a direction perpendicular to the substrate, both ends of the electrostatic protection unit overlap with the two adjacent second signal lines respectively.

[0014] In an exemplary embodiment, a third insulating layer is provided between the first metal layer and the second metal layer; the third insulating layer includes a first via hole, and the first signal line is electrically connected to the electrostatic protection unit through the first via hole.

[0015] In an exemplary embodiment, the first via hole exposes a surface of the static electricity protection unit, and the first signal line contacts the static electricity protection unit through the first via hole.

[0016] In an exemplary embodiment, the first metal layer includes a first connection portion, an orthographic projection of the first connection portion on the substrate and an orthographic projection of the electrostatic protection unit on the substrate overlap with each other, the first via hole exposes a surface of the first connection portion, and the first signal line contacts the first connection portion through the first via hole.

[0017] In an exemplary embodiment, the display backplane includes a substrate and a second light-shielding layer, a second semiconductor layer and a third metal layer sequentially arranged on the substrate; the first signal line is located in the second light-shielding layer, the electrostatic protection unit is located in the second semiconductor layer, and the second signal line is located in the third metal layer.

[0018] In an exemplary embodiment, the third metal layer further includes a second connection portion that contacts the static electricity protection unit and the first signal line, respectively.

[0019] In an exemplary embodiment, an orthographic projection of the second connection portion on the substrate and an orthographic projection of the electrostatic protection unit on the substrate overlap with each other.

[0020] In a second aspect, an embodiment of the present disclosure provides a display device comprising the display back panel as described above.

[0021] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0022] Summary of the Figures

[0023] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0024] FIG1 is a schematic diagram of a planar structure of a display backplane;

[0025] FIG2 is an enlarged schematic diagram of the dotted area C in FIG1 in an exemplary embodiment;

[0026] FIG3 is an enlarged schematic diagram of the dotted area E in FIG2 in an exemplary embodiment;

[0027] FIG4 is a cross-sectional view along line AA of FIG2 in an exemplary embodiment;

[0028] FIG5 is an enlarged schematic diagram of the dotted area C in FIG1 in another exemplary embodiment;

[0029] FIG6 is a cross-sectional view taken along line BB of FIG5 in an exemplary embodiment;

[0030] FIG7 is an enlarged schematic diagram of the dotted area C in FIG1 in another exemplary embodiment;

[0031] FIG8 is a cross-sectional view along the FF direction of FIG7 in an exemplary embodiment;

[0032] FIG. 9 is an enlarged schematic diagram of the dotted area C in FIG. 1 in yet another exemplary embodiment.

[0033] Details

[0034] The present disclosure describes a plurality of embodiments, but this description is exemplary rather than restrictive, and it will be apparent to those skilled in the art that there may be more embodiments and implementations within the scope of the embodiments described in the present disclosure. Although many possible feature combinations are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with any other feature or element in any other embodiment, or may replace any other feature or element in any other embodiment.

[0035] The present disclosure includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The disclosed embodiments, features, and elements of the present disclosure may also be combined with any conventional features or elements to form a unique inventive solution defined by the claims. Any features or elements of any embodiment may also be combined with features or elements from other inventive solutions to form another unique inventive solution defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any appropriate combination. Therefore, the embodiments are not subject to other limitations except for the limitations set forth in the appended claims and their equivalents. In addition, various modifications and changes may be made within the scope of protection of the appended claims.

[0036] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As will be understood by those skilled in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation on the claims. In addition, the claims to the method and / or process should not be limited to performing their steps in the order written, and those skilled in the art can readily understand that these orders can be changed and still remain within the spirit and scope of the disclosed embodiments.

[0037] In the drawings, the size of one or more components, thickness of layers, or regions may be exaggerated for clarity. In addition, the drawings schematically illustrate ideal examples, and one embodiment of the present disclosure is not limited to the shapes or numerical values ​​shown in the drawings.

[0038] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. In this disclosure, "plurality" means two or more.

[0039] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0040] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be interpreted broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the meaning of these terms in this disclosure based on the specific circumstances.

[0041] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain) and a source electrode (source electrode terminal, source region, or source), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0042] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0043] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables transmission of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0044] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0045] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0046] FIG1 is a schematic diagram of a planar structure of a display backplane. As shown in FIG1 , in an exemplary embodiment, the display backplane includes a display area 100 and a frame area 300 arranged around the display area 100. The frame area 300 may include a binding area 200 located on one side of the display area 100 along the second direction Y. The display area 100 includes at least a plurality of regularly arranged pixel units. For example, the plurality of pixel units may be arranged in an array along a first direction X and a second direction Y, and the first direction X and the second direction Y intersect. The plurality of pixel units are configured to display dynamic images or still images, and the display area 100 may be referred to as an active area (AA). In an exemplary embodiment, the display substrate may be deformable, such as curled, bent, folded, or rolled up.

[0047] In an exemplary embodiment, the display area 100 may be in a quadrilateral, a circle, an ellipse, a polygon of other shapes, or an irregular shape, and the corners of the display area 100 may be rounded, which is not limited in the present disclosure.

[0048] In an exemplary embodiment, the binding area 200 may include a fan-out area, a driver chip area, and a binding pin area, which are sequentially arranged in a direction away from the display area 100. The fan-out area is connected to the display area 100 and may include at least a plurality of mutually parallel data lead lines. The driver chip area may include at least an integrated circuit (IC) configured to connect to the plurality of data fan-out lines. The binding pin area may include at least a plurality of bonding pads configured to be bonded to an external flexible printed circuit (FPC).

[0049] In an exemplary embodiment, the binding area 200 may further include a bending area, which may be located between the fan-out area and the driving chip area, the bending area being connected to the fan-out area, and may include a composite insulating layer having a groove, configured to bend the binding area 200 to the back of the display area 100.

[0050] In an exemplary embodiment, the border area 300 may include a circuit area, which may be arranged on both sides of the display area 100 along the first direction X and may be connected to the display area 100. The circuit area may include at least a gate driving circuit 301, and the gate driving circuit 301 is connected to the scanning signal line and the light-emitting signal line of the pixel driving circuit in the display area 100.

[0051] In an exemplary embodiment, the display backplane may include a plurality of gate lines 401 extending along the second direction Y and a gate connection line (Propel Link Gate, PLG) 501 extending along the first direction X. The gate lines 401 may be connected to the gate driver circuit 301. The gate connection lines 501 may connect the gate lines 401 to the binding pins 201 of the integrated circuit to transmit signals from the integrated circuit to the gate driver circuit 301. In an exemplary embodiment, the gate connection lines 501 may be connected to the pins 201 of the integrated circuit via the fan-out region. In an exemplary embodiment, the gate connection lines 501 may connect the gate lines 401 to the corresponding bonding pads, which is not limited in this disclosure.

[0052] Research has found that during the display backplane manufacturing process, static electricity is easily generated during the handling, dry etching, and cleaning processes. When signal lines of adjacent film layers overlap, the signal lines at the overlap are easily damaged by static electricity, affecting the yield of the display backplane. As shown in Figure 1, in the direction perpendicular to the display backplane, due to the overlap between multiple gate connection lines 501 and multiple gate lines 401, the risk of static electricity damage is greater if static electricity cannot be discharged in time, which will have a significant impact on the yield of the display backplane.

[0053] An embodiment of the present disclosure provides a display backplane, comprising: a plurality of first signal lines extending along a first direction, the plurality of first signal lines being arranged in sequence along a second direction, and the first direction and the second direction intersecting; a plurality of second signal lines extending along the second direction, the plurality of second signal lines being arranged in sequence along the first direction; the first signal line being connected to at least one second signal line, and the second signal line and the first signal line overlapping with each other in a direction perpendicular to the display backplane; a plurality of electrostatic protection units, the electrostatic protection units being electrically connected to the first signal line; the electrostatic protection units being located between two adjacent second signal lines in a direction perpendicular to the display backplane, and the electrostatic protection units respectively overlapping with the two adjacent second signal lines.

[0054] The display backplane provided by the embodiment of the present disclosure, when the first signal line and the second signal line overlap with each other, is provided with an electrostatic protection unit between two adjacent second signal lines, and the electrostatic protection unit overlaps with the two adjacent second signal lines respectively, and the electrostatic protection unit is electrically connected to the first signal line. When static electricity exists on the first signal line, the static electricity can be introduced into the electrostatic protection unit along the first signal line. When static electricity exists on the second signal line, the static electricity can be introduced into the electrostatic protection unit from the overlapping part of the second signal line and the electrostatic protection unit, thereby releasing the static electricity in time, preventing the signal line from being damaged by static electricity, and helping to improve the yield of the display backplane.

[0055] In an exemplary embodiment, the display backplane includes a display area and a border area surrounding the display area; the border area includes a binding area located on one side of the display area along the second direction; the border area includes a gate drive circuit, and the binding area includes a plurality of binding pins; the second signal line is connected to the gate drive circuit, one end of the first signal line is connected to at least one second signal line, and the other end of the first signal line is connected to the binding pin.

[0056] In an exemplary embodiment, a minimum overlap dimension between the electrostatic protection unit and the second signal line is greater than or equal to 0.9 micrometers.

[0057] In an exemplary embodiment, overlapping areas between the static electricity protection unit and different second signal lines are equal.

[0058] In an exemplary embodiment, a single electrostatic protection unit overlaps with a single first signal line, and overlapping areas between different electrostatic protection units and the first signal lines are equal.

[0059] In an exemplary embodiment, an orthographic projection of the electrostatic protection unit on the display back panel is axially symmetrical, and the symmetry axis of the electrostatic protection unit extends along the second direction.

[0060] In the following embodiments, the display backplane provided by the embodiments of the present disclosure is described by taking the first signal line 1 as the gate connection line 501 and the second signal line 2 as the gate line 401 as an example. The first signal line 1 and the second signal line 2 are marked only in FIG2 and are omitted in other drawings. The electrostatic protection unit mentioned in the embodiments of the present disclosure can be applied not only between the gate connection line 501 and the gate line 401, but also in other cases where the lines overlap, and the present disclosure does not limit this.

[0061] FIG2 is an enlarged schematic diagram of the dotted area C of FIG1 in an exemplary embodiment. As shown in FIG2 , two adjacent gate lines 401 extend along the second direction Y, and the two gate lines 401 overlap with the gate connection line 501 extending along the first direction X. An electrostatic protection unit 601 is provided on the display backplane, and the electrostatic protection unit 601 is electrically connected to the gate connection line 501. In the direction perpendicular to the display backplane, the electrostatic protection unit 601 is located between the two adjacent gate lines 401, and the orthographic projection of the electrostatic protection unit 601 overlaps with the orthographic projection of the two adjacent gate lines 401. In the case of static electricity on the gate connection line 501, the static electricity can be introduced into the electrostatic protection unit 601 along the gate connection line 501. In the case of static electricity on the gate line 401, the static electricity can be introduced into the electrostatic protection unit 601 from the overlapping portion of the gate line 401 and the electrostatic protection unit 601, thereby releasing static electricity in time, preventing electrostatic damage to the signal line, and helping to improve the yield of the display backplane. Figure 2 illustrates the overlap of two adjacent gate lines 401 and a gate connection line 501, and a single electrostatic protection unit 601 is set between the two adjacent gate lines 401. In other embodiments, multiple gate lines 401 and multiple gate connection lines 501 may overlap with each other, and multiple electrostatic protection units 601 may be set, and the present disclosure does not limit this.

[0062] In an exemplary embodiment, the gate connection line 501 may be connected to the electrostatic protection unit 601 through the first via hole K1 , which is not limited in the present disclosure.

[0063] In an exemplary embodiment, the electrostatic protection unit 601 may have a symmetry axis o extending along the second direction Y, the electrostatic protection unit 601 may be axially symmetrical along the symmetry axis o, and the electrostatic protection unit 601 and the gate line 401 overlapping with the electrostatic protection unit 601 may also be axially symmetrical along the symmetry axis o. The present disclosure does not limit this.

[0064] FIG3 is an enlarged schematic diagram of the dotted area E of FIG2 in an exemplary embodiment. As shown in FIG3 , the minimum overlap size between the electrostatic protection unit 601 and the gate line 401 can be a first overlap size d, and the first overlap size d can be a size along the first direction X. The first overlap size d can be set to be greater than or equal to 0.9 microns, for example, it can be set to be greater than or equal to 1 micron, and the present disclosure does not limit this. By setting the minimum value of the first overlap size d, the overlap area between the electrostatic protection unit 601 and the gate line 401 can be guaranteed, thereby ensuring the smooth discharge of electrostatics.

[0065] In an exemplary embodiment, the electrostatic protection unit 601 may overlap with multiple gate lines 401, and the overlapping area between the electrostatic protection unit 601 and each gate line 401 may be set to be equal. By setting the overlapping area between the electrostatic protection unit 601 and each gate line 401 to be equal, the electrostatic discharge conditions of each gate line 401 can be guaranteed to be the same, which helps to stabilize the discharge of static electricity. In the case where the overlapping area between the electrostatic protection unit 601 and the gate line 401 is unequal, static electricity tends to concentrate and move toward the electrostatic protection unit 601 with a smaller overlapping area, thereby affecting the electrostatic discharge effect.

[0066] In an exemplary embodiment, the display backplane may include multiple gate connection lines 501, and the multiple gate connection lines 501 may be arranged in sequence along the second direction Y. The overlapping areas between different gate connection lines 501 and the corresponding electrostatic protection units 601 may be equal, which helps to ensure that the entire display backplane has a uniform electrostatic release effect.

[0067] In an exemplary embodiment, the material of the electrostatic protection unit 601 can be a semiconductor material, such as non-conductive indium gallium zinc oxide (IGZO). The electrostatic protection unit 601 can be provided in the same layer as the active layer of the transistor in the display backplane, which helps to save preparation steps and save production costs. The "A and B are provided in the same layer" mentioned in the present disclosure means that when the display backplane is prepared, A and B are formed simultaneously through the same patterning process. In other embodiments, other materials with high impedance characteristics can be selected, such as low-temperature polysilicon, etc., and the present disclosure is not limited to this.

[0068] In an exemplary embodiment, the electrostatic discharge effect of the electrostatic protection unit 601 depends on its own impedance, and the resistance value of the electrostatic protection unit 601 can be set according to the normal operating voltage of the gate line 401 and the gate connection line 501. In an exemplary embodiment, the normal operating voltage of the gate line 401 can be a first voltage, and the normal operating voltage of the gate connection line 501 can be a second voltage. When the difference between the first voltage and the second voltage is 10 volts, the resistance value of the electrostatic protection unit 601 can be set to be greater than or equal to 45 kilo-ohms and less than or equal to 55 kilo-ohms. For example, the resistance value of the electrostatic protection unit 601 can be about 50 kilo-ohms. The smaller the difference between the first voltage and the second voltage, the smaller the resistance value of the electrostatic protection unit 601 can be. The greater the resistance value of the electrostatic protection unit 601, the greater the electrostatic current it can withstand, but the slower the electrostatic derivation speed is. Therefore, the resistance value of the electrostatic protection unit 601 can be set in combination with actual needs to achieve better electrostatic derivation effect, and the present disclosure is not limited to this.

[0069] In an exemplary embodiment, since the resistance value of the electrostatic protection unit 601 is related to its own dimensions such as length and diameter, after determining the resistance value of the electrostatic protection unit 601, the length and diameter and other dimensional parameters of the electrostatic protection unit 601 can be set as needed. For example, when the distance between adjacent gate lines 401 is close, the diameter of the electrostatic protection unit 601 can be set to be smaller and the length can be longer to facilitate wiring arrangement. In the accompanying drawings, a single electrostatic protection unit 601 is presented in the shape of a wiring. In actual applications, the shape of the electrostatic protection unit 601 can be set as needed, such as a straight line, a broken line, an arc, a wavy line, an "S" shape, an irregular line, etc. It can also be set to a triangle, a circle, an ellipse, a quadrilateral, a polygon, an irregular shape, etc., and the present disclosure does not limit this.

[0070] Figure 4 is a cross-sectional view of Figure 2 along the AA direction in an exemplary embodiment, illustrating the structure of the display backplane at the gate line and the gate connection line, and omitting the illustration of the remaining structure of the display backplane. As shown in Figure 4, in a direction perpendicular to the display backplane, the display backplane may include a substrate 10, a first insulating layer 12, a first semiconductor layer 13, a second insulating layer 14, a first metal layer 15, a third insulating layer 16, and a second metal layer 17 arranged in sequence, the electrostatic protection unit 601 may be located in the first semiconductor layer 13, the gate line 401 may be located in the first metal layer 15, and the gate connection line 501 may be located in the second metal layer 17. In an exemplary embodiment, the active layer of the transistor in the display backplane can be located in the first semiconductor layer 13, the gate of the transistor can be located in the first metal layer 15, the first metal layer 15 can be called a gate layer, the first and second electrodes of the transistor can be located in the second metal layer 17, the second metal layer 17 can be called a source-drain metal layer, and the second insulating layer 14 can be called a gate insulating layer. Since the thickness of the gate insulating layer is relatively small, when static electricity exists, the static electricity can pass from the gate line 401 located in the first metal layer 15 through the second insulating layer 14 and enter the electrostatic protection unit 601 located in the first semiconductor layer 13. Therefore, there may be no direct connection between the gate line 401 and the electrostatic protection unit 601, and the electrostatic release effect will not be affected. The first insulating layer 12 can be called a buffer layer, and the third insulating layer 16 can be called an interlayer insulating layer. A light-shielding layer can be set between the substrate 10 and the first insulating layer 12, and the present disclosure does not limit this.

[0071] Figure 5 is an enlarged schematic diagram of the dotted area C in Figure 1 in another exemplary embodiment. The difference between Figure 5 and Figure 2 is that a first connection portion 411 is added. The orthographic projection of the first connection portion 411 on the substrate can overlap with the orthographic projection of the electrostatic protection unit 601 on the substrate, and the gate connection line 501 can be connected to the first connection portion 411 through the first via K1. As shown in Figure 5, the first connection portion 411 can be set on the same layer as the gate line 401. After the static electricity of the gate connection line 501 moves to the first connection portion 411, it can pass through the second insulating layer 14 and enter the electrostatic protection unit 601. By providing the first connection portion 411, the first via K1 that was originally directly opened to the surface of the electrostatic protection unit 601 can be opened only to the first connection portion 411. The first connection portion 411 can release static electricity from the electrostatic protection unit 601 through the second insulating layer 14, which can improve the flexibility of the wiring layout and reduce the difficulty and accuracy of drilling. The first connection portion 411 can be made of the same material as the gate line 401, and will not increase the production process.

[0072] Figure 6 is a cross-sectional view taken along line BB of Figure 5 in an exemplary embodiment, illustrating the structure of the display backplane at the gate lines and gate connection lines, omitting the remaining structure of the display backplane. Figure 6 differs from Figure 4 in that the first metal layer 15 includes a first connection portion 411, to which the gate connection line 501 is connected. The remaining structure can be referred to in the description of Figure 4 and will not be repeated here.

[0073] Figure 7 is an enlarged schematic diagram of the dotted area C of Figure 1 in another exemplary embodiment. The difference between Figure 7 and Figure 2 is that a second connecting portion 412 is added, and the shape of the electrostatic protection unit 601 and the position of the film layer are different. Figure 8 is a cross-sectional view of Figure 7 along the FF direction in an exemplary embodiment, illustrating the structure of the display backplane at the gate line and the gate connection line, and omitting the remaining structure of the display backplane. As shown in Figure 8, in a direction perpendicular to the display backplane, the display backplane may include a substrate 20, a second light shielding layer 22, a fifth insulating layer 23, a second semiconductor layer 24, a sixth insulating layer 25 and a third metal layer 26 arranged in sequence. The display backplane provided in this embodiment has two metal layers, the second light shielding layer 22 and the third metal layer 26, which can be prepared using five masks and can be used for an array substrate for a liquid crystal display, wherein the electrostatic protection unit 601 can be located in the second semiconductor layer 24, the gate line 401 and the second connecting portion 412 can be located in the third metal layer 26, and the gate connection line 501 can be located in the second light shielding layer 22. In an exemplary embodiment, the active layer of the transistor in the display backplane can be located in the second semiconductor layer 24, and the gate, first electrode, and second electrode of the transistor can be located in the third metal layer 26. The first conductive layer 21 can be made of a transparent conductive material, the fifth insulating layer 23 can be called a buffer layer, and the sixth insulating layer 25 can be called a gate insulating layer. If desired, a first conductive layer can be provided between the substrate 20 and the second light shielding layer 22, and this is not limited in this disclosure.

[0074] As shown in Figures 7 and 8, the orthographic projection of the second connecting portion 412 on the substrate can overlap with the orthographic projection of the electrostatic protection unit 601 on the substrate, and the second connecting portion 412 and the electrostatic protection unit 601 are in contact with each other, and the gate connecting line 501 can be connected to the second connecting portion 412 through the first via K1, thereby realizing electrical connection between the gate connecting line 501 and the electrostatic protection unit 601.

[0075] As shown in FIG7 , when the distance between two adjacent gate lines 401 is relatively close, the shape of the electrostatic protection unit 601 can be controlled, and the main portion of the electrostatic protection unit 601 can extend along the second direction Y. By arranging an extension portion extending along the first direction X and overlapping the gate lines 401, a smaller space can be occupied, thereby facilitating wiring on the display backplane.

[0076] Figure 9 is an enlarged schematic diagram of the dotted area C of Figure 1 in another exemplary embodiment. The difference between Figure 9 and Figure 7 is that the shape of the electrostatic protection unit 601 is different. The cross-sectional structure of Figure 9 at the same position can refer to Figure 8, and the remaining structures can refer to the description of Figures 7 and 8, which will not be repeated here. As shown in Figure 9, when the distance between two adjacent gate lines 401 is close, the shape of the electrostatic protection unit 601 can be "n"-shaped, and the two ends of the "n" shape can overlap with the gate line 401, and the top of the "n" shape can overlap with the second connecting portion 412, thereby occupying a smaller space.

[0077] The present disclosure also provides a display device including the display backplane described in any of the above embodiments. The display device can be any product or component with a display function, such as an OLED display, an LED display, an LCD display, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system, but the present disclosure is not limited thereto.

[0078] Although the embodiments disclosed herein are as described above, the contents described herein are merely embodiments for facilitating understanding of the present invention and are not intended to limit the present invention. Any person skilled in the art may make any modifications and variations in the form and details of the embodiments without departing from the spirit and scope of the present invention. However, the scope of patent protection of the present invention shall remain subject to the scope defined by the appended claims.

Claims

1. A display backplane, comprising: a plurality of first signal lines extending along a first direction, wherein the plurality of first signal lines are sequentially arranged along a second direction, and the first direction and the second direction intersect; a plurality of second signal lines extending along the second direction, the plurality of second signal lines being sequentially arranged along the first direction; the first signal line being connected to at least one of the second signal lines, and the second signal line and the first signal line overlapping each other in a direction perpendicular to the display backplane; Multiple electrostatic protection units are electrically connected to the first signal line; in a direction perpendicular to the display backplane, the electrostatic protection unit is located between two adjacent second signal lines, and the electrostatic protection unit overlaps with the two adjacent second signal lines respectively.

2. The display backplane according to claim 1, wherein: The display backplane includes a display area and a frame area surrounding the display area; the frame area includes a binding area located on one side of the display area along the second direction; the frame area includes a gate drive circuit, and the binding area includes a plurality of binding pins; The second signal line is connected to the gate driving circuit, one end of the first signal line is connected to at least one second signal line, and the other end of the first signal line is connected to the binding pin.

3. The display backplane according to claim 1, wherein: A minimum overlapping dimension between the electrostatic protection unit and the second signal line is greater than or equal to 0.9 micrometers.

4. The display backplane according to claim 3, wherein: The overlapping areas between the electrostatic protection unit and different second signal lines are equal.

5. The display backplane according to claim 1, wherein: A single electrostatic protection unit overlaps with a single first signal line, and overlapping areas between different electrostatic protection units and the first signal lines are equal.

6. The display backplane according to claim 1, wherein: The orthographic projection of the electrostatic protection unit on the display back panel is axially symmetrical, and the symmetry axis of the electrostatic protection unit extends along the second direction.

7. The display backplane according to claim 1, wherein: The material of the electrostatic protection unit is semiconductor material.

8. The display backplane according to claim 1, wherein: The display backplane includes a substrate and a first semiconductor layer, a first metal layer, and a second metal layer sequentially arranged on the substrate; the electrostatic protection unit is located in the first semiconductor layer, the second signal line is located in the first metal layer, and the first signal line is located in the second metal layer; A single electrostatic protection unit is provided between two adjacent second signal lines, and the electrostatic protection unit is in the shape of a line; In a direction perpendicular to the substrate, two ends of the electrostatic protection unit overlap with two adjacent second signal lines respectively.

9. The display back panel according to claim 8, wherein: A third insulating layer is provided between the first metal layer and the second metal layer; the third insulating layer includes a first via hole, and the first signal line is electrically connected to the electrostatic protection unit through the first via hole.

10. The display back panel according to claim 9, wherein: The first via hole exposes a surface of the electrostatic protection unit, and the first signal line contacts the electrostatic protection unit through the first via hole.

11. The display back panel according to claim 9, wherein: The first metal layer includes a first connecting portion, the orthographic projection of the first connecting portion on the substrate and the orthographic projection of the electrostatic protection unit on the substrate overlap with each other, the first via exposes the surface of the first connecting portion, and the first signal line contacts the first connecting portion through the first via.

12. The display back panel according to claim 1, wherein: The display backplane includes a substrate and a second light-shielding layer, a second semiconductor layer and a third metal layer arranged in sequence on the substrate; the first signal line is located in the second light-shielding layer, the electrostatic protection unit is located in the second semiconductor layer, and the second signal line is located in the third metal layer.

13. The display back panel according to claim 12, wherein: The third metal layer further includes a second connection portion, and the second connection portion is in contact with the electrostatic protection unit and the first signal line respectively.

14. The display back panel according to claim 13, wherein: An orthographic projection of the second connecting portion on the substrate and an orthographic projection of the electrostatic protection unit on the substrate overlap with each other.

15. A display device comprising the display back panel according to any one of claims 1 to 14.

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