Pixel driving circuit and display apparatus

Abstract

Disclosed are a pixel driving circuit (100) and a display apparatus. The pixel driving circuit (100) comprises a pixel circuit (12). The pixel circuit (12) comprises: at least one light-emitting element (14); at least one driving current generation circuit (16), which comprises a switching element (20) electrically connected to the light-emitting element (14), and is configured to provide a driving current to the corresponding light-emitting element (14) when the switching element (20) is switched on; and a control unit (18), which is electrically connected to the switching element (20), and can perform a logical operation on input multibit pixel data within the pixel circuit (12) and control the switching on and off of the corresponding switching element (20) and the on duration of a switching element (20) that has been switched on, so as to modulate the brightness of the light-emitting element (14).

Description

Pixel driving circuit and display device

[0001] Priority information

[0002] This application claims priority and benefits of patent application No. 202410246286.5 filed with the State Intellectual Property Office of China on March 4, 2024, and the entire text of which is incorporated herein by reference. Technical Field

[0003] The present invention relates to the field of pixel driving technology, and in particular to a pixel driving circuit and a display device. Background Art

[0004] In related technologies, display devices can use micro-light-emitting diodes (Micro-LEDs) as light-emitting elements for display. The display device includes a Micro-LED pixel driver circuit. The pixel driver circuit controls the brightness of the light-emitting element based on a control signal. However, current pixel driver circuits have various shortcomings that limit the application scenarios of Micro-LEDs. Summary of the Invention

[0005] The present invention provides a pixel driving circuit and a display device to solve at least one of the above-mentioned technical problems.

[0006] In a first aspect, the present invention provides a pixel driving circuit including a pixel circuit, wherein the pixel circuit includes:

[0007] at least one light-emitting element;

[0008] at least one driving current generating circuit, the driving current generating circuit comprising a switching element, the switching element being electrically connected to the light-emitting element, the driving current generating circuit being configured to provide a driving current to a corresponding light-emitting element when the corresponding switching element is turned on;

[0009] A control unit is electrically connected to the switching element, and the control unit can perform logical operations on the input multi-bit pixel data in the pixel circuit to control the on and off of the corresponding switching element and the on time of the switched-on switching element to modulate the brightness of the light-emitting element.

[0010] In the above-mentioned pixel driving circuit, the control unit can perform logical operations on the input multi-bit pixel data, control the on and off of the corresponding switching elements and the conduction time of the switched-on switching elements, so as to modulate the brightness of the light-emitting elements, thereby making the light-emitting elements suitable for more application scenarios.

[0011] In some optional technical solutions of the present invention, the multi-bit pixel data may form one or more bits of analog signals and one or more bits of digital signals;

[0012] The control unit performs a logic operation on the analog signal and the digital signal to jointly modulate the on / off state of the corresponding switching element and / or the on-time of the switched-on switching element.

[0013] In some optional technical solutions of the present invention, the multi-bit pixel data is a mixed signal formed by inputting an analog signal and a digital signal through one channel, and the mixed signal is parsed to obtain the analog signal and the digital signal;

[0014] Alternatively, the multi-bit pixel data includes the analog signal input from one path and the digital signal input from another path.

[0015] In some optional technical solutions of the present invention, the analog signal is used to control the on-off state of the corresponding switching element to control the magnitude of the driving current, and the digital signal is used to control the on-time of the switched element to control the luminous time of the luminous element.

[0016] In some optional technical solutions of the present invention, the control unit includes a logic operation gate, the output end of the logic operation gate is connected to the switching element, and the input end of the logic operation gate is used to receive the analog signal and the pulse width modulation signal, and the pulse width modulation signal is modulated according to the digital signal.

[0017] In some optional technical solutions of the present invention, the pulse width of the pulse width modulation signal is positively correlated or negatively correlated with a set value, and the set value is determined by the digital signal.

[0018] In some optional technical solutions of the present invention, the pixel driving circuit includes a clock circuit, a counter and a comparator;

[0019] The clock circuit is configured to output a clock signal;

[0020] The counter is configured to receive the clock signal and count the number of pulses of the clock signal;

[0021] The comparator is configured to output the pulse width modulation signal according to the relationship between the count value of the counter and the set value;

[0022] The logic operation gate is configured to output a control signal for controlling the on / off state of the switch element according to the pulse width modulation signal and the analog signal.

[0023] In some optional technical solutions of the present invention, when the count value of the counter is less than or equal to the set value, the level of the pulse width modulation signal is the first level, and the level of the analog signal is the first level, the control signal output by the logic operation gate is a signal for controlling the switching element to be turned on;

[0024] When the count value of the counter is less than or equal to the set value, the level of the pulse width modulation signal is the first level, and the level of the analog signal is the second level, the control signal output by the logic operation gate is a signal for controlling the switching element to be turned off;

[0025] When the count value of the counter is greater than the set value, the level of the pulse width modulation signal is the second level, and when the level of the analog signal is the second level, the control signal output by the logic operation gate is a signal for controlling the switching element to be turned off;

[0026] When the count value of the counter is greater than the set value, the level of the pulse width modulation signal is the second level, and when the level of the analog signal is the first level, the control signal output by the logic operation gate is a signal for controlling the switching element to be turned off.

[0027] In some optional technical solutions of the present invention, when the count value of the counter is less than or equal to the set value, the level of the pulse width modulation signal is the first level, and the level of the analog signal is the second level, the control signal output by the logic operation gate is a signal for controlling the switching element to be turned on;

[0028] When the count value of the counter is less than or equal to the set value, the level of the pulse width modulation signal is the first level, and the level of the analog signal is the first level, the control signal output by the logic operation gate is a signal for controlling the switching element to be turned off;

[0029] When the count value of the counter is greater than the set value, the level of the pulse width modulation signal is the second level, and when the level of the analog signal is the first level, the control signal output by the logic operation gate is a signal for controlling the switching element to be turned on;

[0030] When the count value of the counter is greater than the set value, the level of the pulse width modulation signal is the second level. When the level of the analog signal is the second level, the control signal output by the logic operation gate is a signal for controlling the switching element to be turned on.

[0031] In some optional technical solutions of the present invention, the pixel driving circuit has a global mode. In the global mode, the pixel driving circuit is configured to allow the analog signal to be directly input into the logic operation gate.

[0032] In some optional technical solutions of the present invention, the pixel driving circuit has a local mode, and the pixel driving circuit includes a memory. In the local mode, the pixel driving circuit is configured to input the analog signal and the digital signal into the memory, and to input the analog signal from the memory into the logic operation gate.

[0033] In some optional technical solutions of the present invention, the pixel driving circuit includes a reference current generating circuit, which is electrically connected to the at least one driving current generating circuit, and the reference current generating circuit and the corresponding one of the driving current generating circuits form a current mirror structure.

[0034] In some optional technical solutions of the present invention, the reference current generating circuit is configured to provide a reference current to each of the driving current generating circuits;

[0035] The drive current generating circuit is configured to generate the drive current related to the reference current.

[0036] In some optional technical solutions of the present invention, the driving current and the reference current meet the following conditions: I M =K M ×I ref , I ref Represents the reference current, I M Indicates the driving current generated by the Mth driving current generating circuit, K M is the coefficient of the Mth driving current generating circuit, M<=J, J is the number of the driving current generating circuits, M and J are natural numbers and J>=1.

[0037] In some optional technical solutions of the present invention, the reference current generating circuit includes a first transistor, the drive current generating circuit includes a second transistor, and the coefficient of the drive current generating circuit is negatively correlated with the aspect ratio of the first transistor and positively correlated with the aspect ratio of the second transistor.

[0038] In some optional technical solutions of the present invention, the control unit is configured to control the on-off state of the switch element according to the analog signal to obtain 2 J -1 different driving current magnitudes, where J is the number of the driving current generating circuits, J is a natural number and J>=1.

[0039] In some optional technical solutions of the present invention, the control unit is configured to: after receiving the multi-bit pixel data, parse the multi-bit pixel data using a first preset information table to obtain the analog signal and the digital signal.

[0040] In some optional technical solutions of the present invention, the pixel driving circuit includes a level converter, which is electrically connected between the control unit and the switching element, and the level converter is configured to achieve mutual conversion between the analog voltage domain and the digital voltage domain.

[0041] In some optional technical solutions of the present invention, the pixel driving circuit includes an inverter, and the inverter is connected between the level converter and the switching element.

[0042] In some optional technical solutions of the present invention, the pixel driving circuit includes a memory, the memory is electrically connected to the control unit, and the memory is configured to store the digital signal and the analog signal.

[0043] In some optional technical solutions of the present invention, the pixel driving circuit includes a memory, which is electrically connected to the control unit. The memory is configured to, after receiving the pixel data, parse the multi-bit pixel data using a second preset information table to obtain and store the digital signal and the analog signal, and transmit the digital signal and the analog signal to the control unit.

[0044] In some optional technical solutions of the present invention, the pixel driving circuit includes a digital processing unit, which is electrically connected to the control unit, and the digital processing unit is configured as follows:

[0045] In the process of the control unit controlling the driving current size according to the analog signal, if the actual driving current does not meet the expected value, the digital signal is adjusted according to the difference between the actual driving current and the expected value to compensate for the luminous duration, thereby eliminating the problem of discontinuous luminous brightness of the light-emitting element caused by the actual driving current not meeting the expected value.

[0046] In a second aspect, the present invention provides a display device comprising a pixel driving circuit according to any of the above solutions.

[0047] In the above-mentioned display device, the control unit can control the on-off state of the switching element according to the analog signal and thereby control the driving current, and / or control the on-time of the switching element according to the digital signal and thereby control the light-emitting time of the light-emitting element, so that the light-emitting element can be suitable for more application scenarios.

[0048] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned by practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments with reference to the following drawings, in which:

[0050] FIG1 is a circuit diagram of a pixel driving circuit according to an embodiment of the present invention;

[0051] FIG2 is a schematic diagram of a module of a control unit according to an embodiment of the present invention;

[0052] FIG3 is a second schematic diagram of a module of a control unit according to an embodiment of the present invention;

[0053] FIG4 is a circuit diagram of a pixel driving circuit having two current branches according to an embodiment of the present invention;

[0054] FIG5 is a timing diagram of a pixel driving circuit having two current branches according to an embodiment of the present invention;

[0055] FIG6 is a second timing diagram of a pixel driving circuit having two current branches according to an embodiment of the present invention;

[0056] 7 is a circuit diagram of a pixel driving circuit having four current branches according to an embodiment of the present invention;

[0057] FIG8 is a timing diagram of a pixel driving circuit having four current branches according to an embodiment of the present invention;

[0058] FIG9 is a second timing diagram of a pixel driving circuit having four current branches according to an embodiment of the present invention;

[0059] FIG10 is a second circuit diagram of a pixel driving circuit according to an embodiment of the present invention;

[0060] FIG. 11 is a third circuit diagram of a pixel driving circuit according to an embodiment of the present invention.

[0061] Explanation of main component symbols: pixel driving circuit 100, pixel circuit 12, light-emitting element 14, driving current generating circuit 16, control unit 18, switching element 20, reference current generating circuit 22, first transistor 24, second transistor 26, clock circuit 28, counter 30, comparator 32, logic operation gate 34, memory 36, level converter 38, digital processing unit 40. DETAILED DESCRIPTION

[0062] The embodiments of the present invention are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention and are not to be construed as limiting the present invention.

[0063] The disclosure below provides many different embodiments or examples for realizing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. In addition, the present invention may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides examples of various specific processes and materials, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0064] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features being referred to. Thus, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0065] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as limiting the present invention.

[0066] In the present invention, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Furthermore, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0067] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they may refer to fixed connections, removable connections, or integral connections. They may refer to mechanical connections or electrical connections. They may refer to direct connections or indirect connections through an intermediary, and they may refer to internal communication between two components or interactions between two components. Those skilled in the art will understand the specific meanings of these terms in the present invention based on the specific circumstances.

[0068] Referring to FIG. 1 , a pixel driving circuit 100 according to an embodiment of the present invention includes a pixel circuit 12 . The pixel circuit 12 includes at least one light-emitting element 14 , at least one driving current generating circuit 16 , and a control unit 18 .

[0069] The driving current generating circuit 16 includes a switching element 20 , which is electrically connected to the light emitting element 14 . The driving current generating circuit 16 is configured to provide a driving current to a corresponding light emitting element 14 when a corresponding switching element 20 is turned on.

[0070] The control unit 18 is electrically connected to the switching element 20 . The control unit 18 can perform logical operations on the input multi-bit pixel data in the pixel circuit 12 to control the on and off of the corresponding switching element 20 and the on-time of the switched-on switching element 20 to modulate the brightness of the light-emitting element 14 .

[0071] In the above-mentioned pixel driving circuit 100, the control unit 18 can perform logical operations on the input multi-bit pixel data, control the on and off of the corresponding switching element 20 and the on-time of the switched-on switching element 20, so as to modulate the brightness of the light-emitting element 14, so that the light-emitting element 14 can be suitable for more application scenarios.

[0072] Specifically, the pixel driving circuit 100 can be applied to a self-luminous display device, in which the light-emitting element 14 can serve as a pixel of the self-luminous display device. In one embodiment, the luminous brightness of the light-emitting element 14 can be the time integral of the driving current. When the driving current is constant, the luminous duration can be gradually varied to adjust the luminous brightness of the light-emitting element 14. Similarly, when the luminous duration is constant, gradually varying the driving current flowing through the light-emitting element 14 can also adjust the luminous brightness of the light-emitting element 14. Furthermore, the luminous brightness of the light-emitting element 14 can also be adjusted by synchronously adjusting the driving current flowing through the light-emitting element 14 and the luminous duration of the light-emitting element 14. The digital-analog hybrid modulation circuit of this architecture effectively modulates the luminous brightness of the light-emitting element 14, making it suitable for a variety of application scenarios. Optionally, in the embodiment shown in the figure, the light-emitting element 14 is a micro-light-emitting diode (Micro-LED). It is understood that in other embodiments, the light-emitting element 14 can also be a light-emitting diode (LED) or an organic light-emitting diode (OLED), and this is not specifically limited in the present invention.

[0073] In one embodiment, the control unit 18 can control the on / off state of the switch element 20 according to the multi-bit pixel data and thus control the driving current. When the light emitting duration of the light emitting element 14 is constant, the light emitting brightness of the light emitting element 14 can be adjusted.

[0074] In one embodiment, the control unit 18 can control the conduction duration of the switched element 20 according to the multi-bit pixel data and thereby control the luminous duration of the light-emitting element 14. When the driving current is constant, the luminous brightness of the light-emitting element 14 can be adjusted.

[0075] In one embodiment, the control unit 18 can control the on-off state of the switching element 20 according to the multi-bit pixel data and thereby control the driving current, and control the conduction time of the switched element 20 that has been turned on and thereby control the light-emitting time of the light-emitting element 14, thereby synchronously adjusting the driving current and light-emitting time of the light-emitting element 14, and adjusting the light-emitting brightness of the light-emitting element 14.

[0076] Alternatively, in one embodiment, the multi-bit pixel data may be formed into one or more analog signals and one or more digital signals. The control unit 18 performs a logical operation on the analog and digital signals to jointly modulate the on / off state of the corresponding switching element 20 and / or the on-time of the switched-on switching element 20.

[0077] Therefore, the control method is simple and efficient.

[0078] Specifically, by performing a logical operation on the analog signal and the digital signal, a corresponding operation result can be quickly obtained, and the operation result can be used to control the on / off state of the switching element 20 and / or control the on-time of the switching element 20 that is already turned on. Logical operations include, but are not limited to, logical AND gate operations, logical NAND gate operations, and combinations of logical AND gate operations and logical NAND gate operations, etc., and this embodiment does not specifically limit this.

[0079] In one embodiment, the multi-bit pixel data may form a one-bit analog signal and a one-bit digital signal.

[0080] In one embodiment, the multi-bit pixel data may form a one-bit analog signal and a multi-bit digital signal.

[0081] In one embodiment, the multi-bit pixel data may form a multi-bit analog signal and a one-bit digital signal.

[0082] In one embodiment, the multi-bit pixel data may form a multi-bit analog signal and a multi-bit digital signal.

[0083] Specifically, in one embodiment, the control unit 18 can perform logical operations based on analog signals and digital signals to control the on-off state of the switching element 20 and thereby control the size of the driving current. When the light-emitting duration of the light-emitting element 14 is constant, the light-emitting brightness of the light-emitting element 14 can be adjusted.

[0084] In one embodiment, the control unit 18 can perform logical operations based on analog signals and digital signals to control the conduction duration of the switched element 20 that has been turned on, thereby controlling the duration of the light-emitting element 14. When the driving current is constant, the brightness of the light-emitting element 14 can be adjusted.

[0085] In one embodiment, the control unit 18 can perform logical operations based on analog signals and digital signals to control the on-off state of the switching element 20 and thereby control the driving current, and control the conduction time of the switched element 20 that has been turned on according to the digital signal and thereby control the luminous duration of the light-emitting element 14, thereby synchronously adjusting the driving current and luminous duration of the light-emitting element 14, and adjusting the luminous brightness of the light-emitting element 14.

[0086] Optionally, when the pixel circuit 12 includes multiple light-emitting elements 14, the multiple light-emitting elements 14 can be arranged in an array in multiple rows and columns. In the embodiment shown in the figure, only one light-emitting element 14 and the connected driving current generating circuit 16 are shown. Optionally, one light-emitting element 14 can be equivalent to one pixel of the display device.

[0087] In Figure 1, each light-emitting element 14 is connected to multiple drive current generating circuits 16. When the switch element 20 is turned on, the drive current generated by the corresponding drive current generating circuit 16 can flow to the connected light-emitting element 14, providing the drive current to the light-emitting element 14. Therefore, the drive current flowing through the light-emitting element 14 is the sum of the currents generated by all the drive current generating circuits 16 corresponding to the turned-on switch elements 20.

[0088] For example, the pixel driving circuit 100 includes J driving current generating circuits 16, which are T <0> ~T <m-1>, including J switching elements 20, N <0> ~N <m-1>, M, J are natural numbers and M<=J, J>=1. In Figure 1, J is greater than 1. When N <0> When the other switching elements 20 are turned off, T <0> Supplying a driving current I to the light emitting element 14 <0> At this time, the driving current of the light emitting element 14 is I <0> When N <0> and N <1> When the other switching elements 20 are turned off, T <0> Supplying a driving current I to the light emitting element 14 <0> , T <1> Supplying a driving current I to the light emitting element 14 <1> At this time, the driving current of the light emitting element 14 is I <0> +I <1> By analogy, by controlling the on-off state of the switch element 20 , the driving current generating circuit 16 provides different driving currents to the light emitting element 14 , thereby adjusting the brightness of the light emitting element 14 .

[0089] Alternatively, in one embodiment, the multi-bit pixel data may be a mixed signal formed by mixing an analog signal and a digital signal through a mixed input path, which together determine the modulation information. In this case, the control unit 18 may parse the input multi-bit pixel data to obtain the corresponding analog signal and digital signal. Optionally, the analog signal may occupy one or more bits, and the digital signal may occupy one or more bits.

[0090] Specifically, the multi-bit pixel data includes a modulation signal determined by a mixture of an analog signal and a digital signal. The analog signal can be represented as Analog Bits, the digital signal can be represented as Digital Bits, and the mixed signal can be represented as Analog & Digital. The mixed signal can be matched to the corresponding modulation signal by a lookup table matching method through a first preset information table. For example, for a mixed signal of Analog & Digital mixed mode, in the first preset information table, 0001 is set to correspond to analog 1 digital 0 (indicating that the analog signal is 1 and the digital signal is 0, the same below), 0010 corresponds to analog 1 digital 1, 0011 corresponds to analog 1 digital 2, etc. This setting method can be relatively random, but the corresponding method can be flexibly defined in advance, making the data input method more flexible and adjustable.

[0091] Optionally, in one embodiment, the multi-bit pixel data includes an analog signal input from one path and a digital signal input from another path, that is, the analog signal and the digital signal may each occupy a certain number of bits, and the control unit 18 may perform logical operations on the input analog signal and digital signal.

[0092] Specifically, both analog signals and digital signals can be matched to corresponding modulation signals by looking up the first preset information table.

[0093] In some embodiments, the analog signal is used to control the on / off state of the corresponding switching element 20 to control the driving current, and the digital signal is used to control the on-time of the turned-on switching element 20 to control the luminous duration of the light-emitting element 14.

[0094] Specifically, in one embodiment, when the digital signal is constant, the analog signal may be 01 to control the switch element 20 to be turned on, and the analog signal may be 00 to control the switch element 20 to be turned off. It is understood that the present invention does not impose any specific limitation on this.

[0095] Optionally, the digital signal may have a certain number of bits, and the control unit 18 may parse the input multi-bit pixel data to obtain a digital signal, and the light-emitting duration may be determined by the digital signal. In one embodiment, when the digital signal is 01 and the switch element 20 is turned on by analog signal control at the corresponding time, the light-emitting element 14 connected to the switched-on switch element 20 may emit light. For a frame timing, the on-time of the switch element 20 may be the cumulative time when the digital signal is 01 in the timing, and the light-emitting duration of the light-emitting element 14 connected to the switched-on switch element 20 may be controlled. When the digital signal is 00 and the switch element 20 is turned off by analog signal control at the corresponding time, the light-emitting element 14 connected to the switched-off switch element 20 does not emit light. Optionally, the duration corresponding to a frame timing may be determined by the refresh rate of the display device.

[0096] In some embodiments, the control unit 18 includes a logic operation gate 34, the output end of the logic operation gate 34 is connected to the switch element 20, and the input end of the logic operation gate 34 is used to receive an analog signal and a pulse width modulation signal, where the pulse width modulation signal is modulated according to the digital signal.

[0097] Thus, the on-off state of the switching element 20 can be controlled by the pulse width modulation signal and the analog signal.

[0098] Specifically, the pulse width of the pulse width modulation (PWM) signal can be modulated by a digital signal, and then combined with an analog signal to control the on / off state of the switch element 20 and / or control the on-time of the switched-on switch element 20 .

[0099] Specifically, when the analog signal remains unchanged, the pulse width of the pulse-width modulated signal changes when the digital signal is adjusted, thereby adjusting the on-time duration of the already-on switching element 20. When the digital signal remains unchanged, the analog signal changes when the analog signal is adjusted, thereby changing the operation result of the logic operation gate 34, thereby controlling the on-off state of the switching element 20. When both the analog signal and the digital signal are adjusted, the pulse width of the pulse-width modulated signal changes, thereby adjusting the on-time duration of the already-on switching element 20. The operation result of the logic operation gate 34 changes, thereby controlling the on-off state of the switching element 20.

[0100] In some embodiments, the pulse width of the pulse width modulation signal is positively correlated or negatively correlated with a set value, and the set value is determined by a digital signal.

[0101] Thus, the size of the pulse width of the pulse width modulation signal can be adjusted to adjust the size of the set value.

[0102] Specifically, in one embodiment, the pulse width of the PWM signal is positively correlated with the set value, that is, when the set value increases, the pulse width of the PWM signal increases, and when the set value decreases, the pulse width of the PWM signal may decrease.

[0103] In one embodiment, the pulse width of the PWM signal is negatively correlated with the set value, that is, when the set value increases, the pulse width of the PWM signal decreases. When the set value decreases, the pulse width of the PWM signal may increase.

[0104] The set value is determined by a digital signal. The control unit 18 acquires the digital signal and analyzes the digital signal to obtain the set value. For example, there is a corresponding relationship between the digital signal and the set value. After acquiring the digital signal, the control unit 18 analyzes the digital signal to obtain the digital signal, and then obtains the set value based on the corresponding relationship.

[0105] In some embodiments, the pixel driving circuit 100 includes a clock circuit 28, a counter 30, and a comparator 32;

[0106] The clock circuit 28 is configured to output a clock signal;

[0107] The counter 30 is configured to receive a clock signal and count the number of pulses of the clock signal;

[0108] The comparator 32 is configured to output a pulse width modulation signal according to the relationship between the count value of the counter 30 and the set value;

[0109] The logic operation gate 34 is configured to output a control signal for controlling the on / off state of the switch element 20 according to the pulse width modulation signal and the analog signal.

[0110] In this way, the control signal for the on / off state of the switching element 20 can be adjusted.

[0111] Specifically, the control unit 18 can function as a controller and analog modulation module (PWM Control & Analog Tune). The clock circuit is used to generate the required clock signal and implement PWM (Pulse Width Modulation) modulation for the pixel circuit 12. A single clock signal can be input to the pixel circuit 12, or multiple clock signals can be input to the pixel circuit 12, which is not specifically limited in the present invention.

[0112] In one embodiment, the clock signal provided by the clock circuit 28 may have a period of uniform width, that is, the width of each pulse is equal. In one embodiment, the clock signal provided by the clock circuit 28 may have a period of unequal width, that is, the width of each pulse is unequal, or some pulses have equal widths and some pulses have unequal widths, which is not specifically limited in the present invention.

[0113] The counter 30 (Counter) can count the number of pulses of the clock signal. Optionally, in a frame sequence, the count value of the counter 30 is used to control the light-emitting duration of the light-emitting element 14 in the frame sequence.

[0114] The clock signal can be used by the counter 30 to perform relevant calculations to generate a corresponding pulse width modulation signal (grayscale signal). The number of bits of the counter 30 is determined by the period of the clock signal and the pulse width length of the desired pulse width modulation signal.

[0115] The set value can serve as the comparison value of the comparator 32, and the set value can be set to m. The comparison value of the comparator 32 can be set according to the required luminous duration, and combined with the set signal (Reset) in the circuit, the luminous duration corresponding to each grayscale is determined. More specifically, the control unit 18 can set the set value m based on the digital signal, thereby adjusting the pulse width of the pulse width modulation signal to achieve pulse width modulation of the pulse width modulation signal. Specifically, for each frame timing, if the required luminous duration is short, the m value can be adjusted to a smaller value, and if the required luminous duration is longer, the m value can be adjusted to a larger value. By adjusting the m value using the digital signal, the pulse width of the pulse width modulation signal can be adjusted by adjusting the comparison value of the comparator 32, thereby achieving the purpose of adjusting the luminous duration of the light-emitting element 14. It is understood that in other embodiments, for each frame timing, if the required luminous duration is short, the m value can be adjusted to a larger value, and if the required luminous duration is longer, the m value can be adjusted to a smaller value, and corresponding adjustments can be made in the circuit. The present invention is not specifically limited to this.

[0116] The logic operation gate 34 can output a corresponding control signal based on the level of the input signal. Specifically, the logic operation gate 34 can output a control signal that controls the on / off state of the switching element 20 based on the level of the pulse width modulation signal and the level of the analog signal. Optionally, the number of gates of the logic operation gate 34 is the same as the number of switching elements 20.

[0117] Optionally, in the embodiment shown in the figure, the control unit 18 includes a counter 30 and a comparator 32, and the counter 30 and the comparator 32 can be provided in the pixel circuit 12. Alternatively, the counter 30 and the comparator 32 can also be provided in a peripheral circuit of the pixel circuit 12. The present invention is not specifically limited to this.

[0118] In some embodiments, when the count value of the counter 30 is less than or equal to the set value, the level of the pulse width modulation signal is at the first level, and the level of the analog signal is at the first level, the control signal output by the logic operation gate 34 is a signal for controlling the switching element 20 to be turned on;

[0119] When the count value of the counter 30 is less than or equal to the set value, the level of the pulse width modulation signal is the first level, and the level of the analog signal is the second level, the control signal output by the logic operation gate 34 is a signal for controlling the switch element 20 to be turned off;

[0120] When the count value of the counter 30 is greater than the set value, the level of the pulse width modulation signal is the second level. When the level of the analog signal is the second level, the control signal output by the logic operation gate 34 is a signal for controlling the switch element 20 to be turned off.

[0121] When the count value of the counter 30 is greater than the set value, the level of the pulse width modulation signal is the second level, and when the level of the analog signal is the first level, the control signal output by the logic operation gate 34 is a signal for controlling the switch element 20 to be turned off.

[0122] Thus, the control signal for the on / off state of the switching element 20 can be determined by a logic AND gate operation.

[0123] Specifically, the switch element may include an NMOS, and the logic operation gate 34 may include an AND logic gate. Each AND logic gate has two input terminals, and the logic operation may be an AND gate operation. In one embodiment, the first level may be a high level, and the second level may be a low level. If the pulse width modulation signal output by the comparator 32 is at a high level and the analog signal is at a high level, the control signal output by the logic operation gate 34 is at a high level, turning on the corresponding switch element 20.

[0124] The level of the pulse width modulation signal output by the comparator 32 is high, and the level of the analog signal is low. Then, the control signal output by the logic operation gate 34 is low, so that the corresponding switch element 20 is turned off.

[0125] The level of the pulse width modulation signal output by the comparator 32 is low, and the level of the analog signal is low. Then, the control signal output by the logic operation gate 34 is low, so that the corresponding switch element 20 is turned off.

[0126] The level of the pulse width modulation signal output by the comparator 32 is low, and the level of the analog signal is high. Then, the control signal output by the logic operation gate 34 is low, so that the corresponding switch element 20 is turned off.

[0127] In some embodiments, when the count value of the counter 30 is less than or equal to the set value, the level of the pulse width modulation signal is the first level, and the level of the analog signal is the second level, the control signal output by the logic operation gate 34 is a signal for controlling the switching element 20 to be turned on;

[0128] When the count value of the counter 30 is less than or equal to the set value, the level of the pulse width modulation signal is the first level, and the level of the analog signal is the first level, the control signal output by the logic operation gate 34 is a signal for controlling the switch element 20 to be turned off;

[0129] When the count value of the counter 30 is greater than the set value, the level of the pulse width modulation signal is the second level, and when the level of the analog signal is the first level, the control signal output by the logic operation gate 34 is a signal for controlling the switch element 20 to be turned on;

[0130] When the count value of the counter 30 is greater than the set value, the level of the pulse width modulation signal is the second level. When the level of the analog signal is the second level, the control signal output by the logic operation gate 34 is a signal for controlling the switch element 20 to be turned on.

[0131] Thus, the control signal for determining the on / off state of the switch element 20 can be determined by a logic NAND gate operation.

[0132] Specifically, the switch element may include a PMOS transistor. The logic operation gate 34 includes a NAND logic gate, each of which has two input terminals, and the logic operation may be a NAND gate operation. In one embodiment, the first level may be a high level, and the second level may be a low level. If the pulse width modulation signal output by the comparator 32 is at a high level and the analog signal is at a low level, the control signal output by the logic operation gate 34 is at a high level, turning on the corresponding switch element 20.

[0133] The level of the pulse width modulation signal output by the comparator 32 is high, and the level of the analog signal is high. Then, the control signal output by the logic operation gate 34 is low, so that the corresponding switch element 20 is turned off.

[0134] The level of the pulse width modulation signal output by the comparator 32 is low, and the level of the analog signal is high. Then, the control signal output by the logic operation gate 34 is high, so that the corresponding switch element 20 is turned on.

[0135] The level of the pulse width modulation signal output by the comparator 32 is low, and the level of the analog signal is low, then the control signal output by the logic operation gate 34 is high, so that the corresponding switch element 20 is turned on.

[0136] In some embodiments, referring to FIG. 2 , the pixel driving circuit 100 has a global mode. In the global mode, the pixel driving circuit 100 is configured to allow the analog signal to be directly input into the logic operation gate 34 .

[0137] Therefore, in the global mode, the control unit 18 can control the on / off states of all the switch elements 20 connected to the logic operation gate 34 through the logic operation gate 34 .

[0138] Specifically, the external analog signal can be directly input into the logic operation gate 34 , thereby controlling the on / off states of the switch elements 20 of all current branches connected to the logic operation gate 34 .

[0139] It can be understood that in the global mode, the analog signal can control the on-off state of the switching element 20 of all current branches in the pixel circuit 12, or it can control the on-off state of the switching element 20 of all current branches corresponding to a row of light-emitting elements 14, or it can control the on-off state of the switching element 20 of all current branches of a column of light-emitting elements 14. The present invention does not make specific limitations on this.

[0140] 2 , the pixel driving circuit 100 includes a memory 36. Optionally, the memory 36 is located in the pixel circuit 12. The memory 36 has an N-bit number. The input digital signal can be stored in the memory 36, while the analog signal can be directly input to the logic operation gate 34. Optionally, the memory 36 is located in a peripheral circuit of the pixel circuit 12.

[0141] For example, if a light-emitting element 14 is connected to J current branches (driving current generating circuit 16), then the analog signal controlling the light-emitting element 14 will also have J bits. Each bit of the analog signal controls the on / off state of the switch element 20 in the corresponding current branch. For example, if J = 4 and the analog signal = 0001, the most significant bit (MSB) of the analog signal is 0, the bit below the MSB is 0, the two bits below the MSB are 0, and the least significant bit (LSB) is 1. This analog signal, combined with the level of the pulse width modulation signal output by the comparator 32, allows the logic gate 34 to output four control signals that control the on / off states of the four switch elements 20.

[0142] In some embodiments, referring to FIG. 3 , the pixel driving circuit 100 has a local mode, and the pixel driving circuit 100 includes a memory 36 . In the local mode, the pixel driving circuit 100 is configured to input analog signals and digital signals into the memory 36 , and to input analog signals from the memory 36 into the logic operation gate 34 .

[0143] Therefore, in the local mode, the control unit 18 can control the on / off state of one or more switching elements 20 connected to the logic operation gate 34 through the logic operation gate 34 .

[0144] Specifically, in the local mode, multi-bit pixel data can be input to the memory 36. The memory 36 can be a memory 36 with a multi-bit (bit) function. For example, the memory 36 has J+N bits. Some bits of the multi-bit pixel data are allocated to analog signals, and some bits are allocated to digital signals. In other words, some analog signals of the multi-bit pixel data are input to the logic operation gate 34, rather than all of the multi-bit pixel data. As a result, one or more analog signals input to the logic operation gate 34 can correspondingly control the on / off state of one or more switching elements 20.

[0145] It can be understood that in the local mode, the analog signal can control the on-off state of one or several switching elements 20 of all current branches in the pixel circuit 12, or it can control the on-off state of one or several switching elements 20 corresponding to a row of light-emitting elements 14, or it can control the on-off state of one or several switching elements 20 corresponding to a column of light-emitting elements 14. The present invention does not make specific limitations on this.

[0146] In some embodiments, the pixel driving circuit 100 includes a reference current generating circuit 22 , which is electrically connected to at least one driving current generating circuit 16 . The reference current generating circuit 22 and the corresponding driving current generating circuit 16 form a current mirror structure.

[0147] Therefore, the current mirror structure can be used to generate the driving current, reducing the circuit complexity. Specifically, in FIG1 , the number of the driving current generating circuits 16 is J, which are T <0> ~T <m-1>, the reference current generating circuit 22 is T0, T0 and T <0> Forming a current mirror structure, T0 and T <1> Form a current mirror structure, and so on, T0 and T <m-1>A current mirror structure is formed, and the reference current generating circuit 22 and the J driving current generating circuits 16 respectively form J current mirror structures. Correspondingly, each driving current generating circuit 16 can serve as a current mirror branch and a current branch.

[0148] The reference current generating circuit 22 can convert voltage to current and provide a reference current source for the current mirror branch. This current mirror structure facilitates the sharing of circuit modules and reduces circuit complexity. It fully utilizes the existing bandgap reference circuit module and provides a reference current for the current mirror branch.

[0149] The present invention does not impose any specific limitation on the placement of the reference current generating circuit 22. Alternatively, the reference current generating circuit 22 may be disposed outside the pixel circuit 12.

[0150] In some embodiments, the reference current generating circuit 22 is configured to provide a reference current to each driving current generating circuit 16;

[0151] The driving current generating circuit 16 is configured to generate a driving current related to a reference current.

[0152] Thus, after determining the reference current, the drive current generated by each drive current generating circuit 16 can be determined. The drive current generation method is simple. Specifically, a voltage can be provided to the reference current generating circuit 22, and the reference current generating circuit 22 can convert the voltage into a reference current. The voltage and the reference current have a certain relationship, and the specific relationship is determined according to the circuit design.

[0153] Through the current mirror structure, each drive current generating circuit 16 can generate a drive current related to the reference current. More specifically, after a voltage is input to the reference current generating circuit 22, the reference current generating circuit 22 can generate a reference current. In response, the drive current generating circuit 16 can replicate a certain proportion of the reference current to generate a corresponding drive current. When the switch element 20 is turned on, the drive current generated by the corresponding drive current generating circuit 16 can flow to the light-emitting element 14, causing the light-emitting element 14 to emit light.

[0154] In one embodiment, the driving current and the reference current satisfy the following conditions: M =K M ×I ref , I ref Indicates the reference current, I M represents the driving current generated by the Mth driving current generating circuit 16, K M is the coefficient of the Mth driving current generating circuit 16 , M<=J, J is the number of the driving current generating circuits 16 , M and J are natural numbers and J>=1.

[0155] Therefore, the driving current calculation method of each driving current generating circuit 16 is simple and efficient.

[0156] Specifically, referring to FIG. 1 , from left to right, for the first driving current generating circuit 16 , its driving current I1=K1×I ref For the second driving current generating circuit 16, its driving current I2=K2×I ref , and so on, for the Mth driving current generating circuit 16, its driving current I M =K M ×I ref .

[0157] Optionally, the coefficient K of all driving current generating circuits 16 is the same, optionally, the coefficient K of all driving current generating circuits 16 is different, optionally, the coefficient K of several driving current generating circuits 16 is the same, and the coefficient K of several driving current generating circuits 16 is different. The present invention does not make any specific limitation on this.

[0158] The specific value of the coefficient K of the driving current generating circuit 16 can be determined according to actual needs, and the present invention does not impose any specific limitation on this.

[0159] In some embodiments, the reference current generating circuit 22 includes a first transistor 24 , the driving current generating circuit 16 includes a second transistor 26 , and the coefficient of the driving current generating circuit 16 is negatively correlated with the width-to-length ratio of the first transistor 24 and positively correlated with the width-to-length ratio of the second transistor 26 .

[0160] Thus, it is convenient to determine the coefficient of the drive current generating circuit 16. Specifically, the coefficient of the drive current generating circuit 16 is negatively correlated with the aspect ratio of the first transistor 24. When the aspect ratio of the first transistor 24 increases, the coefficient of the drive current generating circuit 16 decreases. The coefficient of the drive current generating circuit 16 is positively correlated with the aspect ratio of the second transistor 26. When the aspect ratio of the second transistor 26 increases, the coefficient of the drive current generating circuit 16 increases.

[0161] Optionally, in FIG1 , the first transistor 24 and the second transistor 26 are both PMOS transistors, the first transistor 24 is a P0 transistor, the length ratio of the P0 transistor is A0=W / L, and the second transistor 26 of the first driving current generating circuit 16 is a P <0> Tube, P <0> The width to length ratio of the tube is A <0> , where A <0> =K1×A0, the coefficient of the first driving current generating circuit 16 is K1=A <0> / A0, driving current I1=K1×I ref The second transistor 26 of the second driving current generating circuit 16 is P <1> Tube, P <1> The width to length ratio of the tube is A <1> , where A <1> =K2×A0, the coefficient K2 of the second driving current generating circuit 16 =A <1> / A0, driving current I2=K2×I ref , and so on, the second transistor 26 of the Mth driving current generating circuit 16 is P <m-1>Tube, P <m-1>The width to length ratio of the tube is A <m-1>, where A <m-1>=K M ×A0, coefficient K of the Mth driving current generating circuit 16 M =A <m-1> / A0, driving current I M =K M ×I ref .

[0162] Optionally, in other embodiments, both the first transistor 24 and the second transistor 26 are NMOS transistors, which is not specifically limited in the present invention.

[0163] In some embodiments, the control unit 18 is configured to control the on / off state of the switch element 20 according to the analog signal to obtain 2 J -1 different driving current magnitudes, where J is the number of the driving current generating circuits 16 , J is a natural number and J>=1.

[0164] Thus, a variety of drive current sizes can be obtained, which expands the adjustment range of the luminous brightness of the light emitting element 14 and expands the application range of the light emitting element 14. Specifically, in the embodiment shown in the figure, a current mirror structure can be used to realize output 2 J -1 different drive current size. More specifically, please refer to Figure 1, N <0> ~N <m-1>The switch element 20 of the current mirror branch is used to control the on or off working state of the corresponding current mirror branch. The J current mirror branches are combined with the on or off state of the J switch elements 20 to generate 2 J -1 different current size. 2 J -1 different current value is exactly equal to the driving current flowing through the light emitting element 14, which is used to drive the light emitting element 14 to emit light, thereby adjusting the light emitting brightness of the light emitting element 14. As shown in FIG4 , when J=2, combined with N <0> and N <1> The working state can generate 3 sets of driving current values, namely I1=K1×I ref , I2=K2×I ref , I3=K1×I ref +K2×I ref .2 J -1 driving current, and can be combined with digital signals to modulate the conduction time of the switch element 20, so that the adjustable brightness range of the light emitting element 14 is wider and applicable to more application scenarios. It is understandable that N <0> ~N <m-1>In the all-off state, the light emitting element 14 cannot be lit, so there are 2 J -1 current size.

[0165] It is understood that in other embodiments, other methods can be used to enable the drive current generating circuit 16 to generate the drive current, and it is not limited to the current mirror structure. The specific value of J can be determined based on factors such as the requirements for adjusting the luminance of the light-emitting element 14, the cost and complexity of the pixel circuit 12, etc. For example, if the luminance adjustment of the light-emitting element 14 is more refined, the value of J can be set to a larger value. If the cost requirements for the pixel circuit 12 are low, or if the luminance adjustment of the light-emitting element 14 does not need to be refined, the value of J can be set to a smaller value, etc. The present invention is not specifically limited to this.

[0166] In some embodiments, the control unit 18 is configured to: after receiving the multi-bit pixel data, parse the multi-bit pixel data using the first preset information table to obtain an analog signal and a digital signal.

[0167] In this way, analog signals and digital signals can be obtained quickly and conveniently. Specifically, the first preset information table can be an information table pre-configured with a certain correspondence relationship, and the first preset information table can be stored in the control unit 18 or other locations, which is not specifically limited in the present invention.

[0168] After receiving the multi-bit pixel data, the control unit 18 can match the corresponding modulation signal by table lookup matching, and the modulation signal includes an analog signal and a digital signal. In one embodiment, the multi-bit pixel data includes an analog signal input from one path and a digital signal input from another path. In one embodiment, the multi-bit pixel data is a mixed signal formed by the analog signal and the digital signal input from one path, and the mixed signal is parsed to obtain the analog signal and the digital signal. In one embodiment, the analog signal can be represented as Analog Bits, the digital signal can be represented as Digital Bits, and the mixed signal can be represented as Analog & Digital. Whether it is an analog signal, a digital signal or a mixed signal, it can be matched to the corresponding modulation signal by table lookup matching through the first preset information table. For example, for a mixed signal of Analog & Digital mixed mode, in the first preset information table, 0001 is set to correspond to analog 1 digital 0 (indicating that the analog signal is 1 and the digital signal is 0, the same below), 0010 corresponds to analog 1 digital 1, 0011 corresponds to analog 1 digital 2, etc. This setting method can be relatively random, but the corresponding method can be flexibly defined in advance, making the data input method more flexible and adjustable.

[0169] In some embodiments, the pixel driving circuit 100 includes a level converter 38 , which is electrically connected between the control unit 18 and the switch element 20 . The level converter 38 is configured to implement mutual conversion between the analog voltage domain and the digital voltage domain.

[0170] This allows the control unit 18 to control conduction of the switching element 20 .

[0171] Specifically, the level shifter 38 can be used to achieve mutual conversion between the analog voltage domain and the digital voltage domain. In one embodiment, because the turn-on voltage range of the micro-LED is between 2V and 3V, combined with the conduction voltage drop of the MOS switch tube and the current tube, the analog voltage domain range will be higher than 3V. Since the digital voltage domain is generally lower than the analog voltage domain, the level shifter 38 can be used to enable the low digital voltage domain to drive the higher analog voltage domain, thereby increasing the voltage of the control signal output by the control unit 18, so that the control signal can control the conduction of the switch element 20.

[0172] In one embodiment, if no conversion between levels is involved, the level converter 38 can be omitted. Optionally, based on resource requirements, the level converter 38 can be provided in the pixel circuit 12 or in a peripheral circuit of the pixel circuit 12, which is not specifically limited in the present invention.

[0173] In some embodiments, the pixel driving circuit 100 includes an inverter connected between the level shifter 38 and the switching element 20 .

[0174] This allows the pixel driving circuit 100 to have a wider range of applications. Specifically, in the embodiments of Figures 1 to 9 , the switch element 20 is an NMOS transistor, and the logic operation gate 34 is an AND logic gate. In the embodiment of Figure 10 , when the switch element 20 is a PMOS transistor, the pixel driving circuit 100 includes an inverter connected between the level converter 38 and the switch element 20. The inverter can invert the control signal output by the level converter 38, thereby controlling the on / off state of the PMOS transistor, thereby expanding the application range of the pixel driving circuit 100.

[0175] In some embodiments, the pixel driving circuit 100 includes a memory 36 , which is electrically connected to the control unit 18 , and the memory 36 is configured to store digital signals and analog signals.

[0176] Thus, the digital signal and the analog signal can be stored in the memory 36. Specifically, after the control unit 18 obtains the analog signal and the digital signal, the analog signal and the digital signal can be stored in the memory 36. The memory 36 can be a memory 36 (memory) with a multi-bit function.

[0177] Optionally, the memory 36 may be provided in the pixel circuit 12 (Memory in Pixel) or in a peripheral circuit of the pixel circuit 12, which is not specifically limited in the present invention.

[0178] It is understandable that in other implementations, the input analog signals and digital signals may not be stored. This allows for selective storage based on demand, saves certain resources, and allows for flexible multi-mode storage in a variety of application scenarios.

[0179] In some embodiments, the pixel driving circuit 100 includes a memory 36, which is electrically connected to the control unit 18. The memory 36 is configured to, after receiving multi-bit pixel data, parse the multi-bit pixel data using a second preset information table to obtain and store digital signals and analog signals, and transmit the digital signals and analog signals to the control unit 18.

[0180] Thus, the memory 36 can be used to acquire and store digital signals and analog signals, and send the analog signals and digital signals to the control unit 18 .

[0181] Specifically, the memory 36 can be a memory 36 with a multi-bit (bits) function, and the second preset information table can be an information table pre-configured with a certain correspondence. The memory 36 can use the second preset information table to match the multi-bit pixel data to the corresponding digital signal (digital modulation signal) and analog signal (analog modulation signal) through a table lookup matching method. The matched digital signal and analog signal can be input to the control unit 18. The specific configuration method of the second preset information table can refer to the configuration method of the first preset information table. Optionally, the second preset information table and the first preset information table can have the same configuration method.

[0182] The second preset information table can flexibly define the corresponding method and can also flexibly match the corresponding relationship according to needs. The input multi-bit pixel data can be stored or not stored. This can not only achieve selective storage according to needs, but also save certain resources and flexibly realize multi-mode storage in various application scenarios.

[0183] In some embodiments, the pixel driving circuit 100 includes a digital processing unit 40, which is electrically connected to the control unit 18 and configured as follows:

[0184] In the process of the control unit 18 controlling the driving current size according to the analog signal, if the actual driving current does not meet the expected value, the digital signal is adjusted according to the difference between the actual driving current and the expected value to compensate for the luminous duration, thereby eliminating the problem of discontinuous luminous brightness of the light-emitting element 14 caused by the actual driving current not meeting the expected value.

[0185] In this way, the continuity of brightness during the analog modulation process can be guaranteed. Specifically, a digital IP module is provided in the digital processing unit 40, which can determine the calculation and distribution of analog and digital data. In this embodiment, the magnitude of the driving current is obtained by copying a certain proportion of the reference current through a current mirror structure. In actual use, due to errors in the process differences, size differences, etc. of the various components of the driving current generating circuit 16 exceeding the design value, or factors such as current mirror mismatch, the actual driving current obtained by the conduction state of the switching element 20 does not meet the expected value. The actual driving current does not meet the expected value can be understood as the difference between the actual driving current and the expected value is outside the expected range. For example, referring to Figure 4, each light-emitting element 14 is connected to two current branches. When both switching elements 20 are turned on, the expected value of the driving current flowing through the light-emitting element 14 is I3'=K1×I ref +K2×I ref When the difference |I3-I3'| between the actual driving current I3 and the expected value I3' is outside the expected range, it is determined that the actual driving current does not meet the expected value. The expected range can be set according to needs and is not specifically limited in the present invention.

[0186] Because the brightness of light-emitting element 14 is the integral of the current over time, when the actual driving current does not meet the expected value, the brightness of light-emitting element 14 may be discontinuous, for example, the light-emitting element 14 may suddenly dim or brighten. Therefore, digital processing unit 40 can adjust the digital signal based on the difference between the actual driving current and the expected value to compensate for the lighting duration, thereby eliminating the discontinuous brightness of light-emitting element 14 caused by the actual driving current not meeting the expected value.

[0187] For example, when the actual driving current does not meet the expected value and is less than the expected value, the control unit 18 can adjust the digital signal to increase the light-emitting duration to compensate, so that the light-emitting brightness of the light-emitting element 14 remains substantially unchanged. Optionally, when adjusting the digital signal to increase the light-emitting duration to compensate, the comparison value (m) of the comparator 32 can be increased by adjusting the digital signal, thereby increasing the pulse width of the pulse width modulation signal.

[0188] For another example, if the actual drive current does not meet the expected value and is greater than the expected value, the control unit 18 can adjust the digital signal to reduce the light-emitting duration to compensate, so that the light-emitting brightness of the light-emitting element 14 remains substantially unchanged. Alternatively, when adjusting the digital signal to reduce the light-emitting duration, the digital signal can be adjusted to reduce the comparison value (m) of the comparator 32, thereby reducing the pulse width of the pulse-width modulation signal. The amount of increase or decrease can be pre-calibrated and stored through simulation, testing, etc., and is not specifically limited in this invention.

[0189] The present invention does not specifically limit the location of the digital processing unit 40. Alternatively, the digital processing unit 40 can be located outside the pixel circuit 12.

[0190] Thus, the digital processing unit 40 can ensure the continuity of brightness during the analog modulation process. Specifically, when brightness discontinuity occurs during the analog modulation process, digital compensation adjustment can be performed or dynamic adjustment can be achieved by adjusting the modulation signal length, thereby ensuring the continuity of brightness during the analog modulation process.

[0191] 1 to 11 , the pixel driving circuit 100 according to a specific embodiment of the present invention will be further described below.

[0192] 1 and 4 , for the pixel driving circuit 100 shown in FIG1 , assuming the number of bits of the analog signal (Analog Bits) J=2 and the global mode (Global mode), the corresponding digital-analog hybrid pixel circuit 12 with a current mirror structure is shown in FIG4 .

[0193] Assume that N=8, J=2, m=2, LSB=1, MSB=0 in the analog signal, and the working timing diagram under this condition is shown in Figure 5. The timing diagrams in the relevant embodiments all select a periodic mode of uniform width of the clock signal. The actual clock signal can be a period of equal width or a period of unequal width. When the count value of the counter 30 is ≤2, the level of the modulation signal output by the comparator 32 (Comparator) is a high level (first level). Combined with the set signal (Reset), the final output of the comparator 32 is shown in Figure 5. The output of the comparator 32 performs a logical AND operation with the input 2-bit analog signal, and the final output is the control signal EM that determines the selection of the switch element 20. <0> With EM <1> The output control signal is converted into voltage domain by level converter 38 (Level Shifter), thus realizing the <0> With N <1> At this time, the control signal EM <0> The value is 1 during the time when the count value is ≤ 2 after the set signal is set high. <0> Conductivity, K1×I ref The driving current flows through the light emitting element 14, and the light emitting duration is determined by the output of the comparator 32. The control signal EM <1> The whole process is low level, N <1> Shut down.

[0194] Assuming N = 8, J = 2, m = 4, and the analog signal has LSB = 1 and MSB = 1, the operating timing diagram under this condition is shown in Figure 6. When the count value of counter 30 is ≤ 4, the level of the modulation signal output by comparator 32 is high. Combined with the set signal, the modulation signal output by comparator 32 is shown in Figure 6. The modulation signal output by comparator 32 is logically ANDed with the input 2-bit analog signal, and the final output is the control signal EM that determines the gating of switch element 20. <0> With EM <1> As shown in Figure 6. <0> &EM <1> The count value of the counter 30 after the set signal is set high is 1 for a period of time ≤ 4. <0> &N <1> All conduction, K1×I ref +K2×I ref The driving current flows through the light-emitting element 14, and the light-emitting duration is determined by the output of the comparator 32.

[0195] 5 and 6 and the output waveform of the comparator 32 and the driving current I of the light emitting element 14 Micro-LED The waveforms and numerical values ​​show that adjusting the set value m determines the duration of the light emission. Changing the information in the analog signal adjusts the operating state of the switch element 20 in the current mirror branch, thereby determining the magnitude of the drive current flowing through the light-emitting element 14. The light emission duration and the magnitude of the drive current together determine the brightness of the light-emitting element 14.

[0196] For the pixel circuit 12 of FIG1 , assuming that the number of bits of the analog signal J=4 and the global mode is used, the corresponding digital-analog hybrid pixel circuit 12 of the current mirror structure is shown in FIG7 .

[0197] Assuming N = 8, J = 4, m = 3, and the 4 bits of the analog signal are 0111 from high to low, the operating timing diagram under this condition is shown in Figure 8. When the count value of counter 30 is ≤ 3, the level of the modulation signal output by comparator 32 is high. Combined with the set signal, the modulation signal output by comparator 32 is shown in Figure 8. The modulation signal output by comparator 32 is logically ANDed with the input 4-bit analog signal, and the final output is the control signal EM that determines the gating of switch element 20. <0> ~EM <3> As shown in Figure 8. <0> ~EM <2> The value is 1 within the time when the count value is ≤3 after the set signal is set high. <0> &N <1> &N <2> All conduction, K1×I ref +K2×I ref +K3×I ref A current flows through the light-emitting element 14 , and the light-emitting duration is determined by the output of the comparator 32 .

[0198] The above Figures 4 to 8 are explained using one frame timing as an example. In order to better present the modulation mode of this mode, a continuous 2-frame timing is used to describe the modulation mode. Assume that N=8, J=4, m=2 in the first frame, and the 4 bits of the analog signal are 0111 from high to low. In the second frame, m=7, and the 4 bits of the analog signal are 1010 from high to low. The corresponding timing diagram is shown in Figure 9. It can be seen that changing the m value can modulate the luminous duration, and changing the analog signal can adjust the driving current of the light-emitting element 14. Therefore, the pixel driving circuit 100 of this architecture can realize the modulation of the luminous brightness of the light-emitting element 14 in the following three ways.

[0199] 1. Ensure the consistency of the luminous duration, adjust the analog signal, switch the on-off state of the switch element 20, adjust the driving current of the light-emitting element 14, and realize luminous brightness modulation.

[0200] 2. Ensure the consistency of the analog signal (ie the driving current flowing through the light-emitting element 14 is consistent), adjust the light-emitting duration, and realize light-emitting brightness modulation.

[0201] 3. Synchronously adjust the luminous duration and analog signal (driving current) to achieve luminous brightness modulation.

[0202] It should be noted that the above embodiments are all described with NMOS transistors as the switch element 20 in the current mirror branch. If the NMOS transistor is replaced with a PMOS transistor, the same solution is also applicable. Simply replace the AND logic gate of the control unit 18 with a NAND logic gate, or add an inverter after the level shifter 38, depending on the difference in logic control signals between the NMOS and PMOS transistors. The corresponding structure after replacement is shown in Figure 10 , and the relevant embodiments can be equivalently replaced.

[0203] The above embodiments all describe analog signals in global mode. This solution also applies if the analog signal is adjusted to local mode. For example, with an analog signal with a bit number J = 4 and in local mode, the corresponding digital-analog hybrid pixel circuit 12 with a replaced current mirror structure is shown in FIG11 . Equivalent replacements can be made for other related embodiments.

[0204] The pixel driving circuit 100 according to the embodiment of the present invention has at least the following features:

[0205] 1. This pixel driver circuit 100 uses a current mirror structure to generate the drive current for the light-emitting element 14. The number of current mirror branches is flexibly adjustable, allowing for flexible current modulation of the light-emitting element 14 by increasing or decreasing the number of current mirror branches based on actual needs. This solution offers a wider current modulation range, making it suitable for various application scenarios; it also eliminates the need to consider Vth compensation consistency issues for the driver transistor.

[0206] 2. Digital-Analog Hybrid Modulation Mode: Control unit 18 controls the pulse width of the modulation signal based on the PWM signal. It also modulates the on / off state of switch element 20 in the current mirror branch based on the input J-bit analog signal, thereby determining the driving current flowing through light-emitting element 14. This hybrid digital-analog modulation method jointly determines the brightness of light-emitting element 14.

[0207] 3. The analog signal in the multi-bit pixel data of the pixel driving circuit 100 can be either a global signal or a local signal, which makes the signal mode more flexible and enables flexible modulation of the on-off state of the current mirror branch switch element 20.

[0208] 4. In the pixel driving circuit 100, the memory 36 in the pixel circuit 12 (Memory in Pixel) has a storage capacity of multiple bits. A certain correspondence can be pre-configured for controlling digital and analog signals to achieve modulation of the analog and digital signals. The correspondence can be flexibly defined, and the correspondence can be flexibly matched as needed. The analog and digital signals can be analog signals with a certain number of bits, digital signals with a certain number of bits, or mixed signals in a mixed analog and digital form.

[0209] 5. The memory 36 in the pixel driving circuit 100 is more flexible and selective. For the input analog signals and digital signals, relevant processing can be performed immediately without storage, or they can be stored and subsequently processed as needed.

[0210] 6. The clock circuit 28 can be a single clock signal input to the pixel circuit 12 or multiple clock signals can be input to the pixel circuit 12. The clock signal can have a period of equal width or a period of unequal width, and the period can be adjusted accordingly.

[0211] 7. The digital processing unit 40 includes a digital IP module that determines the calculation and distribution of analog and digital data. If brightness discontinuities occur during analog modulation, digital compensation can be implemented or dynamic adjustment can be achieved by adjusting the pulse width of the modulation signal, thereby ensuring brightness continuity during analog modulation.

[0212] An embodiment of the present invention provides a display device including the pixel driving circuit 100 of any of the above embodiments.

[0213] In the above-mentioned display device, the control unit 18 can perform logical operations on the input multi-bit pixel data, control the on and off of the corresponding switching element 20 and the on-time of the switched-on switching element 20, so as to modulate the brightness of the light-emitting element 14, so that the light-emitting element 14 can be suitable for more application scenarios.

[0214] Specifically, the display device can be a self-luminous display device, including but not limited to a micro light-emitting diode (Micro-LED) display device, a light-emitting diode (LED) display device, an organic light-emitting diode (OLED) display device, etc., and the present invention does not make specific limitations on this.

[0215] It should be noted that the above explanations of the implementation and beneficial effects of the pixel driving circuit 100 are also applicable to the display device of this embodiment, and will not be elaborated here in detail to avoid redundancy.

[0216] Throughout this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" indicate that a specific feature, structure, material, or characteristic described in connection with an embodiment or example is included in at least one embodiment or example of the present invention. In this specification, illustrative uses of these terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0217] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, combinations, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A pixel driving circuit, characterized in that: A pixel circuit is included, wherein the pixel circuit includes: at least one light-emitting element; at least one driving current generating circuit, the driving current generating circuit comprising a switching element, the switching element being electrically connected to the light-emitting element, the driving current generating circuit being configured to provide a driving current to a corresponding light-emitting element when a corresponding switching element is turned on; A control unit is electrically connected to the switching element, and the control unit can perform logical operations on the input multi-bit pixel data in the pixel circuit to control the on and off of the corresponding switching element and the on time of the switched-on switching element to modulate the brightness of the light-emitting element.

2. The pixel driving circuit according to claim 1, wherein: The multi-bit pixel data may form one or more bits of analog signals and one or more bits of digital signals; The control unit performs a logic operation on the analog signal and the digital signal to jointly modulate the on / off state of the corresponding switching element and / or the on-time of the switched-on switching element.

3. The pixel driving circuit according to claim 2, wherein: The multi-bit pixel data is a mixed signal formed by inputting an analog signal and a digital signal through one channel, and the mixed signal is parsed to obtain the analog signal and the digital signal; Alternatively, the multi-bit pixel data includes the analog signal input from one path and the digital signal input from another path.

4. The pixel driving circuit according to claim 3, wherein: The analog signal is used to control the on / off state of the corresponding switching element to control the magnitude of the driving current, and the digital signal is used to control the on-time of the switched-on switching element to control the luminous time of the luminous element.

5. The pixel driving circuit according to claim 4, wherein: The control unit includes a logic operation gate, the output end of the logic operation gate is connected to the switch element, and the input end of the logic operation gate is used to receive the analog signal and a pulse width modulation signal, and the pulse width modulation signal is modulated according to the digital signal.

6. The pixel driving circuit according to claim 5, wherein: The pulse width of the pulse width modulation signal is positively correlated or negatively correlated with a set value, and the set value is determined by the digital signal.

7. The pixel driving circuit according to claim 6, wherein: The pixel driving circuit includes a clock circuit, a counter and a comparator; The clock circuit is configured to output a clock signal; The counter is configured to receive the clock signal and count the number of pulses of the clock signal; The comparator is configured to output the pulse width modulation signal according to the relationship between the count value of the counter and the set value; The logic operation gate is configured to output a control signal for controlling the on / off state of the switch element according to the pulse width modulation signal and the analog signal.

8. The pixel driving circuit according to claim 7, wherein: When the count value of the counter is less than or equal to the set value, the level of the pulse width modulation signal is the first level, and the level of the analog signal is the first level, the control signal output by the logic operation gate is a signal for controlling the switching element to be turned on; When the count value of the counter is less than or equal to the set value, the level of the pulse width modulation signal is the first level, and the level of the analog signal is the second level, the control signal output by the logic operation gate is a signal for controlling the switching element to be turned off; When the count value of the counter is greater than the set value, the level of the pulse width modulation signal is the second level, and when the level of the analog signal is the second level, the control signal output by the logic operation gate is a signal for controlling the switching element to be turned off; When the count value of the counter is greater than the set value, the level of the pulse width modulation signal is the second level, and when the level of the analog signal is the first level, the control signal output by the logic operation gate is a signal for controlling the switching element to be turned off.

9. The pixel driving circuit according to claim 7, characterized in that: When the count value of the counter is less than or equal to the set value, the level of the pulse width modulation signal is the first level, and the level of the analog signal is the second level, the control signal output by the logic operation gate is a signal for controlling the switching element to be turned on; When the count value of the counter is less than or equal to the set value, the level of the pulse width modulation signal is the first level, and the level of the analog signal is the first level, the control signal output by the logic operation gate is a signal for controlling the switching element to be turned off; When the count value of the counter is greater than the set value, the level of the pulse width modulation signal is the second level, and when the level of the analog signal is the first level, the control signal output by the logic operation gate is a signal for controlling the switching element to be turned on; When the count value of the counter is greater than the set value, the level of the pulse width modulation signal is the second level. When the level of the analog signal is the second level, the control signal output by the logic operation gate is a signal for controlling the switching element to be turned on.

10. The pixel driving circuit according to claim 5, wherein: The pixel driving circuit has a global mode. In the global mode, the pixel driving circuit is configured to allow the analog signal to be directly input to the logic operation gate.

11. The pixel driving circuit according to claim 5, wherein: The pixel driving circuit has a local mode, and the pixel driving circuit includes a memory. In the local mode, the pixel driving circuit is configured to input the analog signal and the digital signal into the memory, and input the analog signal from the memory into the logic operation gate.

12. The pixel driving circuit according to claim 1, wherein: The pixel driving circuit includes a reference current generating circuit, which is electrically connected to the at least one driving current generating circuit. The reference current generating circuit and the corresponding one of the driving current generating circuits form a current mirror structure.

13. The pixel driving circuit according to claim 12, wherein: The reference current generating circuit is configured to provide a reference current to each of the driving current generating circuits; The drive current generating circuit is configured to generate the drive current related to the reference current.

14. The pixel driving circuit according to claim 13, wherein: The driving current and the reference current satisfy the following conditions: M =K M ×I ref , I ref Represents the reference current, I M Indicates the driving current generated by the Mth driving current generating circuit, K M is the coefficient of the Mth driving current generating circuit, M<=J, J is the number of the driving current generating circuits, M and J are natural numbers and J>=1.

15. The pixel driving circuit according to claim 14, wherein: The reference current generating circuit includes a first transistor, the driving current generating circuit includes a second transistor, and a coefficient of the driving current generating circuit is negatively correlated with the aspect ratio of the first transistor and positively correlated with the aspect ratio of the second transistor.

16. The pixel driving circuit according to claim 2, wherein: The control unit is configured to control the on-off state of the switch element according to the analog signal to obtain 2 J -1 different driving current magnitudes, where J is the number of the driving current generating circuits, J is a natural number and J>=1.

17. The pixel driving circuit according to claim 2, wherein: The control unit is configured to: after receiving the multi-bit pixel data, parse the multi-bit pixel data using a first preset information table to obtain the analog signal and the digital signal.

18. The pixel driving circuit according to claim 2, wherein: The pixel driving circuit includes a level converter, which is electrically connected between the control unit and the switching element. The level converter is configured to achieve mutual conversion between an analog voltage domain and a digital voltage domain.

19. The pixel driving circuit according to claim 18, wherein: The pixel driving circuit includes an inverter connected between the level shifter and the switching element.

20. The pixel driving circuit according to claim 1, wherein: The pixel driving circuit includes a memory electrically connected to the control unit, and the memory is configured to store the multi-bit pixel data.

21. The pixel driving circuit according to claim 2, wherein: The pixel driving circuit includes a memory, which is electrically connected to the control unit. The memory is configured to, after receiving multi-bit pixel data, parse the multi-bit pixel data using a second preset information table to obtain and store the digital signal and the analog signal, and transmit the digital signal and the analog signal to the control unit.

22. The pixel driving circuit according to claim 4, wherein: The pixel driving circuit includes a digital processing unit, which is electrically connected to the control unit and configured as follows: In the process of the control unit controlling the driving current size according to the analog signal, if the actual driving current does not meet the expected value, the digital signal is adjusted according to the difference between the actual driving current and the expected value to compensate for the luminous duration, thereby eliminating the problem of discontinuous luminous brightness of the light-emitting element caused by the actual driving current not meeting the expected value.

23. A display device, characterized in that: The pixel driving circuit comprises the pixel driving circuit according to any one of claims 1 to 22.

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