Communication method and communication apparatus based on PC code

Abstract

Provided in the present application are a communication method and communication apparatus based on a PC code, in which PC coding and CRC coding are mainly used to implement the precoding of information bit sequences transmitted in a broadcast channel, an uplink data channel and a downlink data channel, or information bit sequences carried in control information, followed by channel coding, so that the coding gain of channel coding can be improved, thereby facilitating an improvement in the communication quality. In addition, the method can improve the error correction performance when the number of payloads increases, and can also achieve a further improvement in the coding gain when a mother code length increases.

Description

A communication method and communication device based on PC code This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on March 22, 2024, with application number 202410345265.9 and application name “A communication method and communication device based on PC code”, the entire contents of which are incorporated by reference into this application. Technical Field The present application relates to the field of channel coding, and more specifically, to a communication method and a communication device based on PC code. Background Art Communication systems usually use channel coding to improve the reliability of data transmission and ensure the quality of communication. The coding gain of channel coding, such as physical broadcast channel (PBCH) coding, physical uplink shared channel (PUSCH) coding, physical downlink shared channel (PDSCH) coding, downlink control information (DCI) coding, and uplink control information (UCI) coding, is directly related to the user's communication quality. Therefore, how to further improve the coding gain of channel coding is an urgent problem to be solved. Summary of the Invention The present application provides a communication method and a communication device based on PC code, which can improve the coding gain of channel coding and help improve communication quality. In a first aspect, a method based on PC code is provided. The method can be performed by a first communication device, a component in the first communication device (e.g., a processor, a chip, a chip system, a hardware circuit, etc.), or a logic module or software capable of implementing all or part of the functions of the first communication device. The method includes: Acquiring a payload sequence, the payload sequence including an information bit sequence carried by control information or an information bit sequence transmitted by any one of a broadcast channel, an uplink data channel, and a downlink data channel; performing pre-transformation coding on the payload sequence, the pre-transformation coding including cyclic redundancy check (CRC) coding and parity check (PC) coding, to obtain an output sequence; and performing channel coding on the output sequence to obtain a codeword sequence. In the above scheme, PC coding and CRC coding are used to implement precoding for information bit sequences transmitted in broadcast channels, uplink data channels, downlink data channels, or information bit sequences carried in control information, and then channel coding is performed. This can improve the coding gain of channel coding and help improve communication quality. In a second aspect, a method based on PC code is provided. The method can be performed by a second communication device, a component in the second communication device (e.g., a processor, a chip, a chip system, a hardware circuit, etc.), or a logic module or software capable of implementing all or part of the functions of the second communication device. The method includes: Acquire a received sequence; perform channel decoding on the received sequence to obtain a first bit sequence; perform pre-transform decoding on the first bit sequence, the pre-transform decoding including CRC decoding and parity check (PC) decoding, to obtain a decoded sequence; wherein the pre-transform decoding is performed on an encoded payload sequence, the payload sequence including an information bit sequence carried by control information or an information bit sequence transmitted by any one of a broadcast channel, an uplink data channel, and a downlink data channel. In the above scheme, after channel decoding is performed on the received sequence, pre-coding decoding is performed. The pre-transformation decoding includes CRC decoding and parity check PC decoding for the information bit sequence transmitted in the broadcast channel, uplink data channel, downlink data channel or the information bit sequence carried in the control information, which can improve the decoding performance. In combination with the first and second aspects, in certain implementations of the first and second aspects, the channel coding includes polarization coding, and a mother code length N used by the polarization coding is greater than or equal to 1024. In this implementation, polarization coding can be used for channel coding, and the mother code length of polarization coding can be increased. Using a longer mother code length can increase the coding gain, which is beneficial to improving network coverage and user transmission rate. In combination with the first aspect and the second aspect, in certain implementations of the first aspect and the second aspect, the payload length K of the payload sequence includes one of 32, 40, 48, 56, and 64. In this implementation, when the payload sequence includes an information bit sequence of any one of an uplink data channel, a downlink data channel, downlink control information, and uplink control information, the payload length of the payload sequence may include one of 32, 40, 48, 56, 64, or any other natural number. It should be understood that the payload length of the payload sequence refers to the information bit sequence in the channel or information, excluding the CRC bit sequence. In combination with the first aspect and the second aspect, in certain implementations of the first aspect and the second aspect, the payload sequence includes an information bit sequence in a broadcast channel. In this implementation, when the payload sequence includes an information bit sequence in a broadcast channel, the payload length of the payload sequence may include one of 32, 40, 48, 56, and 64. In combination with the first aspect and the second aspect, in certain implementations of the first aspect and the second aspect, the rate matching method used by the polar coding is puncturing. In this implementation, when the mother code length increases, the coding bit length supported by the channel resources is the first value (unchanged), and when the mother code length is greater than the first value, the channel resources cannot support the current mother code length to perform rate matching in a repeated manner, and the rate matching method can be puncturing. It should be understood that when the coded bit length supported by the channel resources is greater than the mother code length, the rate matching mode of the polar coding may be repetition. In combination with the first aspect, in certain implementations of the first aspect, the pre-transform encoding of the payload sequence includes: performing PC encoding on the payload sequence according to a first shift register. In this implementation, the PC bits may be generated based on the first shift register. In combination with the first aspect, in certain implementations of the first aspect, the pre-transformation code is a non-systematic code, and if the current position of the payload sequence corresponds to a message bit, the output bit of the first shift register is read from the first shift register. In combination with the first aspect, in certain implementations of the first aspect, the pre-transformation code is a system code, and the output of the first shift register is related to the set to which the current position of the payload sequence belongs. If the current position of the payload sequence belongs to the message bit set, the output of the first shift register is the input of the first shift register; if the current position of the payload sequence belongs to the dynamic frozen bit set, the output bit of the first shift register is read from the first shift register; if the current position of the payload sequence belongs to the frozen bit set, the output of the first shift register is 0. In combination with the first aspect, in certain implementations of the first aspect, the pre-transformation encoding of the payload sequence includes: PC encoding the payload sequence according to a second shift register; the length of the second shift register is 5; if the current position of the payload sequence corresponds to a message bit, the current bit and the value of the leftmost shift register of the second shift register are XORed and stored in the leftmost shift register, and the currently input message bit is used as the bit at the current position, and then the second shift register is cyclically shifted; if the current position of the payload sequence is a check bit, the value of the leftmost shift register is taken out as the check bit, and then the second shift register is cyclically shifted; if the current position of the payload sequence is a frozen bit, zero is directly output as the bit at the current position, and then the second shift register is cyclically shifted. In this implementation, the PC bits may be generated based on the first shift register. In combination with the first aspect and the second aspect, in certain implementations of the first aspect and the second aspect, the payload sequence includes an information bit sequence of a broadcast channel, and the n pc >0, In this implementation, n pc The number increased, but Still 0. This means sacrificing some message bits with smaller row weight and highest reliability as PC positions, which will affect the decoding performance under SC. This means that there is no need to sacrifice message bits as PC positions, thereby ensuring decoding reliability. In a third aspect, a communication device is provided, wherein the communication device has the function of implementing the method of the first aspect or the second aspect, or the method in any possible implementation of the first aspect or the second aspect. The function can be implemented by hardware, or by hardware executing corresponding software implementation. The hardware or software includes one or more units corresponding to the above-mentioned functions. In a fourth aspect, the present application provides a communication device, comprising at least one processor, wherein the at least one processor is coupled to at least one memory, the at least one memory being used to store computer programs or instructions, and the at least one processor being used to call and run the computer program or instructions from the at least one memory, so that the communication device executes the method in the first aspect or any possible implementation thereof, or executes the method in the second aspect or any possible implementation thereof. In a fifth aspect, the present application provides a communication device comprising a communication interface and a circuit, wherein the communication interface is configured to receive a payload sequence and input the payload sequence into the circuit; the circuit is configured to perform pre-transform encoding on the input sequence to obtain an output sequence; and the communication interface is further configured to output the output sequence. Optionally, the circuit can be configured to perform system encoding on the output sequence to obtain a codeword sequence. In this case, the communication interface is configured to output the codeword sequence. As an example, the communication device of the third to fifth aspects is an encoding device, such as an encoder. In a sixth aspect, the present application provides a computer-readable storage medium, which stores computer program code or instructions. When the computer instructions are executed on a computer, the method as in the first aspect or any possible implementation thereof is implemented, or the method as in the second aspect or any possible implementation thereof is implemented. In a seventh aspect, the present application provides a computer program product, comprising computer program code or instructions, which, when the computer program code or instructions are run on a computer, enables the method in the first aspect or any possible implementation thereof to be implemented, or the method in the second aspect or any possible implementation thereof to be implemented. In an eighth aspect, the present application provides a wireless communication system, comprising a communication device as described in any one of the third to fifth aspects. BRIEF DESCRIPTION OF THE DRAWINGS FIG1 is a schematic diagram of a system architecture of a communication system applicable to an embodiment of the present application. Figure 2 is a flow chart of the communication system. FIG3 is a schematic diagram of the PBCH encoding process. FIG4 is a schematic diagram of a PC code-based communication method 400 applicable to an embodiment of the present application. Figure 5 is a schematic diagram of the simulation structure of the coding performance of NR PBCH with different mother code lengths during the coding process applicable to an embodiment of the present application. FIG6 is a schematic diagram of an encoding process applicable to an embodiment of the present application. FIG7 is a schematic structural diagram of a first shift register applicable to an embodiment of the present application. FIG8 is a schematic structural diagram of a first shift register applicable to an embodiment of the present application. FIG9 is a schematic structural diagram of a first shift register applicable to an embodiment of the present application. FIG10 is a schematic structural diagram of a first shift register applicable to an embodiment of the present application. FIG11 is a schematic diagram showing simulation results of the coding performance of the PBCH using PC coding and CRC coding based on the first shifter, which is applicable to an embodiment of the present application. FIG12 is a schematic structural diagram of a second shift register applicable to an embodiment of the present application. FIG13 is a schematic diagram showing simulation results of the coding performance of the PBCH using PC coding and CRC coding based on the second shifter applicable to an embodiment of the present application. FIG14 is a schematic structural diagram of a communication device provided in this application. FIG15 is a schematic structural diagram of another communication device provided in this application. FIG16 is a schematic structural diagram of another communication device provided in this application. DETAILED DESCRIPTION The technical solution in this application will be described below with reference to the accompanying drawings. The technical solutions of the embodiments of the present application can be applied to various communication systems, including but not limited to: satellite communication systems, fifth generation (5G) systems, long term evolution (LTE) systems (LTE frequency division duplex (FDD) systems, LTE time division duplex (TDD) systems), etc. The technical solutions provided in the present application can also be applied to future communication systems, such as the sixth generation mobile communication system. In addition, it can also be applied to device to device (D2D) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), and Internet of Things (IoT) communication systems, or other communication systems, etc., which are not limited in this article. The technical solutions of the embodiments of the present application can also be applied to narrowband Internet of Things (NB-IoT) systems, global system for mobile communications (GSM), enhanced data rate for GSM evolution (EDGE), wideband code division multiple access (WCDMA), code division multiple access 2000 (CDMA2000), time division-synchronization code division multiple access (TD-SCDMA), and the three major application scenarios of the next generation 5G mobile communication system: enhanced mobile broadband (eMBB), ultra-reliable and low-latency communications (URLLC), and massive machine type communications (eMTC). Figure 1 is a schematic diagram of the system architecture of a communication system applicable to the technical solution of the present application. The communication system may include one or more network devices and one or more terminal devices. For example, a terminal device may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, wireless communication device, user agent, or user apparatus. The terminal device in the embodiments of the present application may refer to a device that provides voice and / or data connectivity to a user and can be used to connect people, objects, and machines, such as a handheld device with wireless connection function, a vehicle-mounted device, etc. The terminal device in the embodiments of the present application can be a mobile phone, a tablet computer, a laptop computer, a PDA, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a personal digital assistant, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, a mobile terminal in a vehicle, etc. Optionally, the UE can be used to act as a base station. For example, the UE can act as a scheduling entity that provides sidelink signals between UEs in V2X or D2D, etc. In the embodiments of the present application, the device for implementing the function of the terminal can be the terminal, or it can be a device that can support the terminal to implement the function, such as a chip system or chip, which can be installed in the terminal. In the embodiments of the present application, the chip system can be composed of a chip, or it can include a chip and other discrete devices. Exemplarily, the network device may be a device with wireless transceiver functions, and the network device may be a device that provides wireless communication function services, usually located on the network side, including but not limited to the next generation base station (gNodeB, gNB) in the fifth generation (5G) communication system, the base station in the future mobile communication system, the base station in the future mobile communication system or the access node in the wireless fidelity (Wi-Fi) system, the evolved node B (eNB) in the long term evolution (LTE) system, the radio network controller (RNC), the node B (NB), the base station controller (BSC), the home base station (for example, home evolved NodeB, or home Node B, HNB), the base band unit (BBU), the transmission reception point (TRP), the transmitting point (TP), the base transceiver station (BTS), etc. In a network structure, the network device may include a centralized unit (CU) node, or a distributed unit (DU) node, or a RAN device including a CU node and a DU node, or a RAN device including a control plane CU node and a user plane CU node, and a DU node, or the network device may also be a wireless controller, relay station, vehicle-mounted device, and wearable device in a cloud radio access network (CRAN) scenario. In addition, the base station may be a macro base station, a micro base station, a relay node, a donor node, or a combination thereof. The base station may also refer to a communication module, a modem, or a chip for being set in the aforementioned device or apparatus. The base station may also be a mobile switching center and a device that performs the base station function in D2D, V2X, and M2M communications, a network-side device in a future communication network, a device that performs the base station function in a future communication system, etc. The base station can support networks with the same or different access technologies without limitation. In the embodiments of the present application, the apparatus for implementing the function of the network device may be the network device, or may be an apparatus capable of supporting the network device in implementing the function, such as a chip system or a chip, which may be installed in the network device. In the embodiments of the present application, the chip system may be composed of a chip, or may include a chip and other discrete devices. It should be understood that the parity check (PC) code-based communication method provided in this application can be used in dedicated network devices or general-purpose devices, can be applied to various network devices (e.g., base station devices) as described above, and can also be applied to various terminal devices as described above. Specifically, this solution is mainly implemented by the channel coding unit in these devices. The method provided in the embodiments of the present application can also be implemented by an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), etc., or by software (for example, program code in a memory), without limitation. In order to facilitate understanding of the technical solutions of the present application, a brief introduction to the relevant concepts or technologies involved in the embodiments is first given. 1. Polarization code Polar codes, also known as polar codes, are a new coding method based on channel polarization. They feature a deterministic construction method and are the only known channel coding method rigorously proven to achieve channel capacity. Polar codes offer the best of both algebraic and probabilistic coding. The theoretical basis of Polar codes is channel polarization. Channel polarization involves both channel combination and channel decomposition. When the number of combined channels reaches infinity, polarization occurs: some channels approach noiseless channels, while others approach fully noisy channels. This phenomenon is known as channel polarization linearity. The transmission rate of a noiseless channel reaches its capacity, while the transmission rate of a fully noisy channel approaches zero. The Polar code coding strategy exploits this phenomenon, utilizing noiseless channels to transmit useful information for users, while fully noisy channels transmit agreed-upon information or no information at all. After channel polarization is completed, the portion of the channel with a capacity close to 1 can be used to carry information bits, while the remaining channels can be used to carry frozen bits that are consistent between the transmitter and receiver. This is the polarization coding method. Polar code is a linear block code with a coding matrix (also called a generator matrix) of GN. The coding process can be expressed as follows: in, is a binary row vector (i.e., information bit sequence) with length N, where N=2 n , n is a positive integer. GN is an N×N matrix, Defined as the Kronecker product of log2N matrices F2, The addition and multiplication operations involved in the above formulas are all addition and multiplication operations on the binary Galois Field. The codes generated by this method produce polarization through successive cancellation (SC) decoding. Specifically, some bits in u are decoded correctly with high probability over an equivalent high-reliability channel, while the remaining bits are decoded correctly with low probability over an equivalent low-reliability channel. This allows the high-reliability channel to be used for information transmission, while the bits corresponding to the low-reliability channel are set to zero (i.e., frozen) and not used for data transmission, or are used to transmit data known to both communicating parties. Currently, algorithms for serial cancellation decoding also include successive cancellation list (SCL) decoding and CRC-aided successive cancellation list (CA-SCL) decoding. SC decoding has the worst decoding performance, while SCL decoding offers significant improvements. Furthermore, CA-SCL decoding, coupled with CRC checksums, can make polar codes perform better than LDPC and Turbo codes. It should be noted that Polar coding is an example of a channel coding scheme. Channel coding can also adopt other coding methods, which is not limited in the embodiments of the present application. In the present application, channel coding may include physical broadcast channel (PBCH) coding, physical uplink shared channel (PUSCH) coding, physical downlink shared channel (PDSCH) coding, downlink control information (DCI) coding, and uplink control information (UCI) coding, etc., which are not limited in the embodiments of the present application. 2. Pre-transform coding Performing upper triangular pre-transformation before polar coding can improve the code spectrum of polar codes and enhance their error correction performance. CRC coding, PC coding, and convolutional coding are examples of upper triangular pre-transformation that can improve the code spectrum of polar codes. Figure 2 is a schematic diagram of the communication system flow. As shown in Figure 2, the technical solution of this application primarily involves channel coding. Channel coding, located between source coding and modulation, is responsible for channel coding the bits generated by the source. After modulation, the transmitter sends the modulated symbols across a noisy channel to the receiver. After demodulation, the receiver performs channel decoding. Channel decoding, located between demodulation and source decoding, is responsible for recovering the source bit stream. When using Polar codes for channel coding, the transmitter uses Polar codes to channel code the signal source from the media access control (MAC). The receiver feeds the demodulated log likelihood ratio (LLR) soft information into the Polar decoder, which then recovers the signal source information and uploads it to the MAC. When wireless technology is used for communication, the signal source at the transmitter generally undergoes source coding, channel coding, rate matching, and modulation before being sent over the channel. The receiver receives the signal and undergoes demodulation, rate matching, channel decoding, and source decoding to obtain the destination. Channel coding and decoding is one of the core technologies in the field of wireless communications. Improvements in its performance will directly enhance network coverage and user transmission rates. The following takes PBCH as an example to illustrate the encoding process. FIG3 is a schematic diagram of the PBCH encoding process. In the existing PBCH channel coding, the Polar code uses a mother code length of 512, and then the rate matching method is repetition, repeatedly sending 352 bits to 864 bits long. The specific process is as follows: Step 1: Generate PBCH payload bits; Step 2: Payload scrambling; Step 3: Add CRC bits; Step ④: DCRC interleaving; Step 5: channel coding; Step 6: rate matching; Step 7: scramble the coded bits; Step ⑧: QPSK modulation; Step 9: RE mapping. As mentioned above, existing channel coding (e.g., PBCH) uses Polar codes with a mother code length of 512, but their error correction capabilities still need to be improved. Furthermore, the expected increase in channel payloads in the future will further demand the error correction capabilities of channel coding (e.g., Polar codes). In short, channel coding performance directly impacts network coverage and user transmission efficiency. In view of this, the present application provides a communication method based on PC code, which obtains a greater coding gain by increasing the mother code length during encoding. At the same time, PC coding can be added during channel coding, and the coding gain can be further improved. Figure 4 is a schematic flow chart of a PC code-based communication method 400 provided herein. Method 400 can be executed by a first communication device, a component within the first communication device (e.g., a chip, chip system, or circuit), or a logic module or software capable of implementing all or part of the functionality of the first communication device. As an example, the first communication device can be an encoding device. The following description uses an encoding device as an example. 410. The encoding device obtains a payload sequence. The payload sequence includes an information bit sequence carried by the control information or an information bit sequence transmitted by any one of a broadcast channel, an uplink data channel, and a downlink data channel. As an example, the uplink data channel may be a PUSCH, the downlink data channel may be a PDSCH, and the control information includes information transmitted on a physical uplink control channel (PUCCH) and a physical downlink control channel (PDCCH). In a possible implementation, the payload length of the payload sequence includes one of 32, 40, 48, 56, and 64. Exemplarily, when the payload sequence includes an information bit sequence in a broadcast channel, the payload length of the payload sequence may include one of 32, 40, 48, 56, and 64. Exemplarily, when the payload sequence includes an information bit sequence of any one of an uplink data channel, a downlink data channel, downlink control information, and uplink control information, the payload length of the payload sequence may include one of 32, 40, 48, 56, 64, or any other natural number. It should be understood that the payload length of the payload sequence refers to the information bit sequence in the channel or information, excluding the CRC bit sequence. 420. The encoding device performs pre-transform encoding on the payload sequence to obtain an output sequence. The payload sequence here refers to the input sequence of the pre-transform coding, and the output sequence refers to the output sequence of the pre-transform coding. 430. The encoding device performs channel encoding on the output sequence to obtain a codeword sequence. The coding device further performs channel coding, such as polar coding, on the output sequence of the pre-transform coding. Through steps 410 to 430, the coding device performs concatenated coding of the pre-transform coding and the channel coding to obtain a codeword sequence. In this embodiment, the manner in which the encoding device performs channel encoding on the output sequence of the pre-transform encoding is described using polar coding as an example, but this embodiment of the present application does not limit this. In polarization coding, using a longer mother code length can increase coding gain, which is beneficial to improving network coverage and user transmission rate. In one possible implementation, the mother code length N used in polar coding may be greater than 512. For example, N may be greater than or equal to 1024. For example, PBCH uses mother code length N=2 n Polar code, where n may be greater than 9, for example, n≥10. Figure 5 shows the coding performance of NR PBCH with different mother code lengths during the coding process, taking the performance of NR PBCH with a mother code length of 512 (black dotted line) and a mother code length of 1024 (black solid line) as examples. In Figure 5, the horizontal axis represents the symbol signal-to-noise ratio (Es / N0), and the vertical axis represents the block error rate (BLER). Es / N0 is the ratio of the energy per symbol to the noise power spectral density. This ratio is proportional to the channel conditions; a larger Es / N0 indicates better channel conditions. The block error rate (BLER) is the percentage of erroneous blocks among all transmitted blocks, or the ratio of the number of erroneous blocks to the total number of received blocks in a given time period. A lower BLER indicates better communication quality. As shown in FIG5 , as the amount of PBCH payload increases, the coding gain brought about by increasing the mother code length of PBCH coding becomes larger. In one possible implementation, the mother code length is increased, and the rate matching method used in polar coding is puncturing. It should be understood that when the mother code length increases, the coding bit length supported by the channel resources is the first value (unchanged), and when the mother code length is greater than the first value, the channel resources cannot support the current mother code length to perform rate matching in a repeated manner, and the rate matching method can be puncturing. For example, when the mother code length is 512 and the coded bit length supported by the channel resource is 864, 864 bits can be achieved by repeatedly sending 352 bits. However, when the mother code length is 1024, the coded bit length supported by the channel resource remains unchanged. Therefore, 160 bits need to be punctured from the 1024-bit mother code before polarization coding can be performed on the channel resource. It should be understood that when the coded bit length supported by the channel resources is greater than the mother code length, the rate matching mode of the polar coding may be repetition. As an example, a description of a standard text of a mother code length increase scheme is shown below. One possible example is as follows: Information bits are delivered to the channel coding block.They are denoted by c0,c1,c2,c3,...,c K-1 ,where K is the number of bits,and they are encoded via Polar coding according to Clause 5.3.1,by setting n max =10,I IL =1,n PC =0,and After encoding the bits are denoted by d0,d1,d2,d3,...,d N-1 ,where N is the number of coded bits. Another possible example is as follows: Information bits are delivered to the channel coding block.They are denoted by c0,c1,c2,c3,...,c K-1 ,where K is the number of bits,and they are encoded via Polar coding according to Clause 5.3.1,by setting n=10,I IL =1,n PC =0,and After encoding the bits are denoted by d0,d1,d2,d3,...,d N-1 ,where N is the number of coded bits. In order to further improve the coding of the channel under SCL, PC bits can be added during the pre-transform coding process, that is, n pc >0. The following is a detailed description of the precoding scheme proposed in this application. Pre-transform coding includes CRC coding and PC coding. In one possible implementation, PC bits may be added before CRC encoding. In another possible implementation, PC bits can be added after CRC encoding. It should be understood that CRC encoding is independent of the PC bits, so the relative positions of the CRC module and the PC module do not affect the final encoding result. Figure 6 shows a schematic diagram of a coding process. As shown in Figure 6 (a), PC coding is performed after CRC coding, and then channel coding is performed; as shown in Figure 6 (b), PC coding is performed before CRC coding, and then channel coding is performed. The specific encoding process methods shown in Figures 6(a) and 6(b) can refer to the encoding process shown in Figure 3 and will not be repeated here. Among them, PC encoding is performed based on the shift register. In a possible implementation, PC encoding is performed on the payload sequence according to the first shift register. FIG7 shows a schematic structural diagram of the first shift register. The first shift register includes a register with a length of L and at least two taps, the directions of the at least two taps are writing, and the positions of the taps are determined by the polynomial of the PC code; The polynomial of the PC code is: q(D)=1+q1D+q2D 2 +...+q m D m . Among them, q0, q1, ..., q m It is the coefficient of the polynomial, and the value of the polynomial coefficient is 0 or 1. When the polynomial coefficient is 0, it means that the tap corresponding to the register does not exist. Wherein, D represents a register, the register length L is equal to the highest power m of the polynomial, or in other words, the Lth register is the register corresponding to the highest power term of the precoding polynomial, and L is an integer greater than or equal to 1. In terms of timing, q0 corresponds to the tap at the current moment, q1 corresponds to the tap at one moment before the current moment, that is, the moment after one register; q2 corresponds to the tap at two moments before the current moment, that is, the moment after two registers; similarly, q m The corresponding value is the tap after m registers have passed. represents the exclusive-or operation on a binary field, For binary switches, the polynomial q(D) = 1 + q1D + q2D 2 +…+qm D m The coefficient q i When 0 is taken, is off (no tap at moment i), otherwise is open (there is a tap at the i-th moment). The length of the shift register is L, which is generally equal to the highest power of the pre-transform coding polynomial. For example, if the highest power of the pre-transform coding polynomial is 1, then L = 1, and there is only one register. For another example, if the pre-transform polynomial is 1 + D 2 +D 3 The coefficients of the pre-transform coding polynomial are q0=1, q1=0, q2=1, q3=1. The highest power of the pre-transform coding polynomial is 3. At this time, L=3, so there are three registers, among which D 2 Corresponding to the second register, D 3 Corresponding to the third register. D 1 Corresponding to the first register, but due to D 1 The coefficient q1 in the pre-coding polynomial is 0, so the tap corresponding to the first register does not exist. For another example, if the pre-transform coding polynomial is 1+D+D 3 , the highest power of the pre-transform coding polynomial is 3. At this time, L=3, so there are three registers, among which D corresponds to the first register, D 3 Corresponding to the third register. It should be understood that D 2 Corresponding to the second register, but due to D 2 The coefficient in the precoding polynomial is 0, so the tap corresponding to the second register does not exist. The taps corresponding to the shift register (eg, read tap and / or write tap) will be described in the following embodiments with respect to the structure of a specific shift register. The sequence of pre-transformed input (simplified as input sequence in the embodiment) is the message sequence to be encoded v0, v1, v2, ..., v K-1 , the output sequence is u0,u1,u2,…,u N-1 , N is the length of the polar code mother code, and the relationship between the input sequence and the output sequence is determined according to the shift register and the pre-transformation coding polynomial. The position output from the shift register by the pre-transformation may be independent of the set to which the current position belongs, or may be related to the set to which the current position belongs. When the pre-transform code is a non-systematic code, if the current position of the payload sequence corresponds to a message bit, the output bit of the first shift register is read from the first shift register, for example, from the tap at the end of the shift direction of the first shift register. In this application, the message bit may also be referred to as the information bit, and its specific name does not limit the embodiments of this application. For example, as shown in FIG7 , u i =z i . When the pre-transform code is a systematic code, the output of the first shift register is related to the set to which the current position of the payload sequence belongs. If the current position of the payload sequence belongs to the message bit set, the output of the first shift register is the input of the first shift register. For example, as shown in FIG7 , u i =v i . If the current position of the payload sequence belongs to the dynamic frozen bit set, the output bit of the first shift register is read from the first shift register, for example, from the tap at the end of the shift direction of the first shift register. For example, as shown in FIG7 , u i =z i . If the current position of the payload sequence belongs to the frozen bit set, the output of the first shift register is 0. In addition, in the embodiment of the present application, the shift direction of the first shift register can be left shift or right shift, without limitation. The following embodiments are all described using right shift as an example. Before starting encoding, the values ​​of the L shift registers need to be initialized, for example, the value of each shift register is initialized to 0. It can be understood that the punched and shortened positions directly output 0. In the present application, if the payload size corresponding to the input sequence (payload sequence+CRC sequence) of the pre-transform coding is different, the PC check relationship and the PC bit are different. Specifically, the tap q in FIG7 can be determined according to the PC polynomial o ~q m The specific method is to convert PC poly from decimal to binary sequence, q m On the far right, q0 is on the far left, take q o ~q m The value of determines the switch of the tap. For example, PC poly = 97, its corresponding binary sequence is [1000011], from the highest bit to the lowest bit, respectively, q6 = 1, q5 = 1, q4 = 0, q3 = 0, q2 = 0, q1 = 0, q0 = 1. Among them, q4 to q1 are all zero, indicating that there is no write tap at the time corresponding to q4 to q1. However, there is a write tap at the current time corresponding to q0 and the time corresponding to q6 to q5. Therefore, at the time corresponding to these coefficients equal to 1, the value written to the tap will be XORed with the value in the corresponding register and then written to the register. The following is an exemplary description of the PC check relationship and PC bits corresponding to different payload sizes. FIG8 shows a schematic structural diagram of a shift register. The shift register shown in FIG8 is described by taking a payload sequence of 32 bits and a CRC of 24 bits as an example, and the PBCH payload size is 56 bits. In this shift register, PC Poly=49, and its corresponding binary sequence is [100011]. From the highest bit to the lowest bit, q5=1, q4=1, q3=0, q2=0, q1=0, q0=1. Its corresponding polynomial is q(D)=1+D 4 +D 5 . FIG9 shows a schematic structural diagram of a shift register. The shift register shown in FIG9 is described by taking a payload sequence of 40 bits and a CRC of 24 bits as an example, and the PBCH payload size is 64 bits. In this shift register, PC Poly=21, and its corresponding binary sequence is

[10101] , from the highest bit to the lowest bit, they are q4=1,q3=0,q2=1,q1=0,q0=1. The corresponding polynomial is q(D)=1+D 2 +D 4 . FIG10 shows a schematic structural diagram of a shift register. The shift register shown in FIG10 is described by taking a payload sequence of 48 / 56 / 64 bits and a CRC of 24 bits as an example, and the PBCH payload size is 72 bits / 80 bits / 88 bits. In this shift register, PC Poly=35, and its corresponding binary sequence is

[10101] , from the highest bit to the lowest bit, they are q5=1, q4=0, q3=0, q2=0, q1=1, q0=1. The corresponding polynomial is q(D)=1+D 1 +D 5 . The above PC check relationship and PC bit design are merely exemplary and do not limit the application embodiments. FIG11 is a schematic diagram showing simulation results of the coding performance of PBCH based on the first shifter using PC coding and CRC coding. Figure 11 shows the performance results of a mother code length of 512 / CRC encoding (black dotted line), a mother code length of 1024 / CRC encoding (black solid line), and a mother code length of 1024 / PC encoding + CRC encoding (gray solid line). The PC check bit is generated based on the second shift register. Here, a 3-bit PC check is taken as an example. The horizontal and vertical coordinates in FIG11 can refer to the description of FIG5 and will not be repeated here. As can be seen from Figure 11, the PBCH coding performance using PC coding + CRC coding with a mother code length of 1024 (precoding before Polar coding includes CRC coding and PC coding) is significantly improved compared to the PBCH coding performance using CRC coding with a mother code length of 1024 (precoding before Polar coding includes CRC coding but does not include PC coding) and the PBCH coding performance using PC coding + CRC coding with a mother code length of 1024 (precoding before Polar coding includes CRC coding and PC coding). In addition, as the number of PBCH payloads increases (payload sizes are 32, 40, 48, 56, and 64), the coding gain of the PBCH coding method using PC coding + CRC coding becomes larger. In this application, when the payload sequence includes the information bit sequence of PBCH, the parameters used in the acquisition process of the message bit set I, the dynamic frozen bit set DF and the position of the frozen bit (such as shortened or punctured) are This parameter The value can be 0. The following provides exemplary descriptions of the message bit set I, the dynamic frozen bit set DF, and the positions of the frozen bits corresponding to different payload sizes. As an example, PBCH adopts CRC encoding + PC encoding. When the PBCH payload size is 56 bits (32 + CRC24), the position of the corresponding dynamic frozen bit set DF is shown in Table 1 below, the position of the message bit set I is shown in Table 2 below, the position of the frozen bit is shown in Table 3 below, and the position of the valid DF bit (valid PC bit) is shown in Table 4 below. Table 1 Table 2 Table 3 Table 4 In the above scheme, PBCH adopts mother code length N=2 n , where n=10, i.e., the mother code length is 1024 bits, and the 1024 bits correspond to bit indices 0 to 1023, wherein Table 1 shows the bit indices corresponding to the DF bits, Table 2 shows the bit indices corresponding to the message bits, Table 3 shows the bit indices corresponding to the puncturing bits, and Table 4 shows the bit indices corresponding to the effective DF bits. The above table is only an example for the convenience of listing bit indexes. Direct listing can also be used. For example, the corresponding bit index of DF is {161, 162, ..., 1009}. This embodiment of the present application does not limit this. For example, the encoding parameter n pc =808, Alternatively, the encoding parameter n pc =457, As another example, PBCH uses CRC encoding + PC encoding. When the PBCH payload size is 64 bits (40 + CRC24), the position of the corresponding dynamic frozen bit set DF is shown in Table 5 below, the position of the message bit set I is shown in Table 6 below, the position of the frozen bit is shown in Table 7 below, and the position of the valid DF bit (valid PC bit) is shown in Table 8 below. Table 5 Table 6 Table 7 Table 8 In the above scheme, PBCH adopts mother code length N=2 n , where n = 10. The meanings of Tables 5 to 8 can be referred to Tables 1 to 4 and will not be repeated here. For example, the encoding parameter n pc =800, Alternatively, the encoding parameter n pc =450, As another example, PBCH uses CRC encoding + PC encoding. When the PBCH payload size is 72 bits (48 + CRC24), the position of the corresponding dynamic frozen bit set DF is shown in Table 9 below, the position of the message bit set I is shown in Table 10 below, the position of the frozen bit is shown in Table 11 below, and the position of the valid DF bit (valid PC bit) is shown in Table 12 below. Table 9 Table 10 Table 11 Table 12 In the above scheme, PBCH adopts mother code length N=2 n , where n = 10. The meanings of Tables 9 to 12 can be referred to Tables 1 to 4 and will not be repeated here. For example, the encoding parameter n pc =792, Alternatively, the encoding parameter n pc =443, As another example, PBCH uses CRC encoding + PC encoding. When the PBCH payload size is 80 bits (56 + CRC24), the position of the corresponding dynamic frozen bit set DF is shown in Table 13 below, the position of the message bit set I is shown in Table 14 below, the position of the frozen bit is shown in Table 15 below, and the position of the valid DF bit (valid PC bit) is shown in Table 16 below. Table 13 Table 14 Table 15 Table 16 In the above scheme, PBCH adopts mother code length N=2 n , where n = 10. The meanings of Tables 13 to 16 can be referred to Tables 1 to 4 and will not be repeated here. For example, the encoding parameter n pc =784, Alternatively, the encoding parameter n pc =437, As another example, PBCH uses CRC encoding + PC encoding. When the PBCH payload size is 88 bits (64 + CRC24), the position of the corresponding dynamic frozen bit set DF is shown in Table 17 below, the position of the message bit set I is shown in Table 18 below, the position of the frozen bit is shown in Table 19 below, and the position of the valid DF bit (valid PC bit) is shown in Table 20 below. Table 17 Table 18 Table 19 Table 20 In the above scheme, PBCH adopts mother code length N=2 n , where n = 10. The meanings of Tables 17 to 20 can be referred to Tables 1 to 4 and will not be repeated here. For example, the encoding parameter n pc =776, Alternatively, the encoding parameter n pc =429, It should be noted that in the above examples, n pc >0,n pc The number increased, but Still 0. This means sacrificing some message bits with smaller row weight and highest reliability as PC positions, which will affect the decoding performance under SC. This means that there is no need to sacrifice message bits as PC positions, thereby ensuring decoding reliability. It should be understood that the positions of the DF bit or message bit shown in the above table are only for illustrative purposes and do not limit the application embodiments. In another possible implementation, PC encoding is performed on the payload sequence according to the second shift register. The second shift register reuses the existing NR modulo 5 shift register, and reuses the existing shift register to generate PC check bits, which is conducive to a more unified method of generating PC check under different code types. FIG12 shows a schematic structural diagram of a second shift register. The second shift register includes a register with a length L of 5. Among them, y0 represents the value in the first register, y1 represents the value in the second register. And so on, y L-1 Indicates the value in the Lth register. As shown in Figure 12, if the current position of the payload sequence corresponds to a message bit, the current bit and the value of the leftmost shift register of the second shift register are XORed and stored in the leftmost shift register, and the currently input message bit is used as the bit at the current position, and then the second shift register performs a circular shift; if the current position of the payload sequence is a check bit, the value of the leftmost shift register is taken out as the check bit, and then the second shift register performs a circular shift; if the current position of the payload sequence is a frozen bit, zero is directly output as the bit at the current position, and then the second shift register performs a circular shift. The pseudo code and comments for pre-transformation polar coding based on shift registers in the NR standard are as follows: After the pre-transformed codeword u, polar coding is performed to obtain the output d = [d0d1d2...d N-1 ],d=uG N . As mentioned above, the PC-polar code in the NR standard generates pre-transformed coded codewords based on a single-tap feedback shift register. The shift register is a feedback shift register; the tap direction is write; the number of taps is single; the shift register shifts left; the feedback tap and the output tap are both at the end (leftmost) of the shift direction; and the shift register can only be used to input bits when the bit is in the message position; when the current position is the check position, the shift register is used to output bits. The shift register's shift timing logic is: read at time t and write at time t+1. As an example, PBCH adopts CRC coding + PC coding. When the PBCH payload size is {32, 40, 48, 56, 64} bits (32+CRC24 / 40+CRC24 / 48+CRC24 / 56+CRC24 / 64+CRC24), in the shift register, PC Poly=16, and its corresponding binary sequence is

[0001] , from the highest bit to the lowest bit are q5 = 1, q4 = 0, q3 = 0, q2 = 0, q1 = 0, q0 = 0. The corresponding polynomial is expressed as q(D) = D 5 If the most significant bit (MSB) is on the left, then PC Poly = 16, and the corresponding binary sequence is

[10000] . FIG13 is a schematic diagram showing simulation results of the coding performance of PBCH based on the second shifter using PC coding and CRC coding. Figure 13 shows the performance results of a mother code length of 512 / CRC encoding (black dashed line), a mother code length of 512 / CRC encoding + PC encoding (gray dashed line), and a mother code length of 1024 / PC encoding + CRC encoding (gray solid line). The PC check bit is generated based on the second shift register. Here, a 3-bit PC check is taken as an example. As can be seen from Figure 13, for PBCH coding with a mother code length of 512, the coding performance of using CRC coding + PC coding (precoding before Polar coding includes CRC coding and PC coding) is better than that of using CRC coding (precoding before Polar coding includes CRC coding but does not include PC coding). In addition, as the PBCH payload length increases, the coding gain is greater. It can also be seen from Figure 13 that for PBCH coding with a mother code length of 1024, the coding performance of CRC coding + PC coding (precoding before Polar coding includes CRC coding and PC coding) is that as the PBCH payload length increases, the coding gain becomes smaller. In summary, if the NR PC equation and NR shift register are reused, when the payload length remains unchanged, such as 32+CRC24 bits, a longer mother code length will bring greater benefits; when the payload length increases, such as when the PBCH payload size exceeds 56 bits, a mother code length of N=512 is still used to maximize the coding gain. The present application also provides a communication method based on PC code, which can be executed by a second communication device, a component in the second communication device (for example, a chip, a chip system or a circuit, etc.), or a logic module or software that can realize all or part of the functions of the second communication device. As an example, the second communication device can be a decoding device. For the decoding device, the decoding device can obtain a received sequence, which is a channel sequence sent to the decoding device by the encoding device based on the codeword sequence obtained by encoding; the decoding device performs channel decoding on the received sequence to obtain a first bit sequence; the first bit sequence is pre-transformed and decoded, and the pre-transformed decoding includes CRC decoding and parity check PC decoding to obtain a decoded sequence; wherein the pre-transformed decoding is to decode the encoded payload sequence, and the payload sequence includes an information bit sequence carried by the control information or an information bit sequence transmitted by any one of the broadcast channel, the uplink data channel, and the downlink data channel. The specific solution on the decoding device side can be referred to the encoding device side and will not be repeated here. Based on the above scheme, an embodiment of the present application provides a communication method based on PC code. For the information bit sequence transmitted in the broadcast channel, uplink data channel, downlink data channel, or the information bit sequence carried in the control information, PC coding and CRC coding are used to implement precoding, and then channel coding is performed. This method can improve the error correction performance when the payload amount increases, and can also obtain further improvement in coding gain when the mother code length increases. The above describes the encoding method provided by the present application in detail. The following introduces the communication device provided by the present application. As shown in FIG14 , the present application provides a communication device 1400 . The communication device 1400 can be a coding device, or a device applied to the coding device and capable of realizing the corresponding functions of the coding device in the embodiment of the method of this application, such as a chip, a chip system or a circuit. Optionally, communication device 1400 includes a processing module 1401, which can be a processor, a processing board, a processing unit, or a processing device. Processing module 1401 is configured to perform pre-transform coding on the payload sequence to obtain an output sequence. Optionally, processing module 1001 is further configured to perform channeling on the output sequence of the pre-transform coding to obtain a codeword sequence. The specific process can be found in the detailed description of the method embodiment and is not further described here. Optionally, the communication device 1400 further includes a communication module 1402, which may also be referred to as a transceiver module, transceiver, transceiver, or transceiver device, etc., configured to perform receiving (or inputting) and / or transmitting (or outputting) operations. For example, the communication module 1402 may be configured to obtain a pre-transformed coded payload sequence, output a pre-transformed coded output sequence, or output a concatenated coded codeword sequence. In some embodiments, the aforementioned communication module and / or processing module may be implemented by a virtual module, for example, the processing module may be implemented by a software functional unit or a virtual device, and the communication module may be implemented by a software function or a virtual device. Alternatively, the processing module or the communication module may also be implemented by a physical device, for example, if the device is implemented using a chip / circuit (such as an integrated circuit, a dedicated circuit, a logic circuit, etc.). The communication module may be an input / output circuit and / or a communication interface that performs input operations (corresponding to the aforementioned receiving operations) and output operations (corresponding to the aforementioned sending operations); the processing module is an integrated processor or microprocessor or circuit (such as an integrated circuit, a logic circuit, etc.). The division of modules in this application is illustrative and represents only a logical functional division. In actual implementation, other division methods may be used. Furthermore, the functional modules in the examples of this application may be integrated into a single processor, exist physically as separate modules, or two or more modules may be integrated into a single module. The aforementioned integrated modules may be implemented in either hardware or software functional modules. As shown in Figure 15 , the present application further provides a communication device 1500. The communication device 1500 includes at least one processor 1510, which implements the functions of the encoding device described in the aforementioned method embodiment. Optionally, the processor 1510 is coupled to a memory, which may be located within the communication device, integrated with the processor, or external to the communication device. The communication device 1500 may also include at least one memory 1520. Memory 1520 stores computer programs, instructions, or data necessary to implement any of the aforementioned method embodiments. Processor 1510 may execute the computer programs, instructions, or data stored in memory 1520 to perform the communication method of any of the aforementioned embodiments. Optionally, the communication device 1500 may further include a communication interface 1530, and the communication device 1500 may exchange information with other devices via the communication interface 1530. Exemplarily, the communication interface 1530 may be a transceiver, circuit, bus, module, pin, or other type of interface. Coupling in this application refers to an indirect coupling or communication connection between devices, units, or modules, which can be electrical, mechanical, or other forms, and is used for information exchange between devices, units, or modules. Processor 1510 may operate in conjunction with memory 1520 and communication interface 1530. This application does not limit the specific connection medium between the processor 1510, memory 1520, and communication interface 1530. As shown in Figure 16, the present application also provides a chip (or chip system). Chip (or chip system) 1600 may include a circuit 1610 and an input / input interface 1620. Circuit 1610 may be a logic circuit, an integrated circuit, etc., and input / output interface 1620 may also be an input / output circuit, or an interface circuit, which can input information (or receive information) and output information (or send information). Optionally, the chip system can be composed of chips, or it can include chips and other discrete devices. Chip 1600 can be used to execute the method performed by the encoding device in each embodiment of the present application. In addition, the present application also provides a computer-readable storage medium, which stores computer instructions. When the computer instructions are run on a computer, the operations and / or processing performed by the encoding device in each method embodiment of the present application are executed. The present application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processing performed by the encoding device in the various method embodiments of the present application are executed. In addition, the present application also provides a chip, which includes a processor. A memory for storing a computer program is provided independently of the chip, and the processor is used to execute the computer program stored in the memory so that the operations and / or processing performed by the encoding device in any one of the method embodiments are executed. Furthermore, the chip may also include a communication interface. The communication interface may be an input / output interface, or an interface circuit, etc. Furthermore, the chip may also include a memory that stores the code and / or instructions required for the chip to execute the encoding method of the present application. The present application provides a communication system, including an encoding device according to an embodiment of the present application, which is used to implement steps 410 to 430 of the above method embodiment. In some embodiments, the encoding device is a communication device with corresponding encoding functions as shown in Figure 14 or Figure 15, or a chip for implementing the encoding method according to an embodiment of the present application as shown in Figure 16. In each embodiment of the present application, "plurality" includes two or more. Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application. Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs. In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

Claims

1. A communication method based on PC code, characterized in that: include: Acquire a payload sequence, where the payload sequence includes an information bit sequence carried by control information or an information bit sequence transmitted by any one of a broadcast channel, an uplink data channel, and a downlink data channel; Performing pre-transform coding on the payload sequence, wherein the pre-transform coding includes cyclic redundancy check (CRC) coding and parity check (PC) coding, to obtain an output sequence; Channel coding is performed on the output sequence to obtain a codeword sequence.

2. A communication method based on PC code, characterized in that: include: Get the received sequence; performing channel decoding on the received sequence to obtain a first bit sequence; Performing pre-transform decoding on the first bit sequence, the pre-transform decoding including CRC decoding and parity check PC decoding, to obtain a decoded sequence; The pre-transform decoding is to decode the encoded payload sequence, and the payload sequence includes an information bit sequence carried by the control information or an information bit sequence transmitted by any one of a broadcast channel, an uplink data channel, and a downlink data channel.

3. The method according to claim 1, characterized in that The channel coding includes polarization coding, and a mother code length N used by the polarization coding is greater than or equal to 1024.

4. The method according to claim 1, wherein The payload length K of the payload sequence includes one of 32, 40, 48, 56, and 64.

5. The method according to claim 4, characterized in that The payload sequence includes an information bit sequence in a broadcast channel.

6. The method according to any one of claims 1 or 3-5, characterized in that The rate matching mode adopted by the polar coding is puncturing.

7. The method according to any one of claims 1 or 3 to 6, characterized in that The pre-transform encoding of the payload sequence includes: The payload sequence is PC-encoded according to the first shift register.

8. The method according to claim 7, characterized in that The pre-transformation code is a non-systematic code, and if the current position of the payload sequence corresponds to a message bit, the output bit of the first shift register is read from the first shift register.

9. The method according to claim 7, characterized in that The pre-transformation code is a systematic code, the output of the first shift register is related to the set to which the current position of the payload sequence belongs, and the method includes: If the current position of the payload sequence belongs to the message bit set, the output of the first shift register becomes the input of the first shift register; If the current position of the payload sequence belongs to the dynamic frozen bit set, the output bit of the first shift register is read from the first shift register; If the current position of the payload sequence belongs to the frozen bit set, the output of the first shift register is 0.

10. The method according to any one of claims 1 or 3-6, characterized in that The pre-transform encoding of the payload sequence includes: performing PC encoding on the payload sequence according to a second shift register; The length of the second shift register is 5; If the current position of the payload sequence corresponds to a message bit, performing an exclusive OR operation on the current bit and the value of the leftmost shift register of the second shift register, and storing the result in the leftmost shift register, and using the currently input message bit as the bit at the current position, and then performing a cyclic shift on the second shift register; If the current position of the payload sequence is a check bit, taking out the value of the leftmost shift register as the check bit, and then performing a cyclic shift on the second shift register; If the current position of the payload sequence is a frozen bit, zero is directly output as the bit at the current position, and then the second shift register performs a cyclic shift.

11. The method according to any one of claim 10, wherein the payload sequence comprises an information bit sequence of a broadcast channel, The n pc >0, 12. A communication device, characterized in that: include: A communication module, configured to obtain a payload sequence, wherein the payload sequence includes an information bit sequence carried by control information or an information bit sequence transmitted by any one of a broadcast channel, an uplink data channel, and a downlink data channel; Processing module for: Performing pre-transform coding on the payload sequence, wherein the pre-transform coding includes CRC coding and parity check PC coding, to obtain an output sequence; Channel coding is performed on the output sequence to obtain a codeword sequence.

13. A communication device, characterized in that: include: A communication module, used for acquiring a receiving sequence; Processing module for: performing channel decoding on the received sequence to obtain a first bit sequence; Performing pre-transform decoding on the first bit sequence, the pre-transform decoding including CRC decoding and parity check PC decoding, to obtain a decoded sequence; The pre-transform decoding is to decode the encoded payload sequence, and the payload sequence includes an information bit sequence transmitted by any one of a broadcast channel, an uplink data channel, and a downlink data channel, or an information bit sequence carried in control information.

14. The communication device according to claim 12 or 13, characterized in that: The channel coding includes polarization coding, and a mother code length N used by the polarization coding is greater than or equal to 1024.

15. The communication device according to one of claims 12 to 14, characterized in that The payload length K of the payload sequence includes one of 32, 40, 48, 56, and 64.

16. The communication device according to claim 15, characterized in that The payload sequence includes an information bit sequence in a broadcast channel.

17. The communication device according to any one of claims 12 or 14-16, characterized in that: The rate matching mode adopted by the polar coding is puncturing.

18. The communication device according to any one of claims 12 or 14-17, characterized in that: The processing module is used to perform PC encoding on the payload sequence according to the first shift register.

19. The communication device according to claim 18, wherein: The pre-transformation code is a non-systematic code, and if the current position of the payload sequence corresponds to a message bit, the output bit of the shift register is read from the shift register.

20. The communication device according to claim 18, wherein The pre-transformation code is a systematic code, and the output of the shift register is related to the set to which the current position of the payload sequence belongs. If the current position of the payload sequence belongs to the message bit set, the output of the shift register is the input of the shift register; if the current position of the payload sequence belongs to the dynamic frozen bit set, the output bit of the shift register is read from the shift register; if the current position of the payload sequence belongs to the frozen bit set, the output of the shift register is 0.

21. The communication device according to any one of claims 12 or 14-17, characterized in that: The processing module is used for: performing PC encoding on the payload sequence according to a second shift register; The length of the second shift register is 5; If the current position of the payload sequence corresponds to a message bit, performing an exclusive OR operation on the current bit and the value of the leftmost shift register of the second shift register, and storing the result in the leftmost shift register, and using the currently input message bit as the bit at the current position, and then performing a cyclic shift on the second shift register; If the current position of the payload sequence is a check bit, taking out the value of the leftmost shift register as the check bit, and then performing a cyclic shift on the second shift register; If the current position of the payload sequence is a frozen bit, zero is directly output as the bit at the current position, and then the second shift register performs a cyclic shift.

22. The communication device according to any one of claims 12 to 21, wherein the payload sequence comprises an information bit sequence of a broadcast channel, The n pc >0, 23. A communication device, characterized in that: Including communication interfaces and circuits, The communication interface is used to receive a payload sequence and input the payload sequence into the circuit; the communication interface is also used to output a code word sequence, and the code word sequence is output by the circuit; The circuit is configured to implement the method according to any one of claims 1 to 11.

24. A communication device, characterized in that: include: A processor is coupled to a memory, and is configured to execute a computer program or instruction stored in the memory, so that the method according to any one of claims 1 to 11 is implemented.

25. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions. When the computer instructions are executed on a computer, the method according to any one of claims 1 to 11 is implemented.

26. A computer program product, characterized in that The computer program product comprises computer program codes or instructions. When the computer program codes or instructions are run on a computer, the method according to any one of claims 1 to 11 is implemented.

27. A communication system, characterized in that: The invention comprises a communication device for executing the method according to any one of claims 1, 3-11, and a communication device for executing the method according to any one of claims 2-11.

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