Address translation method, fast mapping table construction method, device, storage medium and program product

Abstract

Provided in the embodiments of the present disclosure are an address translation method, a fast mapping table construction method, a device, a storage medium and a program product. In an embodiment of the present disclosure, the address translation method comprises: constructing a first RMAP table adapted to an EPT, the first RMAP table storing address information of the last-level page table entry respectively corresponding to at least one GPA in the EPT; establishing a fast mapping relationship from GPAs to HPAs on the basis of first RMAP table so as to implement fast address translation from the GPAs to the HPAs; and further, creating a second RMAP table for the EPT, the second RMAP table storing address translation information from at least one HPA to a corresponding GPA to establish a fast mapping relationship from the HPAs to the GPAs so as to implement fast address translation from the HPAs to the GPAs. Bidirectional fast mapping can be implemented on the basis of the first RMAP table and the second RMAP table, so as to improve address translation efficiency.

Description

[0001] This disclosure claims priority to Chinese patent application No. 202410330180.3, filed with the China Patent Office on March 20, 2024, entitled "Method, Device, Storage Medium, and Program Product for Address Translation and Fast Mapping Table Construction," the entire contents of which are incorporated herein by reference. Technical Field This disclosure relates to the field of virtualization technology, and more particularly to a method, device, storage medium, and program product for address translation and fast mapping table construction. Background: Virtualization is a core technology of cloud computing. It achieves the purpose of partitioning and centrally managing physical resources by creating one or more virtualized instances (or clients) on the physical resources of a host machine. A host machine has a host operating system (Host OS) and physical memory (actual physical memory) seen by the host machine. The address of this physical memory is the host physical address (HPA). A client has a guest operating system (Guest OS) and physical memory visible to the client. The address of this physical memory is called the Guest Physical Address (GPA). In a virtualized environment, memory management is performed using Extended Page Tables (EPTs). By providing each client with an independent multi-level page table structure, EPTs are responsible for translating the client's GPA into the host's HPA, while also achieving isolation between different clients. The EPT can translate the client's GPA into the host's HPA, and hardware-supported address translation mechanisms can guide accesses to the correct physical memory location. However, this translation process often requires querying multiple levels of page tables, resulting in low efficiency. SUMMARY OF THE INVENTION Various aspects of the present disclosure provide an address translation and fast mapping table construction method, device, storage medium, and program product to improve address translation efficiency and achieve fast address translation.An embodiment of the present disclosure provides an address translation method, comprising: pre-constructing a first quick mapping table corresponding to a memory page table, the memory page table including a multi-level page table corresponding to at least one client physical address; storing in the first quick mapping table address information of a last-level page table entry corresponding to at least one client physical address; in response to a first address translation triggering event, determining a first client physical address requiring address translation, querying the first quick mapping table for address information of a last-level page table entry corresponding to the first client physical address; and if address information of the last-level page table entry corresponding to the first client physical address is found, generating a host physical address corresponding to the first client physical address based on the address information of the last-level page table entry corresponding to the first client physical address and an address offset of the first client physical address. Embodiments of the present disclosure also provide a method for constructing a fast mapping table, comprising: dividing an address space of a client physical address corresponding to a memory page table into at least one address space; creating a basic structure for each of the at least one address space, wherein the basic structure corresponds to a set page table level; the memory page table includes a multi-level page table corresponding to at least one client physical address; determining, for any client physical address in the memory page table, a first structure corresponding to the client physical address from the basic structures based on address information of the client physical address and the address space corresponding to each basic structure; and recording address information of a last-level page table entry corresponding to the client physical address in the first structure based on a relationship between the last-level page table level corresponding to the client physical address and the set page table level, thereby constructing a first fast mapping table corresponding to the memory page table. The first fast mapping table stores address information of the last-level page table entry corresponding to at least one client physical address. Embodiments of the present disclosure also provide a physical machine, comprising: a memory and a processor; the memory storing a computer program; and the processor coupled to the memory and configured to execute the computer program to implement the steps of the address translation and fast mapping table construction methods provided in the embodiments of the present disclosure. Embodiments of the present disclosure further provide a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the processor implements the steps of the address translation and fast mapping table construction method provided in the embodiments of the present disclosure. Embodiments of the present disclosure further provide a computer program product, including a computer program / instructions. When the computer program / instructions is executed by a processor, the processor implements the steps of the address translation and fast mapping table construction method provided in the embodiments of the present disclosure.In the disclosed embodiment, an adaptive first fast mapping table is constructed for the memory page table. The first fast mapping table stores the address information of the last-level page table entry corresponding to at least one client physical address in the memory page table. Thus, when performing address translation for a client physical address, the first fast mapping table corresponding to the memory page table can be queried first. If the address information of the last-level page table entry corresponding to the client physical address is found in the first fast mapping table, the host physical address corresponding to the client physical address can be directly generated based on the address information of the last-level page table entry corresponding to the client physical address and the address offset of the client physical address. This eliminates the need to query each level of the multi-level page tables corresponding to the client physical address contained in the memory page table. This improves address translation efficiency and achieves fast address translation. In some optional embodiments of the present disclosure, a second fast mapping table adapted for the memory page table is constructed. Address translation information from at least one host physical address to a corresponding guest physical address is stored in the second fast mapping table to support address translation from the host physical address to the corresponding guest physical address. This addresses the limitation of memory page tables, which only support address translation from guest physical addresses to host physical addresses, and meets the requirements for address translation from host physical addresses to guest physical addresses in various virtualization environments. BRIEF DESCRIPTION OF THE DRAWINGS The drawings described herein are provided to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The illustrative embodiments of the present disclosure and their description are provided to explain the present disclosure and are not intended to unduly limit the present disclosure.In the accompanying drawings: Figure 1a is a flow chart of an address conversion method provided by an exemplary embodiment of the present disclosure; Figure 1b is a flow chart of a fast mapping table construction method provided by an exemplary embodiment of the present disclosure; Figure 2a is a structural diagram of a physical machine provided by an exemplary embodiment of the present disclosure; Figure 2b is a structural diagram of another physical machine provided by an exemplary embodiment of the present disclosure; Figure 2c is a system structural diagram of the physical machine shown in Figure 1b provided by an exemplary embodiment of the present disclosure working in root mode; Figure 2d is a system structural diagram of the physical machine shown in Figure 1b provided by an exemplary embodiment of the present disclosure working in non-root mode; Figure 3a is a flow chart of switching a host operating system from root mode to non-root mode provided by an exemplary embodiment of the present disclosure; Figure 3b is a flow chart of creating a memory page table provided by an exemplary embodiment of the present disclosure; Figure 3c is a flow chart of creating an information bearing object provided by an exemplary embodiment of the present disclosure; Figure 3d is a flow chart of mode switching provided by an exemplary embodiment of the present disclosure; Figure 4 is a structural diagram of an address conversion device provided by an exemplary embodiment of the present disclosure; Figure 5 is a structural diagram of a fast mapping table construction device provided by an exemplary embodiment of the present disclosure; Figure 6 is a structural diagram of a physical machine provided by an exemplary embodiment of the present disclosure. To further clarify the objectives, technical solutions, and advantages of this disclosure, the following will provide a clear and complete description of the technical solutions of this disclosure in conjunction with specific embodiments and corresponding figures. Obviously, the described embodiments represent only a portion of the embodiments of this disclosure, and are not exhaustive. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of this disclosure without inventive effort are within the scope of protection of this disclosure. It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, storage, and display) involved in this disclosure are all authorized by the user or fully authorized by all parties. The collection, use, and processing of relevant data must comply with relevant laws, regulations, and standards in the relevant region, and corresponding operation portals are provided for users to choose to authorize or deny. In a virtualized environment, address translation between GPA and HPA is performed using a memory page table. Optionally, the memory page table can be implemented as an EPT. The following embodiments of this disclosure use the EPT as an example for description, but are not limited to this. The EPT stores at least one multi-level page table corresponding to each GPA, but has the problem of low address conversion efficiency.To address this technical issue, in embodiments of the present disclosure, a first Rapid-Mapping (RMAP) table is constructed for the EPT. The first RMAP table stores address information for the last-level page table entry corresponding to at least one GPA. This table is used to establish a rapid mapping relationship between the GPA and the HPA, improving address translation efficiency and enabling fast address translation. Furthermore, the EPT only supports address translation from GPA to HPA and does not support reverse address translation from HPA to GPA. In embodiments of the present disclosure, a second RMAP table is created for the EPT. The second RMAP table stores address translation information from at least one HPA to a corresponding GPA. This table is used to establish a rapid mapping relationship between the HPA and GPA, improving address translation efficiency and enabling fast address translation. Furthermore, embodiments of the present disclosure also provide detailed descriptions of the construction and management processes of the first and second RMAP tables, as well as their synchronization with the EPT status update process. For details, please refer to the detailed descriptions in subsequent embodiments. The technical solutions provided in the embodiments of the present disclosure are applied to a virtualized environment. A virtualized environment refers to an operating environment generated by virtualizing physical resources on a host machine using virtualization technology and creating one or more virtualized instances on the processed virtualized resources. In the embodiments of the present disclosure, the virtualized instances hosted on virtualized resources are referred to as clients, as opposed to hosts. The client has its own operating system (OS) and global page access (GPA), while the host has its own OS and HPA. The embodiments of the present disclosure do not limit the implementation of the virtualized environment. In an optional embodiment, Implementation A of the virtualized environment involves adding a virtualization manager (hypvisor) to the host OS. The hypervisor virtualizes the hardware resources on the host machine and creates one or more virtual machines on the processed virtualized resources. In this virtualized environment, address translation between the client's GPA and the host's HPA is performed using a multi-level page table corresponding to at least one GPA in the EPT.In another optional embodiment, implementation method B of the virtualized environment involves adding a virtualization layer between the host machine's hardware resources and the host operating system. The virtualization layer implements at least a virtual resource provision function. The virtualization layer switches the running host operating system from root mode to non-root mode, provides at least one virtual resource in non-root mode, and runs at least one application on the virtual resource that the host operating system cannot run in root mode due to insufficient resources. Without reinstalling the operating system, the virtual resource provision function can be flexibly implemented for the running host operating system, resolving issues such as application failures due to insufficient resources due to inactive or missing system functions. This supports the operation of more applications and facilitates expanding the capabilities of the host operating system. Root mode is an operating mode in which the host operating system has direct access to hardware resources, while non-root mode is an operating mode in which the virtualization layer virtualizes hardware resources and schedules and accesses the virtualized resources on behalf of the host operating system. In non-root mode, the virtualization layer's access to hardware resources is restricted. Accordingly, the host operating system in non-root mode can also be referred to as a guest operating system. The virtualization layer maintains an EPT, a memory page table used to store the mapping relationship between guest physical addresses in non-root mode and host physical addresses in root mode. Based on the EPT's multi-level page tables, the virtualization layer can convert the GPA into the HPA. In the disclosed embodiments, whether in a virtualization environment implemented using Method A or Method B, a first RMAP table can be created for the EPT to quickly map the GPA to the HPA. Furthermore, a second RMAP table can be created to reversely map the HPA to the GPA, addressing the EPT's inability to achieve reverse mapping from the HPA to the GPA and ensuring reverse mapping from the HPA to the GPA. In mode A, the processes of creating the first RMAP table, performing address translation based on the first RMAP table, and creating the second RMAP table and performing address translation based on the second RMAP table can be completed by the host OS, specifically by the virtualization manager in the host OS. In mode B, the processes of creating the first RMAP table, performing address translation based on the first RMAP table, and creating the second RMAP table and performing address translation based on the second RMAP table can be completed by the virtualization layer in non-root mode.Whether the host OS in Method A or the virtualization layer in Method B, the processes of creating a first RMAP table, performing address translation based on the first RMAP table, and creating a second RMAP table, performing address translation based on the second RMAP table are identical or similar. A solution provided by an embodiment of the present disclosure is described in detail below with reference to the accompanying drawings. FIG1a is a flow diagram of an address translation method provided by an exemplary embodiment of the present disclosure. As shown in FIG1a, the method includes:

[0002] R11. Pre-construct a first RMAP table corresponding to the EPT, where the EPT includes a multi-level page table corresponding to at least one GPA; the first RMAP table stores address information of a last-level page table entry corresponding to at least one GPA;

[0003] R12. In response to the first address translation triggering event, determine a first GPA that requires address translation, and query the first RMAP table for address information of a last-level page table entry corresponding to the first GPA.

[0004] R13. If the address information of the last-level page table entry corresponding to the first GPA is found, generate the HPA corresponding to the first GPA according to the address information of the last-level page table entry corresponding to the first GPA and the address offset of the first GPA. OIn this embodiment, the EPT employs a multi-level page table structure and a hybrid mapping granularity, supporting both small and large page granularity. This supports different physical page mapping requirements and improves memory mapping flexibility. Specifically, the EPT includes a multi-level page table corresponding to at least one GPA. The multi-level page table can be a two-level memory page table, a four-level memory page table, or a five-level memory page table. For example, if the EPT includes a four-level memory page table, the EPT includes a Page Global Directory (PGD), a Page Upper Directory (PUD), a Page Middle Directory (PMD), and a Page Table Entry (PTE). The page table entry pgd_t in the PGD records the address information of the next-level page table (e.g., PUD). The page table entry pud_t in the PUD records the address information of the next-level page table (e.g., PMD). The page table entry pmd_t in the PMD records the address information of the next-level page table (e.g., PTE). The page table entry pte_t in the PTE records the starting address of the physical page corresponding to the HPA. Of course, if the PGD, PUD, and PMD are the last-level page tables, then the page table entries corresponding to the PGD, PUD, and PMD, respectively, record the starting address of the physical page corresponding to the HPA. It should be noted that the GPA address can be divided into several parts, each of which serves as an index, resulting in multiple index values ​​and an address offset. The address offset is the offset relative to the corresponding physical page. Taking the EPT as an example, which includes four levels of memory page tables, the GPA can be divided into five parts: PGD-level index values, PUD-level index values, PMD-level index values, PTE-level index values, and address offsets. Typically, the HP Ao corresponding to the GPA can be obtained by querying the EPT based on each index value and address offset in the GPA address. On the other hand, the EPT is created with different page granularities for different address spaces (GPAs).For example, some address spaces create multi-level page tables for the EPT using small page granularity. If the small page granularity is 4KB (corresponding to the PTE page granularity), the address space corresponds to four levels of page tables, namely, PGD, PUD, PMD, and PTE, with the last-level page table being PTE. Other address spaces can create the EPT using large page granularity. If the large page granularity is 2MB (corresponding to the PMD page granularity), the address space corresponds to three levels of page tables, namely, PGD, PUD, and PMD, with the last-level page table being PMD. Still other address spaces can create the EPT using large page granularity. If the large page granularity is 1GB (corresponding to the PUD page granularity), the address space corresponds to two levels of page tables, namely, PGD and PUD, with the last-level page table being PUDo. In other words, the EPT uses a hybrid mapping granularity, and the last-level page table corresponding to any GPA in the EPT can be PGD, PUD, PMD, or PTE. A detailed description of the EPT page table can be found in the subsequent embodiments and will not be repeated here. To facilitate fast recording of the mapping relationship between GPAs and HPAs, this embodiment provides a first RMAP table data structure. This data structure stores the address information of the last-level page table entries corresponding to at least one GPA, thereby bypassing the multi-level page table translation in the EPT and improving address translation efficiency. In this embodiment, since the last-level page table of each GPA in the EPT page table may be of mixed granularity, the address information of the last-level page table entries stored in the first RMAP table may be address information of at least one of the following page tables: PGD, PUD, PMD, and PTE. In this embodiment, there is no limit on the timing of pre-building the first RMAP table corresponding to the EPT. For example, the first RMAP table may be created after the EPT is created based on the correspondence between the GPA and the last-level page table of the EPT. For another example, the first RMAP table add function may be called when the last-level page table of the EPT is created to create the corresponding first RMAP table. In this way, the first RMAP table is created as the EPT is established. In this embodiment, address translation triggering events are maintained. For ease of distinction and description, the address translation triggering event that triggers GPA to HPA translation is referred to as a first address translation triggering event. The first address translation triggering event may be a memory mapping management event for the GPA, a memory hot / cold management event, a memory swap management event, or the like.Accordingly, when a first address translation trigger event occurs, the first GPA requiring address translation can be determined in response to the first address translation trigger event, and the address information of the last-level page table entry corresponding to the first GPA can be queried in the first RMAP table. If the address information of the last-level page table entry corresponding to the first GPA is found, the HPA corresponding to the first GPA is generated based on the address information of the last-level page table entry corresponding to the first GPA and the address offset of the first GPA. For example, by parsing the address information of the last-level page table entry corresponding to the first GPA, the starting address of the host physical address recorded in the last-level page table entry and the alignment value (HPA_align) of the host physical address can be obtained. The address offset of the first GPA refers to the offset relative to the starting address. Therefore, the HPA corresponding to the first GPA can be generated by adding the HPA_align to the address offset of the first GPA. In an optional embodiment, a basic structure can be created for the GPA address space corresponding to the EPT. Based on the basic structure, a first RMAP table corresponding to the EPT can be pre-constructed. Compared with performing address translation step by step through the EPT, Address translation based on the basic structure eliminates the need for multiple levels of page tables, resulting in high address translation efficiency. Specifically, considering that the EPT has multiple different page table levels, a set page table level can be selected as the basic page table level. The set page table level can be any page table level, such as the PUD page table level, the PMD page table level, the PTE page table level, or the PGD page table level. The GPA address space corresponding to the EPT is divided into at least one address space, and a basic structure corresponding to the basic page table level (i.e., the set page table level) is created for each of the at least one address spaces. The GPA address space corresponding to the EPT can be divided according to the page granularity corresponding to the set page table level. For example, if the set page table level is the PMD page table level and the PMD page table granularity is 2m, the GPA address space corresponding to the EPT can be divided into at least one address space at a 2m granularity, and a basic structure is created for each 2m address space. For another example, if the page table level is set to the PUD page table level and the PUD page table granularity is 1GB, the GPA address space corresponding to the EPT can be divided into at least one address space at a 1GB granularity, and a basic structure is created for each 1GB address space. For any GPA in the EPT, the first structure corresponding to the GPA is determined from the basic structures based on the address information of the GPA and the address space corresponding to each basic structure.The address space corresponding to each basic structure can be understood as an address range, the size of which corresponds to the page granularity corresponding to the set page table level. Any GPA is address information that can fall within the address space corresponding to a certain basic structure. For ease of distinction and description, the basic structure corresponding to the address space to which the address information of any GPA belongs is referred to as the first structure. Based on the relationship between the level of the last-level page table corresponding to any GPA and the set page table level, the first structure records the address information of the last-level page table entry corresponding to any GPA. The last-level page table level can be the same as the set page table level, or the last-level page table level can be the level above or below the set page table level. Furthermore, the address information of the last-level page table entry corresponding to any GPA can be recorded in the first structure, or in a second structure that is an extension of the first structure. For a detailed description of the second structure, please refer to the aforementioned embodiment. Optionally, based on the relationship between the level of the last-level page table corresponding to any GPA and the set page table level, the implementation method of recording the address information of the last-level page table entry corresponding to any GPA in the first structure is not limited. This optional embodiment provides a method in which, if the level of the last-level page table is the same as the set page table level, the address information of the last-level page table entry is recorded in the first structure; if the level of the last-level page table is different from the set page table level, a page table level different from the set page table level is represented by an extended mapping. For example, a second structure is extended from the first structure, the address information of the last-level page table entry is recorded in the second structure, and the address information of the second structure is recorded in the first structure. An exemplary description is provided below. Example C1: If the level of the last-level page table entry corresponding to any GPA is the same as the set page table level, the first structure is deemed unnecessary to be expanded. The first structure is directly used to record the address information of the last-level page table entry. The address information of the last-level page table entry corresponding to any GPA is added to the information field of the first structure, and the flag information in the first structure is set to a first value. The first value indicates that the information field of the first structure stores the address information of the last-level page table entry. The base structure can be a fast map header (rmap_head) structure, for example, struct rmap_head {unsigned long val}, where struct is a structure, unsigned long indicates that the data type is unsigned long, and val is the information field.Example C2: If the level of the last-level page table corresponding to any GPA differs from the set page table level, the first structure is considered to be expanded to generate a second structure adapted to the level of the last-level page table corresponding to any GPA. The address information of the last-level page table entry corresponding to any GPA is added to the information field of the second structure, and the address information of the second structure is added to the information field of the first structure. The flag information in the first structure is set to a second value, indicating that the information field of the first structure stores the address information of the second structure. It should be noted that the flag information in the first structure is primarily used to identify the type of address information stored in the information field of the first structure. If the flag information is the first value, it indicates that the information field of the first structure stores the address information of the last-level page table entry; if the flag information is the second value, it indicates that the information field of the first structure stores the address information of the second structure. The first value and the second value can have different values. For example, the first value and the second value can be represented by different bits in different information fields, with the bit value of 1 indicating which value is valid. For another example, the lower three bits of the information field can be used as flag information. The value range of the lower three bits is 0-7, and the first value and the second value can be any two different values ​​between 0-7. Furthermore, optionally, the implementation method for creating a second structure adapted to the level of the last-level page table corresponding to any GPA is not limited. The following exemplary embodiment illustrates this: the address information of the last-level page table entry is written into the second structure, and the address information of the second structure is written into the base structure. In this case, the base structures corresponding to all GPAs in the pud can share the same second structure, eliminating the need to create a second structure for each base structure. Example D1: When the level of the last-level page table corresponding to any GPA is one level above the set page table level, in an optional embodiment, multiple base structures can be created for the last-level page table. For each base structure, a second structure adapted to the level of the last-level page table is generated. The address information of the last-level page table entry is recorded in each second structure, and the address information of each second structure is written into the corresponding base structure. In another optional embodiment, since each second structure records the address information of the last-level page table entry, multiple base structures can share the same second structure, and the address information of the shared second structure is recorded in each base structure.For example, the page table level is set to the PMD level, i.e., the base structure corresponds to the PMD page table level. The level of the last page table level corresponding to any GPA is the level above the set page table level, i.e., the PUD level. A PUD huge page includes 512 PMD pages, each of which corresponds to a base structure. A PUD huge page corresponds to 512 base structures. Multiple base structures can share the same second structure. The second structure stores address information for the PUD page, and the information field in each base structure stores address information for the shared second structure. Based on the above, if the level of the last page table level corresponding to any GPA is the level above the set page table level, it can be determined whether the second structure already exists. If the second structure does not exist, a new structure matching the level of the last page table level corresponding to any GPA is created as the second structure. The address information of the second structure is added to the information field of the first structure corresponding to the GPA, and the flag information in the first structure is set to the second value. Optionally, if a second structure already exists, the address information of the existing second structure is added to the information field of the first structure corresponding to any GPA, and the flag information in the first structure is set to the second value. When the level of the last page table corresponding to any GPA is one level above the set page table level, the second structure can be represented as rmap_cmpt {unsigned long val; atomic_t num;}. "struct" is a structure, "unsigned long" indicates the data type is unsigned long, "val" is the information field, and "atomic_t num" indicates the number of GPA-HPA fast mappings. Example D2: When the level of the last page table corresponding to any GPA is one level below the preset page table level, a new structure adapted to the level of the last page table corresponding to any GPA is created as the second structure. For example, the preset page table level is the PMD page table level. The last page table level corresponding to any GPA is at the level below the preset page table level, namely, the PTE page table level. The page table at the preset page table level can be extended to generate multiple page tables at the next level. For example, a 2m page table at the PDM level can be mapped to a 512-PTE-level page table. Accordingly, the first structure corresponding to any GPA can be extended to generate multiple (e.g., 512) second structures. The multiple second structures are used to store address information of the next-level page table (PTE page table) mapped from the page table at the preset page table level (e.g., the PMD page table).Furthermore, a unified structure can be used to organize and manage multiple second structures. The unified structure can organize and manage multiple second structures in an array manner, with the address information stored in each second structure being considered an element in the array. The unified structure can be a subsequent rapid map extension (rmap_extd) structure, and the address information stored in the second structure is an element of the array contained in the rmap_extd structure. The unified structure is represented as rmap_extd{unsigned long val[VAL_EXTD_NR]; atomic_t num;}. o Among them, struct is a structure, unsigned long indicates that the data type is unsigned long, and atomic_t num indicates the number of GPA-HPA fast mappings oval[VAL_EXTD_NR] is an array, and the address information stored in the second structure is an element of the val[VAL_EXTD_NR] array. The offset of the next-level page table granularity (e.g., 4KB) within the page table of a preset page table level (e.g., 2M) can be determined, and a new structure corresponding to the offset can be created. This new structure can be used as the second structure corresponding to any GPA. For example, if any GPA is located at the third 4KB page in 2M, a new structure corresponding to offset 3 can be created and used as the second structure corresponding to any GPA. The address information of the last-level page table (e.g., PTE page table) corresponding to any GPA can also be added to the information field of the second structure, and the flag information in the second structure can be set to a second value. In an optional embodiment, if the first RMAP table already exists, operations such as query, add, delete, modify, expand, and shrink can be performed on any GPA. An exemplary explanation is provided below. Example E1: A query operation is performed on the first GPA as an example. The query operation for the HPA corresponding to the first GPA is not limited. For example, when reading or writing data to the first GPA, a query for the HPA corresponding to the first GPA can be triggered, thereby quickly obtaining the HPA corresponding to the first GPA based on the first RMAP table. When querying the HPA corresponding to the first GPA, the first RMAP table is queried for the address information of the last-level page table entry corresponding to the first GPA. If the address information of the last-level page table entry corresponding to the first GPA is found, the HPA corresponding to the first GPA is generated based on the address information of the last-level page table entry corresponding to the first GPA and the address offset of the first GPA. OOptionally, if the address information of the last-level page table entry corresponding to the first GPA is not found, it is assumed that the first GPA does not have an HPA, and a page fault exception may be triggered. In an optional embodiment, based on the address information of the first GPA and the address space corresponding to each basic structure included in the first RMAP table, a first structure corresponding to the first GPA is determined from each basic structure, where the first structure is a basic structure corresponding to the first GPA among the basic structures included in the first RMAP table; the address information of the last-level page table entry corresponding to the first GPA is obtained using the first structure corresponding to the first GPA; and the HPA corresponding to the first GPA is generated based on the address information of the last-level page table entry corresponding to the first GPA and the address offset of the first GPA. Optionally, obtaining the address information of the last-level page table entry corresponding to the first GPA using the first structure corresponding to the first GPA includes: obtaining flag information from the first structure; and the method for obtaining the address information of the last-level page table entry corresponding to the first GPA varies depending on the flag information. If the flag information is the first value, it means that the information field of the first structure records the address information of the last-level page table entry, and the address information of the last-level page table entry corresponding to the first GPA can be directly obtained from the information field in the first structure; if the flag information is the second value, it means that the information field of the first structure records the address information of the second structure, and the second structure stores the address information of the last-level page table entry. The address information of the second structure can be obtained from the information field in the first structure. According to the address information of the second structure, the address information of the last-level page table entry corresponding to the first GPA can be obtained from the information field of the second structure. Further optionally, the information field of the first structure stores address information of the unified structure and an offset (offset, oft) of the second structure in the unified structure array. The offset oft indicates the offset of the address of any GPA in the last level of page granularity in the page table of the set page table level. For example, if the page table level is set to the PMD level and the last level of page granularity is the PTE level, then the offset oft refers to the offset of the address of any GPA in the 4k granularity in the 2m of the PMD level. If the offset is oft3, it indicates that the any GPA is located in the third 4k address space in the 2m.Accordingly, obtaining the address information of the last-level page table entry corresponding to the first GPA from the information field of the second structure includes: selecting the oftth element in the unified structure (e.g., rmap_extd) array based on the offset oft; the value of this element is the address information of the last-level page table entry corresponding to the first GPA. Example E2: An addition operation is performed on the second GPA as an example for illustration. The addition of the second GPA is not limited to specific circumstances. For example, if the GPA is insufficient, the GPA can be added, triggering an addition operation on the GPA address. In this embodiment, one or more GPAs can be added, and the following description uses the addition of the second GPA as an example. In an alternative embodiment, when a second GPA is added to the EPT, the address information of the last-level page table entry corresponding to the second GPA is added to the first RMAP table. Optionally, based on the address information of the second GPA and the address space corresponding to each basic structure included in the first RMAP table, a first structure corresponding to the second GPA is determined from each basic structure. If it is determined that the address information of the last-level page table entry corresponding to the second GPA is not recorded in the first structure, indicating that the address information of the last-level page table entry corresponding to the second GPA is not recorded in the first RMAP table, then, based on the relationship between the level of the last-level page table corresponding to the second GPA and the set page table level, the address information of the last-level page table entry corresponding to the second GPA is recorded in the first structure. Detailed implementation methods can be found in the aforementioned description of "Recording the address information of the last-level page table entry corresponding to any GPA in the first structure based on the relationship between the level of the last-level page table corresponding to any GPA and the set page table level" and will not be repeated here. Example E3: A deletion operation is performed on the third GPA as an example for illustration. The situation of deleting a GPA is not limited. For example, when virtual memory needs to be reduced, some GPAs can be deleted, and the conversion relationship between the GPA and the HPA can be deleted. The following description is made by taking deletion of the third GPA as an example. In an optional embodiment, when the third GPA is deleted from the EPT, the address information of the last-level page table entry corresponding to the third GPA is deleted from the first RMAP table.Optionally, based on the address information of the third GPA and the address space corresponding to each basic structure included in the first RMAP table, a first structure corresponding to the third GPA is determined from each basic structure. If the level of the last-level page table corresponding to the third GPA matches the page table level indicated by the flag information of the first structure, the address information of the last-level page table entry corresponding to the third GPA is deleted via the first structure based on the relationship between the level of the last-level page table corresponding to the third GPA and the set page table level. The matching of the level of the last-level page table corresponding to the third GPA and the page table level indicated by the flag information of the first structure can be understood as: the level of the last-level page table is the same as the page table level to which the address information indicated by the flag information belongs. The flag information of the first structure is not only used to identify the type of address information stored in the information field of the first structure, but also, if the flag information identifies the address information of the last-level page table entry, can also identify the page table level to which the address information recorded in the information field of the first structure belongs, that is, the page table level to which the address information belongs. For example, when the flag information identifies the address information of the last-level page table entry, the flag information is a second value, which can be X0 or XI. XI indicates that the address information is the address information of a page table entry at the next level (e.g., the PTE level) below the set page table level, and X0 indicates that the address information is the address information corresponding to a page table entry at the previous level (e.g., the PUD level) above the set page table level. Example E4: A modification operation is performed on the fourth GPA as an example for illustration. The modification of the HPA address corresponding to the GPA is not limited. For example, when a memory swap operation is performed, if the original HPA page corresponding to the GPA is swapped to disk, the original HPA corresponding to the GPA can be modified to a new HPA. The modification of the fourth GPA is described below as an example. In an optional embodiment, when the first address information of the last-level page table corresponding to the fourth GPA is modified to the second address information in the EPT, the first address information of the last-level page table corresponding to the fourth GPA is modified to the second address information in the first RMAP table. Optionally, the first structure corresponding to the fourth GPA can be determined from the basic structures according to the address information of the fourth GPA and the address space corresponding to the basic structures included in the first RMAP table; and the first address information of the last-level page table entry corresponding to the fourth GPA is modified to the second address information through the first structure.Further, optionally, flag information is obtained from the first structure; if the flag information is a first value, the first address information recorded in the information field of the first structure is modified to the second address information; if the flag information is a second value, the address information of the second structure is obtained from the information field of the first structure, and based on the address information of the second structure, the first address information recorded in the information field of the second structure is modified to the second address information. Example E5: Expanding the last-level page table in the EPT to obtain a next-level page table. The following description uses the expansion of the last-level page table as an example. In an optional embodiment, when the last-level page table in the EPT is expanded to the next-level page table, the address information of the last-level page table entry corresponding to each GPA in the last-level page table is modified in the first RMAP table to the address information of the corresponding next-level page table. Optionally, the address information recorded in each page table entry in the last-level page table (i.e., the address information of the physical page corresponding to the HPA) is cleared in the EPT, and the address information of the last-level page table entries corresponding to each GPA in the last-level page table in the first RMAP table is cleared. A next-level page table corresponding to the last-level page table is created, and the address information of the next-level page table is recorded in the page table entry of the last-level page table. The address information of the physical page corresponding to the corresponding HPA is also recorded in the page table entry of the next-level page table. In the first RMAP table, the address information of the next-level page table entries corresponding to each GPA in the last-level page table is recorded using the first structure based on the relationship between the level of the next-level page table and the set page table level. Example E6: Shrinking the last-level page table in the EPT to obtain the previous-level page table. The following description uses shrinking the last-level page table as an example. In an optional embodiment, when a last-level page table with consecutive addresses in the EPT is shrunk to a previous-level page table, the address information of the last-level page table entries is cleared from the first RMAP table, and the address information of the previous-level page table entries corresponding to each GPA in the last-level page table is added. Optionally, the address information recorded in each page table entry in the last-level page table with consecutive addresses is cleared from the EPT, and the address information of the last-level page table entries corresponding to each GPA in the last-level page table in the first RMAP table is cleared. A previous-level page table corresponding to the last-level page table is created in the EPT, and the base address of the physical page corresponding to the corresponding HPA is recorded in the page table entry of the previous-level page table according to the page granularity corresponding to the previous-level page table entry. In the first RMAP table, the address information of the previous-level page table entries corresponding to each GPA in the last-level page table is recorded using a first structure based on the relationship between the level of the previous-level page table and the set page table level.In an alternative embodiment, considering that the EPT page table cannot perform reverse conversion from HPA to GPA, and that the underlying memory management often uses the HPA as a management unit to facilitate subsequent memory management, hot / cold management, and memory swapping, a fast mapping relationship between HPA and GPA is required. In this alternative embodiment, a second RMAP table corresponding to the EPT is pre-built. The second RMAP table stores address translation information from at least one HPA to a corresponding GPA. The address translation information for the corresponding GPA refers to the base address of the GPA page to which the corresponding GPA belongs, and the size of the GPA page corresponds to the size of the HPA page. For example, the second RMAP table stores address information for HPAs with a 2m granularity in the third structure. The GPA found directly by reverse lookup also corresponds to the 2m granularity. Other granularities of 4k or 1G require storage in the next-level extension structure (e.g., the fourth structure). For example, if the size of the HPA page corresponding to the last-level page table entry maintained in the EPT page table is 4KB, then the 4KB HPA page corresponds to a 4KB GPA page. In the second RMAP table, a 2MB GPA page is recorded through the third structure. Further, the 2MB GPA page is expanded to obtain multiple 4KB pages. The multiple 4KB pages are recorded through the fourth structure. If the size of the HPA page corresponding to the last-level page table entry maintained in the EPT page table is 2MB, then the 2MB HPA page corresponds to a 2MB GPA page. In the second RMAP table, the 2MB GPA page is recorded through the third structure. If the size of the HPA page corresponding to the last-level page table entry maintained in the EPT page table is 1GB, then the 1GB HPA page corresponds to a 1GB GPA page. The 1GB GPA page is split into multiple 2MB GPA pages. In the second RMAP table, the GPA of each 2MB granularity is recorded through the third structure. The address information of the GPA large page to which the 2M granularity page belongs is recorded through the fourth structure. The 512 2M granularity pages under the 1G page share the address information of the same GPA large page.In response to a second address translation triggering event, a first HPA requiring address translation is determined, and address translation information from the first HPA to the corresponding GPA is searched in a second RMAP table. The GPA corresponding to the first HPA is obtained based on the first HPA, its address translation information to the corresponding GPA, and the address offset of the first HPA. For example, the GPA corresponding to the first HPA is obtained by adding the offset of the first HPA to the address translation information. The second address translation triggering event may be a memory mapping management event for the GPA, a memory hot / cold management event, or a memory swap management event. Optionally, an implementation of pre-building a second RMAP table corresponding to the EPT includes: dividing the HPA address space corresponding to the EPT into at least one address space, creating a basic structure for each of the at least one address space, wherein the basic structure corresponds to a set page granularity, which may be 4K, 2M, or 1G. For an HPA corresponding to any GPA in the EPT, a third structure corresponding to the HPA is determined from the base structures based on the address information of the HPA and the address space corresponding to each base structure. The third structure is the base structure corresponding to the HPA in the second RMAP table. The HPA can be considered to be located in the address space corresponding to the third structure. For example, the third structure can be an rmap_head structure. Based on the relationship between the page granularity corresponding to the HPA and the set page granularity, the third structure records address translation information from the HPA to the corresponding GPA. The page granularity corresponding to the HPA is known and can be the same as or different from the set page granularity. Further, optionally, if the page granularity corresponding to any HPA is the same as the set page granularity, address translation information from any HPA to the corresponding GPA is recorded in the information field of the third structure, and the first flag information in the third structure is set to a third value. The third value indicates that the information field of the third structure records address translation information from any HPA to the corresponding GPA. The third value can be 0 or 1, etc. If the page granularity corresponding to any HPA is the same as or different from the set page granularity, a fourth structure adapted to the page granularity corresponding to the HPA is created. The granularity of the address space corresponding to the fourth structure is the same as the page granularity corresponding to the HPA. For example, the fourth structure corresponding to a 4KB page granularity can be rmap_extd, and the fourth structure corresponding to a 1GB page granularity can be rmap_cmpt.The address translation information from any HPA to the corresponding GPA is recorded in the information field of the fourth structure, and the address information of the fourth structure is added to the information field of the third structure. The first flag information in the third structure is set to a fourth value. The fourth value indicates that the information field of the third structure records the address information of the fourth structure, and the fourth value can be 0 or 1. The third and fourth values ​​can be represented by the lower three bits of the information field of the third structure. For example, the third and fourth values ​​can be any two different values ​​between 0 and 7. Alternatively, the third and fourth values ​​can be represented by two flag bits, with a flag bit being 1 indicating a valid value. Furthermore, an optional implementation of creating a fourth structure adapted to the page granularity of any HPA includes: when the page granularity of any HPA is one level higher than the set page granularity, determining whether a fourth structure already exists; if not, creating a new structure adapted to the page granularity of any HPA as the fourth structure. When the page granularity of any HPA is one level below the level of the page table defined by the set page granularity, a new structure adapted to the level of the last page table corresponding to any GPA is created as the fourth structure. A detailed description of this embodiment can be found in the implementation of creating a second structure adapted to the level of the last page table of any GPA, and will not be repeated here. For example, the page granularity, from highest to lowest level, may be: 512GB, 1GB, 2MB, and 4KB. If the page granularity of any HPA is 1GB and the set page granularity is 2MB, the page granularity of any HPA is considered to be one level above the set page granularity. If the page granularity of any HPA is 4KB and the set page granularity is 2MB, the page granularity of any HPA is considered to be one level below the set page granularity. In an optional embodiment, the mapping between the HPA and the GPA may be a one-to-one correspondence or a one-to-many relationship. For example, one HPA may correspond to multiple GPAs. Accordingly, an implementation method of recording address translation information from any HPA to a corresponding GPA using the information field in the third structure includes: when any HPA corresponds to multiple GPAs, creating a fifth structure. The fifth structure is an extension of the third structure and is a structure for recording address translation information from any HPA to multiple GPAs when the page granularity of any HPA is the same as the preset page granularity.The address information in the fifth structure is added to the information field in the third structure, and the address translation information from any HPA to multiple GPAs is added to the fifth structure. A flag indicating a one-to-many relationship is added to the third structure. If any HPA corresponds to one GPA, the address translation information from any HPA to the corresponding GPA is directly added to the information field in the third structure without setting the flag indicating a one-to-many relationship. A one-to-one relationship between HPA and GPA is assumed by default. Accordingly, the address translation information from any HPA to the corresponding GPA is recorded in the information field in the fourth structure. This includes: If any HPA corresponds to multiple GPAs, a sixth structure is created. The sixth structure is an extension of the fourth structure and records the address translation information from any HPA to multiple GPAs when the page granularity of any HPA differs from the set page granularity. The address information of the sixth structure is added to the information field of the fourth structure, and the address translation information from any HPA to multiple GPAs is added to the sixth structure. A flag indicating a one-to-many relationship is added to the fourth structure. When any HPA corresponds to one GPA, the address translation information from any HPA to the corresponding GPA is directly added to the information field of the fourth structure. It should be noted that the fifth and sixth structures can be implemented as rmap_desc structures, namely, rmap_desc {unsigned long val[VAL_DESC_NR]; struct rmap_desc *more;}. Val[VAL_DESC_NR] is used to store address translation information from any HPA to multiple corresponding GPAs. Each element in the array represents address translation information from any HPA to a corresponding GPA. The *more pointer can point to the next rmap_desc structure. The next rmap_desc structure also includes the val[VAL_DESC_NR] array to facilitate storage of address translation information for more GPAs. The following examples illustrate the addition, query, deletion, modification, expansion, and shrink / expand operations based on the first and second RMAP tables, but are not limited thereto. The EPT page table is a four-level page table structure, including four page tables: PGD, PUD, PMD, and PTE. The last-level page table of the EPT may be at least one of PGD, PUD, PMD, and PTE.Accordingly, the last-level page table entry can be pgd_t, pud_t, pmd_t, or pte_to. The base structure is identified by rmap_head. The unified structure at the PTE level is rmap_extd. The address information of the last-level page table entry stored in the second structure is the element in the val[VAL_EXTD_NR] array in the unified structure. The second structure at the PUD level is rmap_cmpto. 1. Query the HP Ao corresponding to the first GPA in the first RMAP table.

[0005] 1. First, based on the address information of the first GPA and the address spaces corresponding to the basic structures in the first RMAP table, determine the first structure (rmap_head) corresponding to the first GPA from the basic structures. The first RMAP table can be considered a large array, where the elements in the large array are basic structures. Each basic structure corresponds to an address space of 2M. Therefore, based on the address information of the first GPA, select the basic structure corresponding to the first GPA from the large array at a granularity of 2M, and use this selected basic structure as the first structure.

[0006] 2. Select different query methods according to the flag information of the information field (val) in the first structure rmap_head.

[0007] 1) If the flag information is the second value corresponding to rmap_cmpt, it means that the page granularity corresponding to the last level page table entry of the second GPA is 1G. a) Parse the rmap_cmpt structure from the information field (val) of rmap_head, that is, obtain the address information of rmap_cmpt; b) Parse the information field in rmap_cmpt (the second structure) into the new rmap_head ,Here, rmap_head is a general structure. The new rmap_head can be understood as the value contained in the information field of rmap_cmpt. c) Determine whether the value val in the new rmap_head is the address information of a page table entry. For example, the flag information in the value val can be used to determine whether the value val is the address information of a page table entry. If so, the base address of the physical page recorded in the address information of the last level of the first GPA recorded in the new rmap_head is read. The address offset of the first GPA is added to the base address to generate the HPA corresponding to the first GPA. The address offset is the offset within the 1GB memory page. If not, it indicates that the value val in the new rmap_head has a next-level extended structure. The value val is the address information of the next-level extended structure. The next-level extended structure can be a structure corresponding to a one-to-many relationship.

[0008] 2) If the flag information is the second value corresponding to rmap_extd, it indicates that the page granularity of the last-level page table entry corresponding to the second GPA is 4KB. a) Parse the rmap_extd structure from the information field of rmap_head to obtain the address information of rmap_extd. b) Based on the offset oft of the second GPA in 4KB granularity within 2MB, select the oftth val element in rmap_extd from the val[VAL_EXTD_NR] array, which is the address information of the second structure. c) Parse the oftth val element into a new rmap_head. d) Determine whether the val value in the new rmap_head is the address information of a page table entry. If so, read the physical page base address recorded in the address information based on the last-level address information of the first GPA recorded in the new rmap_head. Add the address offset of the first GPA to this base address to generate the HPA corresponding to the first GPA. The address offset is the offset within the 4KB memory page. If not, it means that the val value in the new rmap_head has a next-level extension structure, the val value is the address information of the next-level extension structure, and the next-level extension structure may be a structure corresponding to a one-to-many relationship.

[0009] 3) If the flag information is the first value corresponding to rmap_head or the flag information is not set, the page granularity corresponding to the last-level page table entry is 2M, and parsing the lower-level structure is not required. a) Determine whether the value val in the new rmap_head is the address information of the page table entry. If so, the last-level address information of the first GPA recorded in the new rmap_head is read, and the base address of the physical page recorded in this address information is added to the base address of the first GPA to generate the HPA corresponding to the first GPA. The address offset is the offset within the 2M memory page. If not, it indicates that the value val in the new rmap_head has a next-level extension structure. The value val is the address information of the next-level extension structure, which can be a structure corresponding to a one-to-many relationship. This embodiment also includes querying the GPA corresponding to the first HPA in the second RMAP table. This process is similar to the implementation of querying the HPA corresponding to the first GPA in the first RMAP table and will not be repeated here. Furthermore, since HPAs and GPAs are stored in a one-to-many mapping relationship, when querying the GPA corresponding to the first HPA in the second RMAP table, a one-to-many mapping lookup operation may also be included. The following focuses on the differences between one-to-many and one-to-one mapping, and the remaining information is not repeated. For example, when searching for the corresponding GPA for the second HPA, if the flag information in the third structure is the fourth value, the fourth structure is rmap_cmpt, the flag information in the fourth structure rmap_cmpt indicates a one-to-many mapping relationship, and the fourth structure stores the address information of the fifth structure rmap_desc, it is necessary to loop through each val recorded in rmap_desc to determine whether val is the address information of a page table entry. If so, the val value is directly returned.If not, the val value is the address information of the next-level extension structure, and val can be obtained from the next-level extension structure. When querying rmap_desc, all elements in the val[VAL_DESC_NR] array of rmap_desc can be obtained, and the corresponding GPA is calculated based on the address conversion information of the GPA recorded by each element and the offset of the first HPA. Of course, you can also return a certain element in the array according to the set filtering conditions, add the address conversion information of the GPA recorded by the element to the offset of the first HPA, and obtain the GPA corresponding to the first HPA. If the length of val[VAL_DESC_NR] is 5, it means that the array can store 5 elements. The array is connected to the subsequent array through the *more pointer. If you want to get the 13th element of the array, you can use the more pointer in the first rmap_desc to get the address information of the second rmap_desc. Based on the address information of the second rmap_desc, Determine the address information of the third rmap_desc pointed to by the more pointer in the second rmap_desc. Based on the address information of the third rmap_desc, obtain the third element in val[VAL_DESC_NR] of the third rmap_desc. This third element is the address translation information of the GPA corresponding to the first HPA. Adding this to the address offset of the first HPA yields the GPA corresponding to the first HPA. If the length of val[VAL_DESC_NR] is 5, to obtain the third element of the array, directly obtain the third element from val[VAL_DESC_NR] of the first rmap_desc, which is the address translation information of the GPA corresponding to the first HPA. Adding this address translation information to the address offset of the first HPA yields the GPA corresponding to the first HPA. 2. Add the HPA corresponding to the second GPA to the first RMAP table.

[0010] 1. First, based on the address information of the second GPA and the address spaces corresponding to the basic structures in the first RMAP table, determine the first structure (rmap_head) corresponding to the second GPA from the basic structures. The first RMAP table can be considered a large array, where the elements in the large array are basic structures. Each basic structure corresponds to an address space of 2M. Therefore, based on the address information of the second GPA, select the basic structure corresponding to the second GPA from the large array at a granularity of 2M, and use this selected basic structure as the first structure.

[0011] 2. Determine the page table level of the last page table level of the second GPA; obtain the flag information of the first structure and determine whether the address information stored in the information field of the first structure, as indicated by the flag information, corresponds to a structure at the page table level. If so, it is assumed that a structure at the page table level already exists. If not, it is assumed that a structure corresponding to the page table level does not exist, and a structure corresponding to the page table level is created. For example, if the page table level is PUD level, but the flag information of the first structure is not set to the value corresponding to rmap_cmpt, an rmap_cmpt structure is allocated and written into the information field of the first structure.

[0012] 3. Determine whether the address information of the last level page table entry corresponding to the second GPA exists in the structure corresponding to the page table level level. If so, directly return the address information;

[0013] 4. If it does not exist, add HP Ao to the second GPA. At this time, different adding methods can be selected according to the flag information of the information field (val) in the first structure head rmap.

[0014] 1) If the flag information is the second value corresponding to rmap_cmpt, it indicates that the page granularity corresponding to the last-level page table entry of the second GPA is 1GB. It should be noted that when establishing a 1GB granularity mapping for a GPA for the first time, an rmap_cmpt structure can be requested. The address information of the HPA aligned with the 1GB GPA can be recorded in the rmap_cmpt structure, and a count can be incremented. The address information of the 512 rmap_heads contained in the 1GB memory page can be associated with the rmap_cmpt structure. Specifically, the address information of the rmap_cmp is recorded in the information field of each rmap_head. When subsequently establishing mappings for other GPAs in the 1GB memory page, the mapping count can be incremented in the rmap_cmpt structure.

[0015] 2) If the flag information is the second value corresponding to rmap_extd, it indicates that the page granularity corresponding to the last-level page table entry of the second GPA is 4KB. a) Parse the rmap_extd structure from the information field of rmap_head to obtain the address information of rmap_extd. b) Based on the offset oft of the 4KB granularity of the second GPA in 2M, select the oftth val element in rmap_extd from the val[VAL_EXTD_NR] array, which is the address information of the second structure. c) Parse the oftth val element into a new rmap_head. d) Add the map value (i.e., the address information of the pte_t page table entry) to the new rmap_head, that is, add the address information of the pte_t page table entry to the information field of the second structure. e) Add the mapping count num in the rmap_extd structure.

[0016] 3) If the flag information is the first value corresponding to rmap_head or the flag information is not set, the page granularity corresponding to the last-level page table entry is 2m, and parsing of the underlying structure is not required. a) Directly add the map value, i.e., the address information of the last-level page table entry (pmd_t), to the information field of rmap_head. This embodiment also includes adding the GPA corresponding to the second HPA to the second RMAP table. This process is similar to the implementation of adding the HPA corresponding to the second GPA to the first RMAP table and will not be repeated here. In addition, since HPA and GPA are stored in a one-to-many relationship, adding the GPA corresponding to the second HPA to the second RMAP table can also include a one-to-many mapping operation. The following focuses on the differences between "one-to-many" and "one-to-one" mapping, and will not be repeated here. The third structure recording the address translation information from the second HPA to the corresponding GPA is used as an example for explanation. The implementation of recording the address translation information corresponding to the GPA in the fourth structure is the same or similar and will not be repeated here. If this is the first time that address translation information for a GPA is added to the third structure, the address translation information for the GPA corresponding to the second HPA is directly recorded in the information field of the third structure. If the second HPA corresponds to multiple GPAs, the flag information in the third structure is checked to see if it contains the "one-to-many" flag. If not, this indicates the first time the third structure is expanded. A fifth structure (rmap_desc) can be allocated. This rmap_desc structure includes: val[VAL_DESC_NR] . This array can be initialized to a special value, as long as the special value is not used as address information. For example, ffffffff, where f represents the maximum hexadecimal number, or 15, where ffffffff is the last address in the 4GB memory space. The address translation information for the GPA recorded in the third structure is recorded in the first element of val[VAL_DESC_NR] . The address translation information for the GPA to be added is then recorded in the second element of val[VAL_DESC_NR] . The address information of the rmap_desc structure is recorded in the information field of the third structure, and a flag indicating a one-to-many relationship is added to the third structure.If the third structure contains flag information, indicating that it has been extended at least once, the system first searches rmap_desc for any free, unrecorded locations. If so, it selects that location and records the map value, i.e., the address translation information for the second HPA to the GPA. If the recorded location is not found in rmap_desc, a new rmap_desc is allocated and attached to the end of the more pointer of the last rmap_desc. Then, a free location in the newly allocated rmap_desc array is selected and recorded with the map value, i.e., the address translation information for the second HPA to the GPA. Third, the HP Ao corresponding to the third GPA is deleted from the first RMAP table.

[0017] 1. First, based on the address information of the second GPA and the address spaces corresponding to the basic structures in the first RMAP table, determine the first structure (rmap_head) corresponding to the second GPA from the basic structures. The first RMAP table can be considered a large array, where the elements in the large array are basic structures. Each basic structure corresponds to an address space of 2M. Therefore, based on the address information of the second GPA, select the basic structure corresponding to the second GPA from the large array at a granularity of 2M, and use this selected basic structure as the first structure.

[0018] 2. Determine the page table level of the last page table level of the second GPA; obtain the flag information of the first structure and determine whether the address information stored in the information field of the first structure, as indicated by the flag information of the first structure, corresponds to a structure at the page table level. If so, it is assumed that a structure at the page table level already exists, and step 3 is executed. If not, it is assumed that a structure corresponding to the page table level does not exist, and neither does an HPA corresponding to the third GPA, and an error is returned. For example, if the page table level is PUD level, but the flag information of the first structure is not set to the value corresponding to rmap_cmpt, an error is returned.

[0019] 3. Select different deletion methods according to the flag information of the information field (val) in the first structure rmap_head.

[0020] 1) If the flag information is the second value corresponding to rmap_cmpt, it indicates that the page granularity corresponding to the last-level page table entry of the second GPA is 1GB. a) Parse the rmap_cmpt structure from the information field (val) of rmap_head, thereby obtaining the address information of rmap_cmpt. b) Parse the information field of the rmap_cmpt structure into a new head_rmap. c) Delete the map value (i.e., the address information of pud_t) from the new rmap_head. d) Decrement the mapping count num in the rmap_cmpt structure. e) If the mapping count num becomes 0, free the rmap_cmpt structure. It should be noted that when freeing the rmap_cmpt structure, the rmap_cmpt structure corresponds to a 1GB memory page. The val values ​​in the rmap_head corresponding to the 512 2MB memory pages under this 1GB memory page store the address information of the rmap_cmpt structure. When freeing the rmap_cmpt structure, the val values ​​in each rmap_head can be cleared.

[0021] 2) If the flag information is the second value corresponding to rmap_extd, it indicates that the page granularity corresponding to the last-level page table entry corresponding to the second GPA is 4KB. a) Parse the rmap_extd structure from the information field of head_rmap, that is, obtain the address information of rmap_extd. b) Based on the offset oft of the 4KB granularity of the second GPA in 2M, select the oft-th val element in rmap_extd from the val[VAL_EXTD_NR] array, that is, the address information of the second structure. c) Parse the oft-th val element into a new rmap_head. d) Delete the map value (that is, the address information of pte_t) from the new rmap_head, and decrement the mapping count by 1. When the count reaches 0, release the rmap_extd structure. At the same time, the mapping in the rmap_head of the upper layer is also cleared, that is, the address information of rmap_extd recorded in the val of rmap_head is cleared.

[0022] 3) If the flag information is the first value corresponding to rmap_head or the flag information is not set, the page granularity corresponding to the last-level page table entry is 2m, and parsing of the lower-level structure is not required. a) Delete the map value recorded in the information field of rmap_head. This map value is the address information of pmd_t. This embodiment also includes deleting the GPA corresponding to the third HPA from the second RMAP table. This process is similar to the implementation of deleting the HPA corresponding to the third GPA from the first RMAP table and will not be repeated here. In addition, since HPAs and GPAs are stored in a one-to-many relationship, deleting the GPA corresponding to the third HPA from the second RMAP table may also include adding a one-to-many mapping. The following focuses on the differences between "one-to-many" and "one-to-one" mappings, and will not be repeated here. Deleting the address translation information from the third HPA to the corresponding GPA in the third structure is used as an example for explanation. The implementation of deleting the address translation information from the corresponding GPA in the fourth structure is the same or similar and will not be repeated here. In the case where the third HPA corresponds to multiple GPAs, the address information of the rmap_desc structure is obtained from the information field of the third structure, and each element recorded in the rmap_desc structure is looped to determine whether it is the address translation information from the third HPA to the corresponding GPA that needs to be deleted; if the address translation information from the third HPA to the corresponding GPA that needs to be deleted (hereinafter referred to as the map value) is found and the rmap_desc structure exists, first find the position j where the last map value exists in the rmap_desc; replace the value of the last position j with the position i to be deleted, and delete the value of position j; if j is not 0 at this time, return; if j is 0, it indicates that the entire rmap_desc is empty and the rmap_desc can be deleted: if a previous rmap_desc exists, update the rmap_desc information mounted under the more of the current rmap_desc to the more linked list under the previous rmap_desc; if the previous rmap_desc does not exist, change the value of val in rmap_head, Associated with the rmap_desc pointed to by the more of the current rmap_desc. 4. In the first RMAP table, modify the first address information of the last-level page table corresponding to the fourth GPA to the second address information. In the second RMAP table, modify the first address translation information of the GPA corresponding to the fourth HPA to the second address translation information. This description is based on the example of the last-level page table being the PMD level.

[0023] 1. Clear the original HPA-GPA mapping at the PMD level, that is, clear the first address conversion information of the GPA corresponding to the fourth HPA recorded in the second RMAP table;

[0024] 2. Create a new PMD-level page table mapping in the EPT and record the physical page corresponding to the new HPA in the PMD-level page table entry;

[0025] 3. At the same time, a new HPA-GPA mapping of the PMD level is established, that is, the second address translation information of the GPA corresponding to the fourth HPA is recorded in the second RMAP table;

[0026] 4. Refresh the EPT page table to make the changes effective. During subsequent host machine operation, page table expansion, contraction, and updates may occur. In this case, when updating the EPT, the first and second RMAP tables can be updated simultaneously. 5. When the last-level page table in the EPT is expanded to the next-level page table, the address information of the last-level page table entry corresponding to each GPA in the last-level page table is modified in the first RMAP table to the address information of the corresponding next-level page table. The following uses the example of expanding the PMD-level EPT page table to the PTE-level as an example.

[0027] 1. Determine whether the EPT page table needs to be expanded, that is, whether the EPT page table is already at the PTE level; if so, return directly; otherwise, continue;

[0028] 2. Allocate a page EPTP to record the page table at the next level, the PTE level. EPTP stands for extended-page-table pointer (EPT), which is the field that stores the physical address of the EPT page table.

[0029] 3. Clean up the previous PMD-level page table mapping, including cleaning up the physical page address information recorded in the original PMD page table;

[0030] 4. Clear the GPA_HPA mapping (also known as GPA_EPT mapping) and HPA_GPA mapping in the original first RMAP table;

[0031] 5. Establish a corresponding mapping relationship for each PTE-level page table in the next level (that is, write the base address of the physical page in each PTE-level page table entry) and record the address information of the PTE-level page table entry in the allocated page EPTP;

[0032] 6. During the creation of each PTE-level page entry, new GPA_HPA mapping and HPA_GPA mapping are also created synchronously to obtain the expanded first RMAP table and second RMAP table, respectively.

[0033] 7. Finally, associate the newly allocated page EPTP with the original PMD level page table entry;

[0034] 8. Refresh the EPT page table to make the update effective. 6. When the last-level page table with consecutive addresses in the EPT is shrunk to the previous-level page table, the address information of the last-level page table entry corresponding to each GPA in the last-level page table is modified in the first RMAP table to the address information of the previous-level page table entry. The following uses the example of shrinking a PTE page table to a PMD page table.

[0035] 1. Determine whether the EPT page table needs to be shrunk, that is, whether the EPT page table is already at the PMD level; if so, return directly; otherwise, continue;

[0036] 2. Determine whether the next-level PTE page table can be shrunk, that is, the mapping relationship of the next-level PTE page table is completely empty, or the record is a continuous HPA range, and the first HPA address is PMD-level aligned;

[0037] 3. Clean up the corresponding mapping relationship for each PTE-level page table in the next level, for example, clean up the base address of the physical page recorded in each page table entry in the PTE page table;

[0038] 4. During the cleaning of each PTE-level page entry, the old GPA_EPT mapping and HPA_GPA mapping are also cleaned up synchronously, that is, the corresponding mapping relationships in the first RMAP table and the second RMAP table are cleaned up;

[0039] 5. Create a new PMD-level page table mapping, record the HPA mapping information in the EPT page table entry, and disassociate the original lower-level PTE page table;

[0040] 6. At the same time, new PMD-level RMAP table information must be established, including the mapping of GPA_EPT and HPA_GPA;

[0041] 7. Refresh the EPT page table to make the update effective. 8. Release the page that originally recorded the PTE-level page table. Seventh, this may also include: clearing page table entries at a specific page table level. For example, when the page is swapped out, the HPA_GPA mapping is updated. The following uses the clearing of PMD-level page table entries as an example to illustrate.

[0042] 1. Clean up the original PMD-level HPA_GPA mapping;

[0043] 2. Clear the old PMD-level page table mapping recorded in the PMD-level page table entry;

[0044] 3. Refresh the EPT page table to make the update effective. In addition to providing the above-mentioned address translation method, this embodiment also provides a fast mapping table construction method, as shown in FIG1b , which includes:

[0045] R21. Divide the GPA address space corresponding to the EPT into at least one address space, create a basic structure for each of the at least one address space, the basic structure corresponding to a set page table level, and the EPT includes a multi-level page table corresponding to each of the at least one GPAs;

[0046] R22. For any GPA in the EPT, determine a first structure corresponding to the GPA from the basic structures based on the address information of the GPA and the address space corresponding to the basic structures.

[0047] R23. Based on the relationship between the level of the last-level page table corresponding to any GPA and the set page table level, record the address information of the last-level page table entry corresponding to any GPA using a first structure to construct a first RMAP table corresponding to the EPT. The first RMAP table stores the address information of the last-level page table entry corresponding to at least one GPA. The detailed implementation and beneficial effects of each step in the method shown in FIG1a and FIG1b according to the embodiments of the present disclosure have been described in detail in the previous embodiments and will not be elaborated upon here. In addition to the above-described method, the embodiments of the present disclosure also include an introduction to the virtualization layer as follows: In the embodiments of the present disclosure, as shown in FIG2a , a host machine includes hardware resources, a host operating system (host OS) running on the hardware resources, and various applications running on top of the host OS. Compared to hardware resources, the host OS and applications are software resources of the host machine. The host OS is the most basic system software in the host machine. It is responsible for controlling and managing the hardware and software resources of the entire host machine, and can reasonably schedule the host machine's work and resource allocation, providing a convenient interface and environment for users and other software or devices. The host operating system provides various system-level functions, such as file management, memory management, and various input / output (I / O) device management. Based on these system functions, the host operating system provides applications with the resources they need to run, supporting their operation. At least some of these system functions require configuration during host operating system installation, including whether to enable them and in which mode. Unenabled system functions are unavailable during host operating system operation. This inability to use these system functions can cause applications that rely on them to run abnormally or even fail due to a lack of access to the resources provided by these functions. However, as the host operating system and application requirements evolve, these unenabled system functions may need to be used, or enabled system functions may need to be upgraded. This presents the challenge of expanding the host operating system's capabilities. Traditional host systems require either reinstalling the host operating system or forcibly enabling some system functions online. Reinstalling the host operating system requires interrupting all applications, resulting in low efficiency and high cost. Forcibly enabling these system functions online can severely impact system stability.In embodiments of the present disclosure, to address the capability expansion issues faced by a host operating system without reinstalling the host operating system and without affecting the operating performance of the host operating system, a new physical machine architecture is provided. Two operating modes, namely, root mode and non-root mode, are provided for a running host operating system. A virtualization layer is inserted between hardware resources and the host operating system. The virtualization layer implements at least a virtual resource provisioning function. The virtualization layer switches the running host operating system from root mode to non-root mode. In non-root mode, at least one virtual resource is provided and at least one application that the host operating system cannot run in root mode due to insufficient resources is run on the virtual resource. Without reinstalling the operating system, the virtual resource provisioning function can be flexibly implemented for the running host operating system. This solves the problem of application programs being unable to run due to insufficient resources due to reasons such as disabled or missing system functions, supports the operation of more applications, and facilitates expanding the capabilities of the host operating system. For example, assume that the host operating system supports functions A, B, C, and D. When the host operating system is installed, functions A, B, and C are enabled, but function D is disabled and function E is missing (i.e., the host operating system does not support function E). Using the physical machine provided by the embodiments of the present disclosure, a virtualization layer is inserted between the hardware resources and the host operating system. At least the virtualization layer implements the function of providing virtual resources. For example, if the host operating system disables function D and lacks function E, the virtualization layer switches the host operating system from root mode to non-root mode. In the non-root mode, virtual resources corresponding to functions D and E are provided. Applications that were originally unable to run due to the disabled function D and the missing function E are run on these virtual resources. Without reinstalling the host operating system, the virtual resource provision function can be flexibly implemented for the running host operating system, thereby resolving the problem of applications being unable to run due to the disabled function D and the missing function E, and thus facilitating the expansion of the capabilities of the host operating system. Furthermore, to compensate for the deficiencies of the host operating system, virtual resources corresponding to functions D and E may be preferentially provided in non-root mode to resolve the operation issues of applications that rely on functions D and E. Of course, to maintain the compatibility of the host operating system and avoid frequent mode switching, virtual resources corresponding to functions A, B, and C may also be provided in non-root mode to facilitate the operation of corresponding applications that rely on functions A, B, and C on these resources.It should be noted that in the embodiments of this disclosure, the focus is on the host operating system switching process between the two modes. The virtual resources corresponding to the system functions provided in non-root mode and how these virtual resources are provided are not limited. The following, in conjunction with the accompanying figures, details the physical machine architecture and the process of the host operating system switching from root mode to non-root mode provided in the embodiments of this disclosure. Figure 2b is a schematic diagram of the structure of a physical machine provided in an exemplary embodiment of this disclosure. As shown in Figure 2b, the physical machine includes hardware resources 10 and a host operating system 20 running on the hardware resources. A virtualization layer 30 is implemented between the hardware resources 10 and the host operating system 20. Furthermore, an application layer 40 is provided above the host operating system 20. The application layer 40 includes various application programs. Optionally, the hardware resources 10 include at least one physical computing resource object 101 and a physical storage medium 102, which provides a physical address space. In addition, the hardware resources 10 on the physical machine may also include other components, not shown, such as devices, communication components, displays, power components, and audio components. The physical computing resource objects 101 may include various physical resource objects with computing capabilities, such as a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), a tensor processing unit (TPU), a cloud infrastructure processing unit (CIPU), and an application-specific integrated circuit (ASIC). The host operating system 20 may run on at least one physical computing resource object 101. The physical storage medium 102 may include permanent and non-permanent, removable and non-removable media, and may implement information storage using any method or technology. The information may be computer-readable instructions, data structures, program modules, or other data.Physical storage media 102 includes, but is not limited to, phase-change random access memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic tape, disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible by a computing device. Physical memory refers to the actual memory chips or modules within a physical machine that are used to store data and program code. Physical memory may include non-permanent storage within physical storage media 102, random access memory (RAM), and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. The physical address space is the address range corresponding to physical memory. The physical address space is typically related to the hardware architecture and the host operating system, describing the physical location and size of the actual memory bank. In a virtual memory system, the physical address space also involves mechanisms such as memory page tables, which are used to map guest physical addresses to host physical addresses. In this embodiment, the host operating system 20 corresponds to root mode and non-root mode. Root mode is an operating mode in which the host operating system 20 has direct access to hardware resources 10. Non-root mode is an operating mode in which the virtualization layer 30 virtualizes the hardware resources 10 and schedules and accesses the virtualized resources on behalf of the host operating system 20. In non-root mode, the virtualization layer 30 has limited access to the hardware resources 10. Accordingly, the host operating system 20 in non-root mode can also be referred to as a guest operating system. In this embodiment, a lightweight, powerful, and efficient virtualization layer 30 is inserted between the hardware resources 10 and the host operating system 20. The virtualization layer 30 can be developed in advance and inserted between the hardware resources 10 and the host operating system 20. The method of inserting the virtualization layer 30 is not limited.For example, after the host operating system 20 is installed on a physical machine, the virtualization layer 30 can be inserted while the host operating system 20 is in normal operation. The virtualization layer 30 has the capability to provide virtual resources, at least corresponding to resources that the host operating system 20 cannot provide in root mode due to disabled or missing system functions. In other words, the virtualization layer 30 can provide corresponding virtual resources for resources that the host operating system 20 cannot provide in root mode due to disabled or missing system functions, thereby facilitating the running of corresponding applications. Specifically, the virtualization layer 30 can switch the running host operating system 20 from root mode to non-root mode, provide at least one virtual resource in non-root mode, and run at least one application on the at least one virtual resource. This allows the virtualization layer 30 to flexibly implement the virtual resource provision function for the running host operating system without reinstalling the operating system, resolving the issue of the host operating system 20 being unable to provide corresponding resources to run corresponding applications in root mode due to disabled or missing system functions. This can support the running of more applications and facilitate the expansion of the host operating system's capabilities. Furthermore, to maintain host operating system compatibility and reduce frequent mode switching of the host operating system, in non-root mode, corresponding virtual resources can be provided not only for system functions that are disabled or missing in the host operating system 20 in root mode, but also for system functions that are enabled in the host operating system 20 in root mode, thereby supporting more functions of the host operating system 20. For example, the at least one target function implemented in the virtualization layer 30 includes, but is not limited to, memory management, file management, virtualization, and scheduling optimization functions. The memory management, file management, and scheduling optimization functions herein may be newly developed functions not originally supported by the host operating system, or functions originally supported by the host operating system but not enabled during the host operating system installation process. Whether newly expanded or not yet enabled, memory management functions include but are not limited to: memory page fault management, memory swap management, memory mapping management, etc.; file management functions include but are not limited to: directory management, permission management, file backup, creation, query, deletion, modification, etc.; virtualization functions include but are not limited to: virtualization of various elastic resources (such as CPU, GPU, memory, network, etc.); scheduling and tuning functions include but are not limited to: scheduling of physical computing resource objects and scheduling of various virtualized resources, etc.Furthermore, FIG2b shows a schematic diagram of the overall architecture of a physical machine. FIG2c and FIG2d illustrate the internal architecture of a physical machine operating in root mode and non-root mode, respectively. Before a mode switch, the host operating system operates in root mode. In this root mode, as shown in FIG2c , the internal architecture of the running physical machine, from bottom to top, consists of hardware resources 10, host operating system 20, and application layer 40. After the mode switch, the physical machine operates in non-root mode. In this non-root mode, as shown in FIG2d , the architecture of the running physical machine, from bottom to top, consists of hardware resources 10, virtualization layer 30, guest operating system, and application layer 40. The term "guest operating system" refers to the host operating system 20 operating in non-root mode. In an embodiment of the present disclosure, two operating modes are provided for a running host operating system, namely, a root mode and a non-root mode. A virtualization layer is inserted between hardware resources and the host operating system. The virtualization layer implements at least the virtualization layer's virtual resource provision function. The virtualization layer switches the running host operating system from root mode to non-root mode, provides virtual resources in non-root mode, and runs at least applications that the host operating system cannot run in root mode due to insufficient resources on the virtual resources. Without reinstalling the host operating system, the virtual resource provision function can be flexibly implemented for the running host operating system, supporting the operation of more applications and expanding the capabilities of the host operating system. It should be noted that, from the perspective of program code, the implementation code for "providing virtual resources" and "switching from root mode to non-root mode" in the embodiments of the present disclosure belongs to the virtualization layer 30, and this code resides under the host operating system. However, from the perspective of the running state, before the mode switch is actually completed, at least a portion of the program code in the virtualization layer 30 is executed during the operation of the host operating system. In other words, at least a portion of the program code in the virtualization layer 30 is executed in root mode. The program code executed in the virtualization layer 30 in root mode includes at least program code for switching from root mode to non-root mode, such as the upper half of the switching function described in the following embodiments. Correspondingly, after the mode switch is actually completed, a portion of the program code is executed in non-root mode, such as the lower half of the switching function described in the following embodiments.Furthermore, the program code responsible for providing virtual resources within the virtualization layer 30 also runs in root mode, but this code is executed after the switch is complete. The virtualization layer 30 also provides some external interface code, some of which runs in non-root mode, while others require switching to root mode, depending on the specific functionality of the interface code. In an alternative embodiment, as shown in FIG3a , the virtualization layer 30 switches the running host operating system from root mode to non-root mode in three steps:

[0048] 51. Create a memory page table to store the mapping relationship between the guest physical address in non-root mode and the host physical address in root mode;

[0049] 52. Create an information carrier object required for mode switching. The information carrier object is used to synchronize context information between the root mode and the non-root mode.

[0050] S3. Based on the information carrier object and the memory page table, the running host operating system is switched from root mode to non-root mode. The detailed implementation of the above three parts is described below. Step S1: Creating a memory page table. In root mode, the physical address space has host physical addresses, which can be represented by HPA (Host Physical Address), which is the address of physical memory in the physical memory resource. In non-root mode, the physical address space corresponds to a virtual address space, which has guest physical addresses, which can be represented by GPA (Guest Physical Address), which is the address of virtual memory in the virtual memory resource. In this embodiment, the virtualization layer 30 can create a memory page table, which is used to store the mapping between guest physical addresses in non-root mode and host physical addresses in root mode. The memory page table can be represented by EPT (Extended Page Tables). It should be noted that when the memory page table is initially established, since the host operating system is not yet running in non-root mode and has not yet performed operations such as memory reclaim or memory swapping, the guest physical address in non-root mode is the same as the host physical address in root mode. Subsequently, as the host operating system is used in non-root mode, for example, through memory reclaim or memory swapping, the guest physical address may no longer be equal to the host physical address. The memory page table can dynamically maintain the mapping relationship between the guest physical address and the host physical address. In an optional embodiment, as shown in FIG3b , the memory page table creation process includes: S11, establishing a page table structure corresponding to the memory page table; S12, requesting the root page of the memory page table from the physical address space; S13, generating a memory page table entry address based on the host physical address of the root page and adding it to the page table structure; S14, creating a multi-level memory page table based on the address range of the physical address space and the page granularity used to map guest physical addresses to host physical addresses. First, create a page table structure. The purpose of this page table structure is to store various information related to the memory page table, such as the entry address of the memory page table, the address lock array (Address Lock Array) used to operate the memory page table, and the address of the special Advanced Programmable Interrupt Controller (APIC) page.The memory page table entry address is used to access the memory page table. For example, the entry address can be the first address of the memory page table. Each entry in the address lock array corresponds to a page table entry and contains a lock flag that indicates whether the entry is locked. If it is not locked, the process can access the memory space corresponding to the page table entry. The address of a special APIC page is mainly used to access special APIC pages. After creating the page table structure, a physical page can be requested from the physical address space provided by the physical storage medium to serve as the root page of the memory page table. The memory page table entry address is generated based on the host physical address of the root page and added to the page table structure. The format of the memory page table entry address varies depending on the type of physical computing resource object and the manufacturer. For example, the host physical address of the root page can be directly used as the memory page table entry address. In another example, the host physical address of the root page can be added to a set offset or flag to serve as the memory page table entry address. This is not limited to this method. The physical address space has an address range. For example, the address range of the physical address space may be 0-8G < 0-16G, etc. Furthermore, in this embodiment, in non-root mode, the single page granularity supported by the host operating system can be broken, allowing the page granularity for address mapping to be set as needed. For example, the page granularity for address mapping may include, but is not limited to, 4K (Kilobyte) > 2M (Megabyte) or 1G (Gigabyte). In view of this, in an optional embodiment, the virtualization layer 30 may create a multi-level memory page table based on the address range of the physical address space and the page granularity used to map client physical addresses to host physical addresses. The multi-level memory page table may be a two-level memory page table, a four-level memory page table, or a five-level memory page table, etc., depending on the address range and page granularity of the physical address space. For example, for the same address range, a smaller page granularity requires more memory page table levels. For another example, for the same page granularity, a larger address range requires more memory page table levels. Optionally, in this embodiment, the physical address space is divided into a first address space and a second address space. The second address space is larger than the first address space; that is, the address size of the second address space is larger than that of the first address space.For example, if the physical address space is 8GB, the address range of the physical address space can be divided into 0GB-4GB and 4GB-8GB. The first address space can be the address space corresponding to 0GB-4GB, and the second address space can be the address space above 4GB. For another example, if the physical address space is 16GB, the physical address space can be divided into 0GB-4GB and 4GB-16GB. The first address space can be the address space corresponding to 0GB-4GB, and the second address space can be the address space above 4GB. Based on this, when creating a multi-level memory page table, corresponding multi-level memory page tables can be created for the first address space and the second address space, respectively. The first address space is primarily used as a memory address space, while the second address space can be used as at least an I / O address space. The memory address space is used to describe the storage location of programs and data in memory, while the I / O address space is used to describe the address range of the physical machine's I / O devices. For example, the physical address space is typically divided into several different address ranges. The address space in the 0-4GB address range is referred to as the first address space, and the address space in the 4GB-16GB address range is referred to as the second address space. The first address space is often referred to as "base memory" or "system memory." It includes the memory used by the host operating system, applications, and basic hardware drivers. This means the first address space is primarily used as a memory address space. The second address space is often referred to as "bulk memory" or "extended memory." This type of memory is typically used in high-performance computers, servers, and workstations to support more complex computing tasks and multitasking. For example, the second address space can be used as at least 10 memory addresses. Specifically, for the first address space, a first mapping relationship between the client physical address and the host physical address is formed at a first page granularity, that is, the client physical address and the host physical address are mapped according to the page size of the first page granularity, and a multi-level memory page table corresponding to the first address space is created according to the first mapping relationship; for the 10 address space in the second address space, a second mapping relationship between the client physical address and the host physical address is formed at a second page granularity, that is, the client physical address and the host physical address are mapped according to the page size of the second page granularity, and a multi-level memory page table corresponding to the 10 address space is created according to the second mapping relationship; the second page granularity is larger than the first page granularity, for example, the first page granularity is 2M, and the second page granularity is 1G.Using the first page granularity (small page granularity) for memory mapping can reduce internal fragmentation within memory pages, minimize memory waste, and reduce cache page table entry losses, thereby improving address translation efficiency. Using the second page granularity (large page granularity) for memory mapping can reduce page table entry data, reduce the number of memory page table levels, reduce memory management overhead, and improve the performance of physical computing resource objects. Furthermore, the second address space can optionally be used as a memory address space. Based on this, the virtualization layer 30 can also form a third mapping relationship between client physical addresses and host physical addresses at a third page granularity for the memory address space in the second address space. Specifically, the mapping between client physical addresses and host physical addresses is performed according to the page size of the third page granularity, and a multi-level memory page table corresponding to the memory address space is created based on the third mapping relationship. The third page granularity is smaller than the second page granularity, but the size of the third page granularity is not limited. In an optional embodiment, the third page granularity can be equal to the first page granularity. For example, the first and third page granularities are both 2MB. That is, for the memory address space, a smaller page granularity can be used for address space mapping, while for the 1MB address space, a larger page granularity can be used for address space mapping. This can effectively utilize the physical address space and improve memory management performance. Furthermore, in some application scenarios, the memory address space in the second address space includes APIC pages. The APIC pages use a smaller page granularity, such as the fourth page granularity, and the third page granularity is larger than the fourth page granularity.For example, if the third page granularity is 2M and the fourth page granularity is 4Ko, and the memory address space in the second address space includes an APIC page of the fourth page granularity, this means that the APIC page of the fourth page granularity belongs to a physical page of the third page granularity. The physical page of the third page granularity to which the APIC page of the fourth page granularity belongs is referred to as the first physical page. Then, the first physical page of the third page granularity to which the APIC page belongs and the target memory page table corresponding to the first physical page can be obtained. The target memory page table corresponding to the first physical page is the last-level page table in the multi-level memory page table, and the page table entry in the page table points to the address space in the first physical page. To adapt to the page granularity of the APIC page, the first physical page can be split into multiple sub-pages of the fourth page granularity, and a next-level memory page table is further extended below the target memory page table, that is, a next-level memory page table is added below the target memory page table. The next-level memory page table is used to store the host physical addresses of the multiple split sub-pages. For example, each page table entry in the next-level memory page table stores the host physical address corresponding to a sub-page. The host physical address is the first address of the subpage. In this embodiment, when creating a memory page table, a hybrid mapping granularity approach combining the first, second, third, and fourth page granularities is adopted. This approach supports both small and large page granularities, meeting the requirements of different physical page mappings and improving the flexibility of memory mapping. Furthermore, in the non-root mode provided by the embodiments of the present disclosure, when creating a memory page table, the host's physical address space is no longer restricted. Memory page tables can be created for the entire physical address space, thus supporting full memory mapping. Therefore, memory page tables can be created for both user-mode pages and kernel-mode pages. By supporting memory mapping of the entire physical address space, a basic framework is provided for various subsequent operations based on memory mapping. For example, when performing memory swapping based on memory mapping, swapping of both user-mode pages and kernel-mode pages is supported, i.e., full memory swapping is supported. In this embodiment, the specific process of creating a memory page table is exemplified by taking the first page granularity of 2M, the second page granularity of 1G, the third page granularity of 2M, the fourth page granularity of 4K, and the multi-level memory page table implemented as a four-level memory page table as an example.The following is an example of a four-level memory page table. The four-level memory page table includes: Page Global Directory (PGD), Page Upper Directory (PUD), Page Middle Directory (PMD) and Page Table Entry (PTE). Among them, PGD is the highest level directory. PGD includes multiple global page directory entries pgd_t, each pgd_t can map a 512G host physical address (HPA), and pgd_t points to the next level page directory (PUD); PUD includes multiple upper page directory entries pud_t, each pud_t can map a 1G host physical address (HPA), and pud_t points to the next level page directory (PMD); PMD includes multiple intermediate page directory entries pmd_t, each pmd_t can map a 2M host physical address (HPA), and pmd_t points to the next level page directory (PTE). PTE includes multiple direct page directory entries pte_t, each pte_t can map a 4K host physical address (HPA), and each pte_t points to the corresponding physical page in the host physical address (HPA).

[0051] 1) For the first address space in the 0-4GB address range, a first mapping relationship between guest physical addresses and host physical addresses is established at a 2MB page granularity. A multi-level memory page table corresponding to the first address space is created based on the first mapping relationship. a1. Based on the guest physical address (GPA) in the first address space and the index value of the PGD corresponding to the guest physical address (GPA), a page table entry pgd_t in the PGD-level page table is determined. pgd_t points to the PUD-level page table. b2. Based on the flag bit in pgd_t, a determination is made as to whether a PUD-level page table exists. If not, a page is allocated as the PUD-level page table. cl. If a PUD-level page table exists, determine whether the PUD-level page table needs to be expanded based on the first page granularity (e.g., 2MB). Since each pud_t can map a 1GB host physical address (HPA), and 1GB is larger than the first page granularity (e.g., 2MB), it is determined that the next-level PMD-level page table needs to be expanded to prepare for subsequent mapping. dl. Based on the index value of the PUD corresponding to the guest physical address (GPA), determine the page table entry pud_t in the PUD-level page table. This pud_t points to the PMD-level page table. el. Based on the flag bit in the pud_t, determine whether the next-level PMD-level page table exists. If not, request a page as the PMD-level page table. fl. Based on the first page granularity (e.g., 2MB), determine whether the PMD-level page table needs to be expanded. Since each pmd_t can map a 2MB host physical address (HPA), it is determined that the next-level PTE-level page table does not need to be expanded. gl. Based on the PMD index value corresponding to the guest physical address (GPA), determine the page table entry pmd_to in the PMD-level page table. hl. When the mapped page granularity is 2MB, directly create a page table entry pmd_t in the PMD-level page table. pmd_t points to the physical page of the host physical address (HPA), and the physical page size is 2MB. Therefore, it is necessary to assemble a page table entry pmd_t for the PMD-level page table. pmd_t may include the physical page frame number (PFN) corresponding to the corresponding HPA. This page table entry is set to accessible, and the large page flag is set to 1. For example, a large page can be a physical page with a size of 2M or 1G, and a physical page with a size of 4K does not belong to a large page.i1. Fill the combined PMD-level page table entry pmd_t into the PMD-level page table, completing a mapping of the first page granularity (e.g., 2MB). The mapping completion progress and the next client physical address to be mapped are recorded until a mapping of the first page granularity (e.g., 2MB) is established for the first address space. j1. Determine whether the mapping of the first page granularity (e.g., 2MB) is completed. If not, return to step b. Otherwise, terminate.

[0052] 2) For the input / output (IO) address space in the second address space, a second mapping relationship between the client physical address and the host physical address is formed at a second page granularity, and a multi-level memory page table corresponding to the IO address space is created based on the second mapping relationship. That is, based on the address space (i.e., physical memory space and physical IO space) of the host operating system recorded in the IO memory resource (iomem_resource), a multi-level memory page table of a second page granularity (e.g., 1G granularity) is established for the IO address space (e.g., memory address space of 4G or more) in the second address space. The process of establishing the multi-level memory page table is similar to the above-mentioned implementation method of establishing the multi-level memory page table at the first page granularity, with the difference being that: to establish the multi-level memory page table at the second page granularity (e.g., 1G granularity), it is necessary to establish pud_t in the PUD-level page table, where pud_t points to the physical page of the host physical address (HPA), and the size of the physical page is 1G.

[0053] 3) For the memory address space in the second address space, a third mapping relationship between the guest physical address and the host physical address is formed at a third page granularity (e.g., 2MB). A multi-level memory page table corresponding to the memory address space is created based on the third mapping relationship. The third page granularity is smaller than the second page granularity. The process of establishing the multi-level memory page table can be found in the aforementioned implementation of establishing the multi-level memory page table at the first page granularity and is not further described here.

[0054] 4) When the memory address space includes an APIC page of the fourth page granularity, obtain the first physical page of the third page granularity to which the APIC page belongs and the target memory page table corresponding to the first physical page; split the first physical page into multiple sub-pages of the fourth page granularity, and add a next-level memory page table under the target memory page table. The next-level memory page table is used to store the host physical addresses of the multiple split sub-pages.

[0055] 5) Apply for a special APIC page. The physical address of the APIC page is the client physical address.

[0056] 6) Establish a mapping between the host physical address of the APIC and the fourth page granularity (e.g., 4k granularity) of this special APIC page. The default host physical base address of the APIC (APIC_DEFAULT_PHYS_BASE) is

[0057] (OxfeeOOOOO), this physical address corresponds to the memory address space in the second memory space. This process involves splitting the already established third page granularity (e.g., 2MB granularity). The mapping process is as follows: a2. Execute steps a1-e1 in step 1) sequentially. Based on the fourth page granularity (e.g., 4KB), determine whether the PMD-level page table needs to be expanded. Since each pmd_t can map a 2MB host physical address (HPA), and 2MB is not equal to 4KB, it is determined that the next-level PTE-level page table needs to be expanded. b2. Based on the index value of the PTE corresponding to the guest physical address (GPA), determine the page table entry pte_t in the PTE-level page table. The contents of pte_t are assembled, including the physical page frame number corresponding to the HPA, and the page table entry is set to accessible. In this case, the large page flag is not set. c2. Fill the page table entry content of the combined PTE-level page table into the corresponding pte_t to complete this mapping.

[0058] S2. Creating the Information Carrying Object Required for Mode Switching. In this embodiment, to perform mode switching for the host operating system, a physical descriptor structure is created for any physical computing resource object 101, as shown in step S21 in Figure 3c. The physical descriptor structure may be referred to as pcpu in subsequent descriptions. This physical descriptor structure is used to store context information for any physical computing resource object operating in root mode during mode switching. The context information for any physical computing resource object in root mode may include, but is not limited to, the values ​​of various registers used by the physical computing resource object, the state information of the physical computing resource object, host state information, and related configuration information. Relevant configuration information includes, but is not limited to, the frequency of the High Voltage (HV) timer. In this embodiment, the implementation of the physical descriptor structure is not limited; any implementation structure that can store context information for a physical computing resource object operating in root mode is applicable to the disclosed embodiments. In an optional embodiment, the physical descriptor structure may include, but is not limited to, the following parts or fields: a first register structure (regs), a field carrying status information of the physical computing resource object, a field carrying status information of the host machine, and a field carrying configuration information. The first register structure may include, but is not limited to, general register fields, debug register fields, stack-related register fields, floating-point (fpu) register fields, and model-specific register (MSR) fields. To perform mode switching for the host operating system, a virtualization descriptor structure is created for any physical computing resource object, as shown in step S22 in Figure 3c. The virtualization descriptor structure may be referred to as vcpu in the subsequent description. The virtualization descriptor structure is used to synchronize context information in the physical descriptor structure during mode switching. This virtualization descriptor structure represents a virtual computing resource object obtained by virtualizing the physical computing resource object. The implementation of the virtualization descriptor structure is not limited, and any implementation structure that can synchronize the context information in the physical computing resource object is applicable to the embodiments of the present disclosure.In an optional embodiment, the vcpu may include but is not limited to the following fields: a second register structure (regs) corresponding to the first register structure. In addition, the vcpu further includes: a field carrying a virtual computing resource object identification instruction (e.g., cpu-id), a field carrying an interrupt vector number (apic-id), a field carrying the running status of the vcpu, a field carrying a switch flag indicating a state change during a vcpu switch process, a field carrying relevant configuration information of an APIC register, a field carrying configuration information of a specific model register (e.g., an MSR register), a field carrying configuration information of a processor opcode (e.g., CPUID), a field carrying a descriptor of a Program Interrupt ion (PI), and a field carrying configuration information related to an exit event. Furthermore, to switch the host operating system's mode, a virtualization control structure is created for any physical computing resource object, as shown in step S230 in FIG3c . For example, the virtualization control structure can be implemented as vmcs (Virtual Machine Control System). The virtualization control structure is used to store the operating state information and operating control information of any physical computing resource object in non-root mode. For example, the operating state information of the physical computing resource object in non-root mode may include the values ​​of certain registers and the state of the physical computing resource object, such as active, halted (HLT), or shutdown. Operation control information primarily refers to control information for the host operating system in non-root mode. For example, the operation control information stored in the virtualization control structure may include, but is not limited to, the following fields: fields for non-root mode exit events, fields for specific processor model register bitmaps (msr_bitmap), fields for APIC virtualization, fields for interrupt virtualization, fields for preemption timers, fields for clock configuration, or fields for I / O control information. The information in these fields can be configured as needed when initializing the virtualization control structure, depending on actual circumstances. In an optional embodiment, the virtualization layer 30 may also create an I / O bitmap (io_bitmap), as shown in step S24o in FIG. 3c . The I / O bitmap is used to record the access rights of any physical computing resource object to various I / O ports in non-root mode. The access rights are related to the I / O control information in the operation control information. The access rights can default to 0, meaning that access to all I / O ports is permitted. If partial I / O needs to be intercepted later, the io_bitmap can be configured as needed.oFurthermore, the virtualization layer 30 may also create a new stack. For ease of description and distinction, this new stack is referred to as the first stack, as shown in step S25 in Figure 3c. The new stack (i.e., the first stack) is relative to the old stack. For ease of description and distinction, the old stack is referred to as the second stack. The old stack (i.e., the second stack) is the stack currently used by any physical computing resource object. After switching from root mode to non-root mode, any physical computing resource object will continue to use the old stack to operate in non-root mode. For purposes of illustration, after switching from root mode to non-root mode, a physical computing resource object can be implemented as a virtual physical computing resource object. For example, a physical CPU can be implemented as a virtual CPU. The first stack is a stack prepared for the virtualization layer 30 and is used by the virtualization layer 30 to perform memory access in root mode based on the new stack (i.e., the first stack). In an optional embodiment, the virtualization layer 30 may also initialize the virtualization descriptor structure and the virtualization control structure, as shown in step S26 in Figure 3c. The initialization process involves enabling required functions, allocating memory pages for the required functions, and configuring initial values. The initialization process for the virtualization descriptor structure may include adding initialization information corresponding to the functions to be enabled to the corresponding fields of the virtualization descriptor structure. The initialization process for the virtualization control structure may include adding initialization information corresponding to the functions to be enabled to the corresponding fields of the virtualization control structure. Optionally, the virtualization layer 30 may configure, in the virtualization control structure, operation control information for any physical computing resource object when running in non-root mode. For example, the operation control information may include, but is not limited to, at least one of: MSR control information, PI control information, APIC control information, hardware register operation instruction information, memory page table entry address, and configuration information related to exiting non-root mode.Further optionally, when configuring the operation control information, the virtualization layer 30 is specifically configured to perform at least one of the following configuration operations: a3, establishing a specific model register bitmap (e.g., msr_bitmap) and allocating a second physical page for storing the bitmap; b3, setting the PI interrupt function and setting the PI notification vector; c3, setting the APIC interrupt control function, allocating a third physical page for storing the APIC table from the physical address space, and storing the base address of the page where the APIC table is located in the APIC field; in addition, it is also necessary to set APICJD to the apic_id of the current physical computing resource object (e.g., CPU), and the APIC Local Vector Register (APIC_LVR) inherits the settings of the current physical computing resource object (e.g., CPU); if the APIC timer is intercepted, the timer configuration and processing function may also be configured; d3, setting the processor opcode (e.g., CPUID), and establishing a cache for the virtual computing resource object; e3, setting the PAUSE-Loop Exiting (PLE), PLE configuration is used to reduce the waste of virtual computing resources caused by loop waits. f3. Save the entry address of the multi-level memory page generated in step S1 in the virtualization control structure. The RIP instruction location executed after exiting non-root mode must also be set. g3. Configure the default general registers for root and non-root modes. The process of initializing each virtualization descriptor structure and virtualization control structure is as follows:

[0059] 1) Load each virtualization descriptor structure (vcpu) in sequence and initialize each vcpu structure;

[0060] 2) Load the virtualization control structure (vines) corresponding to the vcpu as the current vines:

[0061] 3) For the current vines configuration operation control information, ie, perform steps a3 to g3 above;

[0062] 4) Clear the current vines structure; 5) Determine whether the vCPU to be initialized has been initialized. If not, repeat steps 1) to 4). If initialization is complete, terminate initialization. As can be seen from the above, switching the host operating system's mode involves switching from physical computing resource objects to virtual computing resource objects, as well as context information synchronization, access control for I / O operations, and memory access switching. Therefore, physical descriptor structures corresponding to physical computing resource objects and virtualized descriptor structures corresponding to virtual computing resource objects are created to synchronize context information during the mode switching process. A I / O bitmap is created to facilitate access control for I / O operations during the mode switching process, and a first stack is created to facilitate memory access switching by the virtualization layer 30 during the mode switching process. After creating a memory page table and various information-carrying objects, the foundation for mode switching is established. Based on this foundation, the running host operating system can be switched from root mode to non-root mode based on the information-carrying objects and memory page table.

[0063] S3. Switching the running host operating system from root mode to non-root mode based on the information carrier object and the memory page table. In this embodiment, mode switching can be performed for any physical computing resource object, and the mode switching process for each physical computing resource object is the same. For ease of description and distinction, the following explanation uses mode switching for a target physical computing resource object as an example. The target physical computing resource object can be any physical computing resource object. As shown in Figure 3d, the process of mode switching for the target physical computing resource object includes the following: Step S31: When performing a mode switch for the target physical computing resource object, save the context information of the target physical computing resource object in root mode to the physical descriptor structure corresponding to the target physical computing resource object. Step S32: Synchronize the register values ​​and segment register configuration information in the context information in the physical descriptor structure to the virtualization descriptor structure and virtualization control structure corresponding to the target physical computing resource object. Step S33: Based on the virtualization descriptor structure, the virtualization control structure, and the memory page table, control the operation of the target physical computing resource object to switch the running host operating system from root mode to non-root mode. For example, the values ​​of each register in the context information in the physical descriptor structure are synchronized to the virtualization descriptor structure corresponding to the target physical computing resource object, and the configuration information of the segment registers in the context information in the physical descriptor structure is synchronized to the virtualization control structure corresponding to the target physical computing resource object. The segment register configuration information may include, but is not limited to, the segment size, the segment start address, and the segment management attributes. For example, the segment management attributes may include: write-prohibited, execute-prohibited, or system-only. In this embodiment, steps S1 and S2 may be executed when the virtualization layer 30 is started or initialized, and step S3 may be executed on demand based on dynamic requirements (external instructions). Whether to switch the mode of the target physical computing resource object may be determined by the external instructions. In an optional embodiment, the host operating system 20 of this embodiment provides a symmetric multi-processing (SMP) call interface, allowing an external user to send an SMP call request to any physical computing resource object on the physical machine. The SMP call request indicates a need to switch the mode of the physical computing resource object. For ease of distinction and description, the following example uses sending an SMP call request to a target physical computing resource object as an example.For example, an upper-layer application running on the host operating system 20 can initiate an SMP call request to the target physical computing resource object, or a developer can initiate an SMP call request to the target physical computing resource object through the host operating system 20. Upon receiving the SMP call request, the target physical computing resource object can initiate a call request to a switch function to trigger a mode switch. Accordingly, the virtualization layer 30 provides a switch function (e.g., the switch_vcpu function) for the host operating system to perform a mode switch. The target physical computing resource object executes the switch function to switch the host operating system from root mode to non-root mode. Specifically, the switch function involves saving the context information of the target physical computing resource object in root mode to the physical descriptor structure corresponding to the target physical computing resource object, and subsequent operations (e.g., steps S32 and S33) to switch the mode of the physical computing resource object. After entering non-root mode, the virtualization layer 30 can also control the target physical computing resource object to exit from non-root mode to root mode when an exit event configured in the virtualization control structure occurs. In an optional embodiment, during the mode switch process, before saving context information, a determination can be made as to whether the switch flag corresponding to the target physical computing resource object is in the pending switching state. If so, the switch flag is updated to the switching-in-progress state. For example, the target physical computing resource object can obtain the switch flag status. If the switch flag is in the unswitched state (e.g., VMXJ3FF), the switch flag is updated to the switching-in-progress state (e.g., VMX_SWITCH). If the switch flag is in the switch-completed state (e.g., VMXJ3N), the SMP call is directly returned without performing a mode switch. Optionally, other finishing steps can be performed after returning to the SMP call. The virtualization layer 30 can also configure the first instruction after first entering non-root mode as the entry point address of the switch function. The switch function is divided into an upper half and a lower half. For example, the switch function can be entered through a function entry point such as switch_vcpu. As the host operating system switches between different modes, the code path after entering the switch function will vary.For the first switch from root mode to non-root mode, an SMP call can be initiated to the target physical computing resource object to trigger the mode switch. The call first checks the state of the switch flag. If it is determined to be in the pending state, the mode switch is triggered, and the first half of the switch function is entered. In this first half, the switch flag is set to the switching-in-progress state (e.g., VMX_SWITCH) and the first instruction to be executed after entering non-root mode, i.e., the entry address of the switch function, is set. Subsequently, the first half of the switch function executes the operation to switch the host operating system from root mode to non-root mode. After the target physical computing resource object enters non-root mode, it executes the first instruction set above. This first instruction is the execution of the switch function. At this point, the flag is already set to the switching-in-progress state. The call then enters the second half of the switch function, where the switch is completed and the SMP call is returned. Optionally, for ease of distinction and description, the stack currently used by the target physical computing resource object (i.e., before switching to non-root mode) is referred to as the second stack. When the virtualization layer 30 saves the context information of the target physical computing resource object in root mode into the physical descriptor structure corresponding to the target physical computing resource object, it is specifically configured to: save the values ​​of each register in the context information and the top and bottom addresses of the second stack into the physical descriptor structure. For example, the values ​​of each register in the context information may be saved into the physical descriptor structure, specifically by saving the control register, segment register, and general register into the register structure in the physical descriptor structure, and saving the top and bottom addresses of the second stack into the corresponding stack fields of the host register in the physical descriptor structure (pcpu), which will be used in subsequent mode switching. The virtualization layer 30 may also switch the second stack currently used by the target physical computing resource object to the newly created first stack, so that the virtualization layer 30 continues to operate based on the first stack in root mode. Further, optionally, the virtualization layer 30, based on the virtualization descriptor structure, The virtualization control structure and memory page table control the runtime of the target physical computing resource object. Specifically, they are used to load the values ​​of the dedicated registers in the virtualization control structure and virtualization descriptor structure. Dedicated registers are a set of registers with specific functions and are accessed and used by specific instructions or hardware modules. Examples include the PI register, debug register (DR) register, MSR register, or segment register. Furthermore, they can save the segment registers of the PCPU and load the values ​​of the segment registers in the VCPU.The execution control information in the virtualization control structure is injected into the target physical computing resource object, and the values ​​of the general registers in the virtualization descriptor structure are loaded. General registers are a set of registers available to developers for storing general information such as data and addresses. General registers can be accessed and used by any instruction in the program. For example, pointer registers or index registers can be accessed and used by any instruction in the program. Loading the corresponding register values ​​means loading the register values ​​stored in the vCPU into specific hardware registers to enable the target physical computing resource object to run in non-root mode. A mode switch instruction is executed to control the target physical computing resource object to enter non-root mode and start running from the first instruction. During operation, memory management and access are performed based on the memory page table. Further optionally, after switching the running host operating system from root mode to non-root mode, the virtualization layer 30 may also restore the second stack to the addresses of the top and bottom of the stack saved in the physical descriptor structure, and update the switching flag to a switching completion state (e.g., VMX_0N). In this case, after switching from root mode to non-root mode, the second stack (i.e., the old stack) is restored to the addresses of the top and bottom of the stack saved in the physical descriptor structure, so that the target physical computing resource object continues to run based on the second stack in non-root mode. In the embodiments of the present disclosure, hardware virtualization is utilized to insert a lightweight virtualization layer between the host operating system and hardware resources. The virtualization layer implements the virtual resource provision function. The virtualization layer switches the running host operating system from root mode to non-root mode, thereby providing at least one virtual resource in non-root mode and running at least one application on the at least one virtual resource. The at least one application includes at least one application that the host operating system cannot run in root mode due to insufficient resources. Without reinstalling the host operating system, the virtual resource provision function can be flexibly implemented for the running host operating system, resolving the issue of applications being unable to run in root mode due to insufficient resources caused by the lack of enabled or missing relevant system functions. This allows the host operating system to support the running of more applications, thereby expanding the capabilities of the host operating system. After the host operating system switches from root mode to non-root mode, the at least one application that can be run on the virtual resources provided in non-root mode includes, but is not limited to, memory management, file management, virtualization, scheduling optimization, and other target functions in non-root mode. In the following embodiments, memory page fault management in memory management is taken as an example to describe the memory page fault management process in non-root mode in detail.One application scenario for memory page faults is memory swapping. That is, memory page faults may occur during the memory swapping process, but memory page faults are not limited to memory swapping. To illustrate the advantages of memory page fault management implemented in non-root mode in the present disclosure, this article will use memory page faults for memory swapping as an example, and first introduce memory swapping. The memory swap function in a host operating system (e.g., Linux) is a mechanism that uses free hard disk space as memory expansion. When the main memory (e.g., RAM) is running low on memory pages, the swap function can move some infrequently used memory pages to the hard disk to free up space for other pages. This process is called page swapping. When a process uses the swapped-out content again, it triggers a page swapping. The swap function of a host operating system (e.g., Linux) consists of two aspects: the swap partition and the swap file. The swap partition is used to exchange hard disk space and is also called swap space. Swap partitions are typically allocated when the host operating system is installed. You can also create a swap partition manually using commands such as fdisk or mkswap. After allocating free disk space as a swap partition, you can mount it as a swap partition using the swapon command. Swap partitions offer advantages such as speed and stability, but they require pre-planned partition sizes and cannot be dynamically adjusted. The fdisk command is used to create, delete, modify, and display disk partitions. The mkswap command is used to create swap partitions. The swapon command is used to enable swap partitions on a physical machine. A swap file is a file created on a regular file system that can be used as swap space. Use commands such as dd or f allocate to create a swap file, then use the mkswap command to format it as a swap file system, and finally use the swapon command to mount it as swap space. Both the dd and fallocate commands can be used to create files. Swap files offer advantages such as high flexibility, dynamic resizing, and ease of management, but their performance is slightly inferior to that of swap partitions. In host operating systems (such as Linux), the swap space size is typically set to two or three times the physical memory. If there is sufficient physical memory, swap space usage will be low and will not significantly affect physical machine performance. If there is insufficient physical memory, swap space usage will be high and will seriously affect physical machine performance.Therefore, the performance of swap space is crucial to the stability of physical machine performance. Furthermore, the swap feature of the host operating system kernel (such as Linux) is for user processes and does not directly affect the swapping of kernel pages. If memory is insufficient, the kernel will attempt to reclaim some unnecessary pages and swap them to disk through the swap function to free up memory space. These unnecessary pages include user process pages, cache pages, anonymous memory pages, etc., but not kernel pages, as kernel pages are generally not swappable. Kernel code and data are typically locked in memory and not swapped to disk, so they are not affected by the swap function. Furthermore, the swap function currently only supports small 4KB pages. Large page sizes (such as 2MB or 1GB) are increasingly used in cloud computing scenarios, but large page swap is not yet supported. If the running operating system does not have swap configured, enabling it online can only use the file method, which has very low performance and seriously affects system stability. Although some system functions missing from the host operating system can be implemented by loading functional modules, this approach is invasive and subject to the constraints of the operating system's existing structures and functions. Furthermore, it may not address all issues, such as the kernel-mode page swapping mentioned above. In the disclosed embodiments, a virtualization layer is used to switch from root mode to non-root mode, providing virtual memory resources in non-root mode to enable memory swapping, freeing it from the constraints of whether the host operating system has memory swap enabled. Furthermore, the solutions provided by the disclosed embodiments are more transparent, imperceptible to upper-layer applications, and enable more comprehensive functionality. Furthermore, in the disclosed embodiments, a hybrid mapping granularity approach combining first, second, third, and fourth page granularities is adopted when creating memory page tables. This approach supports both small and large page granularities, meeting the requirements of different physical page mappings and improving memory mapping flexibility. Using small page granularity for memory mapping can reduce internal fragmentation in memory pages and reduce memory waste; using large page granularity for memory mapping can reduce page table entry data, reduce the level of memory page tables, reduce memory management overhead, and improve the performance of physical computing resource objects.Furthermore, in the disclosed embodiments, memory page table creation is no longer restricted to the host machine's physical address space. Memory page tables can be created for the entire physical address space, supporting full memory mapping. Therefore, memory page tables can be created for both user-mode and kernel-mode pages. Supporting memory mapping for the entire physical address space provides a foundational framework for subsequent memory mapping-based operations. For example, memory swapping based on memory mapping supports swapping not only user-mode pages but also kernel-mode pages, i.e., full memory swapping. The following briefly describes the process of implementing memory page fault management after switching to non-root mode.

[0064] 1) The memory page tables (e.g., the ept page tables) prepared for mode switching in the host operating system have a one-to-one correspondence between guest physical addresses (GPAs) and host physical addresses (HPAs). Normal operation in non-root mode does not trigger page faults. To extend the host operating system's memory management capabilities, some memory pages (with a granularity of 4KB or 2MB) can be reclaimed by methods such as reclaiming free pages, compressing used pages, swapping memory pages to disk, or expanding new virtual memory space. The corresponding page table entries are then cleared. This allows subsequent accesses in non-root mode to trigger page faults. Currently, a page fault can be triggered by directly clearing the memory page tables for a batch of free pages.

[0065] 2) Since a batch of memory pages have been cleared and recycled in step 1), a simple memory management system can be used, for example, using status bits to manage memory for subsequent page fault exceptions.

[0066] 3) Before performing page fault exception handling, you can set a processing function in the exit event of non-root mode, for example, set the page fault handling function associated with the exit reason EPT page fault (EXIT_REASON_EPT_VIOLATION)

[0067] (ept_handler).

[0068] 4) In the page fault handling function (ept_handler), an unused host physical page can be selected from the underlying memory management system and marked as used.

[0069] 5) A mapping relationship is established between the physical address (HPA) of the unused host physical page and the guest physical address (GPA) of the page fault. A corresponding page table entry is created in the corresponding memory page table (e.g., the ept page table). This enables the host operating system to implement memory management in non-root mode. Memory management here includes, but is not limited to, memory swapping. It should be noted that the execution entity of each step of the method provided in the above embodiment can be the same device, or the method can be executed by different devices. For example, steps R11 to R12 can be executed by device A; for another example, steps R11 and R12 can be executed by device A, and step R13 can be executed by device B; and so on. In addition, some processes described in the above embodiments and accompanying figures include multiple operations that appear in a specific order. However, it should be understood that these operations may be executed in a different order than the order in which they appear herein or in parallel. Operation sequence numbers, such as steps R11 to R12, are merely used to distinguish between different operations and do not represent any specific execution order. Furthermore, these processes may include more or fewer operations, and these operations may be executed sequentially or in parallel. It should be noted that terms such as "first" and "second" are used herein to distinguish between different messages, devices, modules, etc., and do not imply a sequential order, nor do they limit "first" and "second" to different types. FIG4 is a schematic structural diagram of an address translation device provided in an exemplary embodiment of the present disclosure. As shown in FIG4 , the device includes a construction module 41, a determination module 42, a query module 43, and a generation module 44. A construction module 41 is configured to pre-construct a first RMAP table corresponding to an EPT, where the EPT includes a multi-level page table corresponding to at least one GPA. The first RMAP table stores address information of a last-level page table entry corresponding to at least one GPA. A determination module 42 is configured to respond to a first address translation trigger event and determine a first GPA requiring address translation. A query module 43 is configured to query the first RMAP table for address information of a last-level page table entry corresponding to the first GPA. A generation module 44 is configured to, upon finding address information of the last-level page table entry corresponding to the first GPA, generate an HPA corresponding to the first GPA based on the address information of the last-level page table entry corresponding to the first GPA and an address offset of the first GPA. OIn an optional embodiment, the construction module is further configured to pre-build a second RMAP table corresponding to the EPT, the second RMAP table storing address translation information from at least one HPA to a corresponding GPA. The determination module is further configured to, in response to a second address translation trigger event, determine a first HPA requiring address translation and query the second RMAP table for address translation information from the first HPA to the corresponding GPA. The generation module is further configured to generate a GPA corresponding to the first HPA based on the first HPA, its address translation information to the corresponding GPA, and the address offset of the first HPA. In an optional embodiment, the construction module is further configured to: divide the GPA address space corresponding to the EPT into at least one address space, create a basic structure for each of the at least one address space, the basic structure corresponding to a set page table level; for any GPA in the EPT, determine a first structure corresponding to the GPA from each of the basic structures based on the address information of the GPA and the address space corresponding to each of the basic structures; and record address information of the last-level page table entry corresponding to the GPA in the first structure based on the relationship between the last-level page table level corresponding to the GPA and the set page table level. Optionally, the construction module is specifically used to: if the level of the last-level page table corresponding to any GPA is the same as the set page table level, then add the address information of the last-level page table entry corresponding to any GPA to the information field in the first structure, and set the flag information in the first structure to a first value; if the level of the last-level page table corresponding to any GPA is different from the set page table level, then create a second structure adapted to the level of the last-level page table corresponding to any GPA, add the address information of the last-level page table entry corresponding to any GPA to the information field in the second structure, add the address information of the second structure to the information field in the first structure, and set the flag information in the first structure to a second value. Further optionally, the construction module is specifically used to: when the level of the last-level page table corresponding to any GPA is the previous level of the set page table level, determine whether the second structure already exists; if not, create a new structure adapted to the level of the last-level page table corresponding to any GPA as the second structure; when the level of the last-level page table corresponding to any GPA is the next level of the set page table level, create a new structure adapted to the level of the last-level page table corresponding to any GPA as the second structure.In an optional embodiment, the construction module is specifically configured to: divide the HPA address space corresponding to the EPT into at least one address space, create a basic structure for each of the at least one address space, where the basic structure corresponds to a set page granularity; determine, for an HPA corresponding to any GPA in the EPT, a third structure corresponding to any HPA from each of the basic structures based on address information of the HPA and the address space corresponding to each of the basic structures; and record, in the third structure, address translation information from any HPA to the corresponding GPA based on a relationship between the page granularity corresponding to any HPA and the set page granularity. Optionally, the construction module is specifically configured to: if the page granularity corresponding to any HPA is the same as the set page granularity, record address translation information from any HPA to the corresponding GPA through the information field in the third structure, and set the first flag information in the third structure to a third value; if the page granularity corresponding to any HPA is different from the set page granularity, create a fourth structure adapted to the page granularity of any HPA, record address translation information from any HPA to the corresponding GPA through the information field in the fourth structure, add the address information of the fourth structure to the information field in the third structure, and set the first flag information in the third structure to a fourth value. Further optionally, the construction module is specifically configured to: when any HPA corresponds to multiple GPAs, create a fifth structure, add address information of the fifth structure to the information field of the third structure, add address translation information from any HPA to multiple GPAs to the fifth structure, and add a flag indicating a one-to-many relationship to the third structure; when any HPA corresponds to one GPA, directly add address translation information from any HPA to the corresponding GPA to the information field of the third structure; the construction module is specifically configured to: when any HPA corresponds to multiple GPAs, create a sixth structure, add address information of the sixth structure to the information field of the fourth structure, add address translation information from any HPA to multiple GPAs to the sixth structure, and add a flag indicating a one-to-many relationship to the fourth structure; when any HPA corresponds to one GPA, directly add address translation information from any HPA to the corresponding GPA to the information field of the fourth structure.In an optional embodiment, the query module is specifically configured to: determine, from the basic structures, a first structure corresponding to the first GPA based on the address information of the first GPA and the address space corresponding to each basic structure included in the first RMAP table, the first structure corresponding to the set page table level; and obtain, using the first structure corresponding to the first GPA, the address information of the last-level page table entry corresponding to the first GPA. Optionally, the query module is specifically configured to: obtain flag information from the first structure; if the flag information is a first value, obtain the address information of the last-level page table entry corresponding to the first GPA from an information field in the first structure; if the flag information is a second value, obtain the address information of a second structure from the information field in the first structure, and, based on the address information of the second structure, obtain the address information of the last-level page table entry corresponding to the first GPA from the information field in the second structure. In an optional embodiment, the following modules are further included: an adding module, configured to, when a second GPA is added to the EPT, add address information of a last-level page table entry corresponding to the second GPA to the first RMAP table; a deleting module, configured to, when a third GPA is deleted from the EPT, delete address information of the last-level page table entry corresponding to the third GPA from the first RMAP table; a modifying module, configured to, when the first address information of the last-level page table corresponding to the fourth GPA is modified in the EPT to the second address information, modify first address information of the last-level page table corresponding to the fourth GPA in the first RMAP table to the second address information; an expanding module, configured to, when the last-level page table is expanded to a next-level page table in the EPT, modify address information of last-level page table entries corresponding to respective GPAs in the last-level page table to address information of the corresponding next-level page table in the first RMAP table; and a shrinking module, configured to, when the last-level page table with continuous addresses in the EPT is shrunk to an previous-level page table, modify address information of last-level page table entries corresponding to respective GPAs in the last-level page table to address information of the previous-level page table entry in the first RMAP table. Optionally, the adding module is specifically configured to: determine, from each basic structure, a first structure corresponding to the second GPA according to the address information of the second GPA and the address space corresponding to each basic structure included in the first RMAP table, where the first structure corresponds to the set page table level; if it is determined that the address information of the last-level page table entry corresponding to the second GPA is not recorded through the first structure, then, based on the relationship between the level of the last-level page table corresponding to the second GPA and the set page table level, record the address information of the last-level page table entry corresponding to the second GPA through the first structure.Optionally, the deletion module is specifically configured to: determine, from the basic structures, a first structure corresponding to the third GPA based on the address information of the third GPA and the address space corresponding to each basic structure included in the first RMAP table, where the first structure corresponds to a set page table level; if the level of the last-level page table corresponding to the third GPA matches the page table level indicated by the flag information of the first structure, then, based on a relationship between the level of the last-level page table corresponding to the third GPA and the set page table level, delete the address information of the last-level page table entry corresponding to the third GPA through the first structure. Optionally, the extension module is specifically configured to: clear, in the EPT, address information recorded in each page table entry in the last-level page table, and clear address information of the last-level page table entries corresponding to each GPA in the last-level page table in the first RMAP table; create a next-level page table corresponding to the last-level page table, record address information of the next-level page table in a page table entry of the last-level page table, and record a base address of a physical page corresponding to a corresponding HPA in a page table entry of the next-level page table; and record, in the first RMAP table, address information of the next-level page table entries corresponding to each GPA in the last-level page table through a first structure according to a relationship between the level of the next-level page table and the set page table level. Optionally, the shrink module is specifically configured to: clear the address information recorded in each page table entry in the last-level page table with continuous addresses in the EPT, and clear the address information of the last-level page table entries corresponding to each GPA in the last-level page table in the first RMAP table; create a previous-level page table corresponding to the last-level page table, and record the address information of the physical pages corresponding to the corresponding HPAs in the page table entries of the previous-level page table; and record the address information of the previous-level page table entries corresponding to each GPA in the last-level page table in the first RMAP table via a first structure based on the relationship between the level of the previous-level page table and the set page table level. In an optional embodiment, the execution body of the device is a virtualization manager in a host operating system (OS); or, the execution body of the device is a virtualization layer between the host OS and host hardware resources, the virtualization layer being configured to switch the running host OS from root mode to non-root mode.The present disclosure also provides a fast mapping table construction device, as shown in FIG5 . The device includes: a partitioning module 51 for partitioning the GPA address space corresponding to the EPT into at least one address space; a creation module 52 for creating a basic structure for each of the at least one address space, wherein the basic structure corresponds to a set page table level. The EPT includes a multi-level page table corresponding to at least one GPA; a determination module 53 for determining, for any GPA in the EPT, from each of the basic structures based on the address information of the GPA and the address space corresponding to each of the basic structures, a first structure corresponding to any GPA; and a recording module 54 for recording, based on the relationship between the level of the last-level page table corresponding to any GPA and the set page table level, the address information of the last-level page table entry corresponding to any GPA in a first structure, thereby constructing a first RMAP table corresponding to the EPT. The first RMAP table stores the address information of the last-level page table entry corresponding to at least one GPA. The detailed implementation and beneficial effects of each step in the device shown in FIG4 and FIG5 according to the present disclosure have been described in detail in the previous embodiments and will not be elaborated on here. FIG6 is a schematic diagram of the structure of a physical machine provided by an exemplary embodiment of the present disclosure. This physical machine is also referred to as an address translation device. As shown in FIG6 , the device includes a memory 64 and a processor 65. Memory 64 is used to store computer programs and can be configured to store various other data to support operations on the address translation device. Examples of such data include instructions for any application or method operating on the address translation device. Processor 65, coupled to memory 64, is configured to execute the computer program in memory 64 to: pre-build a first RMAP table corresponding to an EPT, where the EPT includes a multi-level page table corresponding to at least one GPA; the first RMAP table stores address information of a last-level page table entry corresponding to at least one GPA; in response to a first address translation trigger event, determines a first GPA requiring address translation, queries the first RMAP table for address information of a last-level page table entry corresponding to the first GPA; and, if address information of the last-level page table entry corresponding to the first GPA is found, generates an HPA corresponding to the first GPA based on the address information of the last-level page table entry corresponding to the first GPA and the address offset of the first GPA. OIn an optional embodiment, the processor 65 is further configured to: pre-build a second RMAP table corresponding to the EPT, the second RMAP table storing address translation information from at least one HPA to a corresponding GPA; in response to a second address translation trigger event, determine a first HPA requiring address translation, query the second RMAP table for address translation information from the first HPA to a corresponding GPA; and generate a GPA corresponding to the first HPA based on the first HPA, its address translation information to the corresponding GPA, and the address offset of the first HPA. OIn an optional embodiment, when pre-building the first RMAP table corresponding to the EPT, the processor 65 is specifically configured to: divide the GPA address space corresponding to the EPT into at least one address space, create a basic structure for each of the at least one address space, where the basic structure corresponds to a set page table level; for any GPA in the EPT, determine a first structure corresponding to the GPA from each of the basic structures based on address information of the GPA and the address space corresponding to each of the basic structures; and record address information of a last-level page table entry corresponding to the GPA in the first structure based on a relationship between the level of the last-level page table corresponding to the GPA and the set page table level. Optionally, when the processor 65 records the address information of the last-level page table entry corresponding to any GPA through the first structure according to the relationship between the level of the last-level page table corresponding to any GPA and the set page table level, it is specifically configured to: if the level of the last-level page table corresponding to any GPA is the same as the set page table level, add the address information of the last-level page table entry corresponding to any GPA to the information field in the first structure, and set the flag information in the first structure to the first value; if the level of the last-level page table corresponding to any GPA is different from the set page table level, create a second structure adapted to the level of the last-level page table corresponding to any GPA, add the address information of the last-level page table entry corresponding to any GPA to the information field in the second structure, add the address information of the second structure to the information field in the first structure, and set the flag information in the first structure to the second value. Further optionally, when creating the second structure adapted to the level of the last-level page table corresponding to any GPA, the processor 65 is specifically configured to: when the level of the last-level page table corresponding to any GPA is one level above the set page table level, determine whether the second structure already exists; if not, create a new structure adapted to the level of the last-level page table corresponding to any GPA as the second structure; when the level of the last-level page table corresponding to any GPA is one level below the set page table level, create a new structure adapted to the level of the last-level page table corresponding to any GPA as the second structure.In an optional embodiment, when pre-building the second RMAP table corresponding to the EPT, the processor 65 is specifically configured to: divide the HPA address space corresponding to the EPT into at least one address space, create a basic structure for each of the at least one address space, where the basic structure corresponds to a set page granularity; determine, for an HPA corresponding to any GPA in the EPT, a third structure corresponding to each HPA from each basic structure based on address information of the HPA and the address space corresponding to each basic structure; and record, in the third structure, address translation information from any HPA to the corresponding GPA based on a relationship between the page granularity corresponding to the HPA and the set page granularity. Optionally, when recording the address translation information from any HPA to the corresponding GPA through the third structure based on the relationship between the page table level corresponding to any HPA and the set page table level, the processor 65 is specifically configured to: if the page granularity corresponding to any HPA is the same as the set page granularity, record the address translation information from any HPA to the corresponding GPA through the information field in the third structure, and set the first flag information in the third structure to a third value; if the page granularity corresponding to any HPA is different from the set page granularity, create a fourth structure adapted to the page granularity of any HPA, record the address translation information from any HPA to the corresponding GPA through the information field in the fourth structure, add the address information of the fourth structure to the information field in the third structure, and set the first flag information in the third structure to a fourth value.Further optionally, when recording the address translation information from any HPA to the corresponding GPA through the information field in the third structure, the processor 65 is specifically configured to: if any HPA corresponds to multiple GPAs, create a fifth structure, add the address information of the fifth structure to the information field in the third structure, add the address translation information from any HPA to the multiple GPAs to the fifth structure, and add a flag indicating a one-to-many relationship to the third structure; if any HPA corresponds to one GPA, directly add the address translation information from any HPA to the corresponding GPA to the information field in the third structure; accordingly, when recording the address translation information from any HPA to the corresponding GPA through the information field in the fourth structure, the processor 65 is specifically configured to: if any HPA corresponds to multiple GPAs, create a sixth structure, add the address information of the sixth structure to the information field in the fourth structure, add the address translation information from any HPA to the multiple GPAs to the sixth structure, and add a flag indicating a one-to-many relationship to the fourth structure; if any HPA corresponds to one GPA, The address translation information from any HPA to the corresponding GPA is directly added to the information field in the fourth structure. In an optional embodiment, when the processor 65 queries the first RMAP table for the address information of the last-level page table entry corresponding to the first GPA, the processor 65 is specifically configured to: determine, from the base structures, a first structure corresponding to the first GPA based on the address information of the first GPA and the address space corresponding to each base structure included in the first RMAP table, where the base structure corresponds to the set page table level; and obtain, using the first structure corresponding to the first GPA, the address information of the last-level page table entry corresponding to the first GPA. Optionally, when the processor 65 obtains the address information of the last-level page table entry corresponding to the first GPA through the first structure corresponding to the first GPA, the processor 65 is specifically configured to: obtain flag information from the first structure; if the flag information is a first value, obtain the address information of the last-level page table entry corresponding to the first GPA from the information field in the first structure; if the flag information is a second value, obtain the address information of the second structure from the information field in the first structure, and obtain the address information of the last-level page table entry corresponding to the first GPA from the information field in the second structure based on the address information of the second structure.In an optional embodiment, the processor 65 is further configured to perform at least one of the following operations: when a second GPA is added to the EPT, adding address information of a last-level page table entry corresponding to the second GPA to the first RMAP table; when a third GPA is deleted from the EPT, deleting address information of the last-level page table entry corresponding to the third GPA from the first RMAP table; when first address information of a last-level page table corresponding to a fourth GPA is modified to second address information in the EPT, modifying first address information of the last-level page table corresponding to the fourth GPA in the first RMAP table to second address information; when a last-level page table is expanded to a next-level page table in the EPT, modifying address information of last-level page table entries corresponding to respective GPAs in the last-level page table in the first RMAP table to address information of the corresponding next-level page table; and when a last-level page table with continuous addresses in the EPT is shrunk to an upper-level page table, modifying address information of last-level page table entries corresponding to respective GPAs in the last-level page table in the first RMAP table to address information of the upper-level page table entry. In an optional embodiment, when the processor 65 adds the address information of the last-level page table entry corresponding to the second GPA to the first RMAP table, the processor 65 is specifically configured to: determine, from the basic structures, a first structure corresponding to the second GPA based on the address information of the second GPA and the address space corresponding to each basic structure included in the first RMAP table, where the first structure corresponds to the set page table level; and if it is determined that the address information of the last-level page table entry corresponding to the second GPA is not recorded through the first structure, record the address information of the last-level page table entry corresponding to the second GPA through the first structure based on the relationship between the level of the last-level page table corresponding to the second GPA and the set page table level. In an optional embodiment, when deleting the address information of the last-level page table entry corresponding to the third GPA from the first RMAP table, the processor 65 is specifically configured to: determine, from the basic structures, a first structure corresponding to the third GPA based on the address information of the third GPA and the address space corresponding to each basic structure included in the first RMAP table, where the first structure corresponds to the set page table level; and if the level of the last-level page table corresponding to the third GPA matches the page table level indicated by the flag information of the first structure, delete the address information of the last-level page table entry corresponding to the third GPA through the first structure based on the relationship between the level of the last-level page table corresponding to the third GPA and the set page table level.In an optional embodiment, when the processor 65 expands the last-level page table into a next-level page table in the EPT, and modifies the address information of the last-level page table entry corresponding to each GPA in the last-level page table to the address information of the corresponding next-level page table in the first RMAP table, the processor 65 is specifically configured to: clear the address information recorded in each page table entry in the last-level page table in the EPT, and clear the address information of the last-level page table entry corresponding to each GPA in the last-level page table in the first RMAP table; create a next-level page table corresponding to the last-level page table, record the address information of the next-level page table in the page table entry of the last-level page table, and record the base address of the physical page corresponding to the corresponding HPA in the page table entry of the next-level page table; and record, in the first RMAP table, the address information of the next-level page table entry corresponding to each GPA in the last-level page table according to the relationship between the level of the next-level page table and the set page table level, using the first structure. In an optional embodiment, when the last-level page table with consecutive addresses in the EPT is shrunk to the previous-level page table, the processor 65 modifies the address information of the last-level page table entry corresponding to each GPA in the last-level page table to the address information of the previous-level page table entry in the first RMAP table. The processor 65 is specifically configured to: clear the address information recorded in each page table entry in the last-level page table with consecutive addresses in the EPT, and clear the address information of the last-level page table entry corresponding to each GPA in the last-level page table in the first RMAP table; create a previous-level page table corresponding to the last-level page table, and record the address information of the physical page corresponding to the corresponding HPA in the page table entry of the previous-level page table; and record the address information of the previous-level page table entry corresponding to each GPA in the last-level page table in the first RMAP table according to the relationship between the level of the previous-level page table and the set page table level through the first structure. In an alternative embodiment, the processor 65 performs the above operations via a virtualization manager in the host operating system (OS); alternatively, the processor 65 performs the above operations via a virtualization layer between the host OS and the host hardware resources, where the virtualization layer is used to switch the running host OS from root mode to non-root mode. The detailed implementation and beneficial effects of each step in the device shown in FIG. 6 according to the embodiments of the present disclosure have been described in detail in the previous embodiments and will not be elaborated upon here. Furthermore, as shown in FIG. 6 , the address translation device also includes: a communication component 66, a display 67, a power supply component 68, an audio component 69, and other components. FIG. 6 only schematically illustrates some components and does not mean that the address translation device only includes the components shown in FIG. Furthermore, the components within the dashed boxes in FIG. 6 are optional, not mandatory, and may depend on the product form factor of the address translation device.The address translation device of this embodiment can be implemented as a terminal device such as a desktop computer, laptop computer, smartphone, or IoT device, or as a server-side device such as a conventional server, cloud server, or server array. If the address translation device of this embodiment is implemented as a terminal device such as a desktop computer, laptop computer, or smartphone, it may include the components within the dashed box in Figure 6 . If the address translation device of this embodiment is implemented as a server-side device such as a conventional server, cloud server, or server array, it may not include the components within the dashed box in Figure 6 . The disclosed embodiments also provide a fast mapping construction device. The implementation structure of this fast mapping construction device is the same as or similar to the implementation structure of the fast mapping construction device shown in Figure 6 , and can be implemented with reference to the structure of the fast mapping construction device shown in Figure 6 . The fast mapping construction device provided in this embodiment differs from the fast mapping construction device in the embodiment shown in Figure 6 primarily in that the functions implemented by the processor executing the computer program stored in the memory are different. In the address translation device provided in this embodiment, its processor executes a computer program stored in a memory, which is configured to: divide the GPA address space corresponding to the memory page table (EPT) into at least one address space; create a basic structure for each of the at least one address space, wherein the basic structure corresponds to a set page table level; the EPT includes a multi-level page table corresponding to each of the at least one GPA; determine, for any GPA in the EPT, a first structure corresponding to the GPA from each of the basic structures based on the address information of the GPA and the address space corresponding to each of the basic structures; and record the address information of the last-level page table entry corresponding to the GPA in the first structure based on the relationship between the level of the last-level page table corresponding to the GPA and the set page table level, thereby constructing a first RMAP table corresponding to the EPT. The first RMAP table stores the address information of the last-level page table entry corresponding to each of the at least one GPA. The detailed implementation and beneficial effects of the fast mapping construction device provided in the embodiments of the present disclosure have been described in detail in the aforementioned embodiments and will not be elaborated upon here. Accordingly, embodiments of the present disclosure further provide a computer-readable storage medium storing a computer program. When executed, the computer program can implement the steps in the method embodiments shown in Figures 4 and 5 . Embodiments of the present disclosure further provide a computer program product, including a computer program / instructions. When executed by a processor, the computer program / instructions causes the processor to implement the steps in the methods shown in Figures 4 and 5 .The aforementioned memory can be implemented by any type of volatile or non-volatile memory device, or a combination thereof, such as static random-access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, a magnetic disk, or an optical disk. The aforementioned communication component is configured to facilitate wired or wireless communication between the device containing the communication component and other devices. The device containing the communication component can access a wireless network based on a communication standard, such as WiFi, 2G, 3G, 4G / LTE, 5G, or other mobile communication networks, or a combination thereof. In an exemplary embodiment, the communication component receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, the communication component also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID), infrared data association (IrDA), ultra-wideband (UWB), Bluetooth (BT), and other technologies. The aforementioned display includes a screen, which may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, it can be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, slides, and gestures on the touch panel. The touch sensors can not only detect the boundaries of a touch or slide action, but also the duration and pressure associated with the touch or slide action. The aforementioned power supply component provides power to the various components of the device in which the power supply component is located.The power supply component may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the device in which the power supply component resides. The aforementioned audio component may be configured to output and / or input audio signals. For example, the audio component may include a microphone (MIC) configured to receive external audio signals when the device in which the audio component resides is in an operating mode, such as call mode, recording mode, or voice recognition mode. The received audio signals may be further stored in a memory or transmitted via a communication component. In some embodiments, the audio component also includes a speaker for outputting audio signals. Those skilled in the art will appreciate that embodiments of the present disclosure may be provided as methods, systems, or computer program products. Therefore, the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to magnetic disk storage, compact disc read-only memory (CD-ROM), optical storage, etc.) containing computer-usable program code. The present disclosure is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each process flow and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, such that the instructions, when executed by the processor of the computer or other programmable data processing device, produce a device for implementing the functions specified in one or more processes in the flowcharts and / or one or more blocks in the block diagrams. These computer program instructions can also be stored in a computer-readable memory capable of directing the computer or other programmable data processing device to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means that implement the functions specified in one or more processes in the flowcharts and / or one or more blocks in the block diagrams.These computer program instructions can also be loaded onto a computer or other programmable data processing device, causing the computer or other programmable device to execute a series of operational steps to produce a computer-implemented process. The instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more flow charts and / or one or more blocks in the block diagrams. In a typical configuration, a computing device includes one or more processors (Central Processing Units, CPUs), input / output interfaces, network interfaces, and memory. Memory may include non-volatile memory in the form of computer-readable media, random access memory (RAM), and / or non-volatile memory, such as read-only memory (ROM) or flash memory. Memory is an example of computer-readable media. Computer-readable media, including both permanent and non-permanent, removable and non-removable media, can implement information storage using any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change random access memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices, or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media does not include transitory media such as modulated data signals and carrier waves. It should also be noted that the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, commodity, or apparatus that includes a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity, or apparatus.In the absence of further limitations, elements defined by the phrase "comprising a..." do not preclude the presence of other identical elements in the process, method, product, or device comprising the elements. The foregoing are merely examples of the present disclosure and are not intended to limit the present disclosure. Those skilled in the art will readily appreciate that various modifications and variations of the present disclosure are possible. Any modifications, equivalent substitutions, improvements, and the like made within the spirit and principles of the present disclosure are intended to be encompassed by the claims of the present disclosure.

Claims

49 Claims 1. An address translation method, wherein: include: Pre-building a first fast mapping table corresponding to a memory page table, wherein the memory page table includes at least one multi-level page table corresponding to each client physical address; The first fast mapping table stores address information of a last-level page table entry corresponding to each of the at least one client physical addresses; in response to a first address translation trigger event, determining a first client physical address requiring address translation, and querying the first fast mapping table for address information of a last-level page table entry corresponding to the first client physical address; If the address information of the last-level page table entry corresponding to the first client physical address is queried, the host physical address corresponding to the first client physical address is generated according to the address information of the last-level page table entry corresponding to the first client physical address and the address offset of the first client physical address.

2. The method according to claim 1, wherein: Also includes: A second quick mapping table corresponding to the memory page table is pre-constructed, wherein the second quick mapping table stores address translation information from at least one host physical address to a corresponding client physical address; in response to a second address translation trigger event, a first host physical address requiring address translation is determined, and address translation information from the first host physical address to the corresponding client physical address is queried in the second quick mapping table; and a client physical address corresponding to the first host physical address is generated based on the first host physical address, the address translation information from the first host physical address to the corresponding client physical address, and the address offset of the first host physical address.

3. The method according to claim 1 or 2, wherein: Pre-constructing a first quick mapping table corresponding to a memory page table, including: dividing the address space of the client physical address corresponding to the memory page table into at least one address space, creating a basic structure for each of the at least one address space, and the basic structure corresponding to the set page table level; for any client physical address in the memory page table, determining a first structure corresponding to the any client physical address from each of the basic structures according to the address information of the any client physical address and the address space corresponding to each of the basic structures; recording the address information of the last-level page table entry corresponding to the any client physical address through the first structure according to the relationship between the level of the last-level page table corresponding to the any client physical address and the set page table level.

4. The method according to claim 3, wherein: According to the relationship between the level of the last-level page table corresponding to any client physical address and the set page table level, the address information of the last-level page table entry corresponding to any client physical address is recorded through the first structure, including: if the level of the last-level page table corresponding to any client physical address is the same as the set page table level, the address information of the last-level page table entry corresponding to any client physical address is added to the information field in the first structure, and the flag information in the first structure is set to the first value; if the level of the last-level page table corresponding to any client physical address is different from the set page table level, a second structure adapted to the level of the last-level page table corresponding to any client physical address is created, and the address information of the last-level page table entry corresponding to any client physical address is added to the information field in the second structure 50, and add the address information of the second structure to the information field in the first structure, and set the flag information in the first structure to a second value.

5. The method according to claim 4, wherein: Creating a second structure adapted to the level of the last-level page table corresponding to any one of the client physical addresses, including: when the level of the last-level page table corresponding to any one of the client physical addresses is the previous level of the set page table level, determining whether the second structure already exists; if not, creating a new structure adapted to the level of the last-level page table corresponding to any one of the client physical addresses as the second structure; when the level of the last-level page table corresponding to any one of the client physical addresses is the next level of the set page table level, creating a new structure adapted to the level of the last-level page table corresponding to any one of the client physical addresses as the second structure.

6. The method according to claim 2, wherein: Pre-constructing a second fast mapping table corresponding to a memory page table includes: dividing an address space of a host physical address corresponding to the memory page table into at least one address space, creating a basic structure for each of the at least one address space, wherein the basic structure corresponds to a set page granularity; for a host physical address corresponding to any client physical address in the memory page table, determining a third structure corresponding to the any host physical address from each of the basic structures based on address information of the any host physical address and the address space corresponding to each of the basic structures; and recording address conversion information from the any host physical address to the corresponding client physical address through the third structure based on a relationship between the page granularity corresponding to the any host physical address and the set page granularity.

7. The method according to claim 6, wherein: According to the relationship between the corresponding page table level and the set page table level in any host physical address, the address conversion information from any host physical address to the corresponding client physical address is recorded through the third structure, including: if the page granularity corresponding to any host physical address is the same as the set page granularity, the address conversion information from any host physical address to the corresponding client physical address is recorded through the information field in the third structure, and the first flag information in the third structure is set to a third value; if the page granularity corresponding to any host physical address is different from the set page granularity, a fourth structure adapted to the page granularity of the any host physical address is created, the address conversion information from any host physical address to the corresponding client physical address is recorded through the information field in the fourth structure, the address information of the fourth structure is added to the information field in the third structure, and the first flag information in the third structure is set to a fourth value.

8. The method according to claim 7, wherein: Recording the address translation information of any host physical address to the corresponding client physical address through the information field in the third structure includes: when any host physical address corresponds to multiple client physical addresses, creating a fifth structure, adding the address information of the fifth structure to the information field in the third structure, and adding the address translation information of any host physical address to multiple client physical addresses to the fifth structure respectively, and in the 51. Adding a flag bit indicating a one-to-many relationship to the third structure; when any host physical address corresponds to one client physical address, directly adding address translation information from any host physical address to the corresponding client physical address to the information field in the third structure; correspondingly, recording the address translation information from any host physical address to the corresponding client physical address through the information field in the fourth structure, including: when any host physical address corresponds to multiple client physical addresses, creating a sixth structure, adding the address information of the sixth structure to the information field in the fourth structure, and adding the address translation information from any host physical address to the multiple client physical addresses to the sixth structure respectively; adding a flag bit indicating a one-to-many relationship to the fourth structure; when any host physical address corresponds to one client physical address, directly adding the address translation information from any host physical address to the corresponding client physical address to the information field in the fourth structure. Based on the address information of the first client physical address and the address spaces corresponding to the basic structures included in the first quick mapping table, a first structure corresponding to the first client physical address is determined from the basic structures, where the basic structure corresponds to a set page table level; and address information of a last-level page table entry corresponding to the first client physical address is obtained through the first structure corresponding to the first client physical address.

10. The method according to claim 9, wherein: Obtaining address information of a last-level page table entry corresponding to the first client physical address through a first structure corresponding to the first client physical address, including: obtaining flag information from the first structure; if the flag information is a first value, obtaining address information of the last-level page table entry corresponding to the first client physical address from an information field in the first structure; if the flag information is a second value, obtaining address information of a second structure from the information field in the first structure, and obtaining address information of the last-level page table entry corresponding to the first client physical address from the information field of the second structure based on the address information of the second structure.

11. The method according to any one of claims 1-2 and 4-10, wherein: The method further includes at least one of the following operations: adding address information of a last-level page table entry corresponding to a second client physical address in the first fast mapping table when the second client physical address is newly added to the memory page table; When the third client physical address is deleted from the memory page table, address information of the last-level page table entry corresponding to the third client physical address is deleted from the first fast mapping table; In the case where the first address information of the last level page table corresponding to the fourth client physical address is modified to the second address information in the memory page table, the last level page table corresponding to the fourth client physical address is modified to the second address information in the first fast mapping table.

52. Modify the first address information of the next-level page table to the second address information; when the last-level page table in the memory page table is expanded to the next-level page table, modify the address information of the last-level page table entry corresponding to each client physical address in the last-level page table in the first quick mapping table to the address information of the next-level page table; when the last-level page table with continuous addresses in the memory page table is shrunk to the previous-level page table, clear the address information of the last-level page table entry in the first quick mapping table, and add the address information of the previous-level page table entry corresponding to each client physical address in the last-level page table.

12. The method according to claim 11, wherein: Adding the address information of the last-level page table entry corresponding to the second client physical address in the first quick mapping table includes: determining a first structure corresponding to the second client physical address from each basic structure according to the address information of the second client physical address and the address space corresponding to each basic structure included in the first quick mapping table, wherein the first structure corresponds to a set page table level; if it is determined that the address information of the last-level page table entry corresponding to the second client physical address is not recorded through the first structure, then recording the address information of the last-level page table entry corresponding to the second client physical address through the first structure according to the relationship between the level of the last-level page table corresponding to the second client physical address and the set page table level.

13. The method according to claim 11, wherein: Deleting the address information of the last-level page table entry corresponding to the third client physical address in the first quick mapping table includes: determining a first structure corresponding to the third client physical address from each basic structure according to the address information of the third client physical address and the address space corresponding to each basic structure contained in the first quick mapping table, the first structure corresponding to the set page table level; if the level of the last-level page table corresponding to the third client physical address is compatible with the page table level indicated by the flag information of the first structure, deleting the address information of the last-level page table entry corresponding to the third client physical address through the first structure according to the relationship between the level of the last-level page table corresponding to the third client physical address and the set page table level.

14. The method according to claim 11, wherein: In the case where the last-level page table in the memory page table is expanded to the next-level page table, the address information of the last-level page table entry corresponding to each client physical address in the last-level page table is modified in the first fast mapping table to the address information of the next-level page table, including: clearing the address information recorded in each page table entry in the last-level page table in the memory page table, and clearing the address information of the last-level page table entry corresponding to each client physical address in the last-level page table in the first fast mapping table; creating a next-level page table corresponding to the last-level page table, recording the address information of the next-level page table in the page table entry of the last-level page table, and recording the base address of the physical page corresponding to the corresponding host physical address in the page table entry of the next-level page table; in the first fast mapping table, according to the relationship between the level of the next-level page table and the set page table level, The structure records the address information of the next-level page table entry corresponding to each client physical address in the last-level page table.

15. The method according to claim 11, wherein: When a last-level page table with continuous addresses in the memory page table is shrunk to an upper-level page table, address information of the last-level page table entries is cleared in the first fast mapping table, and address information of the upper-level page table entries corresponding to each client physical address in the last-level page table is added, including: clearing address information recorded in each page table entry in the last-level page table with continuous addresses in the memory page table, and clearing address information of the last-level page table entries corresponding to each client physical address in the last-level page table in the first fast mapping table; creating an upper-level page table corresponding to the last-level page table in the memory page table, and recording base addresses of physical pages corresponding to corresponding host physical addresses in page table entries of the upper-level page table according to the page granularity corresponding to the upper-level page table entries; clearing address information of the last-level page table entries in the first fast mapping table, and recording address information of the upper-level page table entries corresponding to each client physical address in the last-level page table through a first structure according to a relationship between the level of the upper-level page table and a set page table level.

16. The method according to any one of claims 1-2, 4-10, 12-15, wherein: The method is performed by a virtualization manager in a host operating system (OS); or, the method is performed by a virtualization layer between the host OS and host hardware resources, the virtualization layer being used to switch a running host OS from root mode to non-root mode.

17. A method for constructing a fast mapping table, wherein: include: The address space of the client physical address corresponding to the memory page table is divided into at least one address space, and a basic structure is created for each of the at least one address space, wherein the basic structure corresponds to a set page table level, and the memory page table includes a multi-level page table corresponding to at least one client physical address; for any client physical address in the memory page table, a first structure corresponding to the any client physical address is determined from each of the basic structures according to the address information of the any client physical address and the address space corresponding to each of the basic structures; according to the relationship between the level of the last-level page table corresponding to the any client physical address and the set page table level, the address information of the last-level page table entry corresponding to the any client physical address is recorded through the first structure to construct a first quick mapping table corresponding to the memory page table, wherein the first quick mapping table stores the address information of the last-level page table entry corresponding to the at least one client physical address.

18. A physical machine, wherein: include: memory and processor; The memory is used to store computer programs; The processor, coupled to the memory, is configured to execute the computer program to implement the steps in the method of any one of claims 1-16 and claim 17.

19. A computer-readable storage medium storing a computer program, wherein: When the computer program is executed by a processor, the processor is caused to implement the steps of the method according to any one of claims 1 to 16 and claim 17.

20. A computer program product comprising a computer program / instructions, wherein: When the computer program / instructions are executed by a processor, the processor is caused to implement the steps of the method according to any one of claims 1 to 16 and claim 17.

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