Decoding device

Abstract

A decoding device for use in coherent digital signal processing, comprising: a distributor for distributing, to each of a first through d-th lanes (where d is an integer of 2 or more), a decoding metric obtained by demodulating transmission data transmitted from a transmission device, on the basis of information of noise occurring in a communication path and a received signal; (d-1) decoding units for decoding the outputs of first likelihood calculation units disposed in the first lane to the d-th lane, and feeding back the decoding results to all the first likelihood calculation units disposed in the lower-numbered lanes; and a second likelihood calculation unit for making a hard decision on the basis of the output of the first likelihood calculation unit provided in the d-th lane.　

Description

Decryption device

[0001] The present invention relates to a decoding device.

[0002] In optical transmission, the trade-off between power consumption and decoding performance is important for forward error correction (FEC). Optical transmission networks for data centers use short-length linear codes and soft-decision decoding methods with low computational complexity, such as Chase 2 decoding. However, the performance of low-complexity decoding of short-length linear codes is limited by the code length.

[0003] In response to this, a configuration using CP-MLC (Channel-polarized multilevel coding) has been proposed in recent years (see, for example, Non-Patent Document 1). The CP-MLC method can improve the decoding performance limit for low-overhead, short-code-length linear codes.

[0004] T. Kakizaki et al., “Improved Performance-complexity Trade-offs for Soft-decision Decoding by Channel-polarized Multilevel Coding”, ECOC2023.

[0005] However, when the overhead is high, the CP-MLC method has a problem in that performance is degraded due to an error floor.

[0006] In view of the above circumstances, an object of the present invention is to provide a technique that can improve decoding performance when using a short code length linear code.

[0007] One aspect of the present invention is a decoding device used in coherent digital signal processing, comprising: a distributor that distributes decoding metrics obtained by demodulating transmission data transmitted from a transmitting device based on information about noise generated in a communication channel and a received signal to each of the first to dth lanes (d is an integer greater than or equal to 2); (d-1) decoding units that decode the outputs of first likelihood calculation units arranged in the first to dth lanes and feed back the decoding results to first likelihood calculation units arranged in all lower lanes; and a second likelihood calculation unit that makes hard decisions based on the output of the first likelihood calculation unit arranged in the dth lane.

[0008] The present invention makes it possible to improve decoding performance when using short code length linear codes.

[0009] Fig. 1 is a block diagram showing an example of the configuration of a transmitting device in an embodiment. Fig. 2 is a block diagram showing an example of the configuration of a receiving device in an embodiment. Fig. 3 is a block diagram showing an example of the configuration of a decoding circuit in an embodiment. Fig. 4 is a diagram showing the results of a comparison experiment to evaluate the decoding performance between a method using the conventional CP-MLC method shown in Non-Patent Document 1 and a method in an embodiment.

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0011] 1 is a block diagram showing an example of the configuration of a transmitting device 1 according to an embodiment. The transmitting device 1 is part of a digital coherent communication system and is a transmitting device used to transmit data to be transmitted (hereinafter referred to as "transmission data"). The transmitting device 1 transmits the transmission data to a receiving device connected via a communication path. The communication path is assumed to be, for example, an AWGN (Additive White Gaussian Noise) communication path.

[0012] The transmitting device 1 includes a coding circuit 10, a symbol mapper 11, and a transmitting unit 12. The coding circuit 10 has, for example, a short code length linear code as an element code. The coding circuit 10 is configured with an HD-FEC coding unit 110, a 1:d converter 120, an SD-FEC coding unit 130, a bit conversion circuit 140, and a d:1 converter 150.

[0013] Data to be transmitted is input to the HD-FEC encoding unit 110. The HD-FEC encoding unit 110 encodes the input data to be transmitted using HD-FEC (Hard-Decision FEC) technology. The data to be transmitted obtained by encoding is referred to as data z. The HD-FEC encoding unit 110 outputs data z to the 1:d converter 120.

[0014] The 1:d converter 120 divides the data z output from the HD-FEC encoding unit 110 into a predetermined division number d (d is an integer equal to or greater than 2). As a result, the data z is divided into d pieces. Hereinafter, the divided data z will be referred to as divided data z （１）´ , z （２）´ ,…, z （ｄ） The 1:d converter 120 converts the divided data z （１）´ , z （２）´ ,…, z （ｄ） are output to the first lane to the dth lane, respectively.

[0015] The 1:d converter 120 may include a bit interleaver for bit interleaving. However, the total bit length of the (d-1) lanes from the first lane to the (d-1)th lane is nR ＳＤ (d-1) / d, n represents an arbitrary constant, and R ＳＤ denotes the rate of the SD-FEC code.

[0016] The SD-FEC encoding unit 130 is provided on the first lane to the (d-1)th lane, and encodes the divided data z （１）´ , z （２）´ ,…, z （ｄ－１）´ The SD-FEC encoding unit 130 encodes the divided data z （１） , z （２） ,…, z （ｄ－１） The SD-FEC encoding unit 130 obtains the obtained divided data z （１） , z （２） ,…, z （ｄ－１） to the bit conversion circuit 140. In this way, the SD-FEC encoding unit 130 converts the divided data z（ｄ） is not encoded using error correction codes.

[0017] The bit conversion circuit 140 is a conversion circuit that converts a bit sequence into another bit sequence using exclusive OR. Specifically, the bit conversion circuit 140 converts the divided data z （ｄ） For example, the bit conversion circuit 140 converts the divided data z output from the SD-FEC encoding unit 130 to the first lane into （１） and the divided data z output from the 1:d converter 120 to the d-th lane. （ｄ） Similarly, the bit conversion circuit 140 performs an exclusive OR on the divided data z output from the SD-FEC encoding unit 130 to the second lane. （２） and the divided data z output from the 1:d converter 120 to the d-th lane. （ｄ） The exclusive OR is taken with

[0018] The bit conversion circuit 140 performs the above-described process on the divided data z output to each lane from the first lane to the (d-1)th lane. （１） , z （２） ,…, z （ｄ－１） The bit conversion circuit 140 converts the divided data z （１） , z （２） ,…, z （ｄ－１） and the divided data z output from the 1:d converter 120 to the d-th lane. （ｄ） The bit conversion circuit 140 outputs the result of the exclusive OR operation with the input divided data z （ｄ） is output to the d:1 converter 150 as is.

[0019] The d:1 converter 150 converts the divided data z transmitted in the first to d-th lanes into （１） , z （２） ,…, z （ｄ） The d:1 converter 150 converts the 1-lane series data into 1-lane series data by parallel-to-serial conversion. The d:1 converter 150 outputs the 1-lane series data to the symbol mapper 11.

[0020] The symbol mapper 11 generates transmission data by assigning gray labeling to the data of the one-lane series output from the d:1 converter 150. The symbol mapper 11 outputs the generated transmission data to the transmitter 12.

[0021] The transmitter 12 transmits the transmission data generated by the symbol mapper 11 .

[0022] 2 is a block diagram showing an example of the configuration of a receiving device 2 according to an embodiment. The receiving device 2 is a receiving device used in a digital coherent communication system. The receiving device 2 receives transmission data transmitted from a transmitting device 1 connected via a communication path.

[0023] The receiving device 2 includes a receiving unit 20 , a symbol demapper 21 , and a decoding circuit 22 .

[0024] The receiving unit 20 receives the transmission data transmitted from the transmitting device 1 via a communication path.

[0025] The symbol demapper 21 demodulates the transmission data received by the receiver 20 based on the channel information and the received signal using a demodulation method corresponding to the modulation method, and obtains a decoding metric. The decoding metric is, for example, a log-likelihood ratio (LLR). The channel information represents the distribution of noise in the channel. The channel information can be measured using a spectrum analyzer or the like. It is assumed that the channel information is measured in advance and stored in the likelihood calculation unit 230, which will be described later.

[0026] The decoding circuit 22 decodes the transmission data based on the decoding metric obtained by the symbol demapper 21. Specifically, the decoding circuit 22 in this embodiment applies multi-stage decoding, sequentially decoding from the higher lane, and feeds back the decoded results of each lane to the lower lane. For example, if the decoding circuit 22 has three lanes, the decoding circuit 22 feeds back the decoded result of the first lane to the second and third lanes, and feeds back the decoded result of the second lane to the third lane. In this way, the number of decoded results fed back from each higher lane increases as the lane advances to the lower lane. The decoding circuit 22 is one aspect of a decoding device. A specific configuration of the decoding circuit 22 will be described using FIG. 3.

[0027] 3 is a block diagram showing an example configuration of the decoding circuit 22 in this embodiment. The decoding circuit 22 is composed of a distributor 220, a plurality of likelihood calculation units 230, a plurality of SD-FEC decoding units 240, an HD likelihood calculation unit 250, a d:1 converter 260, and an HD-FEC decoding unit 270. As shown in FIG. 3, the decoding circuit 22 includes d likelihood calculation units 230-1 to 230-d and (d−1) SD-FEC decoding units 240-1 to 240-(d−1).

[0028] The distributor 220 receives the value demapped by the symbol demapper 21. The value demapped by the symbol demapper 21 is the received signal l:=(l （１） ,l （２） ,…,l （ｄ） ) The distributor 220 shares the received signal l among the first to d-th lanes. Specifically, the distributor 220 copies the same symbol to all lanes from the first to d-th lanes and shares it.

[0029] The likelihood calculation units 230-1 to 230-d are respectively provided on the first lane to the dth lane, and calculate the log-likelihood ratio for each of the first lane to the dth lane based on a value (e.g., received signal l) shared by the distributor 220 to each of the first lane to the dth lane.

[0030] The likelihood calculation unit 230-1 calculates a log-likelihood ratio based on, for example, a value (e.g., received signal l) shared by the divider 220. The likelihood calculation unit 230-2 calculates a log-likelihood ratio based on, for example, a value (e.g., received signal l) shared by the divider 220 and the decoding result output from the SD-FEC decoding unit 240-1. The likelihood calculation unit 230-d calculates a log-likelihood ratio based on, for example, a value (e.g., received signal l) shared by the divider 220 and the decoding results output from each of the SD-FEC decoding units 240-1 to 240-(d-1).

[0031] The SD-FEC decoders 240-1 to 240-(d-1) perform error correction decoding using the log-likelihood ratios calculated by the likelihood calculators 230-1 to 230-(d-1), respectively. （ｉ）´ ,^z （ｉ） is output to the d:1 converter 260 and is also fed back to each likelihood calculation unit 230 located in the lower lane. Here, "^" is a superscript of z. ^z （ｉ）´ is the information bit of the SD-FEC code, and ̂z （ｉ） is the codeword and the information bits ̂z （ｉ）´ with a parity bit attached, where i is an integer of 1 or greater.

[0032] The HD likelihood calculation unit 250 is provided on the d-th lane and performs hard decision on the log-likelihood ratio output from the likelihood calculation unit 230-d. The HD likelihood calculation unit 250 outputs the hard decision result to the d:1 converter 260.

[0033] The d:1 converter 260 converts the values ​​transmitted on each of the first to dth lanes (e.g., ̂z （１）‘ ,^z （２）‘ ,…,^z （ｄ） ) is converted into one lane of data by parallel-to-serial conversion.

[0034] The HD-FEC decoder 270 decodes the one-lane series of data output from the d:1 converter 260 using a decoding technique corresponding to the encoding performed by the HD-FEC encoder 110 .

[0035] Here, we will explain the flow of processing in the decoding circuit 22. In explaining the flow of processing in the decoding circuit 22, we will define equations (1) and (2) below.

[0036]

[0037]

[0038] The decoding circuit 22 then repeatedly executes the following processes (1) and (2) for i=1 to d: (1) Each likelihood calculation unit 230-i calculates a logarithmic likelihood ratio φ （ｉ） However, in the dth processing, φ （ｉ） Instead of Ψ （ｉ） That is, in likelihood calculation section 230-d, the log likelihood ratio Ψ （ｄ） (2): Each SD-FEC decoder 240 and HD likelihood calculator 250 calculates estimates of the information bits of each SD-FEC code, the codeword, and the bits bypassed by the encoding circuit.

[0039] The likelihood calculation unit 230-i calculates the log-likelihood ratio φ based on the input value shared by the divider 220 (for example, the received signal l). （ｉ） Here, the log likelihood ratio φ （ｉ） is expressed as the following equation (3).

[0040]

[0041] Furthermore, the process of (1) and the Ψ （ｉ） is expressed as the following equations (4) and (5).

[0042]

[0043]

[0044] When i=1, likelihood calculation unit 230-1 uses the input value shared by divider 220 (for example, received signal l) to calculate log-likelihood ratio φ based on equation (3) above. （１） The likelihood calculation unit 230-1 calculates the calculated log likelihood ratio φ （１） to the SD-FEC decoding unit 240-1.

[0045] The SD-FEC decoder 240-1 uses the log-likelihood ratio φ calculated by the likelihood calculator 230-1. （１） By performing error correction decoding using （１）´ ,^z （１） The SD-FEC decoder 240-1 obtains the decoded result ^z （１）´ is output to the d:1 converter 260, and the decoded result ^z （１） are output to likelihood calculation units 230-2 to 230-d.

[0046] Next, when i=2, the likelihood calculation unit 230-2 receives the value shared by the distributor 220 (for example, the received signal l) and the decoded result ^z output from the SD-FEC decoding unit 240-1. （１） The likelihood calculation unit 230-2 receives the input of the value shared by the divider 220 (for example, the received signal l) and the decoded result ^z （１） Using the log-likelihood ratio φ based on the above equation (3), （２） The likelihood calculation unit 230-2 calculates the calculated log likelihood ratio φ （２） to the SD-FEC decoding unit 240-2.

[0047] The SD-FEC decoder 240-2 calculates the log-likelihood ratio φ calculated by the likelihood calculator 230-2. （２） By performing error correction decoding using （２）´ ,^z （２） The SD-FEC decoder 240-2 obtains the decoded result ^z （２）´ is output to the d:1 converter 260, and the decoded result ^z （２） are output to likelihood calculation units 230-3 to 230-d.

[0048] Next, when i=d, the likelihood calculation unit 230-d receives the value shared by the distributor 220 (for example, the received signal l) and the decoding results ^z output from the SD-FEC decoding units 240-1 to 240-(d-1), respectively. （１） ,^z （２） ,…,^z （ｄ－１） The likelihood calculation unit 230-d receives the input of the value shared by the divider 220 (for example, the received signal l) and the decoding result ^z （１） ,^z （２） ,…,^z （ｄ－１）Using the log-likelihood ratio Ψ based on the above equation (5), （ｄ） The likelihood calculation unit 230-d calculates the calculated log-likelihood ratio Ψ （ｄ） to the HD likelihood calculation unit 250.

[0049] The HD likelihood calculation unit 250 calculates the log likelihood ratio Ψ calculated by the likelihood calculation unit 230-d. （ｄ） The HD likelihood calculation unit 250 performs hard decision on the error correction decoding using the hard decision result ^z ｄ to the d:1 converter 260.

[0050] The d:1 converter 260 converts the values ​​transmitted on each of the first to dth lanes (e.g., ̂z （１）‘ ,^z （２）‘ ,…,^z （ｄ） ) is converted into one-lane series data by parallel-to-serial conversion. The d:1 converter 260 outputs the one-lane series data to the HD-FEC decoding unit 270. The HD-FEC decoding unit 270 decodes the one-lane series data output from the d:1 converter 260 using a decoding technique corresponding to the encoding performed by the HD-FEC encoding unit 110.

[0051] Next, the results of a comparison experiment to evaluate the decoding performance between the method using the conventional CP-MLC scheme shown in Non-Patent Document 1 and the method in the above embodiment will be described with reference to Fig. 4. Fig. 4 is a diagram showing the results of a comparison experiment to evaluate the decoding performance between the method using the conventional CP-MLC scheme shown in Non-Patent Document 1 and the method in the embodiment.

[0052] In the evaluation experiments, OSD (Ordered Statistical Decoding) was used for the BCH code (see Reference 1). The code size was set to 20,000 for the conventional method and 1,300 for the method of this embodiment. (Reference 1: Marc. P.C. Fossorier and Shu Lin, "Soft-decision decoding of linear block codes based on ordered statistics," IEEE TRANSACTIONS ON INFORMATION THEORY, VOL. 41, NO. 5, SEPTEMBER 1995.)

[0053] In the conventional method, the element code was (127, 92, 5)-BCH, and in the embodiment (d=3), element code 1 was (127, 99, 4)-BCH, and element code 2 was (127, 106, 3)-BCH.

[0054] 4, TH represents the KP4-FEC threshold, line L1 represents the decoding performance of the conventional method, and line L2 represents the decoding performance of the method of the embodiment. The conventional method had an overhead of 22.8% (including KP4-FEC), while the method of the embodiment had an overhead of 21.5% (including KP4-FEC).

[0055] In the conventional method, the number of test patterns (number of TPs) is 20,000 or more, while in the method of the embodiment, the number of test patterns is 5,000 or less in total for element codes, and if the number of test patterns is considered to be the decoding calculation amount, the calculation amount can be reduced.

[0056] The receiving device 2 configured as described above includes a distributor 220 that distributes the decoded metrics obtained by demodulating the transmission data transmitted from the transmitting device 1 to each of the first to d-th lanes based on information about noise generated in the communication path and the received signal, an SD-FEC decoding unit 240 that decodes the outputs of likelihood calculation units 230-1 to 230-(d-1) arranged in the first to (d-1)-th lanes and feeds back the decoded results to likelihood calculation units 230 arranged in all lower lanes, and an HD likelihood calculation unit 250 that makes hard decisions based on the output of likelihood calculation unit 230-d arranged in the d-th lane.

[0057] As described above, the decoding circuit 22 performs decoding in order from the highest lane to the lowest lane and feeds back the decoded results to all lower lanes. Unlike the conventional CP-MLC method, which only feeds back to the highest lane, this method feeds back from each lane to all lanes lower than that lane. For example, the decoding circuit 22 feeds back the decoded results obtained in the first lane to each of the likelihood calculation units 230-2 to 230-d arranged in the second lane to the dth lane. For example, the decoding circuit 22 feeds back the decoded results obtained in the second lane to each of the likelihood calculation units 230-2 to 230-d arranged in the third lane to the dth lane. In this way, each SD-FEC decoding unit 240 feeds back the decoded results to all lanes lower than its own lane. This increases the likelihood of the lowest lane, which is bypassed, and reduces the error floor. This makes it possible to improve decoding performance when using short code length linear codes.

[0058] Although an embodiment of the present invention has been described above in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and includes designs within the scope of the gist of the present invention.

[0059] Some of the functional units (e.g., encoding circuits 10, 10a) of the transmitting device 1 and some of the functional units (e.g., decoding circuits 22, 22a) of the receiving device 2 in the above-described embodiment may be implemented by a computer. In this case, a program for implementing this function may be recorded on a computer-readable recording medium, and the program recorded on this recording medium may be read into a computer system and executed. Note that the term "computer system" here includes hardware such as an OS and peripheral devices.

[0060] Furthermore, "computer-readable recording media" refers to portable media such as flexible disks, optical magnetic disks, ROMs, and CD-ROMs, as well as storage devices such as hard disks built into computer systems. Furthermore, "computer-readable recording media" may also include devices that dynamically store programs for a short period of time, such as communication lines used when transmitting programs over networks like the Internet or communication lines like telephone lines, or devices that store programs for a fixed period of time, such as volatile memory within the computer systems that serve as servers or clients. Furthermore, the programs may be designed to realize some of the aforementioned functions, or may be capable of realizing the aforementioned functions in combination with programs already stored in the computer system, or may be realized using programmable logic devices such as FPGAs (Field Programmable Gate Arrays).

[0061] Although an embodiment of the present invention has been described above in detail with reference to the drawings, the specific configuration is not limited to this embodiment, and includes designs within the scope of the gist of the present invention.

[0062] The present invention is applicable to communication systems that use encoders and decoders.

[0063] REFERENCE SIGNS LIST 1... transmitting device, 2... receiving device, 10... encoding circuit, 11... symbol mapper, 12... transmitting unit, 20... receiving unit, 21... symbol demapper, 22... decoding circuit, 110... HD-FEC encoding unit, 120... 1:d converter, 130... SD-FEC encoding unit, 140... bit conversion circuit, 150... d:1 converter, 220... distributor, 230, 230-1 to 230-d... SD likelihood calculation unit, 240, 240-1 to 240-(d-1)... SD-FEC decoding unit, 250... HD likelihood calculation unit, 260... d:1 converter, 270... HD-FEC decoding unit

Claims

1. A decoding device used in coherent digital signal processing, comprising: a distributor that distributes to each of the first to dth (d is an integer of 2 or greater) lanes a decoding metric obtained by demodulating transmission data transmitted from a transmitting device based on information about noise occurring in a communication channel and a received signal; (d-1) decoding units that decode the outputs of the first likelihood calculation units arranged in the first to dth lanes and feed back the decoding results to the first likelihood calculation units arranged in all lower lanes; and a second likelihood calculation unit that makes hard decisions based on the output of the first likelihood calculation unit arranged in the dth lane.

2. The decoding device described in claim 1, wherein a first likelihood calculation unit provided in the first lane calculates a log-likelihood ratio based on the decoding metric, and each first likelihood calculation unit provided in a lane other than the first lane calculates a log-likelihood ratio based on the decoding metric and a decoding result by a decoding unit provided in a lane higher than the lane to which it belongs.

3. The decoding device according to claim 1 or 2, wherein the (d-1) decoding units apply multi-stage decoding.

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