Display substrate, manufacturing method therefor, and display device

Abstract

A display substrate, a manufacturing method therefor, and a display device. The display substrate comprises: a driving backplane (1), the driving backplane (1) comprising a base substrate (11), at least one pad group (12) located on one side of the base substrate (11), and a plurality of first power lines (13) arranged on the same layer as the pad group (12), the pad group (12) being located in a display region, each pad group (12) comprising a first welding electrode (121) and a second welding electrode (122), and the first power lines (13) extending from the display region to a fan-out region; a plurality of connection electrodes (2) respectively located on the sides of the first welding electrode (121) and of the second welding electrode (122) facing away from the driving backplane (1); a first auxiliary power line (3) arranged on the same layer as the connection electrodes (2), the first auxiliary power line (3) being located on the side of the first power lines (13) facing away from the base substrate (11), the first auxiliary power line (3) extending from the display region to the fan-out region, and the first auxiliary power line (3) being electrically connected to the first power lines (13); and a plurality of light-emitting chips (4), a positive electrode pin (42) of each light-emitting chip (4) being electrically connected to the first welding electrode (121) by means of a corresponding connection electrode (2), and a negative electrode pin (43) being electrically connected to the second welding electrode (122) by means of a corresponding connection electrode (2).

Description

Display substrate, manufacturing method thereof, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate, a manufacturing method thereof, and a display device. Background Art

[0002] Micro-LEDs (micro light-emitting diodes) typically refer to traditional LED chip structures, with the chip size reduced to less than 100 microns. Using mass transfer technology, these micron-scale micro-LEDs of varying color are transferred to a driver backplane, creating a full-color Micro-LED display. These displays offer advantages such as independent light control, high brightness, low power consumption, ultra-high resolution, and color saturation. They also offer flexible and transparent displays. Furthermore, because Micro-LEDs use inorganic materials and have a simpler structure, they offer significantly better lifespan and reliability than OLEDs, making them a key next-generation product in the display industry.

[0003] Summary of the Invention

[0004] The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The specific solutions are as follows:

[0005] An embodiment of the present disclosure provides a display substrate, comprising a display area and a fan-out area located on one side of the display area;

[0006] The display substrate comprises:

[0007] A driving backplane, the driving backplane comprising: a base substrate, at least one pad group located on one side of the base substrate, and a plurality of first power lines arranged on the same layer as the pad group; the pad group is located in the display area, each pad group comprises a first welding electrode and a second welding electrode, and the first power line extends from the display area to the fan-out area;

[0008] a plurality of connecting electrodes, respectively located on a side of the first welding electrode and the second welding electrode facing away from the driving back plate;

[0009] a first auxiliary power line, disposed in the same layer as the connecting electrode, the first auxiliary power line being located on a side of the first power line facing away from the base substrate, the first auxiliary power line extending from the display area to the fan-out area, and the first auxiliary power line being electrically connected to the first power line;

[0010] A plurality of light-emitting chips are arranged corresponding to the pad group, and the light-emitting chip includes a light-emitting body and a positive pin and a negative pin connected to the side of the light-emitting body facing the driving backplane, the positive pin is electrically connected to the first welding electrode through the corresponding connecting electrode, and the negative pin is electrically connected to the second welding electrode through the corresponding connecting electrode.

[0011] In a possible implementation, in the display substrate provided in an embodiment of the present disclosure, the orthographic projections of the first auxiliary power line and the first power line on the base substrate overlap with each other.

[0012] In a possible implementation, in the display substrate provided in the embodiment of the present disclosure, the driving backplane further includes a source-drain metal layer located between the base substrate and the first power line, and the driving backplane further includes a plurality of second power lines, wherein the second power lines extend from the display area to the fan-out area, and the second power lines include a first portion located in the display area and a second portion located in the fan-out area, wherein the first portion is provided on the same layer as the first power line, and the second portion is located in the source-drain metal layer; wherein

[0013] The display substrate further includes a second auxiliary power line provided in the same layer as the connection electrode and located on a side of the first portion of the second power line away from the base substrate, and the second auxiliary power line is electrically connected to the second power line.

[0014] In one possible implementation, in the above-mentioned display substrate provided in an embodiment of the present disclosure, the source-drain metal layer also includes a third auxiliary power line arranged corresponding to the first power line and a fourth auxiliary power line arranged corresponding to the second power line, the third auxiliary power line is electrically connected to the first power line, and the fourth auxiliary power line is electrically connected to the second power line.

[0015] In a possible implementation, in the above-mentioned display substrate provided in an embodiment of the present disclosure, the driving backplane further includes a source-drain metal layer located between the base substrate and the first power line, and the source-drain metal layer includes a second power line, and the second power line extends from the display area to the fan-out area.

[0016] In a possible implementation, in the display substrate provided in an embodiment of the present disclosure, the source / drain metal layer further includes a third auxiliary power line arranged corresponding to the first power line, and the third auxiliary power line is electrically connected to the first power line.

[0017] In a possible implementation, in the display substrate provided in the embodiment of the present disclosure, the plurality of light-emitting chips are distributed in an array, and the first power line and the second power line are located in gaps between adjacent light-emitting chips.

[0018] In a possible implementation, in the display substrate provided in the embodiment of the present disclosure, the driving backplane further includes: a first planar layer located between the source / drain metal layer and the first power line, a first passivation layer located between the first planar layer and the first power line, a second passivation layer located between the first power line and the connection electrode, and a second planar layer located between the second passivation layer and the connection electrode; wherein,

[0019] Each connecting electrode is electrically connected to the corresponding first welding electrode and second welding electrode through a via hole penetrating the second flat layer and the second passivation layer, and the first auxiliary power line is electrically connected to the first power line through a via hole penetrating the second flat layer and the second passivation layer.

[0020] In a possible implementation, in the above-mentioned display substrate provided in an embodiment of the present disclosure, the driving backplane further includes: a first gate layer located between the base substrate and the source-drain metal layer, a first gate insulating layer located between the first gate layer and the source-drain metal layer, an active layer located between the first gate insulating layer and the source-drain metal layer, a second gate insulating layer located between the active layer and the source-drain metal layer, a second gate layer located between the second gate insulating layer and the source-drain metal layer, and an interlayer insulating layer located between the second gate layer and the source-drain metal layer; wherein,

[0021] The first gate layer, the active layer, the second gate layer, and the source / drain metal layer are configured to form a thin film transistor.

[0022] In a possible implementation, in the display substrate provided in an embodiment of the present disclosure, the first power line is electrically connected to the positive electrode pin through the thin film transistor, and the second power line is electrically connected to the negative electrode pin;

[0023] Alternatively, the first power line is electrically connected to the negative electrode pin, and the second power line is electrically connected to the positive electrode pin through the thin film transistor.

[0024] In a possible implementation, in the display substrate provided in an embodiment of the present disclosure, materials of the pad group and the first power line both include Cu.

[0025] In a possible implementation, in the display substrate provided in the embodiment of the present disclosure, the material of the connecting electrode and the material of the first auxiliary power line both include Au.

[0026] In a possible implementation, in the display substrate provided in the embodiment of the present disclosure, the material of the connecting electrode and the material of the first auxiliary power line both include Ag.

[0027] In a possible implementation, in the display substrate provided in an embodiment of the present disclosure, a material of the connecting electrode includes Au, and a material of the first auxiliary power line includes Ag.

[0028] Correspondingly, an embodiment of the present disclosure further provides a display device, comprising the above-mentioned display substrate provided by an embodiment of the present disclosure.

[0029] Accordingly, an embodiment of the present disclosure further provides a method for manufacturing a display substrate, comprising:

[0030] A driving backplane is manufactured; the driving backplane comprises: a base substrate, at least one pad group located on one side of the base substrate, and a first power line arranged on the same layer as the pad group; the pad group is located in the display area, each pad group comprises a first welding electrode and a second welding electrode, and the first power line extends from the display area to the fan-out area;

[0031] A connecting electrode is formed on a side of the pad group facing away from the base substrate, and a first auxiliary power line is formed on a side of the first power line facing away from the base substrate using a one-time manufacturing process;

[0032] The positive electrode pin and the negative electrode pin of the light-emitting chip are aligned and welded to the corresponding connecting electrodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] FIG1 is a schematic diagram of a planar structure of a display substrate provided by an embodiment of the present disclosure;

[0034] FIG2 is a schematic diagram of an equivalent circuit for driving a Micro / Mini-LED display screen;

[0035] FIG3 is a schematic plan view of a display substrate provided by an embodiment of the present disclosure;

[0036] FIG4 is a schematic cross-sectional view of the integration of the display area and the fan-out area in the display substrate shown in FIG3 ;

[0037] FIG5 is a partial enlarged schematic diagram of the display area AA in FIG3 ;

[0038] FIG6 is a planar schematic diagram of a display substrate for a Micro-LED product with a pitch of only tens of μm;

[0039] FIG7 is a partial enlarged schematic diagram of the display area AA in FIG6 ;

[0040] FIG8 is a schematic diagram of the current (I)-EQE efficiency curve of Micro-LED;

[0041] FIG9 is a schematic flow chart of a method for manufacturing a display substrate according to an embodiment of the present disclosure;

[0042] FIG10 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. And in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0044] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the usual meanings understood by persons of ordinary skill in the field to which this disclosure belongs. The words “include” or “comprise” and the like used in this disclosure mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. The words “connect” or “connected” and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Inside”, “outside”, “upper”, “lower”, etc. are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0045] It should be noted that the sizes and shapes of the figures in the accompanying drawings, unless otherwise specified, do not reflect the actual scale and are intended only to illustrate the present disclosure. The same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions.

[0046] Typical LCD and OLED display products have a brightness of several hundred nits, while Micro-LED display products can reach several thousand nits. However, specialized products, such as HUDs, require even higher brightness levels, reaching hundreds of thousands of nits. However, higher brightness leads to higher circuit currents (I). This, due to IR drop, can cause voltage inconsistencies between the far and near ends of the display panel, affecting the display quality and causing significant circuit heating. As shown in Figure 1, at the same grayscale, the brightness of the display farther from the power supply is significantly lower than that closer to the power supply, resulting in poor display quality.

[0047] As shown in Figure 2, an equivalent circuit diagram of a Micro / Mini-LED display driver includes red, green, and blue light-emitting chips (denoted by L_R, L_G, and L_B, respectively) and a driving circuit (TFT) that drives their light. For example, the positive electrodes of the red light-emitting chip (L_R), green light-emitting chip (L_G), and blue light-emitting chip (L_B) can be electrically connected to the power line VDD through TFTs, the negative electrode of the red light-emitting chip (L_R) is electrically connected to the power line VSS_R, and the negative electrodes of the green light-emitting chip (L_G) and blue light-emitting chip (L_B) are electrically connected to the power line VSS_GB. When current flows to the light-emitting chip through a trace (having a resistor R) and a current passing through each trace segment, a voltage difference is generated between the far-end and near-end light-emitting chips. As can be seen from the figure, when the IR drop of VDD and VSS is large, the voltage difference between the LEDs at the far and near ends of the panel can be very large, resulting in poor display. Therefore, in order to make an ultra-high brightness Micro / Mini-LED display panel, when the current I is large, the resistance of the power line (VDD, VSS) must be reduced, thereby reducing the voltage drop across the power line and lowering the power line temperature.

[0048] Currently, the power line material of the driver backplane is generally Ti / Al / Ti, with a thickness of 0.65μm. If Cu is used instead of Ti / Al / Ti, the power line resistance can be reduced. However, when the Cu layer is made using the Sputter process, the maximum thickness of the Cu layer is 2μm, which still cannot meet the low resistance requirements. When the Cu layer is made using the electroplating process, the Cu layer thickness can reach 10μm, but the uniformity is poor and cannot meet the bonding flatness requirements of Micro-LED. Because the pitch (the distance between adjacent LED centers) of Micro-LED products is very small, only tens of μm, the line width of the power line is limited. In this case, it is difficult to further reduce the resistance of the power line.

[0049] The resistance calculation formula of the power line is: R = ρ × L / S = ρ × L / (w × d); where ρ is the resistivity of the power line, measured in ohm-cm; R is the resistance of the power line, measured in ohm; S is the cross-sectional area of ​​the power line, measured in square centimeters; and L is the length of the power line, measured in centimeters. In actual Micro-LED projects, L = pitch × number of pixels in the Y direction, and w = the actual width of the power line. Both L and w are fixed values. To reduce the resistance R of the power line, one can only reduce the resistivity ρ of the power line or increase the thickness d of the power line.

[0050] Therefore, in order to reduce the power line resistance of the Micro-LED display, an embodiment of the present disclosure provides a display substrate, as shown in FIG3 , which is a planar schematic diagram of a display substrate provided by an embodiment of the present disclosure, including a display area AA and a fan-out area BB located on one side of the display area AA;

[0051] As shown in FIG4 , FIG4 is a schematic cross-sectional view of the display area AA and the fan-out area BB in the display substrate shown in FIG3 , and the display substrate includes:

[0052] The driving backplane 1 includes: a base substrate 11, at least one pad group 12 located on one side of the base substrate 11, and a plurality of first power lines 13 arranged on the same layer as the pad group 12; the pad group 12 is located in the display area AA, each pad group 12 includes a first welding electrode 121 and a second welding electrode 122, and the first power lines 13 extend from the display area AA to the fan-out area BB; optionally, the first power lines 13 can be VDD or VSS;

[0053] A plurality of connecting electrodes 2 are respectively located on a side of the first welding electrode 121 and the second welding electrode 122 away from the driving back plate 1;

[0054] A first auxiliary power line 3 is provided on the same layer as the connection electrode 2. The first auxiliary power line 3 is located on a side of the first power line 13 facing away from the base substrate 11. The first auxiliary power line 3 extends from the display area AA to the fan-out area BB. The first auxiliary power line 3 is electrically connected to the first power line 13.

[0055] Multiple light-emitting chips 4 are arranged corresponding to the pad group 12. The light-emitting chip 4 includes a light-emitting body 41 and a positive pin 42 and a negative pin 43 connected to the side of the light-emitting body 41 facing the driving backplane 1. The positive pin 42 is electrically connected to the first welding electrode 121 through the corresponding connecting electrode 2, and the negative pin 43 is electrically connected to the second welding electrode 122 through the corresponding connecting electrode 2.

[0056] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, the size of the light-emitting chip is generally less than 200 μm. For example, the light-emitting chip provided in the present disclosure may be a Micro LED. Due to the smaller size of the Micro LED, the pixel resolution of the display substrate can be improved. Specifically, the size of the Micro LED is generally less than 100 μm. Of course, the light-emitting chip may also be other light-emitting structures such as Mini LED, and the present disclosure does not limit this. Specifically, when the light-emitting chip is a Mini LED, the size of the Mini LED is 100 μm-200 μm.

[0057] In some embodiments, as shown in FIG4 , the connecting electrode 2 is a bonding metal, and its function is to bond the light-emitting chip 4 to the driving backplane 1. After the driving backplane 1 is produced, the connecting electrode 2 can be prepared above the first welding electrode 121 and the second welding electrode 122 of the driving backplane 1 by an electron beam evaporation process. The evaporation material can be a metal or alloy with low resistivity such as Au or Ag, and the thickness can reach 10 μm or even thicker. When the material of the connecting electrode 2 is Au, the material of the positive pin 42 and the negative pin 43 of the light-emitting chip 4 can be In, so that an InAu alloy is formed by hot pressing to achieve bonding between the light-emitting chip 4 and the driving backplane 1; when the material of the connecting electrode 2 is Ag, the material of the positive pin 42 and the negative pin 43 of the light-emitting chip 4 can be Sn, so that a SnAg alloy is formed by hot pressing to achieve bonding between the light-emitting chip 4 and the driving backplane 1.

[0058] In some embodiments, as shown in FIG4 , to improve adhesion between the connecting electrode 2 and the pad group 12 and to reduce contact resistance, the pad group 12 is generally made of Cu. The film layer containing the pad group 12 is hereinafter referred to as the Cu layer. The VDD power line and the VSS power line are generally used to transmit electrical signals to drive the light-emitting chip 4 to emit light. To reduce the resistance of the VDD power line and the VSS power line, the VDD power line and the VSS power line are preferably fabricated in the Cu layer. Existing VDD power lines and VSS power lines are generally fabricated in the source-drain metal layer SD. The material of the source-drain metal layer SD is generally Ti / Al / Ti. Compared to the existing Ti / Al / Ti layer, the Cu layer not only has a lower resistivity but can also be made thicker. Therefore, fabricating the VDD power line and the VSS power line in the Cu layer can greatly reduce resistance. However, for Micro-LED products, whether both the VDD power line and the VSS power line can be made in the Cu layer is related to the pitch of the Micro-LED product. When the pitch is large, for example, greater than 100μm, the VDD power line and the VSS power line can be made in the Cu layer in the display area AA; when the pitch is small, generally only tens of μm, then only one of the VDD power line and the VSS power line can be made in the Cu layer in the display area AA, and the other needs to be made in the source and drain metal layer SD. Therefore, regardless of whether the pitch is large or small, one of the VDD power line and the VSS power line (the first power line 13) can be made in the Cu layer in the display area AA. In this way, when the connecting electrode 2 (Au or Ag) is made on the pad group 12, the first auxiliary power line 3 can be made above the first power line 13 (VDD or VSS) made in the Cu layer at the same time, so that the first auxiliary power line 3 is electrically connected to the first power line 13. Since the material of the first auxiliary power line 3 is Au or Ag, the thickness of the first auxiliary power line 3 can reach 10μm or even thicker. In this way, the first auxiliary power line 3 is connected in parallel with the first power line 13 to greatly reduce the resistance of the first power line 13. When realizing an ultra-high brightness Micro-LED display screen, the embodiment of the present disclosure can reduce the voltage difference between the near-end and far-end light-emitting chips of the display screen due to the low resistance of the first power line 13, thereby improving the uniformity of the display screen.

[0059] Therefore, in response to the application requirements of ultra-high brightness Micro-LED display screens, the present disclosure proposes a solution to improve brightness, which greatly improves the brightness of the display panel, from several thousand nits to several hundred thousand nits, and can reduce the voltage difference between the light-emitting chips at the far end and the near end of the display screen, thereby avoiding poor display. Moreover, the first auxiliary power line is arranged on the same layer as the connecting electrode, and it is only necessary to manufacture the first auxiliary power line on the first power line at the same time as the connecting electrode is manufactured, without adding new process flow and manufacturing time, thus having strong operability and no increase in cost.

[0060] In some embodiments, in the display substrate provided by the embodiments of the present disclosure, as shown in FIG4 , the orthographic projections of the first auxiliary power line 3 and the first power line 13 on the base substrate 11 overlap. This increases the contact area of ​​the electrical connection between the first auxiliary power line 3 and the first power line 13, further reducing the resistance of the first power line 13 and lowering the voltage difference between the light-emitting chips 4 at the far end and the near end of the display screen.

[0061] In some embodiments, in the above-mentioned display substrate provided in the embodiments of the present disclosure, as shown in Figures 3 and 4, multiple light-emitting chips 4 are generally distributed in an array in the display area AA, and the first power line 13 and the second power line 14 are generally arranged in the gap between adjacent light-emitting chips 4.

[0062] In some embodiments, when the pitch of the Micro-LED product is greater than 100 μm, the VDD power line and the VSS power line can be made in the Cu layer in the display area AA. Therefore, in the above-mentioned display substrate provided in the embodiment of the present disclosure, as shown in Figures 3 to 5, Figure 5 is a partial enlarged schematic diagram of the display area AA in Figure 3 (2×2 pixels), the driving backplane 1 also includes a source-drain metal layer SD located between the base substrate 11 and the first power line 13, and the driving backplane 1 also includes a plurality of second power lines 14. The second power line 14 extends from the display area AA to the fan-out area BB. The second power line 14 includes a first portion located in the display area AA and a second portion located in the fan-out area BB. The first portion is arranged in the same layer as the first power line 13, that is, the first portion of the second power line 14 located in the display area AA and the first power line 13 in the display area AA are both made in the Cu layer. In this way, when the connecting electrode 2 is made, an auxiliary power line electrically connected to the second power line 14 can be made above the first portion to reduce the resistance of the second power line 14, that is, the display substrate provided in the embodiment of the present disclosure also includes a second power line located in the same layer as the connecting electrode 2 and located in the second power line 14. The first portion of the second auxiliary power line 5 is located on a side facing away from the base substrate 11, and the second auxiliary power line 5 is electrically connected to the second power line 14. For example, one of the first power line 13 and the second power line 14 is a VDD power line, and the other is a VSS power line. This embodiment can simultaneously reduce the resistance of the VDD power line and the VSS power line, and can significantly reduce the voltage difference between the near end and the far end of the light-emitting chip 4 in the display area AA on the display screen, thereby achieving high brightness while improving brightness uniformity and enhancing the display effect.

[0063] In some embodiments, in the above-mentioned display substrate provided in the embodiment of the present disclosure, as shown in Figures 3-5, the first power line 13 and the second power line 14 have the same extension direction in the display area AA, which is generally the same as the extension direction of the data line (Data) in the driving backplane 1, and the first power line 13 and the second power line 14 both extend from the display area AA to the fan-out area BB, and are then bound to the flexible printed circuit (FPC) to realize the transmission of electrical signals. In order to avoid the first power line 13 and the second power line 14 from short-circuiting in the fan-out area BB, the first power line 13 and the second power line 14 need to be made in different film layers in the fan-out area BB. Since the part of the first power line 13 provided in the embodiment of the present disclosure located in the display area AA and the part located in the fan-out area BB are both made in the Cu layer, the second part of the second power line 14 located in the fan-out area BB can be set in the source and drain metal layer SD. This is equivalent to making the first auxiliary power line 3 arranged on the same layer as the connecting electrode 2 above the entire first power line 13 located in the display area AA and the fan-out area BB, while the second auxiliary power line 5 arranged on the same layer as the connecting electrode 2 can only be made above the first part of the second power line 14 located in the display area AA.

[0064] In some embodiments, in the display substrate provided in the embodiments of the present disclosure, as shown in Figures 3 and 4 , since the first power line 13 and the second power line 14 are both provided in the Cu layer in the display area AA, in order to further reduce the resistance of the first power line 13 and the second power line 14, the source-drain metal layer SD may further include a third auxiliary power line 6 provided corresponding to the first power line 13 and a fourth auxiliary power line 7 provided corresponding to the second power line 14. The third auxiliary power line 6 is electrically connected to the first power line 13, and the fourth auxiliary power line 7 is electrically connected to the second power line 14. In this way, the first power line 13 and the second power line 14 in the display area AA are three metal layers connected in parallel: the source-drain metal layer SD, the Cu layer, and the Au (or Ag) layer. This further reduces the resistance of the first power line 13 and the second power line 14, thereby further reducing the voltage difference between the far end and the near end during high-brightness display.

[0065] It should be noted that, as shown in Figure 3, the first power line 13 and the second power line 14 located in the fan-out area BB both have a narrowed area near the flexible circuit board (FPC). The narrowed area of ​​the first power line 13 is D1, and the narrowed area of ​​the second power line 14 is D2. The power lines in areas D1 and D2 do not overlap, so that the first power line 13 in the narrowed area D1 can be connected in parallel using three layers of source and drain metal layer SD, Cu layer, and Au (or Ag) layer. The first power line 13 between the narrowed area D1 and the display area AA uses two layers of Cu layer and Au (or Ag) layer in parallel. The second power line 14 in the narrowed area D3 can also use three layers of source and drain metal layer SD, Cu layer, and Au (or Ag) layer in parallel. The second power line 14 between the narrowed area D2 and the display area AA uses the source and drain metal layer SD.

[0066] In some embodiments, when the pitch of a Micro-LED product is only tens of μm, only one of the VDD and VSS power lines in the display area AA can be fabricated on the Cu layer. Therefore, in the display substrate provided in the embodiments of the present disclosure, as shown in Figures 4, 6, and 7 (Figure 6 is a schematic plan view of a display substrate for a Micro-LED product with a pitch of only tens of μm, and Figure 7 is a partially enlarged schematic view (3×3 pixels) of the display area AA in Figure 6), the driver backplane 1 also includes a source / drain metal layer SD located between the base substrate 11 and the first power line 13. The source / drain metal layer SD includes a second power line 14, which extends from the display area AA to the fan-out area BB. This means that the first auxiliary power line 3, which is arranged on the same layer as the connection electrode 2, can be fabricated above the entire first power line 13 in both the display area AA and the fan-out area BB, while the entire second power line 14 is fabricated in the source / drain metal layer SD. Therefore, the second auxiliary power line 5 electrically connected to the second power line 14 cannot be fabricated during the fabrication of the connection electrode 2.

[0067] In some embodiments, in the display substrate provided by the embodiments of the present disclosure, as shown in Figures 4, 6, and 7, since the first power line 13 is provided in the Cu layer in both the display area AA and the fan-out area, to further reduce the resistance of the first power line 13, the source / drain metal layer SD further includes a third auxiliary power line 6 provided corresponding to the first power line 13, and the third auxiliary power line 6 is electrically connected to the first power line 13. Thus, the first power line 13 in the display area AA comprises three metal layers in parallel: the source / drain metal layer SD, the Cu layer, and the Au (or Ag) layer. This further reduces the resistance of the first power line 13, thereby further reducing the voltage difference between the far and near ends during high-brightness display.

[0068] It should be noted that Figure 4 is only for schematically illustrating that when the power line located in the display area AA and the power line located in the fan-out area BB are set in the Cu layer, an auxiliary power line set in the same layer as the connecting electrode 2 can be made above the power line. The specific structure of the power line in the product can be found in the above description.

[0069] In some embodiments, as shown in Figures 5 and 7, each light-emitting chip 4 may include four pins (for example, two positive pins and two negative pins); of course, each light-emitting chip may include two pins, and the light-emitting chips may be connected in series; the specific connection method of the light-emitting chips is the same as in the prior art.

[0070] In some embodiments, in the display substrate provided in the embodiment of the present disclosure, as shown in FIG4 , the driving backplane 1 further includes: a first planar layer PLN1 located between the source / drain metal layer SD and the first power line 13, a first passivation layer PVX1 located between the first planar layer PLN1 and the first power line 13, a second passivation layer PVX2 located between the first power line 13 and the connection electrode 2, and a second planar layer PLN2 located between the second passivation layer PVX2 and the connection electrode 2; wherein,

[0071] Each connecting electrode 2 is electrically connected to the corresponding first welding electrode 121 and second welding electrode 122 through a via hole passing through the second flat layer PLN2 and the second passivation layer PVX2, and the first auxiliary power line 3 is electrically connected to the first power line 13 through a via hole passing through the second flat layer PLN2 and the second passivation layer PVX2.

[0072] Specifically, the first planarization layer PLN1 and the second planarization layer PLN2 are intended to flatten the patterned metal layer after it is formed. The first passivation layer PVX1 is intended to improve the adhesion between the upper and lower film layers. The second passivation layer PVX2, on the one hand, enhances adhesion and, on the other hand, can protect the pad group 12.

[0073] Optionally, the materials of the first planarization layer PLN1 and the second planarization layer PLN2 may be organic materials such as resin, and the materials of the first passivation layer PVX1 and the second passivation layer PVX2 may be inorganic materials such as silicon nitride and silicon oxynitride.

[0074] In some embodiments, in the display substrate provided in the embodiment of the present disclosure, as shown in FIG4 , the driving backplane 1 further includes: a first gate layer G1 located between the base substrate 11 and the source-drain metal layer SD, a first gate insulating layer GI located between the first gate layer G1 and the source-drain metal layer SD, an active layer Act located between the first gate insulating layer GI and the source-drain metal layer SD, a second gate insulating layer GI2 located between the active layer Act and the source-drain metal layer SD, a second gate layer G2 located between the second gate insulating layer GI2 and the source-drain metal layer SD, and an interlayer insulating layer ILD located between the second gate layer G2 and the source-drain metal layer SD; wherein,

[0075] The first gate layer G1, active layer Act, second gate layer G2 and source / drain metal layer SD are configured to form a thin film transistor. Thus, the present disclosure uses thin film transistors to drive the light emitting chip 4 to emit light, that is, adopts active drive, which can realize independent light emission control of the light emitting chip 4.

[0076] It should be noted that FIG4 illustrates only one thin-film transistor. In a specific implementation, the driving circuit may employ a 2T1C, 3T1C, or 7T1C driving circuit, where ' ' represents a thin-film transistor and C represents a capacitor. The specific structure and operating principle of each driving circuit are the same as those in the prior art and are not further described here.

[0077] It should be noted that the driving backplane provided in the embodiment of the present disclosure may be an LTPS-type driving backplane, an oxide-type driving backplane, or an LTPO-type driving backplane that is a combination of LTPS and oxide types.

[0078] In some embodiments, in the above-mentioned display substrate provided in the embodiment of the present disclosure, as shown in Figure 4, the first power line 13 can be electrically connected to the positive pin 121 through a thin film transistor, and the second power line 14 can be electrically connected to the negative pin 122; in this way, the first power line 13 is a VDD power line, and the second power line 14 is a VSS power line.

[0079] In some embodiments, in the above-mentioned display substrate provided in the embodiment of the present disclosure, the first power line can also be electrically connected to the negative pin, and the second power line can be electrically connected to the positive pin through a thin film transistor, so that the first power line is a VSS power line and the second power line is a VDD power line.

[0080] In some embodiments, in the display substrate provided by the embodiments of the present disclosure, as shown in FIG. 4 , the materials of the pad group 12 and the first power line 13 may both be Cu.

[0081] In some embodiments, in the display substrate provided by the embodiments of the present disclosure, as shown in FIG4 , the material of the connecting electrode 2 and the material of the first auxiliary power line 3 can both be Au, with a thickness of several μm, or even 10 μm or thicker. The resistivity of Au is 0.024Ω*μm, so when the first auxiliary power line 3 and the first power line 13 are connected in parallel, the resistance of the first power line 13 can be significantly reduced.

[0082] The inventors of this case have discovered through testing that when a first auxiliary power line 3 made of Au is connected in parallel with the first power line 13, the resistance of the new first power line 13 is only about 18% of the resistance of the original first power line 13 fabricated solely in the Cu layer. This resistance is only about 5% of the resistance of the first power line 13 fabricated in the source / drain metal layer SD (Ti / Al / Ti) in the prior art. With the same power line width, the disclosed embodiment can handle LED currents 5, 6, or even 20 times greater than the original, significantly improving brightness. The voltage difference between the far and near ends is minimal, ensuring uniform display brightness.

[0083] In some embodiments, in the display substrate provided by the embodiments of the present disclosure, as shown in FIG4 , the material of the connecting electrode 2 and the material of the first auxiliary power line 3 can both be Ag, with a thickness of several μm, or even 10 μm or more. Ag has a resistivity of 0.0165 Ω*μm, so when the first auxiliary power line 3 and the first power line 13 are connected in parallel, the resistance of the first power line 13 can be significantly reduced.

[0084] In some embodiments, when the pitch of a Micro-LED product is only tens of μm, the spacing between the light-emitting chips is very small. When Ag is used to make the connecting electrode 2, electron migration may occur, causing a short circuit. Therefore, in the above-mentioned display substrate provided in the embodiment of the present disclosure, as shown in FIG4 , the material of the connecting electrode 2 can be Au, and the material of the first auxiliary power line 3 can be Ag. In this way, after preparing the Au pad group 12 on the driving backplane 1, the first auxiliary power line 3 of a certain thickness made of Ag is prepared on the first power line (VDD or VSS) of the display area AA and the fan-out area BB of the driving backplane 1 through an electron beam evaporation process. The thickness can be several μm, or even 10 μm or thicker.

[0085] The inventors of this case have discovered through testing that, for Micro-LED displays where both the connecting electrode 2 and the first auxiliary power line 3 are made of Ag, or where the connecting electrode 2 is made of Au and the first auxiliary power line 3 is made of Ag, the resistance of the new first power line 13 is only about 17% of the resistance of the original first power line 13 fabricated solely in the Cu layer. The resistance of the new first power line 13 is only about 3.4% of the resistance of the first power line 13 fabricated in the source / drain metal layer SD (Ti / Al / Ti) in the prior art. With the same power line width, the disclosed embodiment can withstand LED currents six or even 30 times greater than the original, significantly increasing brightness by approximately nine or even 50 times. Furthermore, the voltage difference between the far and near ends is small, resulting in uniform display brightness.

[0086] As shown in FIG8 , FIG8 is a schematic diagram of the current (I)-EQE efficiency curve of Micro-LED. In the prior art, the current of Micro-LED products is usually at point A, and the EQE is relatively small. However, after the resistance of the power line is reduced and the current of the Micro-LED is increased (for example, the current corresponding to points B, C, and D), the working efficiency of the light-emitting chip is greatly improved, thereby greatly improving the brightness of the Micro-LED display, for example, by dozens of times, and the brightness can reach hundreds of thousands of nits.

[0087] In specific implementation, the display substrate provided in the embodiment of the present disclosure may further include other functional film layers well known to those skilled in the art, which will not be described in detail here.

[0088] Based on the same inventive concept, the present disclosure also provides a method for manufacturing a display substrate, which is used to manufacture the display substrate ( FIG. 4 ) provided in the present disclosure. As shown in FIG. 9 , the manufacturing method includes:

[0089] S901. Fabricate a driving backplane; the driving backplane comprises: a base substrate, at least one pad group located on one side of the base substrate, and a first power line disposed on the same layer as the pad group; the pad group is located in the display area, each pad group comprises a first welding electrode and a second welding electrode, and the first power line extends from the display area to the fan-out area;

[0090] S902, forming a connection electrode on a side of the pad group facing away from the base substrate, and forming a first auxiliary power line on a side of the first power line facing away from the base substrate using a one-step manufacturing process;

[0091] S903 , welding the positive electrode pin and the negative electrode pin of the light-emitting chip to the corresponding connection electrodes.

[0092] The manufacturing method of the display substrate provided by the embodiment of the present disclosure adopts a one-time manufacturing process to manufacture the connecting electrodes and the first auxiliary power line, thus eliminating the need to add new process flows and manufacturing time, thus having strong operability and not increasing costs.

[0093] It should be noted that the manufacturing method of the above-mentioned display substrate provided in the embodiment of the present disclosure is basically the same as that in the prior art. The difference is that when manufacturing the connecting electrode, an auxiliary power line arranged in parallel is also manufactured above the power line manufactured on the Cu layer to reduce the resistance of the power line. Specifically, whether the auxiliary power line is manufactured above the first power line or the second power line, please refer to the relevant description in the aforementioned display substrate.

[0094] In specific implementation, the materials and thicknesses of the relevant film layers involved in the above-mentioned manufacturing method provided in the embodiment of the present disclosure can refer to the description of the aforementioned display substrate and will not be described in detail here.

[0095] Based on the same inventive concept, the present disclosure also provides a display device comprising the display substrate described above. The principles of this display device are similar to those of the display substrate described above, so the implementation of this display device can refer to the implementation of the display substrate described above, and any repetitions will not be repeated here.

[0096] In a specific implementation, the display device provided in the embodiment of the present disclosure may be a full-screen mobile phone as shown in FIG10 . Of course, the display device provided in the embodiment of the present disclosure may also be any product or component with a display function, such as a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. The other essential components of the display device are well understood by those skilled in the art and are not described here in detail, nor should they be construed as limiting the present disclosure.

[0097] The embodiments of the present disclosure provide a display substrate, a manufacturing method thereof, and a display device. By providing a first auxiliary power line provided on the same layer as the connecting electrode, and electrically connecting the first auxiliary power line to the first power line, the first auxiliary power line and the first power line are connected in parallel to reduce the resistance of the first power line. When realizing an ultra-high brightness Micro-LED display screen, the embodiments of the present disclosure can reduce the voltage difference between the near-end and far-end light-emitting chips of the display screen due to the low resistance of the first power line, thereby improving the uniformity of the displayed image. Therefore, in response to the application requirements of ultra-high brightness Micro-LED displays, the present disclosure proposes a brightness improvement solution that greatly improves the brightness of the display panel, from several thousand nits to several hundred thousand nits, and can reduce the voltage difference between the far-end and near-end light-emitting chips of the display screen, thereby avoiding poor display. Furthermore, the first auxiliary power line is provided on the same layer as the connecting electrode, so it is only necessary to fabricate the first auxiliary power line on the first power line at the same time as the connecting electrode is fabricated, without adding a new process flow or manufacturing time. This solution is highly operational and does not increase costs.

[0098] Obviously, those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A display substrate, wherein: comprising a display area and a fan-out area located on one side of the display area; The display substrate comprises: A driving backplane, the driving backplane comprising: a base substrate, at least one pad group located on one side of the base substrate, and a plurality of first power lines arranged on the same layer as the pad group; the pad group is located in the display area, each pad group comprises a first welding electrode and a second welding electrode, and the first power line extends from the display area to the fan-out area; a plurality of connecting electrodes, respectively located on a side of the first welding electrode and the second welding electrode facing away from the driving back plate; a first auxiliary power line, disposed in the same layer as the connecting electrode, the first auxiliary power line being located on a side of the first power line facing away from the base substrate, the first auxiliary power line extending from the display area to the fan-out area, and the first auxiliary power line being electrically connected to the first power line; A plurality of light-emitting chips are arranged corresponding to the pad group, and the light-emitting chip includes a light-emitting body and a positive pin and a negative pin connected to the side of the light-emitting body facing the driving backplane, the positive pin is electrically connected to the first welding electrode through the corresponding connecting electrode, and the negative pin is electrically connected to the second welding electrode through the corresponding connecting electrode.

2. The display substrate according to claim 1, wherein: Orthographic projections of the first auxiliary power line and the first power line on the base substrate overlap with each other.

3. The display substrate according to claim 1 or 2, wherein: The driving backplane further includes a source-drain metal layer located between the base substrate and the first power line, and the driving backplane further includes a plurality of second power lines, wherein the second power lines extend from the display area to the fan-out area, and the second power lines include a first portion located in the display area and a second portion located in the fan-out area, wherein the first portion is provided on the same layer as the first power line, and the second portion is located in the source-drain metal layer; wherein The display substrate further includes a second auxiliary power line provided in the same layer as the connecting electrode and located on a side of the first portion of the second power line away from the base substrate. The second auxiliary power line The second power line is electrically connected to the second power line.

4. The display substrate according to claim 3, wherein: The source-drain metal layer also includes a third auxiliary power line corresponding to the first power line and a fourth auxiliary power line corresponding to the second power line. The third auxiliary power line is electrically connected to the first power line, and the fourth auxiliary power line is electrically connected to the second power line.

5. The display substrate according to claim 1 or 2, wherein: The driving backplane further includes a source-drain metal layer located between the base substrate and the first power line. The source-drain metal layer includes a second power line, and the second power line extends from the display area to the fan-out area.

6. The display substrate according to claim 5, wherein: The source-drain metal layer further includes a third auxiliary power line corresponding to the first power line, and the third auxiliary power line is electrically connected to the first power line.

7. The display substrate according to any one of claims 3 to 6, wherein: The plurality of light emitting chips are distributed in an array, and the first power line and the second power line are located in gaps between adjacent light emitting chips.

8. The display substrate according to any one of claims 3 to 7, wherein: The driving backplane further includes: a first planar layer located between the source / drain metal layer and the first power line, a first passivation layer located between the first planar layer and the first power line, a second passivation layer located between the first power line and the connecting electrode, and a second planar layer located between the second passivation layer and the connecting electrode; wherein, Each connecting electrode is electrically connected to the corresponding first welding electrode and second welding electrode through a via hole penetrating the second flat layer and the second passivation layer, and the first auxiliary power line is electrically connected to the first power line through a via hole penetrating the second flat layer and the second passivation layer.

9. The display substrate according to claim 8, wherein: The driving backplane further includes: a first gate layer located between the base substrate and the source-drain metal layer, a first gate insulating layer located between the first gate layer and the source-drain metal layer, an active layer located between the first gate insulating layer and the source-drain metal layer, a second gate insulating layer located between the active layer and the source-drain metal layer, a second gate layer located between the second gate insulating layer and the source-drain metal layer, and an interlayer insulating layer located between the second gate layer and the source-drain metal layer; wherein, The first gate layer, the active layer, the second gate layer, and the source / drain metal layer are configured to form a thin film transistor.

10. The display substrate according to claim 9, wherein: The first power line is electrically connected to the positive electrode pin through the thin film transistor, and the second power line is electrically connected to the negative electrode pin; Alternatively, the first power line is electrically connected to the negative electrode pin, and the second power line is electrically connected to the positive electrode pin through the thin film transistor.

11. The display substrate according to any one of claims 1 to 10, wherein: The pad group and the first power line are both made of Cu.

12. The display substrate according to any one of claims 1 to 11, wherein: The material of the connection electrode and the material of the first auxiliary power line both include Au.

13. The display substrate according to any one of claims 1 to 11, wherein: The material of the connection electrode and the material of the first auxiliary power line both include Ag.

14. The display substrate according to any one of claims 1 to 11, wherein: The connecting electrode is made of Au, and the first auxiliary power line is made of Ag.

15. A display device, wherein: The display substrate comprises the display substrate according to any one of claims 1 to 14.

16. A method for manufacturing a display substrate, wherein: include: Make a driving backplane; The driving backplane includes: a base substrate, at least one pad group located on one side of the base substrate, and a first power line arranged on the same layer as the pad group; the pad group is located in the display area, each pad group includes a first welding electrode and a second welding electrode, and the first power line extends from the display area to the fan-out area; A connecting electrode is formed on a side of the pad group facing away from the base substrate, and a first auxiliary power line is formed on a side of the first power line facing away from the base substrate using a one-time manufacturing process; The positive electrode pin and the negative electrode pin of the light-emitting chip are aligned and welded to the corresponding connecting electrodes.

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