Shift register unit, gate driving circuit, and display panel and driving method therefor

Abstract

A shift register unit, a gate driving circuit, and a display panel and a driving method for a display panel. The shift register unit comprises: an input circuit (2), a second control circuit (3), a third control circuit (4), a fourth control circuit (5) and a second output circuit (12), wherein the input circuit (2) is used for transmitting an input signal from an input signal end to a fourth node in response to a signal from a third clock signal end; the second control circuit (3) is used for transmitting a signal from a first power supply end to a third control node in response to signals from a first clock signal end and a second control node; the third control circuit (4) is used for transmitting a signal from the first power supply end to the second control node in response to a signal from the third control node; the fourth control circuit (5) is used for controlling the voltage of the second control node in response to signals from the first clock signal end and the third control node; and the second output circuit (12) is used for transmitting a signal from the first clock signal end to a second output end in response to a signal from a first control node, and inputting an inactive level to the second output end in response to a signal from the second control node.

Description

Shift register unit, gate drive circuit, display panel and driving method thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to PCT application No. PCT / CN2024 / 084558, entitled “Shift register unit, gate drive circuit, display panel and driving method thereof,” filed on March 28, 2024. The disclosure of the above-mentioned PCT patent application is hereby incorporated by reference in its entirety as part of this application. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a shift register unit, a gate driving circuit, a display panel and a driving method thereof. Background Art

[0004] In related technologies, a display panel includes a gate driving circuit and a pixel driving circuit. The gate driving circuit includes a plurality of shift register units. The shift register units can provide gate driving signals to the corresponding pixel driving circuits to achieve row-by-row scanning of the display panel.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0006] Summary of the Invention

[0007] According to one aspect of the present disclosure, a shift register unit is provided, comprising:

[0008] an input circuit connected to the input signal terminal, the fourth node, and the third clock signal terminal, wherein the input circuit is configured to transmit the input signal of the input signal terminal to the fourth node in response to a signal of the third clock signal terminal;

[0009] a second control circuit connected to the third control node, the first clock signal terminal, the second control node, and the first power terminal, wherein the third control node is connected to the fourth node, and the second control circuit is configured to respond to signals from the first clock signal terminal and the second control node to transmit the signal from the first power terminal to the third control node;

[0010] a third control circuit connected to the third control node, the first power supply terminal, and the second control node, the third control circuit being configured to respond to a signal from the third control node to transmit a signal from the first power supply terminal to the second control node;

[0011] a fourth control circuit connected to the third control node, the first clock signal terminal, and the second control node, the fourth control circuit being configured to control the voltage of the second control node in response to signals from the first clock signal terminal and the third control node;

[0012] The second output circuit is connected to the first control node, the second control node, the second output end, and the first clock signal end. The first control node is connected to the third control node. The second output circuit is used to respond to the signal of the first control node to transmit the signal of the first clock signal end to the second output end, and to respond to the signal of the second control node to input an invalid level to the second output end.

[0013] In an exemplary embodiment of the present disclosure, the second output circuit is further connected to a third clock signal terminal, and the second output circuit is configured to respond to a signal from the third clock signal terminal to transmit a signal from the first power terminal to the second output terminal.

[0014] In an exemplary embodiment of the present disclosure, the fourth control circuit is also connected to a third node and a first power supply terminal, and the fourth control circuit is used to respond to a signal from the third control node to transmit a signal from the first power supply terminal to the third node, to respond to a signal from the first clock signal terminal to input a valid level signal to the third node, and to respond to a signal from the third node to input a valid level signal to the second control node.

[0015] In an exemplary embodiment of the present disclosure, the shift register unit further includes:

[0016] The isolation circuit is connected to the first control node and the third control node, and is used for responding to a control signal to connect the first control node and the third control node.

[0017] In an exemplary embodiment of the present disclosure, the second output circuit is further connected to the first power supply terminal, and the second output circuit is configured to input an invalid level to the second output terminal using the first power supply terminal in response to a signal from the second control node;

[0018] The second output circuit includes:

[0019] a twelfth transistor, having a first electrode connected to the first clock signal terminal, a second electrode connected to the second output terminal, and a gate connected to the first control node;

[0020] a third capacitor, a first electrode of which is connected to the first control node, and a second electrode of which is connected to the second output terminal;

[0021] a thirteenth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the second output terminal, and a gate connected to the second control node;

[0022] The fourteenth transistor has a first electrode connected to the first power supply terminal, a second electrode connected to the second output terminal, and a gate connected to the third clock signal terminal.

[0023] In an exemplary embodiment of the present disclosure, the input circuit includes:

[0024] a first transistor, having a first electrode connected to the input signal terminal, a second electrode connected to the fourth node, and a gate connected to the third clock signal terminal;

[0025] The second control circuit includes:

[0026] a sixth transistor, having a first electrode connected to the first power supply terminal and a gate connected to the second control node;

[0027] a seventh transistor, having a first electrode connected to the second electrode of the sixth transistor, a second electrode connected to the third control node, and a gate connected to the first clock signal terminal;

[0028] The third control circuit includes:

[0029] The eleventh transistor has a first electrode connected to the first power supply terminal, a second electrode connected to the second control node, and a gate connected to the third control node.

[0030] In an exemplary embodiment of the present disclosure, the fourth control circuit is configured to input a valid level signal to the third node using the first clock signal terminal in response to a signal from the first clock signal terminal, and to input a valid level signal to the second control node using the first clock signal terminal in response to a signal from the third node. The fourth control circuit includes:

[0031] a third transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the third node, and a gate connected to the third control node;

[0032] a second transistor, having a first electrode connected to the first clock signal terminal, a second electrode connected to the third node, and a gate connected to the first clock signal terminal;

[0033] The tenth transistor has a first electrode connected to the first clock signal terminal, a second electrode connected to the second control node, and a gate connected to the third node.

[0034] In an exemplary embodiment of the present disclosure, the isolation circuit is further connected to a third clock signal terminal, and the isolation circuit is configured to connect the third control node and the first control node in response to a signal at the third clock signal terminal;

[0035] The isolation circuit comprises:

[0036] An eighth transistor has a first electrode connected to the third control node, a second electrode connected to the first control node, and a gate connected to the third clock signal terminal.

[0037] In an exemplary embodiment of the present disclosure, the shift register unit further includes a reset circuit, and the reset circuit includes one or more of a first reset circuit, a second reset circuit, a third reset circuit, and a fourth reset circuit;

[0038] The first reset circuit is connected to the first control node, and is configured to input an invalid level to the first control node in response to a reset signal;

[0039] The second reset circuit is connected to the fourth node and the third control node, and is configured to respond to a reset signal to turn off the fourth node and the third control node;

[0040] The third reset circuit is connected to the third control node, and is configured to input an invalid level to the third control node in response to a reset signal;

[0041] The fourth reset circuit is connected to the second output terminal, and is configured to respond to a reset signal to input an invalid level to the second output terminal.

[0042] In an exemplary embodiment of the present disclosure, the first reset circuit is further connected to a first reset signal terminal and a first power supply terminal, and the first reset circuit is configured to input an invalid level to the first control node via the first power supply terminal in response to a signal from the first reset signal terminal.

[0043] In an exemplary embodiment of the present disclosure, the first reset circuit includes:

[0044] A twenty-first transistor has a first electrode connected to the first power supply terminal, a second electrode connected to the first control node, and a gate connected to the first reset signal terminal.

[0045] In an exemplary embodiment of the present disclosure, the first reset circuit is further connected to a second control node and a first power supply terminal, and the first reset circuit is configured to input an invalid level to the first control node using the first power supply terminal in response to a signal from the second control node.

[0046] In an exemplary embodiment of the present disclosure, the first reset circuit includes:

[0047] A twenty-first transistor has a first electrode connected to the first power supply terminal, a second electrode connected to the first control node, and a gate connected to the second control node.

[0048] In an exemplary embodiment of the present disclosure, the second reset circuit is further connected to a second reset signal terminal, and the second reset circuit is configured to respond to a signal at the second reset signal terminal to turn off the fourth node and the third control node;

[0049] The second reset circuit comprises:

[0050] The twenty-second transistor has a first electrode connected to the fourth node, a second electrode connected to the third control node, and a gate connected to the second reset signal terminal.

[0051] In an exemplary embodiment of the present disclosure, the third reset circuit is further connected to the first power supply terminal and the first reset signal terminal, and the third reset circuit is configured to respond to a signal from the first reset signal terminal to input an invalid level to the third control node using the first power supply terminal;

[0052] The third reset circuit includes:

[0053] The twenty-third transistor has a first electrode connected to the first power supply terminal, a second electrode connected to the third control node, and a gate connected to the first reset signal terminal.

[0054] In an exemplary embodiment of the present disclosure, the third reset circuit is also connected to the first power supply terminal, the second power supply terminal, the second reset signal terminal, and the fifth node. The third reset circuit is used to respond to the signal of the second reset signal terminal to transmit the signal of the first power supply terminal to the fifth node, to respond to the signal of the second power supply terminal to transmit the signal of the second power supply terminal to the fifth node, and to respond to the signal of the fifth node to transmit the signal of the first power supply terminal to the third control node.

[0055] In an exemplary embodiment of the present disclosure, the third reset circuit includes:

[0056] a twenty-third transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the third control node, and a gate connected to the fifth node;

[0057] A twenty-fourth transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the fifth node, and a gate connected to the second power supply terminal;

[0058] The twenty-fifth transistor has a first electrode connected to the first power supply terminal, a second electrode connected to the fifth node, and a gate connected to the second reset signal terminal.

[0059] In an exemplary embodiment of the present disclosure, the fourth reset circuit is further connected to the first reset signal terminal and the first power supply terminal, and the fourth reset circuit is configured to respond to a signal from the first reset signal terminal and input an invalid level to the second output terminal using the first power supply terminal;

[0060] The fourth reset circuit includes:

[0061] The twenty-sixth transistor has a first electrode connected to the first power supply terminal, a second electrode connected to the second output terminal, and a gate connected to the first reset signal terminal.

[0062] In an exemplary embodiment of the present disclosure, the shift register unit is applied to a gate driving circuit in a display panel, the gate driving circuit includes a plurality of cascaded shift register units, the display panel includes a pixel driving circuit, and the second output circuit is used to provide an input signal to a lower-level shift register unit;

[0063] The shift register unit further includes:

[0064] The first output circuit is electrically connected to the second output circuit, and the first output circuit is used to provide a gate driving signal to the pixel driving circuit in a first driving state, and to provide an invalid level signal to the pixel driving circuit in a second driving state.

[0065] In an exemplary embodiment of the present disclosure, the first output circuit is connected to a first control node, a second control node, and a first output terminal. The first output circuit is used to respond at least to signals of the first control node and the second control node to provide the gate drive signal or the invalid level signal to the first output terminal. The first output terminal is used to connect to a pixel drive circuit.

[0066] In an exemplary embodiment of the present disclosure, the first output circuit includes:

[0067] a first sub-output circuit connected to the second clock signal terminal, the first control node, and the first output terminal, the first sub-output circuit being configured to transmit the signal of the second clock signal terminal to the first output terminal in response to a signal of the first control node;

[0068] a second sub-output circuit connected to the first power supply terminal, the first output terminal, and a second control node, the second sub-output circuit being configured to transmit a signal from the first power supply terminal to the first output terminal in response to a signal from the second control node;

[0069] Wherein, the first clock signal terminal and the second clock signal terminal are used to output clock signals of corresponding timing in the first driving state of the first output circuit;

[0070] The second clock signal terminal is used to output an invalid level signal in the second driving state of the first output circuit.

[0071] In an exemplary embodiment of the present disclosure, the first output circuit includes:

[0072] a first sub-output circuit connected to a first clock signal terminal, a first control node, a first enable signal terminal, a first output terminal, and a first node, the first sub-output circuit being configured to respond to a signal at the first enable signal terminal to transmit a signal at the first clock signal terminal to the first node, and to respond to a signal at the first control node to transmit a signal at the first node to the first output terminal;

[0073] a second sub-output circuit connected to the first power supply terminal, the first output terminal, and a second control node, the second sub-output circuit being configured to transmit a signal from the first power supply terminal to the first output terminal in response to a signal from the second control node;

[0074] The first enable signal terminal is used to output a valid level in a first driving state of the first output circuit, and is used to output an invalid level in a second driving state of the first output circuit.

[0075] In an exemplary embodiment of the present disclosure, the first output circuit includes:

[0076] a first sub-output circuit connected to a first clock signal terminal, a first control node, a first enable signal terminal, a first output terminal, and a second node, the first sub-output circuit being configured to transmit a signal from the first control node to the second node in response to a signal from the first enable signal terminal, and to transmit a signal from the first clock signal terminal to the first output terminal in response to a signal from the second node;

[0077] a second sub-output circuit connected to the first power supply terminal, the first output terminal, and a second control node, the second sub-output circuit being configured to transmit a signal from the first power supply terminal to the first output terminal in response to a signal from the second control node;

[0078] The first enable signal terminal is used to output a valid level in a first driving state of the first output circuit, and is used to output an invalid level in a second driving state of the first output circuit.

[0079] In an exemplary embodiment of the present disclosure, the first output circuit further includes:

[0080] a first control circuit connected to the first power supply terminal, the second enable signal terminal, and the second node, the first control circuit being configured to transmit the signal of the first power supply terminal to the second node in response to a signal of the second enable signal terminal;

[0081] The second enable signal terminal is used to output an invalid level in a first driving state of the first output circuit, and is used to output a valid level in a second driving state of the first output circuit.

[0082] In an exemplary embodiment of the present disclosure, the second sub-output circuit is further connected to a third clock signal terminal, and the second sub-output circuit is further configured to respond to a signal from the third clock signal terminal to transmit a signal from the first power terminal to the first output terminal.

[0083] In an exemplary embodiment of the present disclosure, the first sub-output circuit includes:

[0084] a fifth transistor, having a first electrode connected to the second clock signal terminal, a second electrode connected to the first output terminal, and a gate connected to the first control node;

[0085] A first capacitor has a first electrode connected to the first control node and a second electrode connected to the first output terminal.

[0086] In an exemplary embodiment of the present disclosure, the first sub-output circuit includes:

[0087] a fifth transistor, having a first electrode connected to the first node, a second electrode connected to the first output terminal, and a gate connected to the first control node;

[0088] a fifteenth transistor, having a first electrode connected to the first clock signal terminal, a second electrode connected to the first node, and a gate connected to the first enable signal terminal;

[0089] A first capacitor has a first electrode connected to the first control node and a second electrode connected to the first output terminal.

[0090] In an exemplary embodiment of the present disclosure, the first sub-output circuit includes:

[0091] a fifth transistor, having a first electrode connected to the first clock signal terminal, a second electrode connected to the first output terminal, and a gate connected to the second node;

[0092] a sixteenth transistor, having a first electrode connected to the first control node, a second electrode connected to the second node, and a gate connected to the first enable signal terminal;

[0093] a first capacitor, a first electrode of which is connected to the second node, and a second electrode of which is connected to the first output terminal;

[0094] The first control circuit includes:

[0095] The fifteenth transistor has a first electrode connected to the first power supply terminal, a second electrode connected to the second node, and a gate connected to the second enable signal terminal.

[0096] In an exemplary embodiment of the present disclosure, the second sub-output circuit includes:

[0097] a fourth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the first output terminal, and a gate connected to the second control node;

[0098] a ninth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the first output terminal, and a gate connected to the third clock signal terminal;

[0099] A second capacitor has a first electrode connected to the second control node and a second electrode connected to the first power supply terminal.

[0100] In an exemplary embodiment of the present disclosure, the duty cycle of the effective level on the first clock signal terminal is greater than the duty cycle of the effective level on the second clock signal terminal.

[0101] In an exemplary embodiment of the present disclosure, the shift register unit is applied to a gate driving circuit in a display panel, and the reset circuit is used to be turned on before the next frame.

[0102] In an exemplary embodiment of the present disclosure, the driving method of the display panel includes a blank period between frames, and the reset circuit is configured to be turned on during the blank period.

[0103] In an exemplary embodiment of the present disclosure, when the first output circuit is in the first driving state, the pulse frequency of the effective level on the first clock signal terminal is n1;

[0104] When the first output circuit is in the second driving state, the pulse frequency of the effective level on the first clock signal terminal is n2;

[0105] Among them, n1 is greater than or equal to n2.

[0106] According to one aspect of the present disclosure, a gate driving circuit is provided, wherein the gate driving circuit includes a plurality of the above-mentioned shift register units, and the plurality of shift register units are cascaded.

[0107] In an exemplary embodiment of the present disclosure, the gate driving circuit includes:

[0108] a plurality of shift register unit groups, each of the shift register unit groups comprising a plurality of cascaded shift register units;

[0109] a switch unit, wherein two cascaded shift register units located in different shift register unit groups are cascaded via the switch unit;

[0110] Wherein, the first-stage shift register unit in each of the shift register unit groups is connected to a different initialization signal terminal.

[0111] According to one aspect of the present disclosure, a display panel is provided, wherein the display panel includes the above-mentioned gate driving circuit.

[0112] According to one aspect of the present disclosure, a display panel driving method is provided, wherein the method is used to drive the above-mentioned display panel, wherein the driving method includes:

[0113] In the same time period, respectively controlling the number of frames in which the shift register units corresponding to different display areas in the display panel are in the second driving state;

[0114] The refresh frequency of the display area corresponding to the shift register unit with a smaller frame number in the second driving state is greater than the refresh frequency of the display area corresponding to the shift register unit with a larger frame number in the second driving state.

[0115] In an exemplary embodiment of the present disclosure, at least a portion of the low-frequency display area forms a tail scanning area of ​​the display panel. In the same frame, the driving method includes:

[0116] When the shift register unit corresponding to the low-frequency display area forming the last scanning area is in the second driving state, the pulse frequency of the effective level on the first clock signal end is set to n2;

[0117] When the shift register unit corresponding to the high-frequency display area is in the first driving state, the pulse frequency of the effective level on the first clock signal end is set to n1;

[0118] Among them, n1 is greater than or equal to n2.

[0119] In an exemplary embodiment of the present disclosure, the display panel includes a plurality of sub-display areas, and the gate driving circuit includes:

[0120] a plurality of shift register unit groups, each of the shift register unit groups comprising a plurality of cascaded shift register units, each of the shift register unit groups being arranged corresponding to the sub-display areas, and each of the shift register unit groups being configured to provide a gate drive signal to the corresponding sub-display area;

[0121] a switch unit, wherein two cascaded shift register units located in different shift register unit groups are cascaded via the switch unit;

[0122] Wherein, the first-stage shift register unit in each of the shift register unit groups is connected to a different initialization signal terminal;

[0123] At least part of the low-frequency display area forms the end scanning area of ​​the sub-display area. In the same frame of the same sub-display area, the driving method includes:

[0124] When the shift register unit corresponding to the low-frequency display area forming the last scanning area is in the second driving state, the pulse frequency of the effective level on the first clock signal end is set to n2;

[0125] When the shift register unit corresponding to the high-frequency display area is in the first driving state, the pulse frequency of the effective level on the first clock signal end is set to n1;

[0126] Among them, n1 is greater than or equal to n2.

[0127] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0128] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0129] FIG1 is a schematic structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0130] FIG2 is a schematic structural diagram of an exemplary embodiment of a shift register unit disclosed herein;

[0131] FIG3 is a timing diagram of each node in a driving method of a shift register unit disclosed in the present invention;

[0132] FIG4 is a schematic structural diagram of another exemplary embodiment of a shift register unit disclosed herein;

[0133] FIG5 is a schematic structural diagram of another exemplary embodiment of a shift register unit disclosed herein;

[0134] FIG6 is a timing diagram of each node in a driving method of the shift register unit disclosed in the present invention;

[0135] FIG7 is a timing diagram of each node of the shift register unit in different display areas of the display panel of the present disclosure;

[0136] FIG8 is a schematic structural diagram of another exemplary embodiment of a shift register unit disclosed herein;

[0137] FIG9 is a timing diagram of each node of the shift register unit in different display areas of the display panel of the present disclosure;

[0138] FIG10 is a schematic structural diagram of another exemplary embodiment of a shift register unit disclosed herein;

[0139] FIG11 is a timing diagram of each node of the shift register unit in different display areas of the display panel of the present disclosure;

[0140] FIG12 is a schematic structural diagram of an exemplary embodiment of a gate driving circuit disclosed herein;

[0141] FIG13 is a timing diagram of various signal lines and nodes in an exemplary embodiment of a display panel driving method disclosed herein;

[0142] FIG14 is a schematic structural diagram of another exemplary embodiment of a shift register unit disclosed herein;

[0143] FIG15 is a schematic structural diagram of another exemplary embodiment of a shift register unit disclosed herein;

[0144] FIG16 is a schematic structural diagram of another exemplary embodiment of a shift register unit disclosed herein;

[0145] FIG17 is a schematic structural diagram of another exemplary embodiment of a shift register unit disclosed herein;

[0146] FIG18 is a schematic structural diagram of another exemplary embodiment of the gate driving circuit disclosed herein;

[0147] FIG19 is a schematic structural diagram of another exemplary embodiment of the gate driving circuit disclosed herein. DETAILED DESCRIPTION

[0148] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent like or similar structures, and thus their detailed description will be omitted.

[0149] The terms "a", "an", and "said" are used to indicate that there are one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0150] As shown in Figure 1, it is a schematic diagram of the structure of an exemplary embodiment of the display panel of the present disclosure. The display panel may include a timing controller, a source driving circuit, a gate driving circuit and a pixel array. The timing controller is respectively connected to the source driving circuit and the gate driving circuit, and the source driving circuit is respectively connected to a plurality of data signal lines (Da1 to Dan). The gate driving circuit includes: a scanning driving circuit and a light-emitting driving circuit. The scanning driving circuit is respectively connected to a plurality of scanning signal lines (S1 to Sm), and the light-emitting driving circuit is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit, the circuit unit may include a pixel driving circuit, and the pixel driving circuit may be respectively connected to the scanning signal line, the light-emitting signal line and the data signal line. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the source driver circuit to the source driver circuit, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver circuit to the scan driver circuit, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver circuit to the light-emitting driver circuit. The source driver circuit may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines Da1, Da2, Da3, ..., and Dan. For example, the source driver circuit may use the clock signal to sample the grayscale values ​​and apply data voltages corresponding to the grayscale values ​​to data signal lines Da1 to Dan in units of pixel rows, where n may be a natural number. The scan driver circuit may generate scan signals to be provided to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver circuit may sequentially provide scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan drive circuit can be constructed in the form of a shift register and can generate a scan signal by sequentially transmitting a scan start signal provided in the form of an on-level pulse to the next stage circuit under the control of a clock signal, and m can be a natural number. The light-emitting drive circuit can generate an emission signal to be provided to the light-emitting signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the light-emitting drive circuit can sequentially provide an emission signal with an off-level pulse to the light-emitting signal lines E1 to Eo. For example, the light-emitting drive circuit can be constructed in the form of a shift register and can generate an emission signal by sequentially transmitting an emission stop signal provided in the form of an off-level pulse to the next stage circuit under the control of a clock signal, and o can be a natural number.

[0151] As shown in Figure 2, it is a structural diagram of an exemplary embodiment of the shift register unit of the present disclosure. The shift register unit includes: an input circuit 2, a second control circuit 3, a third control circuit 4, a fourth control circuit 5, and a second output circuit 12. The input circuit 2 is connected to the input signal terminal IN, the fourth node N4, and the third clock signal terminal CK. The input circuit 2 is used to respond to the signal of the third clock signal terminal CK to transmit the input signal of the input signal terminal IN to the fourth node N4; the second control circuit 3 is connected to the third control node PU3, the first clock signal terminal CB, the second control node PD, and the first power supply terminal VGL. The third control node PU3 is connected to the fourth node N4. The second control circuit 3 is used to respond to the signal of the first clock signal terminal CB and the second control node PD to transmit the signal of the first power supply terminal VGL to the third control node PU3; the third control circuit 4 is connected to the third control node PU3, the first power supply terminal VGL, and the second control node PD. The third control circuit 4 is used to respond to the signal of the third control node PU3 to transmit the signal of the first power supply terminal VGL to the third control node PU3. A signal from a power supply terminal VGL is transmitted to the second control node PD; the fourth control circuit 5 is connected to the third control node PU3, the first clock signal terminal CB, and the second control node PD, and the fourth control circuit 5 is used to respond to the signals from the first clock signal terminal CB and the third control node PU3 to control the voltage of the second control node PD; the second output circuit 12 is connected to the first control node PU1, the second control node PD, the second output terminal OUT2, and the first clock signal terminal CB, the first control node PU1 is connected to the third control node PU3, the second output circuit 12 is used to respond to the signal from the first control node PU1 to transmit the signal from the first clock signal terminal CB to the second output terminal OUT2, and to respond to the signal from the second control node PD to input an invalid level to the second output terminal OUT2.

[0152] In this exemplary embodiment, the first clock signal terminal CB and the third clock signal terminal CK are set so that the second output terminal OUT2 meets the requirements of the gate drive circuit. For example, in this exemplary embodiment, the high bias voltage duration of some transistors in the gate drive circuit can be reduced through the setting of the first clock signal terminal CB and the third clock signal terminal CK, thereby improving the reliability of the gate drive circuit.

[0153] In this exemplary embodiment, as shown in FIG2 , the second output circuit 12 is further connected to the third clock signal terminal CK. The second output circuit 12 is configured to respond to the signal of the third clock signal terminal CK to transmit the signal of the first power supply terminal VGL to the second output terminal OUT2. In this exemplary embodiment, when the first clock signal terminal CB outputs an inactive level, the third clock signal terminal CK outputs an active level. After the second output terminal OUT2 outputs an active level, the inactive level can be maintained until the next active level is output. This setting can reduce noise at the second output terminal OUT2. In this exemplary embodiment, the active level signal is a signal that can drive the target circuit to conduct, and the inactive level signal is a signal that drives the target circuit to shut down. For example, when the target circuit is an N-type transistor, the active level signal is a high level signal, and the inactive level signal is a low level signal.

[0154] In this exemplary embodiment, as shown in Figure 2, the fourth control circuit 5 is also connected to the third node N3 and the first power supply terminal VGL. The fourth control circuit 5 is used to respond to the signal of the third control node PU3 to transmit the signal of the first power supply terminal VGL to the third node N3, to respond to the signal of the first clock signal terminal CB to input a valid level signal to the third node N3, and to respond to the signal of the third node N3 to input a valid level signal to the second control node PD.

[0155] In this exemplary embodiment, as shown in FIG2 , the shift register unit further includes an isolation circuit 6 , wherein the isolation circuit 6 is connected to the first control node PU1 and the third control node PU3 , and the isolation circuit is configured to connect the first control node PU1 and the third control node PU3 in response to a control signal. In this exemplary embodiment, the isolation circuit 6 can be connected to the third clock signal terminal CK, and the isolation circuit is configured to connect the first control node PU1 and the third control node PU3 in response to a signal from the third clock signal terminal CK. The isolation circuit 6 can reduce leakage current from the first control node PU1 to the input signal terminal IN. It should be understood that the isolation circuit 6 can also connect the first control node PU1 and the third control node PU3 in response to other signals. For example, the isolation circuit 6 can be connected to an effective power supply terminal, that is, the isolation circuit 6 is always on.

[0156] In this exemplary embodiment, as shown in FIG2 , the second output circuit 12 is further connected to the first power supply terminal VGL. The second output circuit 12 is configured to input an inactive level to the second output terminal OUT2 using the first power supply terminal VGL in response to a signal at the second control node PD. The second output circuit 12 includes: a twelfth transistor T12, a third capacitor C3, a thirteenth transistor T13, and a fourteenth transistor T14. The twelfth transistor T12 has a first electrode connected to the first clock signal terminal CB, a second electrode connected to the second output terminal OUT2, and a gate connected to the first control node PU1; the third capacitor C3 has a first electrode connected to the first control node PU1, and a second electrode connected to the second output terminal OUT2; the thirteenth transistor T13 has a first electrode connected to the first power supply terminal VGL, a second electrode connected to the second output terminal OUT2, and a gate connected to the second control node PD; and the fourteenth transistor T14 has a first electrode connected to the first power supply terminal VGL, a second electrode connected to the second output terminal OUT2, and a gate connected to the third clock signal terminal CK.

[0157] In this exemplary embodiment, as shown in FIG2 , the input circuit 2 includes: a first transistor T1, wherein a first electrode of the first transistor T1 is connected to the input signal terminal IN, a second electrode is connected to the fourth node N4, and a gate is connected to the third clock signal terminal CK; the isolation circuit includes: an eighth transistor T8, wherein a first electrode of the eighth transistor T8 is connected to the third control node PU3, a second electrode is connected to the first control node PU1, and a gate is connected to the third clock signal terminal CK; the second control circuit 3 includes: a sixth transistor T6 and a seventh transistor T7, wherein a first electrode of the sixth transistor T6 is connected to the first power supply terminal VGL, and a gate is connected to the second control node PD; a first electrode of the seventh transistor T7 is connected to the second electrode of the sixth transistor T6, a second electrode is connected to the third control node PU3, and a gate is connected to the first clock signal terminal CB; and the third control circuit 4 includes: an eleventh transistor T11, wherein a first electrode of the eleventh transistor T11 is connected to the first power supply terminal VGL , the second electrode is connected to the second control node PD, and the gate is connected to the third control node PU3; the fourth control circuit 5 is used to respond to the signal of the first clock signal terminal CB and input a valid level signal to the third node N3 using the first clock signal terminal CB, and is used to respond to the signal of the third node N3 and input a valid level signal to the second control node PD using the first clock signal terminal CB. The fourth control circuit 5 includes: a third transistor T3, a second transistor T2, and a tenth transistor T10. The first electrode of the third transistor T3 is connected to the first power supply terminal VGL, the second electrode is connected to the third node N3, and the gate is connected to the third control node PU3; the first electrode of the second transistor T2 is connected to the first clock signal terminal CB, the second electrode is connected to the third node N3, and the gate is connected to the first clock signal terminal CB; the first electrode of the tenth transistor T10 is connected to the first clock signal terminal CB, the second electrode is connected to the second control node PD, and the gate is connected to the third node N3.

[0158] As shown in Figure 2, each transistor in the shift register unit can be an N-type transistor, and accordingly, the first power supply terminal is a low-level power supply terminal. It should be understood that in other exemplary embodiments, the transistors in the shift register unit can also be P-type transistors.

[0159] Figure 3 shows the timing diagram of each node in a driving method for a shift register unit disclosed herein. CK is the timing diagram of the third clock signal terminal, CB is the timing diagram of the first clock signal terminal, IN is the timing diagram of the input signal terminal, OUT2 is the timing diagram of the second output terminal, PD is the timing diagram of the second control node, PU3 is the timing diagram of the third control node, and PU1 is the timing diagram of the first control node.

[0160] The driving method of the shift register unit includes: a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, and a fifth stage t5.

[0161] In the first phase t1, the input signal terminal IN and the third clock signal terminal CK output high-level signals, the first clock signal terminal CB outputs a low-level signal, the first transistor T1 is turned on, and the high-level signal of the input signal terminal IN is transmitted to the third control node PU3. The eighth transistor T8 is turned on, and the third control node PU3 inputs a high-level signal to the first control node PU1. The twelfth transistor T12 is turned on, and the first clock signal terminal CB inputs a low-level signal to the second output terminal OUT2. Simultaneously, the third transistor T3 and the eleventh transistor T11 are turned on, and the low-level signal of the first power supply terminal VGL is transmitted to the second control node PD and the third node N3. The tenth transistor T10 and the thirteenth transistor T13 are turned off, and the fourteenth transistor T14 is turned on. The first power supply terminal VGL inputs a low-level signal to the second output terminal OUT2. The second output terminal OUT2 outputs a low level.

[0162] In the second phase t2, the input signal terminal IN and the third clock signal terminal CK output low-level signals, the first clock signal terminal CB outputs a high-level signal, the first control node PU1 and the third control node PU3 maintain high levels, the twelfth transistor T12 is turned on, the first clock signal terminal CB inputs a high-level signal to the second output terminal OUT2, the third transistor T3 and the eleventh transistor T11 are turned on, the first power supply terminal VGL inputs a low-level signal to the second control node PD and the third node N3, the thirteenth transistor T13 and the fourteenth transistor T14 are both turned off, and the second output terminal OUT2 outputs a high-level signal.

[0163] In the third phase t3, the input signal terminal IN and the first clock signal terminal CB output low-level signals, the third clock signal terminal CK outputs a high-level signal, the first transistor T1 and the eighth transistor T8 are turned on, the input signal terminal IN inputs a low-level signal to the third control node PU3 and the first control node PU1, the third transistor T3 and the eleventh transistor T11 are turned off, the fourteenth transistor T14 is turned on, and the first power supply terminal VGL inputs a low-level signal to the second output terminal OUT2. The second output terminal OUT2 outputs a low level.

[0164] In the fourth stage t4: the input signal terminal IN and the third clock signal terminal CK output low-level signals, the first clock signal terminal CB outputs a high-level signal, the first control node PU1 and the third control node PU3 maintain a low level, the third transistor T3 and the eleventh transistor T11 are turned off, the second transistor T2 is turned on, the first clock signal terminal CB inputs a high-level signal to the third node N3, the tenth transistor T10 is turned on, the first clock signal terminal CB inputs a high-level signal to the second control node PD, the thirteenth transistor T13 is turned on, the first power supply terminal VGL inputs a low-level signal to the second output terminal OUT2, and the second output terminal OUT2 outputs a low-level signal.

[0165] In the fifth stage t5: the input signal terminal IN and the first clock signal terminal CB output low-level signals, the third clock signal terminal CK outputs a high-level signal, the first transistor T1 and the eighth transistor T8 are turned on, the input signal terminal IN inputs a low-level signal to the third control node PU3 and the first control node PU1, the third transistor T3 and the eleventh transistor T11 are turned off, the fourteenth transistor T14 is turned on, the first power supply terminal VGL inputs a low-level signal to the second output terminal OUT2, and the second output terminal OUT2 outputs a low level.

[0166] Thereafter, the shift register unit may repeat the fourth stage and the fifth stage in sequence, and the second output terminal OUT2 maintains a low level.

[0167] As shown in Figure 2, the thirteenth transistor T13, the fourteenth transistor T14, and the eighth transistor T8 are turned off in part of the time period. For example, the thirteenth transistor T13, the fourteenth transistor T14, and the eighth transistor T8 are turned off in the second stage t2. This setting can reduce the high bias voltage duration of the thirteenth transistor T13, the fourteenth transistor T14, and the eighth transistor T8, thereby improving the reliability of the gate drive circuit.

[0168] In this exemplary embodiment, a shift register unit is used in a gate drive circuit of a display panel. The gate drive circuit includes multiple cascaded shift register units, and the display panel includes a pixel drive circuit. As shown in FIG2 , the second output terminal OUT2 can provide an input signal to a lower-level shift register unit and also provide a gate drive signal to the pixel drive circuit.

[0169] In this exemplary embodiment, as shown in FIG4 , a schematic diagram of the structure of another exemplary embodiment of the shift register unit disclosed herein is provided. The second output circuit 12 is configured to provide an input signal to the lower-level shift register unit. The shift register unit further includes a first output circuit 11 electrically connected to the second output circuit 12. The first output circuit 11 is configured to provide a gate drive signal to the pixel drive circuit in a first drive state and to provide an inactive level signal to the pixel drive circuit in a second drive state.

[0170] In this exemplary embodiment, the first output circuit and the second output circuit are designed independently. The second output circuit can normally provide input signals to the lower-level shift register unit, and the first output circuit can normally output gate drive signals when the pixel drive circuit needs to be refreshed, and output an invalid level signal when the pixel drive circuit does not need to be refreshed. This exemplary embodiment can adjust the refresh frequency of a local area of ​​the display panel, as well as adjust the refresh frequency of the same display area at different time periods. Specifically, when the refresh frequency required for a local area or part of the display screen is low, the display panel can reduce the power consumption of the display panel by reducing the refresh frequency of the local area or part of the display screen.

[0171] It should be noted that, in this exemplary embodiment, the gate drive signal includes an effective level period and an invalid level period, that is, the effective level and invalid level output by the shift register unit for a certain period of time (for example, in a frame) together constitute the gate drive signal. In this exemplary embodiment, the effective level signal is a signal that can drive the target circuit to turn on, and the invalid level signal is a signal that drives the target circuit to turn off. For example, when the target circuit is an N-type transistor, the effective level signal is a high level signal, and the invalid level signal is a low level signal. The second output circuit 12 is used to provide an input signal to the lower-level shift register unit, wherein the lower-level shift register unit can be an adjacent next-level shift register unit or an interval lower-level shift register unit. The first driving state is the driving state when the first output circuit normally provides the gate drive signal, and the second driving state is the driving state when the first output circuit provides an invalid level signal.

[0172] In this exemplary embodiment, the timing of the input signal and the gate drive signal can be the same or different. For example, when the pixel drive circuit does not need to be refreshed, the first output circuit outputs an invalid level signal (e.g., a low level), while the second output circuit 12 is used to provide an input signal (e.g., a high level) to the lower-level shift register unit.

[0173] In this exemplary embodiment, as shown in FIG5 , which is a schematic diagram of the structure of another exemplary embodiment of the shift register unit disclosed herein, a first output circuit 11 is connected to a first control node PU1, a second control node PD, and a first output terminal OUT1. The first output circuit 11 is configured to respond to at least signals from the first control node PU1 and the second control node PD to provide a gate drive signal or an inactive level signal to the first output terminal OUT1. The first output terminal OUT1 is configured to be connected to a pixel drive circuit.

[0174] For example, the second output terminal OUT2 is used to provide an input signal to the lower-stage shift register unit. The active level input to the second output terminal OUT2 is a level that can turn on the target circuit connected to the second output terminal OUT2, and the inactive level input to the second output terminal OUT2 is a level that can turn off the target circuit connected to the second output terminal OUT2. Similarly, the first output terminal OUT1 is used to provide a gate drive signal to the pixel drive circuit. The active level input to the first output terminal OUT1 is a level that can turn on the target circuit connected to the first output terminal OUT1, and the inactive level input to the first output terminal OUT1 is a level that can turn off the target circuit connected to the first output terminal OUT1.

[0175] In this exemplary embodiment, as shown in FIG5 , the first output circuit 11 includes: a first sub-output circuit 111 and a second sub-output circuit 112. The first sub-output circuit 111 is connected to the second clock signal terminal CB2, the first control node PU1, and the first output terminal OUT1. The first sub-output circuit 111 is configured to transmit the signal of the second clock signal terminal CB2 to the first output terminal OUT1 in response to a signal of the first control node PU1. The second sub-output circuit 112 is connected to the first power supply terminal VGL, the first output terminal OUT1, and the second control node PD. The second sub-output circuit 112 is configured to transmit the signal of the first power supply terminal VGL to the first output terminal OUT1 in response to a signal of the second control node PD. The first power supply terminal VGL is configured to provide an inactive level signal. The first clock signal terminal CB and the second clock signal terminal CB2 are configured to output clock signals of corresponding timings in the first driving state of the first output circuit 11, that is, the first clock signal terminal CB and the second clock signal terminal CB2 are configured to output clock signals of the same timing or substantially the same timing in the first driving state of the first output circuit 11. The timings of the active levels on the first clock signal terminal CB and the second clock signal terminal CB2 at least partially overlap. The second clock signal terminal CB2 is used to output an inactive level signal in the second driving state of the first output circuit 11. When the first clock signal terminal CB and the second clock signal terminal CB2 output clock signals of corresponding timings, the first output circuit 11 is in the first driving state, and when the second clock signal terminal CB2 outputs an inactive level signal, the first output circuit 11 is in the second driving state.

[0176] In this exemplary embodiment, as shown in Figure 5, the first sub-output circuit 111 includes: a fifth transistor T5 and a first capacitor C1, the first electrode of the fifth transistor T5 is connected to the second clock signal terminal CB2, the second electrode is connected to the first output terminal OUT1, and the gate is connected to the first control node PU1; the first electrode of the first capacitor C1 is connected to the first control node PU1, and the second electrode is connected to the first output terminal OUT1.

[0177] As shown in Figure 5, the second sub-output circuit 112 includes: a fourth transistor T4, a ninth transistor T9, and a second capacitor C2. The first electrode of the fourth transistor T4 is connected to the first power supply terminal VGL, the second electrode is connected to the first output terminal OUT1, and the gate is connected to the second control node PD; the first electrode of the ninth transistor T9 is connected to the first power supply terminal VGL, the second electrode is connected to the first output terminal OUT1, and the gate is connected to the third clock signal terminal CK; the first electrode of the second capacitor C2 is connected to the second control node PD, and the second electrode is connected to the first power supply terminal VGL.

[0178] As shown in Figure 5, each transistor in the shift register unit is an N-type transistor, and accordingly, the first power supply terminal is a low-level power supply terminal. It should be understood that in other exemplary embodiments, the transistors in the shift register unit may also be P-type transistors.

[0179] As shown in Figure 6, it is a timing diagram of each node in a driving method of the shift register unit disclosed in the present invention. Among them, CB2 is the timing diagram of the second clock signal terminal, CK is the timing diagram of the third clock signal terminal, CB is the timing diagram of the first clock signal terminal, IN is the timing diagram of the input signal terminal, OUT1 is the timing diagram of the first output terminal, OUT2 is the timing diagram of the second output terminal, PD is the timing diagram of the second control node, PU3 is the timing diagram of the third control node, and PU1 is the timing diagram of the first control node.

[0180] The driving method of the shift register unit includes: a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, and a fifth stage t5.

[0181] In the first stage t1: the input signal terminal IN and the third clock signal terminal CK output high-level signals, the first clock signal terminal CB and the second clock signal terminal CB2 output low-level signals, the first transistor T1 is turned on, the high-level signal of the input signal terminal IN is transmitted to the third control node PU3, the eighth transistor T8 is turned on, the third control node PU3 inputs a high-level signal to the first control node PU1, the twelfth transistor T12 and the fifth transistor T5 are turned on, the first clock signal terminal CB inputs a low-level signal to the second output terminal OUT2, and the second clock signal terminal CB2 inputs a low-level signal to the first output terminal OUT1; at the same time, the third transistor T3 and the eleventh transistor T11 are turned on, the low-level signal of the first power supply terminal VGL is transmitted to the second control node PD and the third node N3, the tenth transistor T10, the thirteenth transistor T13, and the fourth transistor T4 are turned off, the fourteenth transistor T14 and the ninth transistor T9 are turned on, and the first power supply terminal VGL inputs a low-level signal to the first output terminal OUT1 and the second output terminal OUT2. That is, the first and second sub-output circuits 111 and 112 input a low level to the first output terminal OUT1, and the third and fourth sub-output circuits 123 and 124 input a low level to the second output terminal OUT2.

[0182] In the second phase t2, the input signal terminal IN and the third clock signal terminal CK output low-level signals, the first clock signal terminal CB and the second clock signal terminal CB2 output high-level signals, the first control node PU1 and the third control node PU3 maintain a high level, the twelfth transistor T12 and the fifth transistor T5 are turned on, the first clock signal terminal CB inputs a high-level signal to the second output terminal OUT2, the second clock signal terminal CB2 inputs a high-level signal to the first output terminal OUT1, the third transistor T3 and the eleventh transistor T11 are turned on, the first power supply terminal VGL inputs a low-level signal to the second control node PD and the third node N3, the thirteenth transistor T13, the fourteenth transistor T14, the fourth transistor T4, and the ninth transistor T9 are all turned off. The first output terminal OUT1 and the second output terminal OUT2 output a high level.

[0183] In the third phase t3, the input signal terminal IN, the first clock signal terminal CB, and the second clock signal terminal CB2 output low-level signals, the third clock signal terminal CK outputs a high-level signal, the first transistor T1 and the eighth transistor T8 are turned on, the input signal terminal IN inputs a low-level signal to the third control node PU3 and the first control node PU1, the third transistor T3 and the eleventh transistor T11 are turned off, the fourteenth transistor T14 and the ninth transistor T9 are turned on, and the first power supply terminal VGL inputs low-level signals to the first output terminal OUT1 and the second output terminal OUT2, respectively. The first output terminal OUT1 and the second output terminal OUT2 output low levels.

[0184] In the fourth stage t4: the input signal terminal IN and the third clock signal terminal CK output low-level signals, the first clock signal terminal CB and the second clock signal terminal CB2 output high-level signals, the first control node PU1 and the third control node PU3 maintain a low level, the third transistor T3 and the eleventh transistor T11 are turned off, the second transistor T2 is turned on, the first clock signal terminal CB inputs a high-level signal to the third node N3, the tenth transistor T10 is turned on, the first clock signal terminal CB inputs a high-level signal to the second control node PD, the thirteenth transistor T13 and the fourth transistor T4 are turned on, and the first power supply terminal VGL inputs low-level signals to the first output terminal OUT1 and the second output terminal OUT2 respectively.

[0185] In the fifth stage t5: the input signal terminal IN, the first clock signal terminal CB, and the second clock signal terminal CB2 output low-level signals, the third clock signal terminal CK outputs a high-level signal, the first transistor T1 and the eighth transistor T8 are turned on, the input signal terminal IN inputs a low-level signal to the third control node PU3 and the first control node PU1, the third transistor T3 and the eleventh transistor T11 are turned off, the fourteenth transistor T14 and the ninth transistor T9 are turned on, and the first power supply terminal VGL inputs low-level signals to the first output terminal OUT1 and the second output terminal OUT2, respectively. The first output terminal OUT1 and the second output terminal OUT2 output low levels.

[0186] Thereafter, the shift register unit may repeat the fourth stage and the fifth stage in sequence, and the first output terminal OUT1 and the second output terminal OUT2 maintain a low level.

[0187] This exemplary embodiment can adjust the refresh frequency of the pixel driving circuit corresponding to the shift register unit by controlling the timing of the second clock signal terminal CB2. As shown in FIG7 , a timing diagram of each node of the shift register unit in different display areas of the display panel disclosed herein is shown. FIG7 illustrates the timing diagram of each signal terminal in a frame, where CB is the timing diagram of the first clock signal terminal, CB2 is the timing diagram of the second clock signal terminal, and CK is the timing diagram of the third clock signal terminal. A method for driving a display panel using this shift register unit may include: controlling the number of frames in which the shift register unit corresponding to different display areas of the display panel is in the second driving state within the same time period; wherein the refresh frequency of the display area corresponding to the shift register unit with a smaller number of frames in the second driving state is greater than the refresh frequency of the display area corresponding to the shift register unit with a larger number of frames in the second driving state. That is, this exemplary embodiment can utilize the second clock signal terminal CB2 to output a low-level signal in some frames, causing the shift register unit to continuously output a low-level signal throughout the frame, thereby reducing the refresh frequency of the display area corresponding to the shift register unit. As shown in FIG7 , the refresh frequency of the first display area will be lower than the refresh frequency of the second display area. The display area corresponding to the shift register unit refers to the display area where the pixel driving circuit connected to the shift register unit is located.

[0188] It should be understood that in other exemplary embodiments, this exemplary embodiment can adjust the refresh frequency of the pixel driving circuit corresponding to the shift register unit by controlling the timing of the second clock signal terminal CB2, so that the display panel includes more partitions with different refresh frequencies, and the refresh frequency of each partition is different.

[0189] In some embodiments, for example, as shown in FIG7 , the second clock signal terminal CB2 is continuously at a fixed potential (e.g., a low-level signal) during a first refresh time (e.g., corresponding to a first refresh frequency of the first display area), and the first clock signal terminal CB is continuously at a periodic clock signal (e.g., a periodic clock signal with a duty cycle of approximately 50%) during the first refresh time (e.g., corresponding to the first refresh frequency of the first display area). The second clock signal terminal CB2 is a periodic clock signal (e.g., a periodic clock signal with a duty cycle of approximately 50%) during a second refresh time (e.g., corresponding to a second refresh frequency of the second display area), and the first clock signal terminal CB is a periodic clock signal (e.g., a periodic clock signal with a duty cycle of approximately 50%) during the second refresh time.

[0190] FIG8 is a schematic diagram of the structure of another exemplary embodiment of a shift register unit according to the present disclosure. One difference between the shift register unit shown in FIG8 and the shift register unit shown in FIG5 is the structure of the first sub-output circuit 111. As shown in FIG8, the first sub-output circuit 111 is connected to the first clock signal terminal CB, the first control node PU1, the first enable signal terminal EM1, the first output terminal OUT1, and the first node N1. The first sub-output circuit 111 is configured to respond to a signal from the first enable signal terminal EM1 to transmit the signal from the first clock signal terminal CB to the first node N1, and to respond to a signal from the first control node PU1 to transmit the signal from the first node N1 to the first output terminal OUT1. The first enable signal terminal EM1 is configured to output a valid level in the first driving state of the first output circuit 11, and to output an invalid level in the second driving state of the first output circuit 11. When the first enable signal terminal EM1 outputs a valid level, the first output circuit 11 is in the first driving state; when the first enable signal terminal EM1 outputs an invalid level, the first output circuit 11 is in the second driving state.

[0191] As shown in FIG8 , the first sub-output circuit 111 includes: a fifth transistor T5, a fifteenth transistor T15, and a first capacitor C1. The first electrode of the fifth transistor T5 is connected to the first node N1, the second electrode is connected to the first output terminal OUT1, and the gate is connected to the first control node PU1. The first electrode of the fifteenth transistor T15 is connected to the first clock signal terminal CB, the second electrode is connected to the first node N1, and the gate is connected to the first enable signal terminal EM1. The first electrode of the first capacitor C1 is connected to the first control node PU1, and the second electrode is connected to the first output terminal OUT1. As shown in FIG8 , each transistor in the shift register unit is an N-type transistor, and accordingly, the first power supply terminal is a low-level power supply terminal. It should be understood that in other exemplary embodiments, the transistors in the shift register unit may also be P-type transistors.

[0192] This exemplary embodiment can adjust the refresh frequency of the pixel driving circuit corresponding to the shift register unit by controlling the timing of the first enable signal terminal EM1. As shown in Figure 9, it is a timing diagram of each node of the shift register unit in different display areas of the display panel of the present disclosure. Figure 9 shows the timing diagram of each signal terminal in a frame, wherein CB is the timing diagram of the first clock signal terminal, CK is the timing diagram of the third clock signal terminal, and EM1 is the timing diagram of the first enable signal terminal. This exemplary embodiment can use the first enable signal terminal EM1 to output a low-level signal in some frames, so that the shift register unit always outputs a low-level signal in the frame, thereby reducing the refresh frequency of the display area corresponding to the shift register unit. As shown in Figure 9, the refresh frequency of the first display area will be lower than the refresh frequency of the second display area.

[0193] It should be understood that in other exemplary embodiments, this exemplary embodiment can adjust the refresh frequency of the pixel driving circuit corresponding to the shift register unit by controlling the timing of the first enable signal terminal EM1, so that the display panel includes more partitions with different refresh frequencies, and the refresh frequency of each partition is different.

[0194] The driving method of the shift register unit shown in FIG8 may also include: a first stage t1 , a second stage t2 , a third stage t3 , a fourth stage t4 , and a fifth stage t5 .

[0195] As shown in Figure 10, a schematic diagram of the structure of another exemplary embodiment of the shift register unit of the present disclosure is shown. The difference between the shift register unit shown in Figure 10 and the shift register unit shown in Figure 5 lies in the different structure of the first output circuit 11. As shown in Figure 10, the first sub-output circuit 111 is connected to the first clock signal terminal CB, the first control node PU1, the first enable signal terminal EM1, the first output terminal OUT1, and the second node N2. The first sub-output circuit 111 is used to respond to the signal of the first enable signal terminal EM1 to transmit the signal of the first control node PU1 to the second node N2, and to respond to the signal of the second node N2 to transmit the signal of the first clock signal terminal CB to the first output terminal OUT1. The first enable signal terminal EM1 is used to output a valid level in the first driving state of the first output circuit 11, and to output an invalid level in the second driving state of the first output circuit 11. When the first enable signal terminal EM1 outputs a valid level, the first output circuit 11 is in the first driving state, and when the first enable signal terminal EM1 outputs an invalid level, the first output circuit 11 is in the second driving state.

[0196] As shown in FIG10 , the first sub-output circuit 111 includes a fifth transistor T5, a sixteenth transistor T16, and a first capacitor C1. The fifth transistor T5 has a first electrode connected to the first clock signal terminal CB, a second electrode connected to the first output terminal OUT1, and a gate connected to the second node N2. The sixteenth transistor T16 has a first electrode connected to the first control node PU1, a second electrode connected to the second node N2, and a gate connected to the first enable signal terminal EM1. The first capacitor C1 has a first electrode connected to the second node N2, and a second electrode connected to the first output terminal OUT1.

[0197] This exemplary embodiment can adjust the refresh frequency of the pixel driving circuit corresponding to the shift register unit by controlling the timing of the first enable signal terminal EM1. As shown in Figure 11, it is a timing diagram of each node of the shift register unit in different display areas of the display panel of the present disclosure. Figure 11 shows the timing diagram of each signal terminal in a frame, wherein CB is the timing diagram of the first clock signal terminal, CK is the timing diagram of the third clock signal terminal, and EM1 is the timing diagram of the first enable signal terminal. This exemplary embodiment can use the first enable signal terminal EM1 to output a low-level signal in some frames, so that the shift register unit always outputs a low-level signal in the frame, thereby reducing the refresh frequency of the display area corresponding to the shift register unit. As shown in Figure 11, the refresh frequency of the first display area will be lower than the refresh frequency of the second display area.

[0198] It should be understood that in other exemplary embodiments, this exemplary embodiment may also utilize the first enable signal terminal EM1 to output a low-level signal in some frames, so that the display panel includes more partitions with different refresh frequencies, and the refresh frequency of each partition is different.

[0199] As shown in FIG10 , the first output circuit 11 may further include a first control circuit 113 connected to a first power supply terminal VGL, a second enable signal terminal EM2, and a second node N2. The first control circuit 113 is configured to respond to a signal at the second enable signal terminal EM2 to transmit the signal at the first power supply terminal VGL to the second node N2. The second enable signal terminal EM2 is configured to output an inactive level in the first driving state of the first output circuit 11 and to output an active level in the second driving state of the first output circuit 11. The first control circuit 113 may include a fifteenth transistor T15, wherein a first electrode of the fifteenth transistor T15 is connected to the first power supply terminal VGL, a second electrode is connected to the second node N2, and a gate is connected to the second enable signal terminal EM2. As shown in FIG10 , each transistor in the shift register unit is an N-type transistor, and accordingly, the first power supply terminal is a low-level power supply terminal. It should be understood that in other exemplary embodiments, the transistors in the shift register unit may also be P-type transistors.

[0200] As shown in FIG11 , when the first enable signal terminal EM1 outputs a high-level signal and the second enable signal terminal EM2 outputs a low-level signal, the first control circuit 113 does not affect the normal driving of the shift register unit. When the first enable signal terminal EM1 outputs a low-level signal and the second enable signal terminal EM2 outputs a high-level signal, the first control circuit 113 can continuously input a low-level signal to the first output terminal, thereby reducing noise at the first output terminal OUT1.

[0201] The driving method of the shift register unit shown in FIG10 may also include: a first stage t1 , a second stage t2 , a third stage t3 , a fourth stage t4 , and a fifth stage t5 .

[0202] As shown in FIG. 5 , 8 and 10 , the shift register unit may not include the second capacitor C2 .

[0203] This exemplary embodiment further provides a gate driving circuit, as shown in Figure 12, which is a schematic structural diagram of an exemplary embodiment of the gate driving circuit disclosed herein. The gate driving circuit includes a plurality of the above-mentioned shift register units GOA.

[0204] As shown in FIG12 , the gate drive circuit further includes a first clock signal line LCB, a second clock signal line LCK, a third clock signal line LCK2, and a fourth clock signal line LCB2. The first clock signal line LCB is used to provide a clock signal to the first clock signal terminal CB of the odd-numbered shift register unit and the third clock signal terminal CK of the even-numbered shift register unit; the second clock signal line LCK is used to provide a clock signal to the first clock signal terminal CB of the even-numbered shift register unit and the third clock signal terminal of the odd-numbered shift register unit; the third clock signal line LCK2 is used to provide a clock signal to the second clock signal terminal of the even-numbered shift register unit; and the fourth clock signal line LCB2 is used to provide a clock signal to the second clock signal terminal of the odd-numbered shift register unit.

[0205] As shown in Figure 13, it is a timing diagram of each signal line and node in an exemplary embodiment of the display panel driving method disclosed in the present disclosure. Among them, LCK is the timing diagram of the signal on the second clock signal line, LCB is the timing diagram of the signal on the first clock signal line, STV is the timing diagram of the signal on the initial signal line, OUT2-1 represents the timing diagram of the second output end of the first-stage shift register unit, OUT2-2 represents the timing diagram of the second output end of the second-stage shift register unit, and so on. OUT2-m represents the timing diagram of the second output end of the m-th stage shift register unit. OUT1-1 represents the timing diagram of the first output end of the first-stage shift register unit, OUT1-2 represents the timing diagram of the first output end of the second-stage shift register unit, and so on. OUT1-m represents the timing diagram of the first output end of the m-th stage shift register unit.

[0206] Figure 13 shows a timing diagram of each signal line and node in three adjacent frames of the display panel. In the refresh frame, the first output circuit 11 of each shift register unit normally outputs a gate drive signal, and the second output circuit 12 of each shift register unit provides an input signal to the lower-level shift register unit. In the partial refresh frame, the display panel includes a low-frequency display area-1, a high-frequency display area, and a low-frequency display area-2. Each display area and the shift register unit connected to the pixel drive circuit therein are correspondingly arranged. In the shift register units corresponding to the low-frequency display area-1 and the low-frequency display area-2: the second output circuit 12 of the shift register unit provides an input signal to the lower-level shift register unit, and at the same time, the first output circuit 11 of the shift register unit outputs an invalid level signal, that is, the pixel drive circuits in the low-frequency display area-1 and the low-frequency display area-2 are not scanned in the partial refresh frame. In the shift register unit corresponding to the high-frequency display area: the second output circuit 12 of the shift register unit provides an input signal to the lower-level shift register unit, and at the same time, the first output circuit 11 of the shift register unit normally outputs a gate drive signal. This driving method can adjust the refresh frequencies of different areas of the display panel.

[0207] It should be noted that in this exemplary embodiment, the low-frequency display area and the high-frequency display area are relative, that is, the low-frequency display area and the high-frequency display area refer to two areas with a high and a low refresh rate, respectively. The low-frequency display area and the high-frequency display area do not specifically refer to a specific refresh rate range.

[0208] In this exemplary embodiment, as shown in FIG13 , at least part of the low-frequency display area forms the end scanning area of ​​the display panel, that is, in the same frame, there is no high-frequency display area after the low-frequency display area. As shown in FIG13 , the low-frequency display area-2 forms the end display area of ​​the display panel. In the same frame, the display panel driving method includes: when the shift register unit corresponding to the low-frequency display area forming the end scanning area is in the second driving state, the pulse frequency of the effective level on the first clock signal terminal CB is set to n2; when the shift register unit corresponding to the high-frequency display area is in the first driving state, the pulse frequency of the effective level on the first clock signal terminal CB is set to n1; wherein n1 is greater than or equal to n2. That is, this exemplary embodiment reduces the power consumption of the display panel by reducing the pulse frequency of the effective level on the first clock signal terminal CB in the low-frequency display area-2. Among them, because the first clock signal line LCB simultaneously provides clock signals to the first clock signal terminal of the odd-numbered shift register unit and the third clock signal terminal of the even-numbered shift register unit, and the second clock signal line LCK simultaneously provides clock signals to the third clock signal terminal of the odd-numbered shift register unit and the first clock signal terminal of the even-numbered shift register unit, the pulse frequency of the effective level on the first clock signal line LCB and the second clock signal line LCK is reduced. In this exemplary embodiment, the effective level pulse frequency on the first clock signal terminal of the shift register unit is reduced, and accordingly, the frequency and speed of the input signal from the second output terminal OUT2 to the lower-level shift register unit are also reduced. At the same time, because the low-frequency display area-2 is the last scanning area of ​​the display panel, even if the frequency and speed of the input signal from the second output terminal OUT2 to the lower-level shift register unit are reduced, this setting will not affect the normal scanning of the current frame.

[0209] As shown in FIG13 , this exemplary embodiment can reduce the frequency of active-level pulses at the first clock signal terminal CB by increasing the duration of the signal cycle at the first clock signal terminal CB. A signal cycle includes adjacent active-level pulses and inactive-level pulses. As shown in FIG13 , this exemplary embodiment extends the duration of active-level pulses at the first clock signal terminal to S1 and extends the duration of inactive-level pulses at the first clock signal terminal to S2. S1 may be equal to or different from S2.

[0210] It should be understood that in other exemplary embodiments, other methods can be used to reduce the pulse frequency of the effective level on the first clock signal terminal. The first clock signal terminal can output a number of signal cycles, then pause for a period of time, and then output a number of signal cycles again. The number of signal cycles can be one or more signal cycles. This driving method can also reduce the pulse frequency of the effective level on the first clock signal terminal.

[0211] However, as shown in Figure 13, since the frequency and speed of the input signal from the second output terminal OUT2 to the lower-level shift register unit are reduced, the time for the second output terminal OUT2 of some shift register units to output a valid level may continue into the next frame. For example, the valid level pulse W output by the second output terminal of the n-th stage shift register unit continues into the next frame, which will cause driving confusion in the next frame.

[0212] Based on this, this exemplary embodiment also provides a shift register unit, as shown in FIG14, which is a schematic structural diagram of another exemplary embodiment of the shift register unit disclosed in the present invention. Based on the shift register unit shown in FIG2, the shift register unit shown in FIG14 may further include at least one of a first reset circuit 81, a second reset circuit 82, and a third reset circuit 83. The first reset circuit 81 is connected to the first control node PU1, and the first reset circuit 81 is used to respond to the reset signal to input an invalid level to the first control node PU1; the second reset circuit 82 is connected to the fourth node N4 and the third control node PU3, and the second reset circuit 82 is used to respond to the reset signal to shut down the fourth node N4 and the third control node PU3; the third reset circuit 83 is connected to the third control node PU3, and the third reset circuit 83 is used to respond to the reset signal to input an invalid level to the third control node PU3.

[0213] In this exemplary embodiment, the reset signals responded to by the first reset circuit 81 , the second reset circuit 82 , and the third reset circuit 83 may be the same reset signal or different reset signals.

[0214] In this exemplary embodiment, as shown in FIG14 , the first reset circuit 81 is further connected to the first reset signal terminal Re1 and the first power supply terminal VGL. In response to the signal at the first reset signal terminal Re1, the first reset circuit 81 utilizes the first power supply terminal VGL to input an inactive level to the first control node PU1. The first reset circuit 81 includes a twenty-first transistor T21. The first electrode of the twenty-first transistor T21 is connected to the first power supply terminal VGL, the second electrode is connected to the first control node PU1, and the gate is connected to the first reset signal terminal Re1.

[0215] In this exemplary embodiment, as shown in Figure 14, the second reset circuit 82 is also connected to the second reset signal terminal Re2, and the second reset circuit 82 is used to respond to the signal of the second reset signal terminal Re2 to turn off the fourth node N4 and the third control node PU3; the second reset circuit 82 may include: a twenty-second transistor T22, the first electrode of the twenty-second transistor T22 is connected to the fourth node N4, the second electrode is connected to the third control node PU3, and the gate is connected to the second reset signal terminal Re2.

[0216] In this exemplary embodiment, as shown in FIG14 , the third reset circuit 83 is further connected to the first power supply terminal VGL and the first reset signal terminal Re1. The third reset circuit 83 is configured to respond to a signal at the first reset signal terminal Re1 by inputting an inactive level to the third control node PU3 using the first power supply terminal VGL. The third reset circuit 83 may include a twenty-third transistor T23 having a first electrode connected to the first power supply terminal VGL, a second electrode connected to the third control node PU3, and a gate connected to the first reset signal terminal Re1.

[0217] The display panel using this shift register unit can reset all shift register units through various reset circuits before the next frame. For example, before the next frame, this exemplary embodiment can: use the first reset circuit 81 to input an invalid level to the first control node PU1, use the second reset circuit 82 to turn off the fourth node N4 and the third control node PU3, and use the third reset circuit 83 to input an invalid level to the third control node PU3. This setting can make the second output terminal OUT2 of all shift register units only output an invalid level, that is, the second output terminal OUT2 no longer provides an input signal to the lower-level shift register unit, so that this setting can solve the problem of chaotic driving in the next frame. In this exemplary embodiment, a blank period can be included between frames, and the display panel can reset all shift register units through the reset circuit during the blank period.

[0218] The twenty-first transistor T21 , the twenty-second transistor T22 , and the twenty-third transistor T23 may be N-type transistors, and the signals on the first reset signal terminal Re1 and the second reset signal terminal Re2 may have opposite polarities.

[0219] FIG15 is a schematic diagram of the structure of another exemplary embodiment of a shift register unit according to the present disclosure. The shift register unit shown in FIG15 may also include a first reset circuit 81, a second reset circuit 82, and a third reset circuit 83. Unlike the shift register unit shown in FIG14, the first reset circuit 81 in the shift register unit shown in FIG15 is connected to the second control node PD. The first reset circuit 81 is configured to respond to a signal from the second control node PD and input an inactive level to the first control node PU1 using the first power supply terminal VGL.

[0220] As shown in FIG15 , the first reset circuit 81 includes a twenty-first transistor T21 , wherein a first electrode of the twenty-first transistor T21 is connected to the first power supply terminal VGL, a second electrode of the twenty-first transistor T21 is connected to the first control node PU1 , and a gate of the twenty-first transistor T21 is connected to the second control node PD.

[0221] Among them, when the third clock signal terminal CK outputs a valid level (high level), the fourteenth transistor T14 is turned on, the first power supply terminal VGL inputs an invalid level (low level) to the second output terminal OUT2, and the second output terminal OUT2 outputs an invalid level; when the first clock signal terminal CB outputs a valid level, the second control node PD is at a valid level, the thirteenth transistor T13 and the twenty-first transistor T21 are turned on, the first power supply terminal VGL inputs an invalid level to the first control node PU1 to turn off the twelfth transistor T12, and at the same time, the first power supply terminal VGL inputs an invalid level to the second output terminal OUT2, and the second output terminal OUT2 outputs an invalid level. In addition, the display panel using this shift register unit can also use the second reset circuit 82 to turn off the fourth node N4 and the third control node PU3 before the next frame, and use the third reset circuit 83 to input an invalid level to the third control node PU3. This setting can make the second output terminal OUT2 of all shift register units only output an invalid level, that is, the second output terminal OUT2 no longer provides an input signal to the lower-level shift register unit, so that this setting can solve the problem of chaotic driving in the next frame. In this exemplary embodiment, a blank period may be included between frames, and the display panel may reset all shift register units through a reset circuit during the blank period.

[0222] FIG16 is a schematic diagram illustrating the structure of another exemplary embodiment of a shift register unit according to the present disclosure. The shift register unit shown in FIG16 may also include at least one of a first reset circuit 81, a second reset circuit 82, and a third reset circuit 83. The shift register unit shown in FIG16 has a different third reset circuit 83 than the shift register unit shown in FIG15.

[0223] As shown in FIG16 , the third reset circuit 83 is further connected to the first power supply terminal VGL, the second power supply terminal VGH, the second reset signal terminal Re2, and the fifth node N5. The third reset circuit 83 is configured to transmit the signal from the first power supply terminal VGL to the fifth node N5 in response to a signal from the second reset signal terminal Re2, transmit the signal from the second power supply terminal VGH to the fifth node N5 in response to a signal from the second power supply terminal VGH, and transmit the signal from the first power supply terminal VGL to the third control node PU3 in response to a signal from the fifth node N5. The third reset circuit 83 may include a twenty-third transistor T23, a twenty-fourth transistor T24, and a twenty-fifth transistor T25. The twenty-third transistor T23 has a first electrode connected to the first power supply terminal VGL, a second electrode connected to the third control node PU3, and a gate connected to the fifth node N5. The twenty-fourth transistor T24 has a first electrode connected to the second power supply terminal VGH, a second electrode connected to the fifth node N5, and a gate connected to the second power supply terminal VGH. The twenty-fifth transistor T25 has a first electrode connected to the first power supply terminal VGL, a second electrode connected to the fifth node N5, and a gate connected to the second reset signal terminal Re2.

[0224] In this exemplary embodiment, the second power supply terminal VGH is an effective power supply terminal (a high level power supply terminal). The twenty-first transistor T21, the twenty-second transistor T22, the twenty-third transistor T23, the twenty-fourth transistor T24, and the twenty-fifth transistor T25 may be N-type transistors.

[0225] When the third clock signal terminal CK outputs a valid level (high level), the fourteenth transistor T14 is turned on, the first power supply terminal VGL inputs an invalid level (low level) to the second output terminal OUT2, and the second output terminal OUT2 outputs an invalid level. When the first clock signal terminal CB outputs a valid level, the second control node PD is at a valid level, the thirteenth transistor T13 and the twenty-first transistor T21 are turned on, the first power supply terminal VGL inputs an invalid level to the first control node PU1 to turn off the twelfth transistor T12. At the same time, the first power supply terminal VGL inputs an invalid level to the second output terminal OUT2, and the second output terminal OUT2 outputs an invalid level. In addition, before the next frame, the display panel using this shift register unit can also use the second reset circuit 82 to turn off the fourth node N4 and the third control node PU3, and use the third reset circuit 83 to input an invalid level to the third control node PU3. When the second reset signal terminal Re2 outputs an invalid level signal (low level), the second power supply terminal VGH inputs a valid level signal (high level) to the fifth node N5, the twenty-third transistor T23 is turned on, and the first power supply terminal VGL inputs an invalid level to the third control node PU3. At the same time, the twenty-second transistor T22 is turned off, and the fourth node N4 and the third control node PU3 are turned off. This setting can make the second output terminal OUT2 of all shift register units only output an invalid level, that is, the second output terminal OUT2 no longer provides an input signal to the lower-level shift register unit, so that this setting can solve the problem of chaotic driving in the next frame. In this exemplary embodiment, a blank period can be included between frames, and the display panel can reset all shift register units through the reset circuit during the blank period. This exemplary embodiment can achieve the reset of the shift register unit only through the second reset signal terminal.

[0226] In the shift register units shown in FIG. 14 to FIG. 16 , the first clock signal terminal and the third clock signal terminal can normally output clock signals during the reset phase of the shift register unit.

[0227] FIG17 is a schematic diagram of the structure of another exemplary embodiment of a shift register unit of the present disclosure. Based on the shift register unit shown in FIG2 , the shift register unit may further include at least one of a first reset circuit 81, a third reset circuit 83, and a fourth reset circuit 84. The first reset circuit 81 is connected to the first control node PU1 and is configured to respond to a reset signal to input an inactive level to the first control node PU1. The third reset circuit 83 is connected to the third control node PU3 and is configured to respond to a reset signal to input an inactive level to the third control node PU3. The fourth reset circuit 84 is connected to the second output terminal OUT2 and is configured to respond to a reset signal to input an inactive level to the second output terminal OUT2.

[0228] In this exemplary embodiment, the reset signals responded to by the first reset circuit 81 , the third reset circuit 83 , and the fourth reset circuit 84 may be the same reset signal or different reset signals.

[0229] In this exemplary embodiment, as shown in FIG17 , the first reset circuit 81 is further connected to the first reset signal terminal Re1 and the first power supply terminal VGL. In response to the signal at the first reset signal terminal Re1, the first reset circuit 81 utilizes the first power supply terminal VGL to input an inactive level to the first control node PU1. The first reset circuit 81 includes a twenty-first transistor T21 having a first electrode connected to the first power supply terminal VGL, a second electrode connected to the first control node PU1, and a gate connected to the first reset signal terminal Re1.

[0230] In this exemplary embodiment, as shown in FIG17 , the third reset circuit 83 is further connected to the first power supply terminal VGL and the first reset signal terminal Re1. The third reset circuit 83 is configured to respond to a signal at the first reset signal terminal Re1 by inputting an inactive level to the third control node PU3 using the first power supply terminal VGL. The third reset circuit 83 may include a twenty-third transistor T23 having a first electrode connected to the first power supply terminal VGL, a second electrode connected to the third control node PU3, and a gate connected to the first reset signal terminal Re1.

[0231] In this exemplary embodiment, as shown in FIG17 , the fourth reset circuit 84 is further connected to the first reset signal terminal Re1 and the first power supply terminal VGL. In response to the signal at the first reset signal terminal Re1, the fourth reset circuit 84 utilizes the first power supply terminal VGL to input an inactive level to the second output terminal OUT2. The fourth reset circuit 84 includes a twenty-sixth transistor having a first electrode connected to the first power supply terminal VGL, a second electrode connected to the second output terminal OUT2, and a gate connected to the first reset signal terminal Re1.

[0232] In this exemplary embodiment, as shown in FIG. 17 , the twenty-first transistor T21 , the twenty-third transistor T23 , and the twenty-sixth transistor T26 may be N-type transistors.

[0233] The display panel using this shift register unit can reset all shift register units through various reset circuits before the next frame. For example, before the next frame, this exemplary embodiment can: use the first reset circuit 81 to input an invalid level to the first control node PU1, use the third reset circuit 83 to input an invalid level to the third control node PU3, and use the fourth reset circuit 84 to directly input an invalid level to the second output terminal OUT2. This setting can make the second output terminal OUT2 of all shift register units only output an invalid level, that is, the second output terminal OUT2 no longer provides an input signal to the lower-level shift register unit, so that this setting can solve the problem of chaotic driving in the next frame. In this exemplary embodiment, a blank period can be included between frames, and the display panel can reset all shift register units through the reset circuit during the blank period.

[0234] In this exemplary embodiment, the first clock signal terminal CB and the third clock signal terminal CK may only output an inactive level during the reset phase of the shift register unit.

[0235] It should be noted that the reset circuit shown in Figures 14 to 17 (including the first reset circuit, the second reset circuit, the third reset circuit, and the fourth reset circuit) can also reset all shift register units at other times. For example, the reset circuit shown in Figures 14 to 17 can reset all shift register units when the power is turned on or off to improve display problems such as ghosting of the display panel.

[0236] The shift register unit shown in FIG. 14 to FIG. 17 may further include any one of the first output circuits 11 in the shift register unit shown in FIG. 5 , FIG. 8 , and FIG. 10 .

[0237] In addition, in other exemplary embodiments, the shift register unit may further include one or any multiple reset circuits (including a first reset circuit, a second reset circuit, a third reset circuit, and a fourth reset circuit) shown in FIG. 14 to FIG. 17 .

[0238] It should be understood that in other exemplary embodiments, the first power supply terminal VGL connected to the thirteenth transistor T13, the fourteenth transistor T14, the fourth transistor T4, and the ninth transistor T9 in the shift register unit shown in Figures 5, 8, 10, and 14-17 can be replaced with a third power supply terminal. The third power supply terminal is also used to provide an inactive level, and the voltage of the third power supply terminal can be greater than the voltage of the first power supply terminal VGL. Taking the thirteenth transistor T13 as an example, when the thirteenth transistor T13 is negatively biased, the threshold voltage of the thirteenth transistor T13 may be less than 0. If the thirteenth transistor T13 is connected as shown in Figures 5, 8, 10, and 14-17, the minimum gate-source voltage difference of the thirteenth transistor T13 is 0, resulting in the thirteenth transistor T13 being unable to be completely turned off. When the second output terminal OUT2 outputs a high-level signal, the second output terminal OUT2 may leak through the thirteenth transistor T13, thereby increasing the power consumption of the gate drive circuit. In this exemplary embodiment, connecting the first output circuit and the second output circuit to the third power supply terminal can solve the aforementioned problem of the transistor being unable to be completely turned off.

[0239] In all of the above embodiments, only the low-frequency display area forming the last scanning area can reduce power consumption by adjusting the pulse frequency of the signal on the first clock signal end. For example, the display panel includes 1080 rows of pixel driving circuits, the pixel driving circuits in the first row to the 360th row are the low-frequency scanning area, the pixel driving circuits in the 361st row to the 720th row are the high-frequency scanning area, and the pixel driving circuits in the 721st row to the 1080th row are the low-frequency scanning area. In order to prevent the shift register unit corresponding to the pixel driving circuit in the 360th row from inputting an abnormal input signal to the shift register unit corresponding to the pixel driving circuit in the 361st row, this exemplary embodiment can only adjust the pulse frequency of the first clock signal end signal of the shift register unit corresponding to the pixel driving circuit in the 721st row to the 1080th row.

[0240] In this exemplary embodiment, in order to significantly reduce the power consumption of the gate drive circuit, this exemplary embodiment also proposes a gate drive circuit, which includes multiple shift register units described above, and the multiple shift register units are cascaded. As shown in Figure 18, which is a structural schematic diagram of another exemplary embodiment of the gate drive circuit disclosed herein, the gate drive circuit may include: multiple shift register unit groups GOAz and a switch unit K, wherein the shift register unit group GOAz includes multiple cascaded shift register units GOA; two cascaded shift register units located in different shift register unit groups GOAz are cascaded via the switch unit K; wherein the first-stage shift register unit in each shift register unit group is connected to a different initialization signal terminal.

[0241] As shown in FIG18 , the gate drive circuit may include three shift register unit groups: GOAz1, GOAz2, and GOAz3. Shift register unit group GOAz1 includes the first-stage shift register unit GOA1 to the 360th-stage shift register unit GOA360; shift register unit group GOAz2 includes the 361st-stage shift register unit GOA361 to the 720th-stage shift register unit GOA720; and shift register unit group GOAz3 includes the 721st-stage shift register unit GOA721 to the 1080th-stage shift register unit GOA1080. The first-stage shift register unit GOA1 to the 360th-stage shift register unit GOA360 provide gate drive signals to the pixel drive circuits in rows 1 to 360, respectively. The 361st-stage shift register unit GOA361 to the 720th-stage shift register unit GOA720 provide gate drive signals to the pixel drive circuits in rows 361 to 720, respectively. The 721st-stage shift register unit GOA721 to the 1080th-stage shift register unit GOA1080 provide gate drive signals to the pixel drive circuits in rows 721 to 1080, respectively. The gate drive circuit may include two switch units K1 and K2, and three initial signal lines STV1, STV2, and STV3. The switch unit K1 is connected between the shift register unit group GOAz1 and the shift register unit group GOAz2, and the switch unit K2 is connected between the shift register unit group GOAz2 and the shift register unit group GOAz3. The initial signal line STV1 provides an input signal to the first-stage shift register unit in the shift register unit group GOAz1; the initial signal line STV2 provides an input signal to the first-stage shift register unit in the shift register unit group GOAz2; the initial signal line STV3 provides an input signal to the first-stage shift register unit in the shift register unit group GOAz3.

[0242] When the pixel driving circuits in rows 1 to 360 are in the low-frequency scanning area, the pixel driving circuits in rows 361 to 720 are in the high-frequency scanning area, and the pixel driving circuits in rows 721 to 1080 are in the low-frequency scanning area, this exemplary embodiment can turn off the switch unit K1 to disconnect the shift register unit group GOAz1 and the shift register unit group GOAz2. When the last-stage shift register unit in the shift register unit group GOAz1 outputs a gate driving signal, the initial signal line STV2 can provide an input signal to the first-stage shift register unit in the shift register unit group GOAz2. The shift register units in the shift register unit group GOAz2 do not need to be provided with input signals by the shift register units in the shift register unit group GOAz1. Thus, the low-frequency display area corresponding to the shift register unit group GOAz1 can also reduce power consumption by adjusting the pulse frequency on the first clock signal terminal.

[0243] Accordingly, this exemplary embodiment provides a display panel driving method, wherein the display panel includes multiple sub-display areas, at least part of the low-frequency display area forms a tail scanning area of ​​the sub-display area, and in the same frame of the same sub-display area, the driving method includes:

[0244] When the shift register unit corresponding to the low-frequency display area forming the last scanning area is in the second driving state, the pulse frequency of the effective level on the first clock signal end is set to n2;

[0245] When the shift register unit corresponding to the high-frequency display area is in the first driving state, the pulse frequency of the effective level on the first clock signal terminal is set to n1;

[0246] Among them, n1 is greater than or equal to n2.

[0247] When at least part of the low-frequency display area forms the end scanning area of ​​the sub-display area, the shift register unit group and the lower-level shift register unit group corresponding to the sub-display area can be turned off by the switch unit, and the initial signal line connected to the lower-level shift register unit group can provide an input signal to the first-level shift register unit of the lower-level shift register unit group when the last-level shift register unit of its upper-level shift register unit group outputs a gate drive signal. In addition, in some exemplary embodiments, when the first clock signal terminal in the upper-level shift register unit group does not adjust the pulse frequency, the switch unit between the upper-level shift register unit group and the lower-level shift register unit group can be turned on, and accordingly, the initial signal line connected to the lower-level shift register unit group does not need to provide a gate drive signal to the shift register unit connected thereto.

[0248] As shown in FIG18 , in this exemplary embodiment, the display panel includes three sub-display areas, and three groups of shift register units are provided corresponding to the three sub-display areas. It should be understood that in other exemplary embodiments, the display panel may be divided into another number of sub-display areas, with each sub-display area corresponding to a shift register unit group. Furthermore, each sub-display area may include another number of rows of pixel driver circuits, and the number of rows of pixel driver circuits in each sub-display area may be the same or different.

[0249] As shown in Figure 18, this exemplary embodiment provides input signals to different initial signal terminals via different initial signal lines. When the number of shift register unit groups in the gate drive circuit is large, the number of initial signal lines required by the gate drive circuit is also large, which is not conducive to the narrow frame design of the display panel.

[0250] As shown in FIG19 , it is a schematic diagram of the structure of another exemplary embodiment of the gate drive circuit disclosed in the present invention. The gate drive circuit includes 8 shift register unit groups GOAz. In addition, the gate drive circuit may also include a decoder 10, which can be connected to three initial signal lines STV1, STV2, and STV3. The decoder 10 can provide input signals to the first-stage shift register unit in the 8 shift register unit groups according to the signals of the three initial signal lines STV1, STV2, and STV3. For example, the signals on the three initial signal lines STV1, STV2, and STV3 can form 2 3 The decoder 10 can provide input signals to any group of shift register units according to different combinations of signals on the three clock signal lines.

[0251] According to one aspect of the present disclosure, a display panel is provided, wherein the display panel includes the above-mentioned gate driving circuit.

[0252] This exemplary embodiment also provides a display panel, which may include the above-mentioned gate driving circuit. The display panel can be used in computers, mobile phones, tablet computers, televisions, etc.

[0253] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0254] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0255] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A shift register unit, wherein: The shift register unit includes: an input circuit connected to the input signal terminal, the fourth node, and the third clock signal terminal, wherein the input circuit is configured to transmit the input signal of the input signal terminal to the fourth node in response to a signal of the third clock signal terminal; a second control circuit connected to a third control node, a first clock signal terminal, a second control node, and a first power terminal, wherein the third control node is connected to the fourth node, and the second control circuit is configured to respond to signals from the first clock signal terminal and the second control node to transmit a signal from the first power terminal to the third control node; a third control circuit connected to the third control node, the first power supply terminal, and the second control node, the third control circuit being configured to respond to a signal from the third control node to transmit a signal from the first power supply terminal to the second control node; a fourth control circuit connected to the third control node, the first clock signal terminal, and the second control node, the fourth control circuit being configured to control the voltage of the second control node in response to signals from the first clock signal terminal and the third control node; The second output circuit is connected to the first control node, the second control node, the second output end, and the first clock signal end. The first control node is connected to the third control node. The second output circuit is used to respond to the signal of the first control node to transmit the signal of the first clock signal end to the second output end, and to respond to the signal of the second control node to input an invalid level to the second output end.

2. The shift register unit according to claim 1, wherein: The second output circuit is further connected to a third clock signal terminal, and is configured to respond to a signal from the third clock signal terminal to transmit a signal from the first power terminal to the second output terminal.

3. The shift register unit according to claim 1, wherein: The fourth control circuit is also connected to the third node and the first power supply terminal. The fourth control circuit is used to respond to the signal of the third control node to transmit the signal of the first power supply terminal to the third node, to respond to the signal of the first clock signal terminal to input a valid level signal to the third node, and to respond to the signal of the third node to input a valid level signal to the second control node.

4. The shift register unit according to claim 1, wherein: The shift register unit further includes: The isolation circuit is connected to the first control node and the third control node, and is used for responding to a control signal to connect the first control node and the third control node.

5. The shift register unit according to claim 2, wherein: The second output circuit is further connected to the first power supply terminal, and is configured to respond to a signal from the second control node and input an invalid level to the second output terminal using the first power supply terminal; The second output circuit includes: a twelfth transistor, having a first electrode connected to the first clock signal terminal, a second electrode connected to the second output terminal, and a gate connected to the first control node; a third capacitor, a first electrode of which is connected to the first control node, and a second electrode of which is connected to the second output terminal; a thirteenth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the second output terminal, and a gate connected to the second control node; The fourteenth transistor has a first electrode connected to the first power supply terminal, a second electrode connected to the second output terminal, and a gate connected to the third clock signal terminal. The shift register unit according to claim 1 , wherein: The input circuit comprises: a first transistor, having a first electrode connected to the input signal terminal, a second electrode connected to the fourth node, and a gate connected to the third clock signal terminal; The second control circuit includes: a sixth transistor, having a first electrode connected to the first power supply terminal and a gate connected to the second control node; a seventh transistor, having a first electrode connected to the second electrode of the sixth transistor, a second electrode connected to the third control node, and a gate connected to the first clock signal terminal; The third control circuit includes: The eleventh transistor has a first electrode connected to the first power supply terminal, a second electrode connected to the second control node, and a gate connected to the third control node.

7. The shift register unit according to claim 3, wherein: The fourth control circuit is configured to input a valid level signal to the third node using the first clock signal terminal in response to a signal from the first clock signal terminal, and to input a valid level signal to the second control node using the first clock signal terminal in response to a signal from the third node. The fourth control circuit includes: a third transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the third node, and a gate connected to the third control node; a second transistor, having a first electrode connected to the first clock signal terminal, a second electrode connected to the third node, and a gate connected to the first clock signal terminal; The tenth transistor has a first electrode connected to the first clock signal terminal, a second electrode connected to the second control node, and a gate connected to the third node.

8. The shift register unit according to claim 4, wherein: The isolation circuit is further connected to a third clock signal terminal, and is configured to connect the third control node and the first control node in response to a signal from the third clock signal terminal; The isolation circuit comprises: An eighth transistor has a first electrode connected to the third control node, a second electrode connected to the first control node, and a gate connected to the third clock signal terminal.

9. The shift register unit according to claim 1, wherein: The shift register unit further includes a reset circuit, and the reset circuit includes one or more of a first reset circuit, a second reset circuit, a third reset circuit, and a fourth reset circuit; The first reset circuit is connected to the first control node, and is configured to input an invalid level to the first control node in response to a reset signal; The second reset circuit is connected to the fourth node and the third control node, and is configured to respond to a reset signal to turn off the fourth node and the third control node; The third reset circuit is connected to the third control node, and is configured to input an invalid level to the third control node in response to a reset signal; The fourth reset circuit is connected to the second output terminal, and is configured to respond to a reset signal to input an invalid level to the second output terminal.

10. The shift register unit according to claim 9, wherein: The first reset circuit is further connected to a first reset signal terminal and a first power supply terminal. The first reset circuit is configured to respond to a signal from the first reset signal terminal and input an invalid level to the first control node via the first power supply terminal.

11. The shift register unit according to claim 10, wherein: The first reset circuit includes: A twenty-first transistor, a first electrode connected to the first power supply terminal, a second electrode connected to the A control node, the gate of which is connected to the first reset signal terminal.

12. The shift register unit according to claim 9, wherein: The first reset circuit is further connected to the second control node and the first power supply terminal. The first reset circuit is configured to respond to a signal from the second control node and input an invalid level to the first control node using the first power supply terminal.

13. The shift register unit according to claim 12, wherein: The first reset circuit includes: A twenty-first transistor has a first electrode connected to the first power supply terminal, a second electrode connected to the first control node, and a gate connected to the second control node.

14. The shift register unit according to claim 9, wherein: The second reset circuit is further connected to a second reset signal terminal, and the second reset circuit is configured to respond to a signal at the second reset signal terminal to turn off the fourth node and the third control node; The second reset circuit comprises: The twenty-second transistor has a first electrode connected to the fourth node, a second electrode connected to the third control node, and a gate connected to the second reset signal terminal.

15. The shift register unit according to claim 9, wherein: The third reset circuit is further connected to the first power supply terminal and the first reset signal terminal, and is configured to respond to a signal from the first reset signal terminal to input an invalid level to the third control node using the first power supply terminal; The third reset circuit includes: The twenty-third transistor has a first electrode connected to the first power supply terminal, a second electrode connected to the third control node, and a gate connected to the first reset signal terminal.

16. The shift register unit according to claim 9, wherein: The third reset circuit is also connected to the first power supply terminal, the second power supply terminal, the second reset signal terminal, and the fifth node. The third reset circuit is used to respond to the signal of the second reset signal terminal to transmit the signal of the first power supply terminal to the fifth node, to respond to the signal of the second power supply terminal to transmit the signal of the second power supply terminal to the fifth node, and to respond to the signal of the fifth node to transmit the signal of the first power supply terminal to the third control node.

17. The shift register unit according to claim 16, wherein: The third reset circuit includes: a twenty-third transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the third control node, and a gate connected to the fifth node; A twenty-fourth transistor, having a first electrode connected to the second power supply terminal, a second electrode connected to the fifth node, and a gate connected to the second power supply terminal; The twenty-fifth transistor has a first electrode connected to the first power supply terminal, a second electrode connected to the fifth node, and a gate connected to the second reset signal terminal.

18. The shift register unit according to claim 9, wherein: The fourth reset circuit is further connected to the first reset signal terminal and the first power supply terminal, and is configured to respond to a signal from the first reset signal terminal and input an invalid level to the second output terminal using the first power supply terminal; The fourth reset circuit includes: The twenty-sixth transistor has a first electrode connected to the first power supply terminal, a second electrode connected to the second output terminal, and a gate connected to the first reset signal terminal.

19. The shift register unit according to any one of claims 1 to 18, wherein: The shift register unit is applied to a gate drive circuit in a display panel, the gate drive circuit includes a plurality of cascaded shift register units, the display panel includes a pixel drive circuit, and the second output circuit is used to provide an input signal to a lower-level shift register unit; The shift register unit further includes: The first output circuit is electrically connected to the second output circuit, and the first output circuit is used to provide a gate driving signal to the pixel driving circuit in a first driving state, and to provide an invalid level signal to the pixel driving circuit in a second driving state.

20. The shift register unit according to claim 19, wherein: The first output circuit is connected to a first control node, a second control node, and a first output terminal. The first output circuit is used to respond at least to signals of the first control node and the second control node to provide the gate drive signal or the invalid level signal to the first output terminal. The first output terminal is used to connect to a pixel drive circuit.

21. The shift register unit according to claim 20, wherein: The first output circuit includes: The first sub-output circuit is connected to the second clock signal terminal, the first control node, and the first output terminal, and the first sub-output circuit is used to respond to the signal of the first control node to The signal of the second clock signal terminal is transmitted to the first output terminal; a second sub-output circuit connected to the first power supply terminal, the first output terminal, and a second control node, the second sub-output circuit being configured to transmit a signal from the first power supply terminal to the first output terminal in response to a signal from the second control node; Wherein, the first clock signal terminal and the second clock signal terminal are used to output clock signals of corresponding timing in the first driving state of the first output circuit; The second clock signal terminal is used to output an invalid level signal in the second driving state of the first output circuit.

22. The shift register unit according to claim 20, wherein: The first output circuit includes: a first sub-output circuit connected to a first clock signal terminal, a first control node, a first enable signal terminal, a first output terminal, and a first node, the first sub-output circuit being configured to respond to a signal at the first enable signal terminal to transmit a signal at the first clock signal terminal to the first node, and to respond to a signal at the first control node to transmit a signal at the first node to the first output terminal; a second sub-output circuit connected to the first power supply terminal, the first output terminal, and a second control node, the second sub-output circuit being configured to transmit a signal from the first power supply terminal to the first output terminal in response to a signal from the second control node; The first enable signal terminal is used to output a valid level in a first driving state of the first output circuit, and is used to output an invalid level in a second driving state of the first output circuit.

23. The shift register unit according to claim 20, wherein: The first output circuit includes: a first sub-output circuit connected to a first clock signal terminal, a first control node, a first enable signal terminal, a first output terminal, and a second node, the first sub-output circuit being configured to transmit a signal from the first control node to the second node in response to a signal from the first enable signal terminal, and to transmit a signal from the first clock signal terminal to the first output terminal in response to a signal from the second node; The second sub-output circuit is connected to the first power supply terminal, the first output terminal, and the second control node, and the second sub-output circuit is used to respond to the signal of the second control node to output the first power supply terminal to the first output terminal. The signal from the source end is transmitted to the first output end; The first enable signal terminal is used to output a valid level in a first driving state of the first output circuit, and is used to output an invalid level in a second driving state of the first output circuit.

24. The shift register unit according to claim 23, wherein: The first output circuit further includes: a first control circuit connected to the first power supply terminal, the second enable signal terminal, and the second node, the first control circuit being configured to transmit the signal of the first power supply terminal to the second node in response to a signal of the second enable signal terminal; The second enable signal terminal is used to output an invalid level in a first driving state of the first output circuit, and is used to output a valid level in a second driving state of the first output circuit.

25. The shift register unit according to any one of claims 21 to 24, wherein: The second sub-output circuit is further connected to a third clock signal terminal, and is further configured to respond to a signal from the third clock signal terminal to transmit a signal from the first power supply terminal to the first output terminal.

26. The shift register unit according to claim 21, wherein: The first sub-output circuit includes: a fifth transistor, having a first electrode connected to the second clock signal terminal, a second electrode connected to the first output terminal, and a gate connected to the first control node; A first capacitor has a first electrode connected to the first control node and a second electrode connected to the first output terminal.

27. The shift register unit according to claim 22, wherein: The first sub-output circuit includes: a fifth transistor, having a first electrode connected to the first node, a second electrode connected to the first output terminal, and a gate connected to the first control node; a fifteenth transistor, having a first electrode connected to the first clock signal terminal, a second electrode connected to the first node, and a gate connected to the first enable signal terminal; A first capacitor has a first electrode connected to the first control node and a second electrode connected to the first output terminal.

28. The shift register unit according to claim 24, wherein: The first sub-output circuit includes: a fifth transistor, having a first electrode connected to the first clock signal terminal, a second electrode connected to the first output terminal, and a gate connected to the second node; a sixteenth transistor, having a first electrode connected to the first control node, a second electrode connected to the second node, and a gate connected to the first enable signal terminal; a first capacitor, a first electrode of which is connected to the second node, and a second electrode of which is connected to the first output terminal; The first control circuit includes: The fifteenth transistor has a first electrode connected to the first power supply terminal, a second electrode connected to the second node, and a gate connected to the second enable signal terminal.

29. The shift register unit according to claim 25, wherein: The second sub-output circuit includes: a fourth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the first output terminal, and a gate connected to the second control node; a ninth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the first output terminal, and a gate connected to the third clock signal terminal; A second capacitor has a first electrode connected to the second control node and a second electrode connected to the first power supply terminal.

30. The shift register unit according to claim 21, wherein The duty cycle of the effective level on the first clock signal terminal is greater than the duty cycle of the effective level on the second clock signal terminal.

31. The shift register unit according to any one of claims 9 to 18, wherein: The shift register unit is applied to a gate driving circuit in a display panel, and the reset circuit is used to be turned on before the next frame.

32. The shift register unit according to claim 31, wherein The driving method of the display panel includes a blank period between frames, and the reset circuit is configured to be turned on during the blank period.

33. The shift register unit according to any one of claims 19 to 30, wherein: When the first output circuit is in the first driving state, the pulse frequency of the effective level on the first clock signal terminal is n1; When the first output circuit is in the second driving state, the pulse frequency of the effective level on the first clock signal terminal is n2; Among them, n1 is greater than or equal to n2.

34. A gate drive circuit, wherein: The gate drive circuit includes a plurality of shift register units according to any one of claims 1 to 33, and the plurality of shift register units are cascaded.

35. The gate driving circuit according to claim 34, wherein: The gate drive circuit includes: a plurality of shift register unit groups, each of the shift register unit groups comprising a plurality of cascaded shift register units; a switch unit, wherein two cascaded shift register units located in different shift register unit groups are cascaded via the switch unit; Wherein, the first-stage shift register unit in each of the shift register unit groups is connected to a different initialization signal terminal.

36. A display panel, wherein: The display panel includes the gate driving circuit according to claim 34 or 35.

37. A display panel driving method, wherein: Used to drive the display panel according to claim 36, wherein the driving method comprises: In the same time period, respectively controlling the number of frames in which the shift register units corresponding to different display areas in the display panel are in the second driving state; The refresh frequency of the display area corresponding to the shift register unit with a smaller frame number in the second driving state is greater than the refresh frequency of the display area corresponding to the shift register unit with a larger frame number in the second driving state.

38. The display panel driving method according to claim 37, wherein: At least part of the low-frequency display area forms the end scanning area of ​​the display panel. In the same frame, the driving method includes: When the shift register unit corresponding to the low-frequency display area forming the last scanning area is in the second driving state, the pulse frequency of the effective level on the first clock signal end is set to n2; When the shift register unit corresponding to the high frequency display area is in the first driving state, the The pulse frequency of the effective level on the first clock signal terminal is set to n1; Among them, n1 is greater than or equal to n2.

39. The display panel driving method according to claim 37, wherein: The display panel includes a plurality of sub-display areas, and the gate driving circuit includes: a plurality of shift register unit groups, each of the shift register unit groups comprising a plurality of cascaded shift register units, each of the shift register unit groups being arranged corresponding to the sub-display areas, and each of the shift register unit groups being configured to provide a gate drive signal to the corresponding sub-display areas; a switch unit, wherein two cascaded shift register units located in different shift register unit groups are cascaded via the switch unit; Wherein, the first-stage shift register unit in each of the shift register unit groups is connected to a different initialization signal terminal; At least part of the low-frequency display area forms the end scanning area of ​​the sub-display area. In the same frame of the same sub-display area, the driving method includes: When the shift register unit corresponding to the low-frequency display area forming the last scanning area is in the second driving state, the pulse frequency of the effective level on the first clock signal end is set to n2; When the shift register unit corresponding to the high-frequency display area is in the first driving state, the pulse frequency of the effective level on the first clock signal end is set to n1; Among them, n1 is greater than or equal to n2.

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