Shift register, driving method therefor, gate driving circuit and display apparatus

Abstract

A shift register, a driving method therefor, a gate driving circuit and a display apparatus. The shift register comprises: a node control sub-circuit which is configured to provide a signal to a driving output sub-circuit under the control of signals of a cascade output sub-circuit, a first power supply end, a second power supply end and a first control input signal end; and a driving output sub-circuit which is configured to provide a signal of the first power supply end or of a second control input signal end to a driving output signal end under the control of signals of the cascade output sub-circuit and the node control sub-circuit. The first control input signal end comprises a second clock signal end, and the second control input signal end comprises a masking signal end, or the first control input signal end comprises a second clock signal end and a masking signal end, and the second control input signal end comprises a second clock signal end.

Description

Shift register and driving method thereof, gate driving circuit, and display device

[0001] This application claims priority to the Chinese patent application filed on March 26, 2024, with application number 202410354593.5 and invention name “Shift register and its driving method, gate drive circuit, display device”, the content of which should be understood as incorporated into this application by reference. Technical Field

[0002] This article relates to the field of display technology, and in particular to a shift register and a driving method thereof, a gate driving circuit, and a display device. Background Art

[0003] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field. Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] In a first aspect, the present disclosure provides a shift register, comprising: a cascade output subcircuit, a drive output subcircuit, and a node control subcircuit;

[0006] The cascade output sub-circuit is electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal and the cascade output signal terminal, respectively, and is configured to provide the signal of the first power supply terminal or the second clock signal terminal to the cascade output signal terminal under the control of the signals of the signal input terminal, the first clock signal terminal, the second clock signal terminal and the second power supply terminal;

[0007] The node control subcircuit is electrically connected to the cascade output subcircuit, the driver output subcircuit, the first power supply terminal, the second power supply terminal, and the first control input signal terminal, respectively, and is configured to provide a signal to the driver output subcircuit under the control of signals from the cascade output subcircuit, the first power supply terminal, the second power supply terminal, and the first control input signal terminal;

[0008] The driver output subcircuit is electrically connected to the cascade output subcircuit, the node control subcircuit, the first power supply terminal, the second control input signal terminal and the driver output signal terminal, respectively, and is configured to provide a signal from the first power supply terminal or the second control input signal terminal to the driver output signal terminal under the control of signals from the cascade output subcircuit and the node control subcircuit;

[0009] The first control input signal terminal includes: a second clock signal terminal, the second control input signal terminal includes: a mask signal terminal, or the first control input signal terminal includes: a second clock signal terminal and a mask signal terminal, and the second control input signal terminal includes: a second clock signal terminal.

[0010] In an exemplary embodiment, the shift register is provided in a display device, content displayed by the display device includes a plurality of display frames, and a display mode of the display device includes: a first display mode and a second display mode, wherein a refresh rate of the first display mode is greater than a refresh rate of the second display mode;

[0011] In the first display mode, the signal at the cascade output signal terminal and the signal at the drive output signal terminal of the shift register are the same;

[0012] In the second display mode, the signal at the cascade output signal terminal and the signal at the drive output signal terminal of the shift register are inverted signals at least partially.

[0013] In an exemplary embodiment, the cascade output subcircuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitor, and a second capacitor;

[0014] The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node;

[0015] The control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the second node;

[0016] A control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is electrically connected to the second power supply terminal, and a second electrode of the third transistor is electrically connected to the second node;

[0017] The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor;

[0018] The control electrode of the fifth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first node;

[0019] The control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the cascade output signal terminal;

[0020] The control electrode of the seventh transistor is electrically connected to the third node, the first electrode of the seventh transistor is electrically connected to the second clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the cascade output signal terminal;

[0021] a control electrode of the eighth transistor electrically connected to the second power supply terminal, a first electrode of the eighth transistor electrically connected to the first node, and a second electrode of the eighth transistor electrically connected to the third node;

[0022] A first end of the first capacitor is electrically connected to the third node, and a second end of the first capacitor is electrically connected to the cascade output signal terminal;

[0023] A first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the first power supply end.

[0024] In an exemplary embodiment, the cascade output subcircuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitor, a second capacitor, and a third capacitor;

[0025] The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node;

[0026] The control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the second power supply terminal, and the second electrode of the second transistor is electrically connected to the second node;

[0027] The control electrode of the third transistor is electrically connected to the first end of the third capacitor, the first electrode of the third transistor is electrically connected to the second clock signal end, and the second electrode of the third transistor is electrically connected to the second node;

[0028] The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the second power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor;

[0029] The control electrode of the fifth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first node;

[0030] The control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the cascade output signal terminal;

[0031] The control electrode of the seventh transistor is electrically connected to the third node, the first electrode of the seventh transistor is electrically connected to the second clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the cascade output signal terminal;

[0032] a control electrode of the eighth transistor electrically connected to the second power supply terminal, a first electrode of the eighth transistor electrically connected to the first node, and a second electrode of the eighth transistor electrically connected to the third node;

[0033] a control electrode of the ninth transistor electrically connected to the first node, a first electrode of the ninth transistor electrically connected to the second power supply terminal, and a second electrode of the ninth transistor electrically connected to the first terminal of the third capacitor;

[0034] A first end of the first capacitor is electrically connected to the third node, and a second end of the first capacitor is electrically connected to the cascade output signal terminal;

[0035] A first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the first power supply end.

[0036] The second end of the third capacitor is electrically connected to the second clock signal end.

[0037] In an exemplary embodiment, the cascade output sub-circuit further includes: a fourth capacitor;

[0038] A first end of the fourth capacitor is electrically connected to the first power supply end, and a second end of the fourth capacitor is electrically connected to the cascade output signal end.

[0039] In an exemplary embodiment, the first control input signal terminal includes: a second clock signal terminal and a mask signal terminal, and the second control input signal terminal includes: a second clock signal terminal;

[0040] The cascade output subcircuit is provided with a first node, a second node and a third node;

[0041] The node control subcircuit is electrically connected to the first node, the second node, the mask signal terminal, the second clock signal terminal, the first power terminal, the second power terminal, and the fifth node, respectively, and is configured to provide a signal from the first power terminal or the mask signal terminal to the fifth node under the control of signals from the first node, the second node, the mask signal terminal, the second clock signal terminal, and the second power terminal;

[0042] The drive output sub-circuit is electrically connected to the second node, the fifth node, the second clock signal terminal, the first power supply terminal and the drive output signal terminal, respectively, and is configured to provide a signal from the first power supply terminal or the second clock signal terminal to the drive output signal terminal under the control of the signals of the second node and the fifth node.

[0043] In an exemplary embodiment, the driving output sub-circuit includes: a tenth transistor, an eleventh transistor, and a fifth capacitor, and the node control sub-circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitor;

[0044] The control electrode of the tenth transistor is electrically connected to the fifth node, the first electrode of the tenth transistor is electrically connected to the second clock signal terminal, and the second electrode of the tenth transistor is electrically connected to the drive output signal terminal;

[0045] The control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the driving output signal terminal;

[0046] The control electrode of the twelfth transistor is electrically connected to the fourth node, the first electrode of the twelfth transistor is electrically connected to the masking signal terminal, and the second electrode of the twelfth transistor is electrically connected to the fifth node;

[0047] a control electrode of the thirteenth transistor electrically connected to the second clock signal terminal, a first electrode of the thirteenth transistor electrically connected to the second electrode of the fourteenth transistor, and a second electrode of the thirteenth transistor electrically connected to the fifth node;

[0048] The control electrode of the fourteenth transistor is electrically connected to the second node, and the first electrode of the fourteenth transistor is electrically connected to the first power supply terminal;

[0049] a control electrode of the fifteenth transistor electrically connected to the second power supply terminal, a first electrode of the fifteenth transistor electrically connected to the first node, and a second electrode of the fifteenth transistor electrically connected to the fourth node;

[0050] A first end of the fifth capacitor is electrically connected to the fifth node, and a second end of the fifth capacitor is electrically connected to the driving output signal terminal;

[0051] A first end of the sixth capacitor is electrically connected to the fourth node, and a second end of the sixth capacitor is electrically connected to the fifth node.

[0052] In an exemplary embodiment, the first control input signal terminal includes: a second clock signal terminal, and the second control input signal terminal includes: a mask signal terminal;

[0053] The cascade output subcircuit is provided with a first node, a second node and a third node;

[0054] The node control subcircuit is electrically connected to the first node, the second node, the second clock signal terminal, the first power terminal, the second power terminal, and the fifth node, respectively, and is configured to provide a signal from the first power terminal or the second clock signal terminal to the fifth node under the control of the signals from the first node, the second node, the second clock signal terminal, and the second power terminal;

[0055] The drive output sub-circuit is electrically connected to the second node, the fifth node, the first power supply terminal, the masking signal terminal and the drive output signal terminal, respectively, and is configured to provide a signal from the first power supply terminal or the masking signal terminal to the drive output signal terminal under the control of signals configured as the second node and the fifth node.

[0056] In an exemplary embodiment, the driving output sub-circuit includes: a tenth transistor, an eleventh transistor, and a fifth capacitor, and the node control sub-circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitor;

[0057] The control electrode of the tenth transistor is electrically connected to the fifth node, the first electrode of the tenth transistor is electrically connected to the masking signal terminal, and the second electrode of the tenth transistor is electrically connected to the driving output signal terminal;

[0058] The control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the driving output signal terminal;

[0059] a control electrode of the twelfth transistor electrically connected to the fourth node, a first electrode of the twelfth transistor electrically connected to the second clock signal terminal, and a second electrode of the twelfth transistor electrically connected to the fifth node;

[0060] a control electrode of the thirteenth transistor electrically connected to the second clock signal terminal, a first electrode of the thirteenth transistor electrically connected to the second electrode of the fourteenth transistor, and a second electrode of the thirteenth transistor electrically connected to the fifth node;

[0061] The control electrode of the fourteenth transistor is electrically connected to the second node, and the first electrode of the fourteenth transistor is electrically connected to the first power supply terminal;

[0062] a control electrode of the fifteenth transistor electrically connected to the second power supply terminal, a first electrode of the fifteenth transistor electrically connected to the first node, and a second electrode of the fifteenth transistor electrically connected to the fourth node;

[0063] A first end of the fifth capacitor is electrically connected to the fifth node, and a second end of the fifth capacitor is electrically connected to the driving output signal terminal;

[0064] A first end of the sixth capacitor is electrically connected to the fourth node, and a second end of the sixth capacitor is electrically connected to the fifth node.

[0065] In an exemplary embodiment, the first control input signal terminal includes: a second clock signal terminal and a mask signal terminal, and the second control input signal terminal includes: a second clock signal terminal;

[0066] The cascade output subcircuit is provided with a first node, a second node and a third node;

[0067] The node control subcircuit is electrically connected to the second node, the third node, the mask signal terminal, the second clock signal terminal, the first power terminal, the second power terminal, and the fifth node, respectively, and is configured to provide a signal from the first power terminal or the mask signal terminal to the fifth node under the control of signals from the second node, the third node, the mask signal terminal, the second clock signal terminal, and the second power terminal;

[0068] The drive output sub-circuit is electrically connected to the second node, the fifth node, the second clock signal terminal, the first power supply terminal and the drive output signal terminal, respectively, and is configured to provide a signal from the first power supply terminal or the second clock signal terminal to the drive output signal terminal under the control of the signals of the second node and the fifth node.

[0069] In an exemplary embodiment, the driving output sub-circuit includes: a tenth transistor, an eleventh transistor, and a fifth capacitor, and the node control sub-circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitor;

[0070] The control electrode of the tenth transistor is electrically connected to the fifth node, the first electrode of the tenth transistor is electrically connected to the second clock signal terminal, and the second electrode of the tenth transistor is electrically connected to the drive output signal terminal;

[0071] The control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the driving output signal terminal;

[0072] The control electrode of the twelfth transistor is electrically connected to the fourth node, the first electrode of the twelfth transistor is electrically connected to the masking signal terminal, and the second electrode of the twelfth transistor is electrically connected to the fifth node;

[0073] a control electrode of the thirteenth transistor electrically connected to the second clock signal terminal, a first electrode of the thirteenth transistor electrically connected to the second electrode of the fourteenth transistor, and a second electrode of the thirteenth transistor electrically connected to the fifth node;

[0074] The control electrode of the fourteenth transistor is electrically connected to the second node, and the first electrode of the fourteenth transistor is electrically connected to the first power supply terminal;

[0075] a control electrode of the fifteenth transistor electrically connected to the second power supply terminal, a first electrode of the fifteenth transistor electrically connected to the third node, and a second electrode of the fifteenth transistor electrically connected to the fourth node;

[0076] A first end of the fifth capacitor is electrically connected to the fifth node, and a second end of the fifth capacitor is electrically connected to the driving output signal terminal;

[0077] A first end of the sixth capacitor is electrically connected to the fourth node, and a second end of the sixth capacitor is electrically connected to the fifth node.

[0078] In an exemplary embodiment, the first control input signal terminal includes: a second clock signal terminal, and the second control input signal terminal includes: a mask signal terminal;

[0079] The cascade output subcircuit is provided with a first node, a second node and a third node;

[0080] The node control subcircuit is electrically connected to the second node, the third node, the second clock signal terminal, the first power terminal, the second power terminal, and the fifth node, respectively, and is configured to provide a signal from the first power terminal or the second clock signal terminal to the fifth node under the control of signals from the second node, the third node, the second clock signal terminal, and the second power terminal;

[0081] The drive output sub-circuit is electrically connected to the second node, the fifth node, the first power supply terminal, the masking signal terminal and the drive output signal terminal, respectively, and is configured to provide a signal from the first power supply terminal or the masking signal terminal to the drive output signal terminal under the control of signals configured as the second node and the fifth node.

[0082] In an exemplary embodiment, the driving output sub-circuit includes: a tenth transistor, an eleventh transistor, and a fifth capacitor, and the node control sub-circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitor;

[0083] The control electrode of the tenth transistor is electrically connected to the fifth node, the first electrode of the tenth transistor is electrically connected to the masking signal terminal, and the second electrode of the tenth transistor is electrically connected to the driving output signal terminal;

[0084] The control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the driving output signal terminal;

[0085] a control electrode of the twelfth transistor electrically connected to the fourth node, a first electrode of the twelfth transistor electrically connected to the second clock signal terminal, and a second electrode of the twelfth transistor electrically connected to the fifth node;

[0086] a control electrode of the thirteenth transistor electrically connected to the second clock signal terminal, a first electrode of the thirteenth transistor electrically connected to the second electrode of the fourteenth transistor, and a second electrode of the thirteenth transistor electrically connected to the fifth node;

[0087] The control electrode of the fourteenth transistor is electrically connected to the second node, and the first electrode of the fourteenth transistor is electrically connected to the first power supply terminal;

[0088] a control electrode of the fifteenth transistor electrically connected to the second power supply terminal, a first electrode of the fifteenth transistor electrically connected to the third node, and a second electrode of the fifteenth transistor electrically connected to the fourth node;

[0089] A first end of the fifth capacitor is electrically connected to the fifth node, and a second end of the fifth capacitor is electrically connected to the driving output signal terminal;

[0090] A first end of the sixth capacitor is electrically connected to the fourth node, and a second end of the sixth capacitor is electrically connected to the fifth node.

[0091] In an exemplary embodiment, the cascade output sub-circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitor, and a second capacitor; the driver output sub-circuit includes: a tenth transistor, an eleventh transistor, and a fifth capacitor; the node control sub-circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitor;

[0092] The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node;

[0093] The control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the second node;

[0094] A control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is electrically connected to the second power supply terminal, and a second electrode of the third transistor is electrically connected to the second node;

[0095] The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor;

[0096] The control electrode of the fifth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first node;

[0097] The control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the cascade output signal terminal;

[0098] The control electrode of the seventh transistor is electrically connected to the third node, the first electrode of the seventh transistor is electrically connected to the second clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the cascade output signal terminal;

[0099] a control electrode of the eighth transistor electrically connected to the second power supply terminal, a first electrode of the eighth transistor electrically connected to the first node, and a second electrode of the eighth transistor electrically connected to the third node;

[0100] a control electrode of the tenth transistor electrically connected to the fifth node, a first electrode of the tenth transistor electrically connected to one of the masking signal terminal and the second clock signal terminal, and a second electrode of the tenth transistor electrically connected to the driving output signal terminal;

[0101] The control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the driving output signal terminal;

[0102] A control electrode of the twelfth transistor is electrically connected to the fourth node, a first electrode of the twelfth transistor is electrically connected to the other of the mask signal terminal and the second clock signal terminal, and a second electrode of the twelfth transistor is electrically connected to the fifth node;

[0103] a control electrode of the thirteenth transistor electrically connected to the second clock signal terminal, a first electrode of the thirteenth transistor electrically connected to the second electrode of the fourteenth transistor, and a second electrode of the thirteenth transistor electrically connected to the fifth node;

[0104] The control electrode of the fourteenth transistor is electrically connected to the second node, and the first electrode of the fourteenth transistor is electrically connected to the first power supply terminal;

[0105] a control electrode of the fifteenth transistor electrically connected to the second power supply terminal, a first electrode of the fifteenth transistor electrically connected to one of the first node and the third node, and a second electrode of the fifteenth transistor electrically connected to the fourth node;

[0106] A first end of the first capacitor is electrically connected to the third node, and a second end of the first capacitor is electrically connected to the cascade output signal terminal;

[0107] A first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the first power supply terminal;

[0108] A first end of the fifth capacitor is electrically connected to the fifth node, and a second end of the fifth capacitor is electrically connected to the driving output signal terminal;

[0109] A first end of the sixth capacitor is electrically connected to the fourth node, and a second end of the sixth capacitor is electrically connected to the fifth node.

[0110] In an exemplary embodiment, the cascade output sub-circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitor, a second capacitor, and a fourth capacitor; the driver output sub-circuit includes: a tenth transistor, an eleventh transistor, and a fifth capacitor; and the node control sub-circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitor.

[0111] The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node;

[0112] The control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the second node;

[0113] A control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is electrically connected to the second power supply terminal, and a second electrode of the third transistor is electrically connected to the second node;

[0114] The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor;

[0115] The control electrode of the fifth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first node;

[0116] The control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the cascade output signal terminal;

[0117] The control electrode of the seventh transistor is electrically connected to the third node, the first electrode of the seventh transistor is electrically connected to the second clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the cascade output signal terminal;

[0118] a control electrode of the eighth transistor electrically connected to the second power supply terminal, a first electrode of the eighth transistor electrically connected to the first node, and a second electrode of the eighth transistor electrically connected to the third node;

[0119] a control electrode of the tenth transistor electrically connected to the fifth node, a first electrode of the tenth transistor electrically connected to one of the masking signal terminal and the second clock signal terminal, and a second electrode of the tenth transistor electrically connected to the driving output signal terminal;

[0120] The control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the driving output signal terminal;

[0121] A control electrode of the twelfth transistor is electrically connected to the fourth node, a first electrode of the twelfth transistor is electrically connected to the other of the mask signal terminal and the second clock signal terminal, and a second electrode of the twelfth transistor is electrically connected to the fifth node;

[0122] a control electrode of the thirteenth transistor electrically connected to the second clock signal terminal, a first electrode of the thirteenth transistor electrically connected to the second electrode of the fourteenth transistor, and a second electrode of the thirteenth transistor electrically connected to the fifth node;

[0123] The control electrode of the fourteenth transistor is electrically connected to the second node, and the first electrode of the fourteenth transistor is electrically connected to the first power supply terminal;

[0124] a control electrode of the fifteenth transistor electrically connected to the second power supply terminal, a first electrode of the fifteenth transistor electrically connected to one of the first node and the third node, and a second electrode of the fifteenth transistor electrically connected to the fourth node;

[0125] A first end of the first capacitor is electrically connected to the third node, and a second end of the first capacitor is electrically connected to the cascade output signal terminal;

[0126] A first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the first power supply terminal;

[0127] A first end of the fourth capacitor is electrically connected to the first power supply terminal, and a second end of the fourth capacitor is electrically connected to the cascade output signal terminal;

[0128] A first end of the fifth capacitor is electrically connected to the fifth node, and a second end of the fifth capacitor is electrically connected to the driving output signal terminal;

[0129] A first end of the sixth capacitor is electrically connected to the fourth node, and a second end of the sixth capacitor is electrically connected to the fifth node.

[0130] In an exemplary embodiment, the cascade output sub-circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitor, a second capacitor, and a third capacitor; the driver output sub-circuit includes: a tenth transistor, an eleventh transistor, and a fifth capacitor; and the node control sub-circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitor.

[0131] The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node;

[0132] The control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the second power supply terminal, and the second electrode of the second transistor is electrically connected to the second node;

[0133] The control electrode of the third transistor is electrically connected to the first end of the third capacitor, the first electrode of the third transistor is electrically connected to the second clock signal end, and the second electrode of the third transistor is electrically connected to the second node;

[0134] The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the second power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor;

[0135] The control electrode of the fifth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first node;

[0136] The control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the cascade output signal terminal;

[0137] The control electrode of the seventh transistor is electrically connected to the third node, the first electrode of the seventh transistor is electrically connected to the second clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the cascade output signal terminal;

[0138] a control electrode of the eighth transistor electrically connected to the second power supply terminal, a first electrode of the eighth transistor electrically connected to the first node, and a second electrode of the eighth transistor electrically connected to the third node;

[0139] a control electrode of the ninth transistor electrically connected to the first node, a first electrode of the ninth transistor electrically connected to the second power supply terminal, and a second electrode of the ninth transistor electrically connected to the first terminal of the third capacitor;

[0140] a control electrode of the tenth transistor electrically connected to the fifth node, a first electrode of the tenth transistor electrically connected to one of the masking signal terminal and the second clock signal terminal, and a second electrode of the tenth transistor electrically connected to the driving output signal terminal;

[0141] The control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the driving output signal terminal;

[0142] A control electrode of the twelfth transistor is electrically connected to the fourth node, a first electrode of the twelfth transistor is electrically connected to the other of the mask signal terminal and the second clock signal terminal, and a second electrode of the twelfth transistor is electrically connected to the fifth node;

[0143] a control electrode of the thirteenth transistor electrically connected to the second clock signal terminal, a first electrode of the thirteenth transistor electrically connected to the second electrode of the fourteenth transistor, and a second electrode of the thirteenth transistor electrically connected to the fifth node;

[0144] The control electrode of the fourteenth transistor is electrically connected to the second node, and the first electrode of the fourteenth transistor is electrically connected to the first power supply terminal;

[0145] a control electrode of the fifteenth transistor electrically connected to the second power supply terminal, a first electrode of the fifteenth transistor electrically connected to one of the first node and the third node, and a second electrode of the fifteenth transistor electrically connected to the fourth node;

[0146] A first end of the first capacitor is electrically connected to the third node, and a second end of the first capacitor is electrically connected to the cascade output signal terminal;

[0147] A first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the first power supply terminal;

[0148] The second end of the third capacitor is electrically connected to the second clock signal end;

[0149] A first end of the fifth capacitor is electrically connected to the fifth node, and a second end of the fifth capacitor is electrically connected to the driving output signal terminal;

[0150] A first end of the sixth capacitor is electrically connected to the fourth node, and a second end of the sixth capacitor is electrically connected to the fifth node.

[0151] In an exemplary embodiment, the cascade output sub-circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; the driver output sub-circuit includes: a tenth transistor, an eleventh transistor, and a fifth capacitor; and the node control sub-circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitor.

[0152] The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node;

[0153] The control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the second power supply terminal, and the second electrode of the second transistor is electrically connected to the second node;

[0154] The control electrode of the third transistor is electrically connected to the first end of the third capacitor, the first electrode of the third transistor is electrically connected to the second clock signal end, and the second electrode of the third transistor is electrically connected to the second node;

[0155] The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the second power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor;

[0156] The control electrode of the fifth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first node;

[0157] The control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the cascade output signal terminal;

[0158] The control electrode of the seventh transistor is electrically connected to the third node, the first electrode of the seventh transistor is electrically connected to the second clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the cascade output signal terminal;

[0159] a control electrode of the eighth transistor electrically connected to the second power supply terminal, a first electrode of the eighth transistor electrically connected to the first node, and a second electrode of the eighth transistor electrically connected to the third node;

[0160] a control electrode of the ninth transistor electrically connected to the first node, a first electrode of the ninth transistor electrically connected to the second power supply terminal, and a second electrode of the ninth transistor electrically connected to the first terminal of the third capacitor;

[0161] a control electrode of the tenth transistor electrically connected to the fifth node, a first electrode of the tenth transistor electrically connected to one of the masking signal terminal and the second clock signal terminal, and a second electrode of the tenth transistor electrically connected to the driving output signal terminal;

[0162] The control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the driving output signal terminal;

[0163] A control electrode of the twelfth transistor is electrically connected to the fourth node, a first electrode of the twelfth transistor is electrically connected to the other of the mask signal terminal and the second clock signal terminal, and a second electrode of the twelfth transistor is electrically connected to the fifth node;

[0164] a control electrode of the thirteenth transistor electrically connected to the second clock signal terminal, a first electrode of the thirteenth transistor electrically connected to the second electrode of the fourteenth transistor, and a second electrode of the thirteenth transistor electrically connected to the fifth node;

[0165] The control electrode of the fourteenth transistor is electrically connected to the second node, and the first electrode of the fourteenth transistor is electrically connected to the first power supply terminal;

[0166] a control electrode of the fifteenth transistor electrically connected to the second power supply terminal, a first electrode of the fifteenth transistor electrically connected to one of the first node and the third node, and a second electrode of the fifteenth transistor electrically connected to the fourth node;

[0167] A first end of the first capacitor is electrically connected to the third node, and a second end of the first capacitor is electrically connected to the cascade output signal terminal;

[0168] A first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the first power supply terminal;

[0169] The second end of the third capacitor is electrically connected to the second clock signal end;

[0170] A first end of the fourth capacitor is electrically connected to the first power supply terminal, and a second end of the fourth capacitor is electrically connected to the cascade output signal terminal;

[0171] A first end of the fifth capacitor is electrically connected to the fifth node, and a second end of the fifth capacitor is electrically connected to the driving output signal terminal;

[0172] A first end of the sixth capacitor is electrically connected to the fourth node, and a second end of the sixth capacitor is electrically connected to the fifth node.

[0173] In an exemplary embodiment, in the first display mode, the signal at the masking signal terminal is a first signal, and in the second display mode, the signal at the masking signal terminal is the first signal during at least a portion of the time period and is the second signal during at least a portion of the time period;

[0174] The time period when the signal of the masked signal terminal is the first signal does not overlap with the time period when the cascade output signal terminal outputs the signal, and the time period when the signal of the masked signal terminal is the second signal at least partially overlaps with the time period when the cascade output signal terminal outputs the signal;

[0175] A voltage value of at least one of the first signal and the second signal is constant, and the voltage value of the first signal is smaller than the voltage value of the second signal.

[0176] In an exemplary embodiment, in the second display mode, a time period during which the cascade output signal terminal outputs a signal is within a time period during which the signal of the masking signal terminal is the second signal.

[0177] In an exemplary embodiment, the moment when the signal at the masking signal terminal changes from the first signal to the second signal is before the output time period, wherein the output time period is the time period during which the cascade output signal terminal outputs a signal.

[0178] In a second aspect, the present disclosure further provides a gate drive circuit, comprising: a plurality of the above-mentioned shift registers;

[0179] The cascade output signal terminal of at least one stage of the shift register is electrically connected to the signal input terminal of at least one stage of the shift register.

[0180] In a third aspect, the present disclosure further provides a display device, comprising: the above-mentioned gate driving circuit.

[0181] In an exemplary embodiment, the device further comprises: sub-pixels arranged in an array, a plurality of first scan signal lines, and a plurality of data signal lines, wherein at least one sub-pixel is electrically connected to each of the first scan signal line and the data signal line;

[0182] At least one sub-pixel includes: a pixel driving circuit, the pixel driving circuit of at least one sub-pixel includes: a write transistor, the write transistor being electrically connected to the first scan signal line and the data signal line connected to the sub-pixel;

[0183] The driving output signal terminal of at least one stage of the shift register is electrically connected to the first scanning signal line connected to at least one row of pixel driving circuits.

[0184] In an exemplary embodiment, the present invention further comprises: a plurality of second reset signal lines and a plurality of second initial signal lines, and at least one sub-pixel is further electrically connected to the second reset signal line and the second initial signal line, respectively;

[0185] The pixel driving circuit of at least one sub-pixel further includes: an anode reset transistor, wherein the anode reset transistor is electrically connected to the second reset signal line and the second initial signal line connected to the sub-pixel;

[0186] The driving output signal terminal of at least one stage of the shift register is electrically connected to a second reset signal line connected to at least one row of pixel driving circuits;

[0187] The first scanning signal line and the second reset signal line connected to at least one row of pixel driving circuits are independently provided, or the second reset signal line connected to at least one row of pixel driving circuits is the same signal line as the first scanning signal line connected to the next row of pixel driving circuits.

[0188] In a fourth aspect, the present disclosure further provides a shift register driving method, which is configured to drive the above-mentioned shift register, the method comprising:

[0189] The cascade output subcircuit provides the signal of the first power supply terminal or the second clock signal terminal to the cascade output signal terminal under the control of the signal of the signal input terminal, the first clock signal terminal, the second clock signal terminal and the second power supply terminal;

[0190] The node control subcircuit provides a signal to the drive output subcircuit under the control of the signals from the cascade output subcircuit, the first power supply terminal, the second power supply terminal and the first control input signal terminal;

[0191] The driver output subcircuit provides the signal of the first power supply terminal or the second control input signal terminal to the driver output signal terminal under the control of the signals of the cascade output subcircuit and the node control subcircuit.

[0192] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0193] Summary of the Figures

[0194] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0195] FIG1 is a schematic structural diagram of a display device;

[0196] FIG2A is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0197] FIG2B is a schematic diagram of an equivalent circuit of another pixel driving circuit;

[0198] FIG3A is an operation timing diagram of the pixel driving circuit provided in FIG2A ;

[0199] FIG3B is an operation timing diagram of the pixel driving circuit provided in FIG2B ;

[0200] FIG4 is a schematic structural diagram of a shift register provided by an embodiment of the present disclosure;

[0201] FIG5 is an equivalent circuit diagram 1 of the cascade output subcircuit;

[0202] FIG6 is a second equivalent circuit diagram of the cascade output sub-circuit;

[0203] FIG7 is an equivalent circuit diagram 1 of the drive output subcircuit and the node control subcircuit;

[0204] FIG8 is a second equivalent circuit diagram of the drive output subcircuit and the node control subcircuit;

[0205] FIG9 is a third equivalent circuit diagram of the drive output subcircuit and the node control subcircuit;

[0206] FIG10 is a fourth equivalent circuit diagram of the drive output subcircuit and the node control subcircuit;

[0207] FIG11 is an equivalent circuit diagram 1 of a shift register;

[0208] FIG12 is a second equivalent circuit diagram of a shift register;

[0209] FIG13 is a third equivalent circuit diagram of a shift register;

[0210] FIG14 is a fourth equivalent circuit diagram of a shift register;

[0211] FIG15 is a fifth equivalent circuit diagram of a shift register;

[0212] FIG16 is an equivalent circuit diagram of a shift register;

[0213] FIG17 is an equivalent circuit diagram of a shift register;

[0214] FIG18 is an equivalent circuit diagram 8 of a shift register;

[0215] FIG19 is an operation timing diagram of the shift register provided in FIG11 to FIG18 in the first display mode;

[0216] FIG20 is an operation timing diagram of the shift register provided in FIG11 to FIG18 in the second display mode.

[0217] Details

[0218] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings below. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits the detailed description of some known functions and known components. The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0219] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0220] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0221] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0222] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0223] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0224] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0225] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0226] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0227] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0228] FIG1 is a schematic diagram of the structure of a display device. As shown in FIG1 , the display device may include a timing controller, a source driver circuit, a gate driver circuit, and a pixel array. The timing controller is respectively connected to the source driver circuit and the gate driver circuit. The source driver circuit is respectively connected to a plurality of data signal lines (D1 to Dn), and the gate driver circuit is respectively connected to a plurality of scan signal lines (S1 to Sm). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit. The circuit unit may include a pixel driver circuit, and the pixel driver circuit may be respectively connected to the scan signal lines and the data signal lines. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the source driver circuit to the source driver circuit, may provide clock signals, scan start signals, etc. suitable for the specifications of the gate driver circuit to the gate driver circuit, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The source driver circuit can generate a data voltage to be provided to the data signal lines D1, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller. For example, the source driver circuit can sample the grayscale value using a clock signal and apply the data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, where n can be a natural number. The gate driver circuit can generate a scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the gate driver circuit can sequentially provide a scan signal with a conduction level pulse to the scan signal lines S1 to Sm. For example, the gate driver circuit can be constructed in the form of a shift register and can sequentially transmit the scan start signal provided in the form of a conduction level pulse to the next level circuit under the control of the clock signal to generate a scan signal, where m can be a natural number.

[0229] In an exemplary embodiment, the subpixels may include a first subpixel P1 that emits a first color light, a second subpixel P2 that emits a second color light, and a third subpixel P3 that emits a third color light. Each of the first subpixel P1, the second subpixel P2, and the third subpixel P3 includes a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are connected to scan signal lines and data signal lines, respectively. The pixel driving circuits are configured to receive data voltages transmitted by the data signal lines under the control of the scan signal lines and output corresponding currents to the light-emitting devices. The light-emitting devices in the first subpixel P1, the second subpixel P2, and the third subpixel P3 are respectively connected to the pixel driving circuits of their respective subpixels. The light-emitting devices are configured to emit light of corresponding brightness in response to the currents output by the pixel driving circuits of their respective subpixels.

[0230] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) emitting red light, the second subpixel P2 may be a blue subpixel (B) emitting blue light, and the third subpixel P3 may be a green subpixel (G) emitting green light.

[0231] In an exemplary embodiment, the shape of the sub-pixel may be rectangular, diamond, pentagonal, or hexagonal, and the plurality of sub-pixels may be arranged in parallel horizontally, vertically, or in a herringbone pattern, which is not limited in the present disclosure.

[0232] In an exemplary embodiment, the light emitting device may be an OLED, which may include a first electrode (anode), a second electrode (cathode), and an organic light emitting layer between the first electrode and the second electrode.

[0233] In an exemplary embodiment, the organic light-emitting layer may include an emissive layer (EML) and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, hole transport layer, electron blocking layer, hole blocking layer, electron transport layer, and electron injection layer of all sub-pixels may be a common layer connected together, and the emissive layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0234] In example embodiments, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure.

[0235] Figure 2A is a schematic diagram of an equivalent circuit of a pixel driving circuit. As shown in Figure 2A, the pixel driving circuit may include 8 transistors (first transistor M1 to eighth transistor M8) and 1 storage capacitor C. Figure 2B is a schematic diagram of an equivalent circuit of another pixel driving circuit. As shown in Figure 2B, the pixel driving circuit may include 8 transistors (first transistor M1 to seventh transistor M7) and 1 storage capacitor C. As shown in Figures 2A and 2B, the pixel driving circuit may be connected to 11 signal lines (data signal line Data, first scan signal line Gate1, second scan signal line Gate2, first reset signal line Reset1, second reset signal line Reset2, light emitting signal line EM, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, first power line VDD and second power line VSS).

[0236] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the second node N2 , ie, the second end of the storage capacitor C is connected to the control electrode of the third transistor M3 .

[0237] The control electrode of the first transistor M1 is connected to the first reset signal line Reset1, the first electrode of the first transistor M1 is connected to the first initialization signal line INIT1, and the second electrode of the first transistor is connected to the third node N3. The first transistor T1 can be referred to as a first node reset transistor. When an on-level scan signal is applied to the first reset signal line Reset1, the first transistor M1 transmits an initialization voltage to the third node N3 to initialize the charge of the third node N3.

[0238] The control electrode of the second transistor M2 is connected to the second scan signal line Gate2, the first electrode of the second transistor M2 is connected to the second node N2, and the second electrode of the second transistor M2 is connected to the third node N3. The second transistor M2 can be called a compensation transistor. When an on-level scan signal is applied to the second scan signal line Gate2, the second transistor M2 connects the control electrode of the third transistor M3 to the second electrode to compensate or reset the control electrode of the third transistor M3.

[0239] The control electrode of the third transistor M3 is connected to the second node N2, the first electrode of the third transistor M3 is connected to the first node N1, and the second electrode of the third transistor M3 is connected to the third node N3. The third transistor M3 can be called a driving transistor. The third transistor M3 determines the magnitude of the driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between the control electrode and the first electrode of the third transistor M3.

[0240] The control electrode of the fourth transistor M4 is connected to the first scan signal line Gate1, the first electrode of the fourth transistor M4 is connected to the data signal line Data, and the second electrode of the fourth transistor M4 is connected to the first node N1. The fourth transistor M4 can be called a write transistor. When an on-level scan signal is applied to the first scan signal line Gate1, the fourth transistor M4 inputs the data voltage of the data signal line Data to the pixel driving circuit.

[0241] The control electrode of the fifth transistor M5 is connected to the light-emitting signal line EM, the first electrode of the fifth transistor M5 is connected to the first power line VDD, and the second electrode of the fifth transistor M5 is connected to the first node N1. The control electrode of the sixth transistor M6 is connected to the light-emitting signal line EM, the first electrode of the sixth transistor M6 is connected to the third node N3, and the second electrode of the sixth transistor M6 is connected to the first electrode of the light-emitting device. The fifth transistor M5 and the sixth transistor M6 can be referred to as light-emitting transistors. When an on-level light-emitting signal is applied to the light-emitting signal line EM, the fifth transistor M5 and the sixth transistor M6 form a drive current path between the first power line VDD and the second power line VSS, thereby causing the light-emitting device to emit light.

[0242] The control electrode of the seventh transistor M7 is connected to the second reset signal line Reset2, the first electrode of the seventh transistor M7 is connected to the second initialization signal line INIT2, and the second electrode of the seventh transistor M7 is connected to the first electrode of the light-emitting device. The seventh transistor M7 can be referred to as an anode reset transistor. When an on-level scan signal is applied to the second reset signal line Reset2, the seventh transistor M7 transmits an initialization voltage to the first electrode of the light-emitting device to initialize or release the charge accumulated in the first electrode of the light-emitting device.

[0243] The control electrode of the eighth transistor M8 is connected to the second reset signal line Reset2, the first electrode of the eighth transistor M8 is connected to the third initialization signal line INIT3, and the second electrode of the eighth transistor M8 is connected to the first node N1. The eighth transistor M8 can be referred to as a second node reset transistor. When an on-level scan signal is applied to the second reset signal line Reset2, the eighth transistor M8 transmits an initialization voltage to the first node to initialize the amount of charge accumulated in the eighth transistor M8.

[0244] In an exemplary embodiment, the second electrode of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a high level signal.

[0245] Transistors can be divided into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0246] In an exemplary embodiment, in the pixel driving circuit shown in FIG. 2A , the second transistor M2 may be an N-type transistor, and the first transistor M1 and the third transistor M3 to the eighth transistor M8 may be P-type transistors.

[0247] In an exemplary embodiment, in the pixel driving circuit shown in FIG. 2B , the first transistor M1 and the second transistor M2 may be N-type transistors, and the third transistor M3 to the seventh transistor M7 may be P-type transistors.

[0248] In an exemplary embodiment, in the pixel driving circuit provided in FIG. 2B , the second reset signal line connected to the sub-pixels in this row and the first scan signal line connected to the sub-pixels in the next row may be the same signal line, or may be the same signal or different signals.

[0249] Figure 3A is an operating timing diagram of the pixel driving circuit provided in Figure 2A. The following illustrates exemplary embodiments of the present disclosure using the operating process of the pixel driving circuit illustrated in Figure 2A. The pixel driving circuit in Figure 2A includes eight transistors (first transistor M1 to eighth transistor M8) and one storage capacitor C. The second transistor M2 is an N-type transistor, and the first transistor M1 and the third transistor M3 to the eighth transistor M8 are all P-type transistors.

[0250] In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0251] The first phase A1 is called the reset phase. The signals on the first reset signal line Reset and the second reset signal line Reset2 are low-level signals, and the signals on the first scan signal line Gate1, the second scan signal line Gate2, and the emission signal line EM are high-level signals. The signal on the first reset signal line Reset is low-level, the first transistor M1 is turned on, and the signal on the first initial signal line INIT1 is written to the third node N3, initializing (resetting) the third node N3 and clearing the existing charge in the third node N3. The signal on the second scan signal line Gate2 is high-level, the second transistor M2 is turned on, and the signal on the third node N3 is provided to the second node N2, initializing (resetting) the storage capacitor C and clearing the existing charge in the storage capacitor. The signal on the second reset signal line Reset2 is a low-level signal, turning on the seventh transistor M7 and the eighth transistor M8. This causes the signal on the second initialization signal line INIT2 to be supplied to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED and clearing the pre-stored voltage therein. The signal on the third initialization signal line INIT3 is supplied to the first node N1, initializing (resetting) the first node N1 and clearing the pre-stored voltage therein. The signals on the first scanning signal line Gate1 and the emission signal line EM are high-level signals, turning off the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6. During this phase, the OLED does not emit light.

[0252] In the second phase A2, also known as the data writing phase or the threshold compensation phase, the signal on the first scanning signal line Gate1 is a low-level signal, the signals on the first reset signal line Reset1, the second reset signal line Reset2, the second scanning signal line Reset2, and the emission signal line EM are high-level signals, and the data signal line Data outputs a data voltage. During this phase, the second end of the storage capacitor C is a low-level signal, so the third transistor M3 is turned on. When the signal on the first scan signal line Gate1 is low, the fourth transistor M4 is turned on, and when the signal on the second scan signal line Reset2 is high, the second transistor M2 is turned on. The second and fourth transistors M2 and M4 are turned on, so that the data voltage output by the data signal line Data is provided to the second node N2 via the first node N1, the turned-on third transistor M3, the third node N3, and the turned-on second transistor M2. The difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor M3 is charged into the storage capacitor C. The voltage at the second end (second node N2) of the storage capacitor C is Vd-|Vth|, where Vd is the data voltage output by the data signal line Data and Vth is the threshold voltage of the third transistor M3. The signals on the first reset signal line Reset1, the second reset signal line Reset2, and the emission signal line EM are high, turning off the first transistor M1, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the eighth transistor M8.

[0253] In the third phase A3, known as the light-emitting phase, the signals on the emission signal line EM and the second scan signal terminal Gate2 are low-level signals, while the signals on the first scan signal line Gate1, the first reset signal line Reset1, and the second reset signal line Reset2 are high-level signals. The low-level signal on the emission signal line EM turns on the fifth transistor M5 and the sixth transistor M6. The power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor M5, the third transistor M3, and the sixth transistor M6, driving the OLED to emit light. The signal on the second scan signal terminal Gate2 is low-level, while the signals on the first scan signal line Gate1, the first reset signal line Reset1, and the second reset signal line Reset2 are high-level signals, turning off the first transistor M1, the second transistor M2, the fourth transistor M4, the seventh transistor M7, and the eighth transistor M8.

[0254] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-|Vth|, the driving current of the third transistor M3 is: I=K*(Vgs-Vth) 2=K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0255] Wherein, I is the driving current flowing through the third transistor M3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0256] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor M3 is no longer affected by the threshold voltage of the third transistor M3, thereby eliminating the influence of the threshold voltage of the third transistor M3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0257] Figure 3B is an operating timing diagram of the pixel driving circuit provided in Figure 2B. The following describes an exemplary embodiment of the present disclosure using the operating process of the pixel driving circuit illustrated in Figure 2B. The pixel driving circuit in Figure 2B includes seven transistors (first transistor M1 to seventh transistor M7) and one storage capacitor C. The first transistor M1 and the second transistor M2 are N-type transistors, and the third transistor M3 to the seventh transistor M7 are P-type transistors.

[0258] In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0259] The first phase B1 is called the first reset phase. The signals on the first reset signal line Reset1, the second reset signal line Reset2, the first scan signal line Gate1, the second scan signal line Gate2, and the light-emitting signal line EM are high-level signals. The signal on the first reset signal line Reset is low-level, the first transistor M1 is turned on, and the signal on the first initial signal line INIT1 is written to the third node N3, initializing (resetting) the third node N3 and clearing the existing charge in the third node N3. The signal on the second scan signal line Gate2 is high-level, the second transistor M2 is turned on, and the signal on the third node N3 is provided to the second node N2, initializing (resetting) the storage capacitor C and clearing the existing charge in the storage capacitor. The signal on the second reset signal line Reset2 is low-level, and the signals on the first scan signal line Gate1, the second reset signal line Reset2, and the light-emitting signal line EM are high-level signals, turning off the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor T7. During this phase, the OLED does not emit light.

[0260] In the second phase B2, also known as the data writing phase or the threshold compensation phase, the signals on the first reset signal line Reset1 and the first scan signal line Gate1 are low-level signals, while the signals on the second reset signal line Reset2, the second scan signal line Reset2, and the luminescence signal line EM are high-level signals. The data signal line Data outputs a data voltage. During this phase, the second end of the storage capacitor C is at a low-level signal, so the third transistor M3 is turned on. The signal on the first scan signal line Gate1 is low, the fourth transistor M4 is turned on, the signal on the second scan signal line Reset2 is high, and the second transistor M2 is turned on. The second and fourth transistors M2 and M4 are turned on, so that the data voltage output by the data signal line Data is provided to the second node N2 via the first node N1, the turned-on third transistor M3, the third node N3, and the turned-on second transistor M2. The difference between the data voltage output by the data signal line Data and the threshold voltage of the third transistor M3 is charged into the storage capacitor C. The voltage at the second end (second node N2) of the storage capacitor C is Vd-|Vth|, where Vd is the data voltage output by the data signal line Data and Vth is the threshold voltage of the third transistor M3. The signal on the first reset signal line Reset1 is low, and the signals on the second reset signal line Reset2 and the emission signal line EM are high, turning off the first transistor M1, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7.

[0261] The third phase B3, known as the anode reset phase, is characterized by low-level signals on the first reset signal line Reset1, the second reset signal line Reset2, and the second scan signal line Gate2, while high-level signals on the first scan signal line Gate1 and the light-emitting signal line EM. The seventh transistor M7 is turned on, allowing the signal on the second initialization signal line INIT2 to be supplied to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED and clearing the pre-stored voltage within it. The signals on the first reset signal line Reset1 and the second scan signal line Gate2 are low-level signals, while the signals on the first scan signal line Gate1 and the light-emitting signal line EM are high-level signals. The first transistor M1, the second transistor M2, the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are turned off.

[0262] In the fourth phase B4, referred to as the light-emitting phase, the signals on the first reset signal line Reset1, the light-emitting signal line EM, and the second scanning signal terminal Gate2 are low-level signals, while the signals on the first scanning signal line Gate1 and the second reset signal line Reset2 are high-level signals. The low-level signal on the light-emitting signal line EM turns on the fifth transistor M5 and the sixth transistor M6. The power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor M5, third transistor M3, and sixth transistor M6, driving the OLED to emit light. The signals on the first scanning signal line Gate1 and the second scanning signal terminal Gate2 are low-level signals, while the signals on the first reset signal line Reset1 and the second reset signal line Reset2 are high-level signals, turning off the first transistor M1, the second transistor M2, the fourth transistor M4, and the seventh transistor M7.

[0263] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor M3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-|Vth|, the driving current of the third transistor M3 is: I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0264] Wherein, I is the driving current flowing through the third transistor M3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor M3, Vth is the threshold voltage of the third transistor M3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0265] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the third transistor M3 is no longer affected by the threshold voltage of the third transistor M3, thereby eliminating the influence of the threshold voltage of the third transistor M3 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0266] When the display device displays a picture, a driving signal is generated by the gate driving circuit, and the pixel driving circuit is initialized and data is written under the control of the driving signal, thereby realizing display. The picture displayed by the display device may include a normal picture and a special picture (for example: an off-screen display picture, a static picture or a picture that is less updated, etc.). When the display device displays a normal picture, it refreshes the picture in each frame, that is, the pixel driving circuit needs to be initialized and data written in each display frame. When the display device displays some special pictures, the original brightness can be maintained by a low-leakage pixel driving circuit. When the display device displays a special picture, the gate driving circuit generates a driving signal in each frame, and writing data to the pixel driving circuit will cause crosstalk in the picture of the display device, affecting the display effect of the display device.

[0267] Figure 4 is a schematic diagram of the structure of a shift register provided by an embodiment of the present disclosure. As shown in Figure 4, the shift register provided by an embodiment of the present disclosure may include: a cascade output subcircuit, a scan output subcircuit, and a node control subcircuit.

[0268] As shown in FIG4 , the cascade output sub-circuit is electrically connected to the signal input terminal IN, the first clock signal terminal CK, the second clock signal terminal CB, the first power supply terminal VGH, the second power supply terminal VGL and the cascade output signal terminal OUT1, and is configured to provide the signal of the first power supply terminal VGH or the second clock signal terminal CB to the cascade output signal terminal OUT1 under the control of the signals of the signal input terminal IN, the first clock signal terminal CK, the second clock signal terminal CB and the second power supply terminal VGL; the node control sub-circuit is electrically connected to the cascade output sub-circuit, the drive output sub-circuit, the first power supply terminal VGH, the second power supply terminal VGL and the first power supply terminal VGL, respectively. A control input signal terminal IN1 is electrically connected and configured to provide a signal to the driver output subcircuit under the control of a signal from the cascade output subcircuit, the first power supply terminal VGH, the second power supply terminal VGL, and the first control input signal terminal IN1. The driver output subcircuit is electrically connected to the cascade output subcircuit, the node control subcircuit, the first power supply terminal VGH, the second control input signal terminal IN2, and the driver output signal terminal OUT2, respectively, and configured to provide a signal from the first power supply terminal VGH or the second control input signal terminal IN2 to the driver output signal terminal OUT2 under the control of signals from the cascade output subcircuit and the node control subcircuit. The first control input signal terminal IN1 includes a second clock signal terminal CB, and the second control input signal terminal IN2 includes a mask signal terminal MS. Alternatively, the first control input signal terminal includes the second clock signal terminal CB and the mask signal terminal MS, and the second control input signal terminal IN2 includes the second clock signal terminal CB.

[0269] In an exemplary embodiment, the signal at the signal input terminal IN is a single pulse signal.

[0270] In an exemplary embodiment, the signal at either the first clock signal terminal CK1 or the second clock signal terminal CB may be a square wave signal that repeats a high voltage and a low voltage. For example, the signal at the first clock signal terminal CK1 and the second clock signal terminal CK2 may have the same period and may be configured as phase-shifted signals. Here, the signal at the second clock signal terminal CK2 may be phase-shifted by half a period compared to the signal at the first clock signal terminal CK1. The high voltage period in each period of the signal at either the first clock signal terminal CK1 or the second clock signal terminal CK2 may be set to be longer than the low voltage period.

[0271] In an exemplary embodiment, the high voltage period of the signal of the first clock signal terminal CK1 can be set so that its width overlaps with the low voltage period of the signal of the second clock signal terminal CK2, and the low voltage period of the signal of the first clock signal terminal CK1 can be set so that its width overlaps with the high voltage period of the signal of the second clock signal terminal CK2.

[0272] In an exemplary embodiment, the signal of the first power supply terminal VGH is a constant voltage signal and a high level signal.

[0273] In an exemplary embodiment, the signal of the second power terminal VGL is a constant voltage signal and a low level signal.

[0274] In an exemplary embodiment, the shift register is provided in a display device, and the content displayed by the display device includes multiple display frames. The driving output subcircuit provided in the embodiment of the present disclosure can control whether the shift register outputs a driving signal to a sub-pixel in the display device within a display frame.

[0275] The node control subcircuit and the drive output subcircuit provided in the shift register provided in the embodiment of the present disclosure can output a drive signal in each display frame when displaying a normal picture, repeatedly initialize and write data to the pixel drive circuit to ensure normal display. It can also not output a drive signal in some display frames when displaying a special picture, thereby avoiding crosstalk in the display device caused by data writing and improving the display effect of the display device.

[0276] In an exemplary embodiment, the display mode of the display device may include a first display mode and a second display mode, and a refresh rate of the first display mode is greater than a refresh rate of the second display mode.

[0277] In an exemplary embodiment, in the first display mode, the signal of the cascade output signal terminal OUT1 and the signal of the driving output signal terminal OUT2 of the shift register are the same.

[0278] In an exemplary embodiment, in the second display mode, the signal at the cascade output signal terminal OUT1 and the signal at the driving output signal terminal OUT2 of the shift register are inverted signals to each other at least partially.

[0279] In an exemplary embodiment, the cascade output sub-circuit may be 8T2C, 8T3C, 9T3C, or 9T4C, which is not limited in the present disclosure.

[0280] FIG5 is an equivalent circuit diagram of a cascade output subcircuit. As shown in FIG5 , in an exemplary embodiment, the cascade output subcircuit may include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a first capacitor C1, and a second capacitor C2.

[0281] As shown in FIG5 , the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal VGL, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is electrically connected to the first power supply terminal VGH, and the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the fifth transistor T5; the control electrode of the fifth transistor T5 is electrically connected to the second clock signal terminal CB, and the fifth transistor T5 is electrically connected to the second clock signal terminal CB. a second electrode of the sixth transistor T6 is electrically connected to the first node N1; a control electrode of the sixth transistor T6 is electrically connected to the second node N2, a first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal VGH, and a second electrode of the sixth transistor T6 is electrically connected to the cascade output signal terminal OUT1; a control electrode of the seventh transistor T7 is electrically connected to the third node N3, a first electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CB, and a second electrode of the seventh transistor T7 is electrically connected to the cascade output signal terminal OUT1; a control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal VGL, a first electrode of the eighth transistor T8 is electrically connected to the first node N1, and a second electrode of the eighth transistor T8 is electrically connected to the third node N3; a first end of the first capacitor C1 is electrically connected to the third node N3, and a second end of the first capacitor C1 is electrically connected to the cascade output signal terminal OUT1; a first end of the second capacitor C2 is electrically connected to the second node N2, and a second end of the second capacitor C2 is electrically connected to the first power supply terminal VGH.

[0282] FIG6 is a second equivalent circuit diagram of the cascade output sub-circuit. In an exemplary embodiment, as shown in FIG6 , the cascade output sub-circuit may include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0283] As shown in FIG6 , the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is electrically connected to the second power supply terminal VGL, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first end of the third capacitor C3, the first electrode of the third transistor T3 is electrically connected to the second clock signal terminal CB, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the second node N2, the first electrode of the fourth transistor T4 is electrically connected to the second power supply terminal VGL, and the second electrode of the fourth transistor T4 is electrically connected to the first electrode of the fifth transistor T5; the control electrode of the fifth transistor T5 is electrically connected to the second clock signal terminal CB, and the second electrode of the fifth transistor T5 is electrically connected to the first node N1; and the control electrode of the sixth transistor T6 is electrically connected to the second node N2. In addition, a first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal VGH, and a second electrode of the sixth transistor T6 is electrically connected to the cascade output signal terminal OUT1; a control electrode of the seventh transistor T7 is electrically connected to the third node N3, a first electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CB, and a second electrode of the seventh transistor T7 is electrically connected to the cascade output signal terminal OUT1; a control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal VGL, a first electrode of the eighth transistor T8 is electrically connected to the first node N1, and a second electrode of the eighth transistor T8 is electrically connected to the third node N3; a control electrode of the ninth transistor T9 is electrically connected to the first node N1, a first electrode of the ninth transistor T9 is electrically connected to the second power supply terminal VGL, and a second electrode of the ninth transistor T9 is electrically connected to a first end of a third capacitor C3; a first end of the first capacitor C1 is electrically connected to the third node N3, and a second end of the first capacitor C1 is electrically connected to the cascade output signal terminal OUT1; a first end of the second capacitor C2 is electrically connected to the second node N2, and a second end of the second capacitor C2 is electrically connected to the first power supply terminal VGH. A second end of the third capacitor C3 is electrically connected to the second clock signal terminal CB.

[0284] In an exemplary embodiment, as shown in FIG5 and FIG6 , the cascade output sub-circuit may further include a fourth capacitor C4 , wherein a first terminal of the fourth capacitor C4 is electrically connected to the first power supply terminal VGH, and a second terminal of the fourth capacitor C4 is electrically connected to the cascade output signal terminal OUT1 .

[0285] The provision of the fourth capacitor C4 in the present disclosure can ensure the stability of the signal at the cascade output signal terminal, thereby improving the reliability of the shift register.

[0286] In an exemplary embodiment, the sixth transistor T6 and the seventh transistor T7 in Figures 5 and 6 may be referred to as output transistors. A capacitance between a control electrode and a source electrode of at least one of the sixth transistor T6 and the seventh transistor T7 is greater than a capacitance between a control electrode and a source electrode of other transistors in the cascade output sub-circuit except the sixth transistor T6 and the seventh transistor T7.

[0287] FIG5 and FIG6 show two exemplary structures of the cascade output sub-circuit, and the implementation of the cascade output sub-circuit in the present disclosure is not limited thereto.

[0288] In an exemplary embodiment, as shown in FIG. 5 and FIG. 6 , a first node N1 , a second node N2 , and a third node N3 are provided in the cascade output sub-circuit.

[0289] In an exemplary embodiment, the first control input signal terminal includes: a second clock signal terminal CB and a mask signal terminal MS, and the second control input signal terminal includes: the second clock signal terminal CB, wherein the node control sub-circuit can be electrically connected to one of the first node N1 and the third node N3, the second node N2, the mask signal terminal MS, the second clock signal terminal CB, the first power supply terminal VGH, the second power supply terminal VGL, and the fifth node N5, respectively, and is configured to provide a signal of the first power supply terminal VGH or the mask signal terminal MS to the fifth node N5 under the control of signals of one of the first node N1 and the third node N3, the second node N2, the mask signal terminal MS, the second clock signal terminal CB, and the second power supply terminal VGL. The drive output sub-circuit is electrically connected to the second node N2, the fifth node N5, the second clock signal terminal CB, the first power supply terminal VGH, and the drive output signal terminal OUT2, respectively, and is configured to provide a signal of the first power supply terminal VGH or the mask signal terminal MS to the drive output signal terminal OUT2 under the control of signals of the second node N2 and the fifth node N5. UT2 provides a signal of the first power supply terminal VGH or the second clock signal terminal CB, or the first control input signal terminal includes: the second clock signal terminal CB, and the second control input signal terminal includes: when the mask signal terminal MS, the node control sub-circuit is electrically connected to one of the first node N1 and the third node N3, the second node N2, the second clock signal terminal CB, the first power supply terminal VGH, the second power supply terminal VGL and the fifth node N5, and is configured to provide the signal of the first power supply terminal VGH or the second clock signal terminal CB to the fifth node N5 under the control of the signals of one of the first node N1 and the third node N3, the second node N2, the second clock signal terminal CB and the second power supply terminal VGL; the drive output sub-circuit is electrically connected to the second node N2, the fifth node N5, the first power supply terminal VGH, the mask signal terminal MS and the drive output signal terminal OUT2, and is configured to provide the signal of the first power supply terminal VGH or the mask signal terminal MS to the drive output signal terminal OUT 2 under the control of the signals configured to be the second node N2 and the fifth node N5. FIG5 and FIG6 are explained by taking the driving output sub-circuit and the first node N1 as an example.

[0290] Figure 7 is an equivalent circuit diagram of the driver output subcircuit and the node control subcircuit. As shown in Figure 7, in the exemplary embodiment, the driver output subcircuit includes: a tenth transistor T10, an eleventh transistor T11, and a fifth capacitor C5, and the node control subcircuit includes: a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a sixth capacitor C6. The control electrode of the tenth transistor T10 is electrically connected to the fifth node N5, the first electrode of the tenth transistor T10 is electrically connected to the second clock signal terminal CB, and the second electrode of the tenth transistor T10 is electrically connected to the drive output signal terminal OUT2; the control electrode of the eleventh transistor T11 is electrically connected to the second node N2, the first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VGH, and the second electrode of the eleventh transistor T11 is electrically connected to the drive output signal terminal OUT2; the control electrode of the twelfth transistor T12 is electrically connected to the fourth node N4, the first electrode of the twelfth transistor T12 is electrically connected to the mask signal terminal MS, and the second electrode of the twelfth transistor T12 is electrically connected to the fifth node N5; the control electrode of the thirteenth transistor T13 is electrically connected to the second clock signal terminal CB, and the thirteenth transistor T13 is electrically connected to the second clock signal terminal CB. A first electrode of the transistor T13 is electrically connected to the second electrode of the fourteenth transistor T14, and the second electrode of the thirteenth transistor T13 is electrically connected to the fifth node N5; a control electrode of the fourteenth transistor T14 is electrically connected to the second node N2, and a first electrode of the fourteenth transistor T14 is electrically connected to the first power supply terminal VGH; a control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal VGL, a first electrode of the fifteenth transistor T15 is electrically connected to the first node N1, and a second electrode of the fifteenth transistor T15 is electrically connected to the fourth node N4; a first end of the fifth capacitor C5 is electrically connected to the fifth node N5, and a second end of the fifth capacitor C5 is electrically connected to the drive output signal terminal OUT2; a first end of the sixth capacitor C6 is electrically connected to the fourth node N4, and a second end of the sixth capacitor C6 is electrically connected to the fifth node N5. Figure 7 is an example of a node control sub-circuit electrically connected to the first node N1, the second node N2, the mask signal terminal MS, the second clock signal terminal CB, the first power supply terminal VGH, the second power supply terminal VGL and the fifth node N5, and a driver output sub-circuit electrically connected to the second node N2, the fifth node N5, the second clock signal terminal CB, the first power supply terminal VGH and the driver output signal terminal OUT2.

[0291] FIG8 is a second equivalent circuit diagram of the driver output subcircuit and the node control subcircuit. In an exemplary embodiment, as shown in FIG8 , the driver output subcircuit may include: a tenth transistor T10, an eleventh transistor T11, and a fifth capacitor C5; the node control subcircuit may include: a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a sixth capacitor C6. The control electrode of the tenth transistor T10 is electrically connected to the fifth node N5, the first electrode of the tenth transistor T10 is electrically connected to the mask signal terminal MS, and the second electrode of the tenth transistor T10 is electrically connected to the drive output signal terminal OUT2; the control electrode of the eleventh transistor T11 is electrically connected to the second node N2, the first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VGH, and the second electrode of the eleventh transistor T11 is electrically connected to the drive output signal terminal OUT2; the control electrode of the twelfth transistor T12 is electrically connected to the fourth node N4, the first electrode of the twelfth transistor T12 is electrically connected to the second clock signal terminal CB, and the second electrode of the twelfth transistor T12 is electrically connected to the fifth node N5; the control electrode of the thirteenth transistor T13 is electrically connected to the second clock signal terminal CB, and the control electrode of the thirteenth transistor T14 is electrically connected to the second clock signal terminal CB. A first electrode of the transistor T13 is electrically connected to the second electrode of the fourteenth transistor T14, and the second electrode of the thirteenth transistor T13 is electrically connected to the fifth node N5; a control electrode of the fourteenth transistor T14 is electrically connected to the second node N2, and a first electrode of the fourteenth transistor T14 is electrically connected to the first power supply terminal VGH; a control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal VGL, a first electrode of the fifteenth transistor T15 is electrically connected to the first node N1, and a second electrode of the fifteenth transistor T15 is electrically connected to the fourth node N4; a first end of the fifth capacitor C5 is electrically connected to the fifth node N5, and a second end of the fifth capacitor C5 is electrically connected to the drive output signal terminal OUT2; a first end of the sixth capacitor C6 is electrically connected to the fourth node N4, and a second end of the sixth capacitor C6 is electrically connected to the fifth node N5. Figure 8 is an example of a node control sub-circuit electrically connected to the first node N1, the second node N2, the second clock signal terminal CB, the first power supply terminal VGH, the second power supply terminal VGL and the fifth node N5, and a driver output sub-circuit electrically connected to the second node N2, the fifth node N5, the masking signal terminal MS, the first power supply terminal VGH and the driver output signal terminal OUT2.

[0292] FIG9 is a third equivalent circuit diagram of the driver output subcircuit and the node control subcircuit. In an exemplary embodiment, as shown in FIG9 , the driver output subcircuit includes a tenth transistor T10, an eleventh transistor T11, and a fifth capacitor C5, and the node control subcircuit includes a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, and a sixth capacitor C6. The control electrode of the tenth transistor T10 is electrically connected to the fifth node N5, the first electrode of the tenth transistor T10 is electrically connected to the second clock signal terminal CB, and the second electrode of the tenth transistor T10 is electrically connected to the drive output signal terminal OUT2; the control electrode of the eleventh transistor T11 is electrically connected to the second node N2, the first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VGH, and the second electrode of the eleventh transistor T11 is electrically connected to the drive output signal terminal OUT2; the control electrode of the twelfth transistor T12 is electrically connected to the fourth node N4, the first electrode of the twelfth transistor T12 is electrically connected to the mask signal terminal MS, and the second electrode of the twelfth transistor T12 is electrically connected to the fifth node N5; the control electrode of the thirteenth transistor T13 is electrically connected to the second clock signal terminal CB, and the thirteenth transistor T13 is electrically connected to the second clock signal terminal CB. A first electrode of the body transistor T13 is electrically connected to the second electrode of the fourteenth transistor T14, and the second electrode of the thirteenth transistor T13 is electrically connected to the fifth node N5; a control electrode of the fourteenth transistor T14 is electrically connected to the second node N2, and a first electrode of the fourteenth transistor T14 is electrically connected to the first power supply terminal VGH; a control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal VGL, a first electrode of the fifteenth transistor T15 is electrically connected to the third node N3, and a second electrode of the fifteenth transistor T15 is electrically connected to the fourth node N4; a first end of the fifth capacitor C5 is electrically connected to the fifth node N5, and a second end of the fifth capacitor C5 is electrically connected to the drive output signal terminal OUT2; a first end of the sixth capacitor C6 is electrically connected to the fourth node N4, and a second end of the sixth capacitor C6 is electrically connected to the fifth node N5. Figure 9 is an example of a node control sub-circuit electrically connected to the third node N3, the second node N2, the second clock signal terminal CB, the mask signal terminal MS, the first power supply terminal VGH, the second power supply terminal VGL and the fifth node N5, and a driver output sub-circuit electrically connected to the second node N2, the fifth node N5, the second clock signal terminal CB, the first power supply terminal VGH and the driver output signal terminal OUT2.

[0293] FIG10 is a fourth equivalent circuit diagram of the driver output subcircuit and the node control subcircuit. In an exemplary embodiment, as shown in FIG10 , the driver output subcircuit may include: a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a fifth capacitor C5, and a sixth capacitor C6. The control electrode of the tenth transistor T10 is electrically connected to the fifth node N5, the first electrode of the tenth transistor T10 is electrically connected to the mask signal terminal MS, and the second electrode of the tenth transistor T10 is electrically connected to the drive output signal terminal OUT2; the control electrode of the eleventh transistor T11 is electrically connected to the second node N2, the first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VGH, and the second electrode of the eleventh transistor T11 is electrically connected to the drive output signal terminal OUT2; the control electrode of the twelfth transistor T12 is electrically connected to the fourth node N4, the first electrode of the twelfth transistor T12 is electrically connected to the second clock signal terminal CB, and the second electrode of the twelfth transistor T12 is electrically connected to the fifth node N5; the control electrode of the thirteenth transistor T13 is electrically connected to the second clock signal terminal CB, and the control electrode of the thirteenth transistor T14 is electrically connected to the second clock signal terminal CB. A first electrode of the body transistor T13 is electrically connected to the second electrode of the fourteenth transistor T14, and the second electrode of the thirteenth transistor T13 is electrically connected to the fifth node N5; a control electrode of the fourteenth transistor T14 is electrically connected to the second node N2, and a first electrode of the fourteenth transistor T14 is electrically connected to the first power supply terminal VGH; a control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal VGL, a first electrode of the fifteenth transistor T15 is electrically connected to the third node N3, and a second electrode of the fifteenth transistor T15 is electrically connected to the fourth node N4; a first end of the fifth capacitor C5 is electrically connected to the fifth node N5, and a second end of the fifth capacitor C5 is electrically connected to the drive output signal terminal OUT2; a first end of the sixth capacitor C6 is electrically connected to the fourth node N4, and a second end of the sixth capacitor C6 is electrically connected to the fifth node N5. Figure 10 is an example of a node control sub-circuit electrically connected to the third node N3, the second node N2, the second clock signal terminal CB, the first power supply terminal VGH, the second power supply terminal VGL and the fifth node N5, and a driver output sub-circuit electrically connected to the second node N2, the fifth node N5, the masking signal terminal MS, the first power supply terminal VGH and the driver output signal terminal OUT2.

[0294] In the driver output sub-circuit provided in Figures 7 to 10, the tenth transistor T10 and the eleventh transistor T11 are output transistors. The capacitance between the control electrode and the source electrode of at least one of the tenth transistor T10 and the eleventh transistor T11 is greater than the capacitance between the control electrode and the source electrode of the other transistors in the shift register except the tenth transistor T10 and the eleventh transistor T11.

[0295] The output signal of the driving output signal terminal OUT2 in Figures 7 and 9 can be the signal of the second clock signal terminal CB, and the signal of the driving output signal terminal OUT2 in Figures 8 and 10 can be the signal of the mask signal terminal MS. Because the signal of the mask signal terminal MS does not frequently jump like the clock signal of the second clock signal terminal CB, the fifth capacitor C5 is charged by the signal of the mask signal terminal MS in Figures 8 and 10, which can reduce the power consumption of the shift register.

[0296] The twelfth transistor T12 and the fifteenth transistor T15 in the driver output sub-circuit provided in Figures 7 to 10 are arranged between the control electrode of the tenth transistor T10 and the first node N1, or between the control electrode of the tenth transistor T10 and the third node N3. That is, the control electrode of the seventh transistor T7 in the cascade output sub-circuit is separated from the control electrode of the tenth transistor T10 in the driver output sub-circuit. This avoids directly providing a control signal from the first node N1 or the third node N3 to the control electrode of the tenth transistor T10 in the driver output sub-circuit. This can prevent the attenuation of the signal at the first node N1 or the third node N3 from affecting the control signal provided by the control electrode of the tenth transistor T10, thereby ensuring the stability of the signal at the control electrode of the tenth transistor T10, and further improving the anti-interference performance of the driver output sub-circuit.

[0297] FIG. 7 to FIG. 10 show two exemplary structures of the driving output sub-circuit, and the implementation of the driving output sub-circuit in the present disclosure is not limited thereto.

[0298] Figure 11 is an equivalent circuit diagram 1 of a shift register, Figure 12 is an equivalent circuit diagram 2 of a shift register, Figure 13 is an equivalent circuit diagram 3 of a shift register, and Figure 14 is an equivalent circuit diagram 4 of a shift register. In exemplary embodiments, as shown in Figures 11 to 14, the cascade output subcircuit may include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a first capacitor C1, and a second capacitor C2, or may include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a first capacitor C1, a second capacitor C2, and a fourth capacitor C4. The driver output subcircuit includes: a tenth transistor T10, an eleventh transistor T11, and a fifth capacitor C5. The node control sub-circuit includes a twelfth transistor T12 , a thirteenth transistor T13 , a fourteenth transistor T14 , a fifteenth transistor T15 and a sixth capacitor C6 .

[0299] As shown in Figures 11 to 14, the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is electrically connected to the first clock signal terminal CK, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first clock signal terminal CK, the first electrode of the third transistor T3 is electrically connected to the second power supply terminal VGL, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the second node N2 is electrically connected, a first electrode of the fourth transistor T4 is electrically connected to the first power supply terminal VGH, a second electrode of the fourth transistor T4 is electrically connected to the first electrode of the fifth transistor T5; a control electrode of the fifth transistor T5 is electrically connected to the second clock signal terminal CB, and a second electrode of the fifth transistor T5 is electrically connected to the first node N1; a control electrode of the sixth transistor T6 is electrically connected to the second node N2, a first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal VGH, and a second electrode of the sixth transistor T6 is electrically connected to the cascade output signal terminal OUT1; a control electrode of the seventh transistor T7 is electrically connected to the third node N3, a first electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CB, and a second electrode of the seventh transistor T7 is electrically connected to the cascade output signal terminal OUT1; The output signal terminal OUT1 is electrically connected; the control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal VGL, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the third node N3; the control electrode of the tenth transistor T10 is electrically connected to the fifth node N5, the first electrode of the tenth transistor T10 is electrically connected to one of the mask signal terminal MS and the second clock signal terminal CB, and the second electrode of the tenth transistor T10 is electrically connected to the drive output signal terminal OUT2; the control electrode of the eleventh transistor T11 is electrically connected to the second node N2, the first electrode of the eleventh transistor T11 is electrically connected to the first power supply terminal VGH, and the second electrode of the eleventh transistor T11 is electrically connected to the The driving output signal terminal OUT2 is electrically connected; the control electrode of the twelfth transistor T12 is electrically connected to the fourth node N4, the first electrode of the twelfth transistor T12 is electrically connected to the other of the mask signal terminal MS and the second clock signal terminal CB, and the second electrode of the twelfth transistor T12 is electrically connected to the fifth node N5; the control electrode of the thirteenth transistor T13 is electrically connected to the second clock signal terminal CB, the first electrode of the thirteenth transistor T13 is electrically connected to the second electrode of the fourteenth transistor T14, and the second electrode of the thirteenth transistor T13 is electrically connected to the fifth node N5; the control electrode of the fourteenth transistor T14 is electrically connected to the second node N2, and the first electrode of the fourteenth transistor T14 is electrically connected to the first power supply terminal VGH;A control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal VGL, a first electrode of the fifteenth transistor T15 is electrically connected to one of the first node N1 and the third node N3, and a second electrode of the fifteenth transistor T15 is electrically connected to the fourth node N4; a first end of the first capacitor C1 is electrically connected to the third node N3, and a second end of the first capacitor C1 is electrically connected to the cascade output signal terminal OUT1; a first end of the second capacitor C2 is electrically connected to the second node N2, and a second end of the second capacitor C2 is electrically connected to the first power supply terminal VGH; a first end of the fourth capacitor C4 is electrically connected to the first power supply terminal VGH, and a second end of the fourth capacitor C4 is electrically connected to the cascade output signal terminal OUT1; a first end of the fifth capacitor C5 is electrically connected to the fifth node N5, and a second end of the fifth capacitor C5 is electrically connected to the drive output signal terminal OUT2; a first end of the sixth capacitor C6 is electrically connected to the fourth node N4, and a second end of the sixth capacitor C6 is electrically connected to the fifth node N5. Figure 11 illustrates an example in which the tenth transistor T10 is electrically connected to the second clock signal terminal CB, the first electrode of the twelfth transistor T12 is electrically connected to the mask signal terminal MS, and the first electrode of the fifteenth transistor T15 is electrically connected to the first node N1. Figure 12 illustrates an example in which the tenth transistor T10 is electrically connected to the second clock signal terminal CB, the first electrode of the twelfth transistor T12 is electrically connected to the mask signal terminal MS, and the first electrode of the fifteenth transistor T15 is electrically connected to the third node N3. Figure 13 illustrates an example in which the tenth transistor T10 is electrically connected to the mask signal terminal MS, the first electrode of the twelfth transistor T12 is electrically connected to the second clock signal terminal CB, and the first electrode of the fifteenth transistor T15 is electrically connected to the first node N1. Figure 14 illustrates an example in which the tenth transistor T10 is electrically connected to the mask signal terminal MS, the first electrode of the twelfth transistor T12 is electrically connected to the second clock signal terminal CB, and the first electrode of the fifteenth transistor T15 is electrically connected to the third node N3.

[0300] In example embodiments, at least one of the first to eighth transistors T1 to T8 and the ninth to fifteenth transistors T9 to T15 may be a P-type transistor.

[0301] FIG15 is an equivalent circuit diagram 5 of a shift register, FIG16 is an equivalent circuit diagram 6 of a shift register, FIG17 is an equivalent circuit diagram 7 of a shift register, and FIG18 is an equivalent circuit diagram 8 of a shift register. In exemplary embodiments, as shown in FIG15 to FIG18 , the cascade output subcircuit includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first capacitor C1, a second capacitor C2, and a third capacitor C3; or the cascade output subcircuit includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first capacitor C1, a second capacitor C2, a third capacitor C3, and a fourth capacitor C4. The driver output subcircuit includes: a tenth transistor T10, an eleventh transistor T11, and a fifth capacitor C5. The node control sub-circuit includes a twelfth transistor T12 , a thirteenth transistor T13 , a fourteenth transistor T14 , a fifteenth transistor T15 and a sixth capacitor C6 .

[0302] As shown in Figures 15 to 18, the control electrode of the first transistor T1 is electrically connected to the first clock signal terminal CK, the first electrode of the first transistor T1 is electrically connected to the signal input terminal IN, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the control electrode of the second transistor T2 is electrically connected to the first node N1, the first electrode of the second transistor T2 is electrically connected to the second power supply terminal VGL, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the control electrode of the third transistor T3 is electrically connected to the first end of the third capacitor C3, the first electrode of the third transistor T3 is electrically connected to the second clock signal terminal CB, and the second electrode of the third transistor T3 is electrically connected to the second node N2; the control electrode of the fourth transistor T4 is electrically connected to the second node N2. , a first electrode of the fourth transistor T4 is electrically connected to the second power supply terminal VGL, a second electrode of the fourth transistor T4 is electrically connected to the first electrode of the fifth transistor T5; a control electrode of the fifth transistor T5 is electrically connected to the second clock signal terminal CB, and a second electrode of the fifth transistor T5 is electrically connected to the first node N1; a control electrode of the sixth transistor T6 is electrically connected to the second node N2, a first electrode of the sixth transistor T6 is electrically connected to the first power supply terminal VGH, and a second electrode of the sixth transistor T6 is electrically connected to the cascade output signal terminal OUT1; a control electrode of the seventh transistor T7 is electrically connected to the third node N3, a first electrode of the seventh transistor T7 is electrically connected to the second clock signal terminal CB, and a second electrode of the seventh transistor T7 is electrically connected to the cascade output signal terminal OUT1 The control electrode of the eighth transistor T8 is electrically connected to the second power supply terminal VGL, the first electrode of the eighth transistor T8 is electrically connected to the first node N1, and the second electrode of the eighth transistor T8 is electrically connected to the third node N3; the control electrode of the ninth transistor T9 is electrically connected to the first node N1, the first electrode of the ninth transistor T9 is electrically connected to the second power supply terminal VGL, and the second electrode of the ninth transistor T9 is electrically connected to the first end of the third capacitor C3; the control electrode of the tenth transistor T10 is electrically connected to the fifth node N5, the first electrode of the tenth transistor T10 is electrically connected to one of the mask signal terminal MS and the second clock signal terminal CB, and the second electrode of the tenth transistor T10 is electrically connected to the drive output signal terminal OUT2; the eleventh transistor T1 a control electrode of the twelfth transistor T12 electrically connected to the fourth node N4, a first electrode of the twelfth transistor T12 electrically connected to the other of the mask signal terminal MS and the second clock signal terminal CB, and a second electrode of the twelfth transistor T12 electrically connected to the fifth node N5; a control electrode of the thirteenth transistor T13 electrically connected to the second clock signal terminal CB, a first electrode of the thirteenth transistor T13 electrically connected to the second electrode of the fourteenth transistor T14, and a second electrode of the thirteenth transistor T13 electrically connected to the fifth node N5;The control electrode of the fourteenth transistor T14 is electrically connected to the second node N2, and the first electrode of the fourteenth transistor T14 is electrically connected to the first power supply terminal VGH; the control electrode of the fifteenth transistor T15 is electrically connected to the second power supply terminal VGL, the first electrode of the fifteenth transistor T15 is electrically connected to one of the first node N1 and the third node N3, and the second electrode of the fifteenth transistor T15 is electrically connected to the fourth node N4; the first end of the first capacitor C1 is electrically connected to the third node N3, and the second end of the first capacitor C1 is electrically connected to the cascade output signal terminal OUT1; the first end of the second capacitor C2 is electrically connected to the second power supply terminal VGL, and the first electrode of the fifteenth transistor T15 is electrically connected to the fourth node N4. The first terminal of the first transistor T10 is electrically connected to the second clock signal terminal CB, the first terminal of the second capacitor C2 is electrically connected to the first power supply terminal VGH, and the second terminal of the third capacitor C3 is electrically connected to the second clock signal terminal CB. The first terminal of the fourth capacitor C4 is electrically connected to the first power supply terminal VGH, and the second terminal of the fourth capacitor C4 is electrically connected to the cascade output signal terminal OUT1. The first terminal of the fifth capacitor C5 is electrically connected to the fifth node N5, and the second terminal of the fifth capacitor C5 is electrically connected to the drive output signal terminal OUT2. The first terminal of the sixth capacitor C6 is electrically connected to the fourth node N4, and the second terminal of the sixth capacitor C6 is electrically connected to the fifth node N5. Figure 15 illustrates the example of the tenth transistor T10 being electrically connected to the second clock signal terminal CB, the first terminal of the twelfth transistor T12 being electrically connected to the mask signal terminal MS, and the first terminal of the fifteenth transistor T15 being electrically connected to the first node N1. Figure 16 illustrates the example of the tenth transistor T10 being electrically connected to the second clock signal terminal CB, the first terminal of the twelfth transistor T12 being electrically connected to the mask signal terminal MS, and the first terminal of the fifteenth transistor T15 being electrically connected to the third node N3. FIG17 illustrates an example in which the tenth transistor T10 is electrically connected to the mask signal terminal MS, the first electrode of the twelfth transistor T12 is electrically connected to the second clock signal terminal CB, and the first electrode of the fifteenth transistor T15 is electrically connected to the first node N1. FIG18 illustrates an example in which the tenth transistor T10 is electrically connected to the mask signal terminal MS, the first electrode of the twelfth transistor T12 is electrically connected to the second clock signal terminal CB, and the first electrode of the fifteenth transistor T15 is electrically connected to the third node N3.

[0303] In example embodiments, at least one of the first to fifteenth transistors T1 to T15 may be a P-type transistor.

[0304] In an exemplary embodiment, any capacitor among the first capacitor C1 to the sixth capacitor C6 can be a capacitor device made by a process. For example, a capacitor device can be realized by making a special capacitor electrode, and multiple capacitor electrodes of the capacitor can be realized by a metal layer, a semiconductor layer (such as doped polysilicon), etc. Alternatively, any capacitor among the first capacitor C1 to the sixth capacitor C6 can be a parasitic capacitance between multiple devices, which can be realized by the transistor itself and other devices and circuits. The connection method of any capacitor among the first capacitor C1 to the sixth capacitor C6 includes but is not limited to the method described above, and can be other applicable connection methods, and the level of the corresponding node can be stored. Here, the exemplary embodiment of the present disclosure is not limited to this.

[0305] Figure 19 is a timing diagram of the operation of the shift register provided in Figures 11 to 18 in the first display mode, and Figure 20 is a timing diagram of the operation of the shift register provided in Figures 11 to 18 in the second display mode. Figures 19 and 20 are described using the example that all transistors in the shift register are P-type transistors.

[0306] In an exemplary embodiment, as shown in FIG. 19 , in the first display mode, the signal at the masking signal terminal MS is the first signal V1 .

[0307] In an exemplary embodiment, as shown in FIG20 , in the second display mode, the signal at the masking signal terminal MS is the first signal V1 for at least a portion of the time period, and is the second signal V2 for at least a portion of the time period. The time period during which the masking signal terminal MS is the first signal V1 does not overlap with the time period during which the cascade output signal terminal OUT1 outputs a signal, while the time period during which the masking signal terminal MS is the second signal at least partially overlaps with the time period during which the cascade output signal terminal OUT1 outputs a signal. The voltage value of at least one of the first signal V1 and the second signal V2 is constant, and the voltage value of the first signal V1 is lower than the voltage value of the second signal V2.

[0308] In an exemplary embodiment, as shown in FIG. 20 , in the second display mode, the time period during which the cascade output signal terminal OUT1 outputs a signal is within the time period during which the signal of the mask signal terminal MS is the second signal.

[0309] In an exemplary embodiment, as shown in FIG20 , the time t at which the signal at the masking signal terminal MS changes from the first signal to the second signal occurs before the output time period, where the output time period is the time period during which the cascade output signal terminal outputs the signal.

[0310] In an exemplary embodiment, the time t at which the signal at the mask signal terminal MS changes from the first signal to the second signal can be within the first time period t1 or the second time period t2. In the first time period t1, the signal at the first clock signal terminal CK is a low-level signal. The first time period t1 occurs before the output time period, and the second time period t2 occurs between the first time period t1 and the output time period. The duration of the second time period t2 is less than the duration of at least one of the first time period t1 or the output time period. FIG. 20 illustrates the case where the time t at which the signal at the mask signal terminal MS changes from the first signal to the second signal is within the first time period t1.

[0311] In the shift registers provided in FIG. 11 to FIG. 18 , since the signal at the second power supply terminal VGL is a low-level signal, the eighth transistor T8 and the fifteenth transistor T15 are continuously turned on.

[0312] The difference between the shift register provided in FIG11 and the shift register provided in FIG12 is that the first electrode of the fifteenth transistor T15 is connected to different nodes. In the shift register provided in FIG11 , the signal of the first node N1 is written to the fourth node N4, while in the shift register provided in FIG12 , the signal of the third node N3 is written to the fourth node N4. Since the fifteenth transistor T15 is continuously turned on, the signals at the first node N1 and the third node N3 are the same. Therefore, the operation process of the shift register provided in FIG11 and the shift register provided in FIG12 is the same.

[0313] As shown in FIG19 , the operation process of the shift register provided in FIG11 and FIG12 in the first display mode is as follows:

[0314] In the first stage S11, the first clock signal terminal CK, the signal input terminal IN and the mask signal terminal MS are low-level signals, the signal of the second clock signal terminal CB is a high-level signal, the first transistor T1 and the third transistor T3 are turned on, and the fifth transistor T5 and the thirteenth transistor T13 are turned off.

[0315] The first transistor T1 is turned on, and the low-level signal of the signal input terminal IN is written into the first node N1. The low-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8. The seventh transistor T7 is turned on, and the high-level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1. The low-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15. The twelfth transistor T12 is turned on, and the low-level signal of the mask signal terminal MS is written into the fifth node N5. The tenth transistor T10 is turned on, and the high-level signal of the second clock signal terminal CB is written into the drive output signal terminal OUT2. The signal at the first node N1 is a low-level signal, the second transistor T2 is turned on, the low-level signal of the first clock signal terminal CK is written into the second node N2, the third transistor T3 is turned on, the low-level signal of the second power supply terminal VGL is written into the second node N2, the signal at the second node N2 is a low-level signal, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned on, and the high-level signal of the first power supply terminal VGH is written into the node connecting the fourth transistor T4 and the fifth transistor T5, the node connecting the thirteenth transistor T13 and the fourteenth transistor T14, the cascade output signal terminal OUT1 and the drive output signal terminal OUT2.

[0316] In this stage, the signals of the first node N1, the second node N2, the third node N3, the fourth node N4 and the fifth node N5 are all low level signals, and the signals of the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are high level signals.

[0317] In the second stage S12, the signals at the second clock signal terminal CB and the mask signal terminal MS are low-level signals, the signals at the first clock signal terminal CK and the signal input terminal IN are high-level signals, the first transistor T1 and the third transistor T3 are turned off, and the fifth transistor T5 and the thirteenth transistor T13 are turned on.

[0318] The first transistor T1 is disconnected, and the high-level signal of the signal input terminal IN cannot be written to the first node N1. The signal of the first node N1 maintains the low-level signal of the previous stage. The low-level signal of the first node N1 is written to the third node N3 through the conductive eighth transistor T8. The seventh transistor T7 is turned on, and the low-level signal of the second clock signal terminal CB is written to the cascade output signal terminal OUT1. The signal of the cascade output signal terminal OUT1 is a low-level signal. Under the action of the first capacitor C1, the signal of the third node N3 is continuously pulled low. The low-level signal of the third node N3 is written to the first node N1 through the conductive eighth transistor T8. The first node N1 is continuously pulled low. The low-level signal of the first node N1 or the third node N3 is written to the fourth node N4 through the conductive fifteenth transistor T15. The twelfth transistor T12 is turned on, and the low-level signal of the mask signal terminal MS is written to the fifth node N5. The tenth transistor T10 is turned on, and the low-level signal of the second clock signal terminal CB is written to the drive output signal terminal OUT2. The signal at the first node N1 is a low-level signal, the second transistor T2 is turned on, the high-level signal of the first clock signal terminal CK is written into the second node N2, the third transistor T3 is turned off, the low-level signal of the second power supply terminal VGL cannot be written into the second node N2, the signal at the second node N2 is a high-level signal, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned off, and the high-level signal of the first power supply terminal VGH cannot be written into the node connecting the fourth transistor T4 and the fifth transistor T5, the node connecting the thirteenth transistor T13 and the fourteenth transistor T14, the cascade output signal terminal OUT1 and the drive output signal terminal OUT2.

[0319] In this stage, the signals at the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all low level signals, the signal at the second node N2 is high level signal, and the signals at the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are low level signals.

[0320] In the third stage S13, the signals at the first clock signal terminal CK and the mask signal terminal MS are low-level signals, the signals at the signal input terminal IN and the second clock signal terminal CB are high-level signals, the first transistor T1 and the third transistor T3 are turned on, and the fifth transistor T5 and the thirteenth transistor T13 are turned off.

[0321] The first transistor T1 is turned on, and the high-level signal at the signal input terminal IN is written to the first node N1. The high-level signal at the first node N1 is written to the third node N3 via the turned-on eighth transistor T8. The seventh transistor T7 is turned off, and the high-level signal at the first node N1 or the third node N3 is written to the fourth node N4 via the turned-on fifteenth transistor T15. The twelfth transistor T12 is turned off, and the low-level signal at the masked signal terminal MS cannot be written to the fifth node N5. Since the signal at the fourth node N4 is pulled high in this stage, the signal at the fifth node N5 is also pulled high by the action of the sixth capacitor C6, and the signal at the fifth node N5 is a high-level signal. The tenth transistor T10 is turned off. The signal at the first node N1 is a high-level signal, the second transistor T2 is turned off, the low-level signal at the first clock signal terminal CK cannot be written into the second node N2, the third transistor T3 is turned on, the low-level signal at the second power supply terminal VGL is written into the second node N2, the signal at the second node N2 is a low-level signal, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned on, and the high-level signal at the first power supply terminal VGH is written into the node connecting the fourth transistor T4 and the fifth transistor T5, the node connecting the thirteenth transistor T13 and the fourteenth transistor T14, the cascade output signal terminal OUT1 and the drive output signal terminal OUT2.

[0322] In this stage, the signals of the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all high-level signals, the signal of the second node N2 is a low-level signal, and the signals of the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are high-level signals.

[0323] In the fourth stage S14, the signals of the second clock signal terminal CB and the mask signal terminal MS are low-level signals, the signals of the first clock signal terminal CK and the signal input terminal IN are high-level signals, the first transistor T1 and the third transistor T3 are turned off, and the fifth transistor T5 and the thirteenth transistor T13 are turned on.

[0324] The first transistor T1 is turned off, and the signal at the first node N1 remains high at the previous stage. The high-level signal at the first node N1 is written to the third node N3 via the conductive eighth transistor T8. The seventh transistor T7 is turned off, and the high-level signal at the first node N1 (third node N3) is written to the fourth node N4 via the conductive fifteenth transistor T15. The twelfth transistor T12 is turned off, preventing the low-level signal at the masked signal terminal MS from being written to the fifth node N5. The signal at the first node N1 remains high, and the second transistor T2 is turned off. The high-level signal at the first clock signal terminal CK cannot be written to the second node N2. Due to the action of the second capacitor C2, the signal at the second node N2 remains low at the previous stage. The fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned on, and the high-level signal at the first power supply terminal VGH is written to the node connecting the fourth transistor T4 and the fifth transistor T5, the node connecting the thirteenth transistor T13 and the fourteenth transistor T14, the cascade output signal terminal OUT1, and the driver output signal terminal OUT2. The high level signal of the first power supply terminal VGH is written into the fifth node N5 through the turned-on thirteenth transistor T13, and the tenth transistor T10 is turned off.

[0325] In this stage, the signals at the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all high level signals, the signal at the second node N2 is low level signal, and the signals at the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are high level signals.

[0326] Before the signal at the signal input terminal IN becomes a low level signal, the shift register continues to execute the third stage S13 and the fourth stage S14.

[0327] As shown in FIG20 , the operation process of the shift register provided in FIG11 and FIG12 in the second display mode is as follows:

[0328] In the first stage S21, the first clock signal terminal CK, the signal input terminal IN and the mask signal terminal MS are low-level signals, the signal of the second clock signal terminal CB is a high-level signal, the first transistor T1 and the third transistor T3 are turned on, and the fifth transistor T5 and the thirteenth transistor T13 are turned off.

[0329] The first transistor T1 is turned on, and the low-level signal of the signal input terminal IN is written into the first node N1. The low-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8. The seventh transistor T7 is turned on, and the high-level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1. The low-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15. The twelfth transistor T12 is turned on, and the low-level signal of the mask signal terminal MS is written into the fifth node N5. The tenth transistor T10 is turned on, and the high-level signal of the second clock signal terminal CB is written into the drive output signal terminal OUT2. The signal at the first node N1 is a low-level signal, the second transistor T2 is turned on, the low-level signal of the first clock signal terminal CK is written into the second node N2, the third transistor T3 is turned on, the low-level signal of the second power supply terminal VGL is written into the second node N2, the signal at the second node N2 is a low-level signal, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned on, and the high-level signal of the first power supply terminal VGH is written into the node connecting the fourth transistor T4 and the fifth transistor T5, the node connecting the thirteenth transistor T13 and the fourteenth transistor T14, the cascade output signal terminal OUT1 and the drive output signal terminal OUT2.

[0330] In this stage, the signals of the first node N1, the second node N2, the third node N3, the fourth node N4 and the fifth node N5 are all low level signals, and the signals of the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are high level signals.

[0331] In the second stage S22, the signal at the second clock signal terminal CB is a low-level signal, the signals at the first clock signal terminal CK, the signal input terminal IN, and the mask signal terminal MS are high-level signals, the first transistor T1 and the third transistor T3 are turned off, and the fifth transistor T5 and the thirteenth transistor T13 are turned on.

[0332] The first transistor T1 is turned off, and the high-level signal at the signal input terminal IN cannot be written to the first node N1. The signal at the first node N1 remains at the low-level signal of the previous stage. The low-level signal at the first node N1 is written to the third node N3 via the conductive eighth transistor T8. The seventh transistor T7 is turned on, and the low-level signal at the second clock signal terminal CB is written to the cascade output signal terminal OUT1. The signal at the cascade output signal terminal OUT1 is a low-level signal. Under the action of the first capacitor C1, the signal at the third node N3 is continuously pulled low. The low-level signal at the third node N3 is written to the first node N1 via the conductive eighth transistor T8. The first node N1 is continuously pulled low. The low-level signal at the first node N1 or the third node N3 is written to the fourth node N4 via the conductive fifteenth transistor T15. The twelfth transistor T12 is turned on, and the high-level signal at the masked signal terminal MS is written to the fifth node N5. The tenth transistor T10 is turned off, and the low-level signal at the second clock signal terminal CB cannot be written to the drive output signal terminal OUT2. Under the action of the fifth capacitor C5, the drive output signal terminal OUT2 remains at the high-level signal of the previous stage. The signal at the first node N1 is a low-level signal, the second transistor T2 is turned on, the high-level signal of the first clock signal terminal CK is written into the second node N2, the third transistor T3 is turned off, the low-level signal of the second power supply terminal VGL cannot be written into the second node N2, the signal at the second node N2 is a high-level signal, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned off, and the high-level signal of the first power supply terminal VGH cannot be written into the node connecting the fourth transistor T4 and the fifth transistor T5, the node connecting the thirteenth transistor T13 and the fourteenth transistor T14, the cascade output signal terminal OUT1 and the drive output signal terminal OUT2.

[0333] In this phase, the signals at the first, third, fourth, and fifth nodes N1, N3, N4, and N5 are all low-level signals, while the signal at the second node N2 is high-level. The signal at the cascade output signal terminal OUT1 is low-level, driving the output signal terminal OUT2 to float, maintaining the low-level signal from the previous phase.

[0334] In the third stage S23, the signal of the first clock signal terminal CK is a low-level signal, the signals of the mask signal terminal MS, the signal input terminal IN and the second clock signal terminal CB are high-level signals, the first transistor T1 and the third transistor T3 are turned on, and the fifth transistor T5 and the thirteenth transistor T13 are turned off.

[0335] The first transistor T1 is turned on, and the high-level signal of the signal input terminal IN is written into the first node N1. The high-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8. The seventh transistor T7 is turned off, and the high-level signal of the first node N1 (or the third node N3) is written into the fourth node N4 through the turned-on fifteenth transistor T15. The twelfth transistor T12 is turned off, and the high-level signal of the masked signal terminal MS cannot be written into the fifth node N5. Since the signal of the fourth node N4 is pulled high in this stage, the signal of the fifth node N5 is also pulled high under the action of the sixth capacitor C6. The signal of the fifth node N5 is a high-level signal, and the tenth transistor T10 is turned off. The signal at the first node N1 is a high-level signal, the second transistor T2 is turned off, the low-level signal at the first clock signal terminal CK cannot be written to the second node N2, the third transistor T3 is turned on, the low-level signal at the second power supply terminal VGL is written to the second node N2, the signal at the second node N2 is a low-level signal, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned on, and the high-level signal at the first power supply terminal VGH is written to the node connected to the fourth transistor T4 and the fifth transistor T5, the node connected to the thirteenth transistor T13 and the fourteenth transistor T14, the cascade output signal terminal OUT1, and the drive output signal terminal OUT2.

[0336] In this stage, the signals of the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all high-level signals, the signal of the second node N2 is a low-level signal, and the signals of the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are high-level signals.

[0337] In the fourth stage S24, the signal at the second clock signal terminal CB is a low-level signal, the signals at the first clock signal terminal CK, the signal input terminal IN and the mask signal terminal MS are high-level signals, the first transistor T1 and the third transistor T3 are turned off, and the fifth transistor T5 and the thirteenth transistor T13 are turned on.

[0338] The first transistor T1 is turned off, and the signal of the first node N1 maintains the high-level signal of the previous stage. The high-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8. The seventh transistor T7 is turned off, and the high-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15. The twelfth transistor T12 is turned off, and the high-level signal of the masked signal terminal MS cannot be written into the fifth node N5. The signal at the first node N1 is a high-level signal, the second transistor T2 is turned off, and the high-level signal at the first clock signal terminal CK cannot be written to the second node N2. Under the action of the second capacitor C2, the signal at the second node N2 remains at the low-level signal of the previous stage. The fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned on. The high-level signal at the first power supply terminal VGH is written into the node connected by the fourth transistor T4 and the fifth transistor T5, the node connected by the thirteenth transistor T13 and the fourteenth transistor T14, the cascade output signal terminal OUT1, and the drive output signal terminal OUT2. The high-level signal at the first power supply terminal VGH is written into the fifth node N5 through the turned-on thirteenth transistor T13, and the tenth transistor T10 is turned off.

[0339] In this stage, the signals at the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all high level signals, the signal at the second node N2 is low level signal, and the signals at the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are high level signals.

[0340] Before the signal at the signal input terminal IN becomes a low level signal, the shift register continues to execute the third stage S23 and the fourth stage S24.

[0341] The difference between the shift register provided in FIG13 and the shift register provided in FIG14 is that the first electrode of the fifteenth transistor T15 is connected to different nodes. In the shift register provided in FIG13 , the signal of the first node N1 is written to the fourth node N4, while in the shift register provided in FIG14 , the signal of the third node N3 is written to the fourth node N4. Since the fifteenth transistor T15 is continuously turned on, the signals at the first node N1 and the third node N3 are the same. Therefore, the operation process of the shift register provided in FIG13 and the shift register provided in FIG14 is the same.

[0342] As shown in FIG19 , the operation process of the shift register provided in FIG13 and FIG14 in the first display mode is as follows:

[0343] In the first stage S11, the first clock signal terminal CK, the signal input terminal IN and the mask signal terminal MS are low-level signals, the signal of the second clock signal terminal CB is a high-level signal, the first transistor T1 and the third transistor T3 are turned on, and the fifth transistor T5 and the thirteenth transistor T13 are turned off.

[0344] The first transistor T1 is turned on, and the low-level signal of the signal input terminal IN is written into the first node N1. The low-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8. The seventh transistor T7 is turned on, and the high-level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1. The low-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15. The twelfth transistor T12 is turned on, and the high-level signal of the second clock signal terminal CB is written into the fifth node N5. The tenth transistor T10 is turned off, and the low-level signal of the masked signal terminal MS cannot be written into the drive output signal terminal OUT2. The signal at the first node N1 is a low-level signal, the second transistor T2 is turned on, the low-level signal of the first clock signal terminal CK is written into the second node N2, the third transistor T3 is turned on, the low-level signal of the second power supply terminal VGL is written into the second node N2, the signal at the second node N2 is a low-level signal, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned on, and the high-level signal of the first power supply terminal VGH is written into the node connecting the fourth transistor T4 and the fifth transistor T5, the node connecting the thirteenth transistor T13 and the fourteenth transistor T14, the cascade output signal terminal OUT1 and the drive output signal terminal OUT2.

[0345] In this stage, the signals of the first node N1, the second node N2, the third node N3, the fourth node N4 and the fifth node N5 are all low level signals, and the signals of the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are high level signals.

[0346] In the second stage S12, the signals at the second clock signal terminal CB and the mask signal terminal MS are low-level signals, the signals at the first clock signal terminal CK and the signal input terminal IN are high-level signals, the first transistor T1 and the third transistor T3 are turned off, and the fifth transistor T5 and the thirteenth transistor T13 are turned on.

[0347] The first transistor T1 is disconnected, and the high-level signal of the signal input terminal IN cannot be written into the first node N1. The signal of the first node N1 maintains the low-level signal of the previous stage. The low-level signal of the first node N1 is written into the third node N3 through the conductive eighth transistor T8. The seventh transistor T7 is turned on, and the low-level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1. The signal of the cascade output signal terminal OUT1 is a low-level signal. Under the action of the first capacitor C1, the signal of the third node N3 is continuously pulled low. The low-level signal of the third node N3 is written into the first node N1 through the conductive eighth transistor T8. The first node N1 is continuously pulled low. The low-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the conductive fifteenth transistor T15. The twelfth transistor T12 is turned on, and the low-level signal of the second clock signal terminal CB is written into the fifth node N5. The tenth transistor T10 is turned on, and the low-level signal of the masking signal terminal MS is written into the driving output signal terminal OUT2. The signal at the first node N1 is a low-level signal, the second transistor T2 is turned on, the high-level signal of the first clock signal terminal CK is written into the second node N2, the third transistor T3 is turned off, the low-level signal of the second power supply terminal VGL cannot be written into the second node N2, the signal at the second node N2 is a high-level signal, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned off, and the high-level signal of the first power supply terminal VGH cannot be written into the node connecting the fourth transistor T4 and the fifth transistor T5, the node connecting the thirteenth transistor T13 and the fourteenth transistor T14, the cascade output signal terminal OUT1 and the drive output signal terminal OUT2.

[0348] In this stage, the signals at the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all low level signals, the signal at the second node N2 is high level signal, and the signals at the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are low level signals.

[0349] In the third stage S13, the signals at the first clock signal terminal CK and the mask signal terminal MS are low-level signals, the signals at the signal input terminal IN and the second clock signal terminal CB are high-level signals, the first transistor T1 and the third transistor T3 are turned on, and the fifth transistor T5 and the thirteenth transistor T13 are turned off.

[0350] The first transistor T1 is turned on, and the high-level signal at the signal input terminal IN is written into the first node N1. The high-level signal at the first node N1 is written into the third node N3 via the turned-on eighth transistor T8. The seventh transistor T7 is turned off, and the high-level signal at the first node N1 or the third node N3 is written into the fourth node N4 via the turned-on fifteenth transistor T15. The twelfth transistor T12 is turned off, and the high-level signal at the second clock signal terminal CB cannot be written into the fifth node N5. Since the signal at the fourth node N4 is pulled high in this stage, the signal at the fifth node N5 is also pulled high by the action of the sixth capacitor C6, and the signal at the fifth node N5 is a high-level signal. The tenth transistor T10 is turned off. The signal at the first node N1 is a high-level signal, the second transistor T2 is turned off, the low-level signal at the first clock signal terminal CK cannot be written into the second node N2, the third transistor T3 is turned on, the low-level signal at the second power supply terminal VGL is written into the second node N2, the signal at the second node N2 is a low-level signal, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned on, and the high-level signal at the first power supply terminal VGH is written into the node connecting the fourth transistor T4 and the fifth transistor T5, the node connecting the thirteenth transistor T13 and the fourteenth transistor T14, the cascade output signal terminal OUT1 and the drive output signal terminal OUT2.

[0351] In this stage, the signals of the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all high-level signals, the signal of the second node N2 is a low-level signal, and the signals of the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are high-level signals.

[0352] In the fourth stage S14, the signals of the second clock signal terminal CB and the mask signal terminal MS are low-level signals, the signals of the first clock signal terminal CK and the signal input terminal IN are high-level signals, the first transistor T1 and the third transistor T3 are turned off, and the fifth transistor T5 and the thirteenth transistor T13 are turned on.

[0353] The first transistor T1 is turned off, and the signal at the first node N1 remains high at the previous stage. The high-level signal at the first node N1 is written to the third node N3 via the conductive eighth transistor T8. The seventh transistor T7 is turned off, and the high-level signal at the first node N1 or the third node N3 is written to the fourth node N4 via the conductive fifteenth transistor T15. The twelfth transistor T12 is turned off, and the low-level signal at the second clock signal terminal CB cannot be written to the fifth node N5. The signal at the first node N1 is high, and the second transistor T2 is turned off. The high-level signal at the first clock signal terminal CK cannot be written to the second node N2. Due to the action of the second capacitor C2, the signal at the second node N2 remains low at the previous stage. The fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned on, and the high-level signal at the first power supply terminal VGH is written to the node connecting the fourth transistor T4 and the fifth transistor T5, the node connecting the thirteenth transistor T13 and the fourteenth transistor T14, the cascade output signal terminal OUT1, and the driver output signal terminal OUT2. The high level signal of the first power supply terminal VGH is written into the fifth node N5 through the turned-on thirteenth transistor T13, and the tenth transistor T10 is turned off.

[0354] In this stage, the signals at the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all high level signals, the signal at the second node N2 is low level signal, and the signals at the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are high level signals.

[0355] Before the signal at the signal input terminal IN becomes a low level signal, the shift register continues to execute the third stage S13 and the fourth stage S14.

[0356] As shown in FIG20 , the operation process of the shift register provided in FIG13 and FIG14 in the second display mode is as follows:

[0357] In the first stage S21, the first clock signal terminal CK, the signal input terminal IN and the mask signal terminal MS are low-level signals, the signal of the second clock signal terminal CB is a high-level signal, the first transistor T1 and the third transistor T3 are turned on, and the fifth transistor T5 and the thirteenth transistor T13 are turned off.

[0358] The first transistor T1 is turned on, and the low-level signal of the signal input terminal IN is written into the first node N1. The low-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8. The seventh transistor T7 is turned on, and the high-level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1. The low-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15. The twelfth transistor T12 is turned on, and the high-level signal of the second clock signal terminal CB is written into the fifth node N5. The tenth transistor T10 is turned off, and the low-level signal of the masked signal terminal MS cannot be written into the drive output signal terminal OUT2. The signal at the first node N1 is a low-level signal, the second transistor T2 is turned on, the low-level signal of the first clock signal terminal CK is written into the second node N2, the third transistor T3 is turned on, the low-level signal of the second power supply terminal VGL is written into the second node N2, the signal at the second node N2 is a low-level signal, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned on, and the high-level signal of the first power supply terminal VGH is written into the node connecting the fourth transistor T4 and the fifth transistor T5, the node connecting the thirteenth transistor T13 and the fourteenth transistor T14, the cascade output signal terminal OUT1 and the drive output signal terminal OUT2.

[0359] In this stage, the signals of the first node N1, the second node N2, the third node N3, the fourth node N4 and the fifth node N5 are all low level signals, and the signals of the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are high level signals.

[0360] In the second stage S22, the signal at the second clock signal terminal CB is a low-level signal, the signals at the first clock signal terminal CK, the signal input terminal IN, and the mask signal terminal MS are high-level signals, the first transistor T1 and the third transistor T3 are turned off, and the fifth transistor T5 and the thirteenth transistor T13 are turned on.

[0361] The first transistor T1 is disconnected, and the high-level signal of the signal input terminal IN cannot be written into the first node N1. The signal of the first node N1 maintains the low-level signal of the previous stage. The low-level signal of the first node N1 is written into the third node N3 through the conductive eighth transistor T8. The seventh transistor T7 is turned on, and the low-level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1. The signal of the cascade output signal terminal OUT1 is a low-level signal. Under the action of the first capacitor C1, the signal of the third node N3 is continuously pulled low. The low-level signal of the third node N3 is written into the first node N1 through the conductive eighth transistor T8. The first node N1 is continuously pulled low. The low-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the conductive fifteenth transistor T15. The twelfth transistor T12 is turned on, and the low-level signal of the second clock signal terminal CB is written into the fifth node N5. The tenth transistor T10 is turned on, and the high-level signal of the masked signal terminal MS is written into the drive output signal terminal OUT2. The signal at the first node N1 is a low-level signal, the second transistor T2 is turned on, the high-level signal of the first clock signal terminal CK is written into the second node N2, the third transistor T3 is turned off, the low-level signal of the second power supply terminal VGL cannot be written into the second node N2, the signal at the second node N2 is a high-level signal, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11 and the fourteenth transistor T14 are turned off, and the high-level signal of the first power supply terminal VGH cannot be written into the node connecting the fourth transistor T4 and the fifth transistor T5, the node connecting the thirteenth transistor T13 and the fourteenth transistor T14, the cascade output signal terminal OUT1 and the drive output signal terminal OUT2.

[0362] In this stage, the signals at the first node N1, the third node N3, the fourth node N4, and the fifth node N5 are all low-level signals, the signal at the second node N2 is high-level signal, the signal at the cascade output signal terminal OUT1 is low-level signal, and the signal at the drive output signal terminal OUT2 is high-level signal.

[0363] In the third stage S23, the signal of the first clock signal terminal CK is a low-level signal, the signals of the mask signal terminal MS, the signal input terminal IN and the second clock signal terminal CB are high-level signals, the first transistor T1 and the third transistor T3 are turned on, and the fifth transistor T5 and the thirteenth transistor T13 are turned off.

[0364] The first transistor T1 is turned on, and the high-level signal of the signal input terminal IN is written into the first node N1. The high-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8. The seventh transistor T7 is turned off, and the high-level signal of the first node N1 (or the third node N3) is written into the fourth node N4 through the turned-on fifteenth transistor T15. The twelfth transistor T12 is turned off, and the high-level signal of the second clock signal terminal CB cannot be written into the fifth node N5. Since the signal of the fourth node N4 is pulled high in this stage, the signal of the fifth node N5 is also pulled high under the action of the sixth capacitor C6. The signal of the fifth node N5 is a high-level signal, and the tenth transistor T10 is turned off. The signal at the first node N1 is a high-level signal, the second transistor T2 is turned off, the low-level signal at the first clock signal terminal CK cannot be written into the second node N2, the third transistor T3 is turned on, the low-level signal at the second power supply terminal VGL is written into the second node N2, the signal at the second node N2 is a low-level signal, the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned on, and the high-level signal at the first power supply terminal VGH is written into the node connected to the fourth transistor T4 and the fifth transistor T5, the node connected to the thirteenth transistor T13 and the fourteenth transistor T14, the cascade output signal terminal OUT1, and the drive output signal terminal OUT2.

[0365] In this stage, the signals of the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all high-level signals, the signal of the second node N2 is a low-level signal, and the signals of the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are high-level signals.

[0366] In the fourth stage S24, the signal at the second clock signal terminal CB is a low-level signal, the signals at the first clock signal terminal CK, the signal input terminal IN and the mask signal terminal MS are high-level signals, the first transistor T1 and the third transistor T3 are turned off, and the fifth transistor T5 and the thirteenth transistor T13 are turned on.

[0367] The first transistor T1 is turned off, and the signal of the first node N1 maintains the high-level signal of the previous stage. The high-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8. The seventh transistor T7 is turned off, and the high-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15. The twelfth transistor T12 is turned off, and the low-level signal of the second clock signal terminal CB cannot be written into the fifth node N5. The signal at the first node N1 is a high-level signal, the second transistor T2 is turned off, and the high-level signal at the first clock signal terminal CK cannot be written to the second node N2. Under the action of the second capacitor C2, the signal at the second node N2 remains at the low-level signal of the previous stage. The fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned on. The high-level signal at the first power supply terminal VGH is written into the node connected by the fourth transistor T4 and the fifth transistor T5, the node connected by the thirteenth transistor T13 and the fourteenth transistor T14, the cascade output signal terminal OUT1, and the drive output signal terminal OUT2. The high-level signal at the first power supply terminal VGH is written into the fifth node N5 through the turned-on thirteenth transistor T13, and the tenth transistor T10 is turned off.

[0368] In this stage, the signals at the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all high level signals, the signal at the second node N2 is low level signal, and the signals at the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are high level signals.

[0369] Before the signal at the signal input terminal IN becomes a low level signal, the shift register continues to execute the third stage S23 and the fourth stage S24.

[0370] The difference between the shift register provided in FIG15 and the shift register provided in FIG16 is that the first electrode of the fifteenth transistor T15 is connected to different nodes. In the shift register provided in FIG15 , the signal of the first node N1 is written to the fourth node N4, while in the shift register provided in FIG16 , the signal of the third node N3 is written to the fourth node N4. Since the fifteenth transistor T15 is continuously turned on, the signals at the first node N1 and the third node N3 are the same. Therefore, the operation process of the shift register provided in FIG15 and the shift register provided in FIG16 is the same.

[0371] As shown in FIG19 , the operation process of the shift register provided in FIG15 and FIG16 in the first display mode is as follows:

[0372] In the first stage S11, the first clock signal terminal CK, the signal input terminal IN and the mask signal terminal MS are low level signals, the signal of the second clock signal terminal CB is high level signal, the first transistor T1 is turned on, and the fifth transistor T5 and the thirteenth transistor T13 are turned off.

[0373] The first transistor T1 is turned on, and the low-level signal of the signal input terminal IN is written into the first node N1. The low-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8. The seventh transistor T7 is turned on, and the high-level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1. The low-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15. The twelfth transistor T12 is turned on, and the low-level signal of the mask signal terminal MS is written into the fifth node N5. The tenth transistor T10 is turned on, and the high-level signal of the second clock signal terminal CB is written into the drive output signal terminal OUT2. The signal at the first node N1 is a low-level signal, the second transistor T2 and the ninth transistor T9 are turned on, the high-level signal at the first power supply terminal VGH is written into the first end of the third capacitor C3 through the turned-on ninth transistor T9, and the third capacitor C3 is charged. The third transistor T3 is turned off, the high-level signal at the first power supply terminal VGH is written into the second node N2 through the turned-on second transistor T2, and the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned off.

[0374] In this stage, the signals at the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all low level signals, the signal at the second node N2 is high level signal, and the signals at the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are high level signals.

[0375] In the second stage S12, the signals at the second clock signal terminal CB and the mask signal terminal MS are low level signals, the signals at the signal input terminal IN and the first clock signal terminal CK are high level signals, the first transistor T1 is turned off, and the fifth transistor T5 and the thirteenth transistor T13 are turned on.

[0376] The first transistor T1 is turned off, so that the high-level signal of the signal input terminal IN cannot be written into the first node N1. The signal of the first node N1 maintains the low-level signal of the previous stage. Under the action of the first capacitor C1, the signal of the third node N3 is a low-level signal. The seventh transistor T7 is turned on, and the low-level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1. The low-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15. The twelfth transistor T12 is turned on, and the low-level signal of the mask signal terminal MS is written into the fifth node N5. The tenth transistor T10 is turned on, and the low-level signal of the second clock signal terminal CB is written into the drive output signal terminal OUT2. The signal at the first node N1 is a low-level signal, the second transistor T2 and the ninth transistor T9 are turned on, the high-level signal at the first power supply terminal VGH is still written into the first end of the third capacitor C3 through the turned-on ninth transistor T9, and the third capacitor C3 is charged. The third transistor T3 is turned off, and the high-level signal at the first power supply terminal VGH is written into the second node N2 through the turned-on second transistor T2. The fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned off.

[0377] In this stage, the signals at the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all low level signals, the signal at the second node N2 is high level signal, and the signals at the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are low level signals.

[0378] In the third stage S13, the signals at the first clock signal terminal CK and the mask signal terminal MS are low level signals, the signals at the signal input terminal IN and the second clock signal terminal CB are high level signals, the first transistor T1 is turned on, and the fifth transistor T5 and the thirteenth transistor T13 are turned off.

[0379] The first transistor T1 is turned on, and the high-level signal of the signal input terminal IN is written into the first node N1. The high-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8. The seventh transistor T7 is turned off. Under the coupling action of the first capacitor C1, the signal of the cascade output signal terminal OUT becomes a high-level signal. The high-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15. The twelfth transistor T12 is turned off, and the low-level signal of the masked signal terminal MS cannot be written into the fifth node N5. Under the coupling action of the sixth capacitor C6, the signal of the fifth node N5 becomes a high-level signal. The tenth transistor T10 is turned off. Under the coupling action of the fifth capacitor C5, the signal of the output signal terminal OUT2 is driven to become a high-level signal. The signal at the first node N1 is a high-level signal, the second transistor T2 and the ninth transistor T9 are disconnected, and the second end of the third capacitor C3 is floating. Due to the high-level signal at the second clock signal terminal CB, the signal at the second end of the third capacitor C3 is a high-level signal under the coupling effect of the third capacitor C3. The third transistor T3 is disconnected, and the second capacitor C2 is discharged, so that the signal at the second node N2 remains a high-level signal in the previous stage. The high-level signal at the first power supply terminal VGH cannot be written to the second node N2 through the conductive second transistor T2. The fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are disconnected.

[0380] In this stage, the signals of the first node N1, the second node N2, the third node N3, the fourth node N4 and the fifth node N5 are all high level signals, and the signals of the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are high level signals.

[0381] In the fourth stage S14, the signals at the second clock signal terminal CB and the mask signal terminal MS are low level signals, the signals at the signal input terminal IN and the first clock signal terminal CK are high level signals, the first transistor T1 is turned off, and the fifth transistor T5 and the thirteenth transistor T13 are turned on.

[0382] The first transistor T1 is disconnected, so that the high-level signal of the signal input terminal IN cannot be written to the first node N1. The signal of the first node N1 maintains the high-level signal of the previous stage. The high-level signal of the first node N1 is written to the third node N3 through the conductive eighth transistor T8. The seventh transistor T7 is disconnected, and the high-level signal of the first node N1 or the third node N3 is written to the fourth node N4 through the conductive fifteenth transistor T15. The twelfth transistor T12 is disconnected, and the low-level signal of the masked signal terminal MS cannot be written to the fifth node N5. The fifth node N5 maintains the high-level signal of the previous stage. The tenth transistor T10 is disconnected. The signal at the first node N1 is a high-level signal, the second transistor T2 and the ninth transistor T9 are disconnected, and the second end of the third capacitor C3 is floating. Due to the low-level signal of the signal at the second clock signal terminal CB, the signal at the second end of the third capacitor C3 is a low-level signal under the coupling effect of the third capacitor C3. The third transistor T3 is turned on, and the low-level signal at the second clock signal terminal CB is written to the second node N2. The fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned on, and the high-level signal of the first power supply terminal VGH is written to the cascade output signal terminal OUT1, the drive output signal terminal OUT2, the node connecting the fourth transistor T4 and the fifth transistor T5, and the node connecting the thirteenth transistor T13 and the fourteenth transistor T14. Since the fourth transistor T4 and the fifth transistor T5 are turned on, the high-level signal of the first power supply terminal VGH is written into the first node N1, so that the signal of the first node N1 remains at a high-level signal. Since the thirteenth transistor T13 and the fourteenth transistor T14 are turned on, the high-level signal of the first power supply terminal VGH is written into the fifth node N5, so that the signal of the fifth node N5 remains at a high-level signal.

[0383] In this stage, the signals of the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all high level signals, the signal of the second node N2 is low level signal, and the signals of the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are all high level signals.

[0384] As shown in FIG20 , the operation process of the shift register provided in FIG15 and FIG16 in the second display mode is as follows:

[0385] In the first stage S21, the signals at the first clock signal terminal CK and the signal input terminal IN are low-level signals, the signal at the masked signal terminal MS is a low-level signal in at least part of the time period and a high-level signal in at least part of the time period, and the time period in which the signal at the masked signal terminal MS is a low-level signal occurs before the time period in which the signal at the masked signal terminal MS is a high-level signal, the signal at the second clock signal terminal CB is a high-level signal, the first transistor T1 is turned on, and the fifth transistor T5 and the thirteenth transistor T13 are turned off.

[0386] The first transistor T1 is turned on, and the low-level signal at the signal input terminal IN is written to the first node N1. The low-level signal at the first node N1 is written to the third node N3 via the turned-on eighth transistor T8. The seventh transistor T7 is turned on, and the high-level signal at the second clock signal terminal CB is written to the cascade output signal terminal OUT1. The low-level signal at the first node N1 or the third node N3 is written to the fourth node N4 via the turned-on fifteenth transistor T15. The twelfth transistor T12 is turned on, and during the time period when the signal at the mask signal terminal MS is a low-level signal, the low-level signal at the mask signal terminal MS is written to the fifth node N5. The tenth transistor T10 is turned on, and the high-level signal at the second clock signal terminal CB is written to the drive output signal terminal OUT2. During the time period when the signal at the mask signal terminal MS is a high-level signal, the high-level signal at the mask signal terminal MS is written to the fifth node N5. The tenth transistor T10 is turned off. The signal at the first node N1 is a low-level signal, the second transistor T2 and the ninth transistor T9 are turned on, the high-level signal at the first power supply terminal VGH is written into the first end of the third capacitor C3 through the turned-on ninth transistor T9, and the third capacitor C3 is charged. The third transistor T3 is turned off, the high-level signal at the first power supply terminal VGH is written into the second node N2 through the turned-on second transistor T2, and the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned off.

[0387] In this stage, the signals at the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all low level signals, the signal at the second node N2 is high level signal, and the signals at the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are high level signals.

[0388] In the second stage S22, the signal at the second clock signal terminal CB is a low level signal, the signals at the signal input terminal IN, the first clock signal terminal CK and the mask signal terminal MS are high level signals, the first transistor T1 is turned off, and the fifth transistor T5 and the thirteenth transistor T13 are turned on.

[0389] The first transistor T1 is turned off, so that the high-level signal of the signal input terminal IN cannot be written to the first node N1. The signal of the first node N1 remains the low-level signal in the previous stage. Under the action of the first capacitor C1, the signal of the third node N3 is a low-level signal. The seventh transistor T7 is turned on, and the low-level signal of the second clock signal terminal CB is written to the cascade output signal terminal OUT1. The low-level signal of the first node N1 or the third node N3 is written to the fourth node N4 through the turned-on fifteenth transistor T15. The twelfth transistor T12 is turned on, and the high-level signal of the masked signal terminal MS is written to the fifth node N5. The tenth transistor T10 is turned off, and the low-level signal of the second clock signal terminal CB cannot be written to the drive output signal terminal OUT2. Under the coupling action of the fifth capacitor C5, the signal of the drive output signal terminal OUT2 remains the high-level signal in the previous stage. The signal at the first node N1 is a low-level signal, the second transistor T2 and the ninth transistor T9 are turned on, the high-level signal at the first power supply terminal VGH is still written into the first end of the third capacitor C3 through the turned-on ninth transistor T9, and the third capacitor C3 is charged. The third transistor T3 is turned off, and the high-level signal at the first power supply terminal VGH is written into the second node N2 through the turned-on second transistor T2. The fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned off.

[0390] In this phase, the signals at the first, third, fourth, and fifth nodes N1, N3, N4, and N5 are all low-level signals, while the signal at the second node N2 is high-level. The signal at the cascade output signal terminal OUT1 is low-level, driving the output signal terminal OUT2 to float and maintain the high-level signal from the previous phase.

[0391] In the third stage S23, the signal at the first clock signal terminal CK is a low level signal, the signals at the signal input terminal IN, the second clock signal terminal CB and the mask signal terminal MS are high level signals, the first transistor T1 is turned on, and the fifth transistor T5 and the thirteenth transistor T13 are turned off.

[0392] The first transistor T1 is turned on, and the high-level signal of the signal input terminal IN is written into the first node N1. The high-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8. The seventh transistor T7 is turned off. Under the coupling action of the first capacitor C1, the signal of the cascade output signal terminal OUT becomes a high-level signal. The high-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15. The twelfth transistor T12 is turned off, and the high-level signal of the masked signal terminal MS cannot be written into the fifth node N5. Under the coupling action of the sixth capacitor C6, the signal of the fifth node N5 becomes a high-level signal. The tenth transistor T10 is turned off. Under the coupling action of the fifth capacitor C5, the signal of the output signal terminal OUT2 is driven to become a high-level signal. The signal at the first node N1 is a high-level signal, the second transistor T2 and the ninth transistor T9 are disconnected, and the second end of the third capacitor C3 is floating. Due to the high-level signal at the second clock signal terminal CB, the signal at the second end of the third capacitor C3 is a high-level signal under the coupling effect of the third capacitor C3. The third transistor T3 is disconnected, and the second capacitor C2 is discharged, so that the signal at the second node N2 remains a high-level signal in the previous stage. The high-level signal at the first power supply terminal VGH cannot be written to the second node N2 through the conductive second transistor T2. The fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are disconnected.

[0393] In this stage, the signals of the first node N1, the second node N2, the third node N3, the fourth node N4 and the fifth node N5 are all high-level signals, the signal of the cascade output signal terminal OUT1 is a high-level signal, driving the output signal terminal OUT2 to float and maintain the high-level signal of the previous stage.

[0394] In the fourth stage S24, the signal at the second clock signal terminal CB is a low level signal, the signals at the signal input terminal IN, the first clock signal terminal CK and the mask signal terminal MS are high level signals, the first transistor T1 is turned off, and the fifth transistor T5 and the thirteenth transistor T13 are turned on.

[0395] The first transistor T1 is disconnected, so that the high-level signal of the signal input terminal IN cannot be written into the first node N1. The signal of the first node N1 maintains the high-level signal of the previous stage. The high-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8. The seventh transistor T7 is disconnected, and the high-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15. The twelfth transistor T12 is disconnected, and the high-level signal of the masked signal terminal MS cannot be written into the fifth node N5. The tenth transistor T10 is disconnected. The signal at the first node N1 is a high-level signal, the second transistor T2 and the ninth transistor T9 are disconnected, and the second end of the third capacitor C3 is floating. Due to the low-level signal of the signal at the second clock signal terminal CB, the signal at the second end of the third capacitor C3 is a low-level signal under the coupling effect of the third capacitor C3. The third transistor T3 is turned on, and the low-level signal at the second clock signal terminal CB is written to the second node N2. The fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned on, and the high-level signal of the first power supply terminal VGH is written to the cascade output signal terminal OUT1, the drive output signal terminal OUT2, the node connecting the fourth transistor T4 and the fifth transistor T5, and the node connecting the thirteenth transistor T13 and the fourteenth transistor T14. Since the fourth transistor T4 and the fifth transistor T5 are turned on, the high-level signal of the first power supply terminal VGH is written into the first node N1, so that the signal of the first node N1 remains at a high-level signal. Since the thirteenth transistor T13 and the fourteenth transistor T14 are turned on, the high-level signal of the first power supply terminal VGH is written into the fifth node N5, so that the signal of the fifth node N5 remains at a high-level signal.

[0396] In this stage, the signals of the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all high level signals, the signal of the second node N2 is low level signal, and the signals of the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are all high level signals.

[0397] The difference between the shift register provided in FIG17 and the shift register provided in FIG18 is that the first electrode of the fifteenth transistor T15 is connected to different nodes. In the shift register provided in FIG17 , the signal of the first node N1 is written to the fourth node N4, while in the shift register provided in FIG18 , the signal of the third node N3 is written to the fourth node N4. Since the fifteenth transistor T15 is continuously turned on, the signals at the first node N1 and the third node N3 are the same. Therefore, the operation process of the shift register provided in FIG17 and the shift register provided in FIG18 is the same.

[0398] As shown in FIG20 , the operation process of the shift register provided in FIG17 and FIG18 in the first display mode is as follows:

[0399] In the first stage S11, the first clock signal terminal CK, the signal input terminal IN and the mask signal terminal MS are low level signals, the signal of the second clock signal terminal CB is high level signal, the first transistor T1 is turned on, and the fifth transistor T5 and the thirteenth transistor T13 are turned off.

[0400] The first transistor T1 is turned on, and the low-level signal of the signal input terminal IN is written into the first node N1. The low-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8. The seventh transistor T7 is turned on, and the high-level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1. The low-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15. The twelfth transistor T12 is turned on, and the high-level signal of the second clock signal terminal CB is written into the fifth node N5. The tenth transistor T10 is turned off, and the low-level signal of the masked signal terminal MS cannot be written into the drive output signal terminal OUT2. The signal at the first node N1 is a low-level signal, the second transistor T2 and the ninth transistor T9 are turned on, the high-level signal at the first power supply terminal VGH is written into the first end of the third capacitor C3 through the turned-on ninth transistor T9, and the third capacitor C3 is charged. The third transistor T3 is turned off, the high-level signal at the first power supply terminal VGH is written into the second node N2 through the turned-on second transistor T2, and the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned off.

[0401] In this phase, the signals at the first, third, and fourth nodes N1, N3, and N4 are all low-level signals, while the signals at the second and fifth nodes N2 and N5 are high-level signals. The signal at the cascade output signal terminal OUT1 is high-level, driving the output signal terminal OUT2 to float and maintain the high-level signal from the previous phase.

[0402] In the second stage S12, the signals at the second clock signal terminal CB and the mask signal terminal MS are low level signals, the signals at the signal input terminal IN and the first clock signal terminal CK are high level signals, the first transistor T1 is turned off, and the fifth transistor T5 and the thirteenth transistor T13 are turned on.

[0403] The first transistor T1 is turned off, so that the high-level signal of the signal input terminal IN cannot be written into the first node N1. The signal of the first node N1 maintains the low-level signal of the previous stage. Under the action of the first capacitor C1, the signal of the third node N3 is a low-level signal. The signal of the third node N3 is a low-level signal. The seventh transistor T7 is turned on, and the low-level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1. The signal of the cascade output signal terminal OUT1 is a low-level signal. The low-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15. The twelfth transistor T12 is turned on, and the low-level signal of the second clock signal terminal CB is written into the fifth node N5. The tenth transistor T10 is turned on, and the low-level signal of the masking signal terminal MS is written into the driving output signal terminal OUT2. The signal at the first node N1 is a low-level signal, the second transistor T2 and the ninth transistor T9 are continuously turned on, the high-level signal at the first power supply terminal VGH is written into the first end of the third capacitor C3 through the turned-on ninth transistor T9, and the third capacitor C3 is charged. The third transistor T3 is turned off, and the high-level signal at the first power supply terminal VGH is written into the second node N2 through the turned-on second transistor T2. The fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned off.

[0404] In this stage, the signals at the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all low level signals, the signal at the second node N2 is high level signal, and the signals at the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are low level signals.

[0405] In the third stage S13, the signals at the first clock signal terminal CK and the mask signal terminal MS are low level signals, the signals at the signal input terminal IN and the second clock signal terminal CB are high level signals, the first transistor T1 is turned on, and the fifth transistor T5 and the thirteenth transistor T13 are turned off.

[0406] The first transistor T1 is turned on, and the high-level signal of the signal input terminal IN is written into the first node N1. The high-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8. The seventh transistor T7 is turned off. Under the coupling effect of the first capacitor C1, the signal of the cascade output signal terminal OUT becomes a high-level signal. The high-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15. The twelfth transistor T12 is turned off, and the high-level signal of the second clock signal terminal CB cannot be written into the fifth node N5. Under the coupling effect of the sixth capacitor C6, the signal of the fifth node N5 becomes a high-level signal. The tenth transistor T10 is turned off. Under the coupling effect of the fifth capacitor C5, the signal of the output signal terminal OUT2 is driven to become a high-level signal. The signal at the first node N1 is a high-level signal, the second transistor T2 and the ninth transistor T9 are disconnected, and the second end of the third capacitor C3 is floating. Due to the high-level signal at the second clock signal terminal CB, the signal at the second end of the third capacitor C3 is a high-level signal under the coupling effect of the third capacitor C3. The third transistor T3 is disconnected, and the second capacitor C2 is discharged, so that the signal at the second node N2 remains a high-level signal in the previous stage. The high-level signal at the first power supply terminal VGH cannot be written to the second node N2 through the conductive second transistor T2. The fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are disconnected.

[0407] In this stage, the signals of the first node N1, the second node N2, the third node N3, the fourth node N4 and the fifth node N5 are all high-level signals, the cascade output signal terminal OUT1 is floating and maintains the high-level signal of the previous stage, and the drive output signal terminal OUT2 is floating and maintains the high-level signal of the previous stage.

[0408] In the fourth stage S14, the signals at the second clock signal terminal CB and the mask signal terminal MS are low level signals, the signals at the signal input terminal IN and the first clock signal terminal CK are high level signals, the first transistor T1 is turned off, and the fifth transistor T5 and the thirteenth transistor T13 are turned on.

[0409] The first transistor T1 is turned off, so that the high-level signal of the signal input terminal IN cannot be written to the first node N1. The signal of the first node N1 maintains the high-level signal of the previous stage. The high-level signal of the first node N1 is written to the third node N3 through the conductive eighth transistor T8. The seventh transistor T7 is turned off, the first capacitor C1 is discharged, the signal of the cascade output signal terminal OUT1 is a high-level signal, the high-level signal of the first node N1 or the third node N3 is written to the fourth node N4 through the conductive fifteenth transistor T15, the twelfth transistor T12 is turned off, the low-level signal of the second clock signal terminal CB cannot be written to the fifth node N5, the fifth node N5 maintains the high-level signal of the previous stage, and the tenth transistor T10 is turned off. The signal at the first node N1 is a high-level signal, the second transistor T2 and the ninth transistor T9 are disconnected, and the second end of the third capacitor C3 is floating. Due to the low-level signal of the signal at the second clock signal terminal CB, the signal at the second end of the third capacitor C3 is a low-level signal under the coupling effect of the third capacitor C3. The third transistor T3 is turned on, and the low-level signal at the second clock signal terminal CB is written to the second node N2. The fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned on, and the high-level signal of the first power supply terminal VGH is written to the cascade output signal terminal OUT1, the drive output signal terminal OUT2, the node connecting the fourth transistor T4 and the fifth transistor T5, and the node connecting the thirteenth transistor T13 and the fourteenth transistor T14. Since the fourth transistor T4 and the fifth transistor T5 are turned on, the high-level signal of the first power supply terminal VGH is written into the first node N1, so that the signal of the first node N1 remains at a high-level signal. Since the thirteenth transistor T13 and the fourteenth transistor T14 are turned on, the high-level signal of the first power supply terminal VGH is written into the fifth node N5, so that the signal of the fifth node N5 remains at a high-level signal.

[0410] In this phase, the signals at the first, third, fourth, and fifth nodes N1, N3, N4, and N5 are all high-level signals, while the signal at the second node N2 is low-level. The cascade output signal terminal OUT1 is floating and maintains the high-level signal from the previous phase. The driver output signal terminal OUT2 is floating and maintains the high-level signal from the previous phase.

[0411] As shown in FIG20 , the operation process of the shift register provided in FIG17 and FIG18 in the second display mode is as follows:

[0412] In the first stage S21, the first clock signal terminal CK and the signal input terminal IN are low-level signals, the signal of the masked signal terminal MS is a low-level signal in at least part of the time period and a high-level signal in at least part of the time period, and the time period when the signal of the masked signal terminal MS is a low-level signal occurs before the time period when the signal of the masked signal terminal MS is a high-level signal, the signal of the second clock signal terminal CB is a high-level signal, the first transistor T1 is turned on, and the fifth transistor T5 and the thirteenth transistor T13 are turned off.

[0413] The first transistor T1 is turned on, and the low-level signal of the signal input terminal IN is written into the first node N1. The low-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8. The seventh transistor T7 is turned on, and the high-level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1. The low-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15. The twelfth transistor T12 is turned on, and the high-level signal of the second clock signal terminal CB is written into the fifth node N5. The tenth transistor T10 is turned off, and the low-level signal of the masked signal terminal MS cannot be written into the drive output signal terminal OUT2. The signal at the first node N1 is a low-level signal, the second transistor T2 and the ninth transistor T9 are turned on, the high-level signal at the first power supply terminal VGH is written into the first end of the third capacitor C3 through the turned-on ninth transistor T9, and the third capacitor C3 is charged. The third transistor T3 is turned off, the high-level signal at the first power supply terminal VGH is written into the second node N2 through the turned-on second transistor T2, and the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned off.

[0414] In this phase, the signals at the first, third, and fourth nodes N1, N3, and N4 are all low-level signals, while the signals at the second and fifth nodes N2 and N5 are high-level signals. The signal at the cascade output signal terminal OUT1 is high-level, driving the output signal terminal OUT2 to float and maintain the high-level signal from the previous phase.

[0415] In the second stage S22, the signal at the second clock signal terminal CB is a low level signal, the signals at the signal input terminal IN, the first clock signal terminal CK and the mask signal terminal MS are high level signals, the first transistor T1 is turned off, and the fifth transistor T5 and the thirteenth transistor T13 are turned on.

[0416] The first transistor T1 is turned off, so that the high-level signal of the signal input terminal IN cannot be written into the first node N1. The signal of the first node N1 maintains the low-level signal of the previous stage. Under the action of the first capacitor C1, the signal of the third node N3 is a low-level signal. The seventh transistor T7 is turned on, and the low-level signal of the second clock signal terminal CB is written into the cascade output signal terminal OUT1. The signal of the cascade output signal terminal OUT1 is a low-level signal. The low-level signal of the third node N3 is written into the first node N1 through the turned-on eighth transistor T8. The low-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15. The twelfth transistor T12 is turned on, and the low-level signal of the second clock signal terminal CB is written into the fifth node N5. The tenth transistor T10 is turned on, and the high-level signal of the masked signal terminal MS is written into the drive output signal terminal OUT2. The signal at the first node N1 is a low-level signal, the second transistor T2 and the ninth transistor T9 are turned on, the high-level signal at the first power supply terminal VGH is written into the first end of the third capacitor C3 through the turned-on ninth transistor T9, and the third capacitor C3 is charged. The third transistor T3 is turned off, the high-level signal at the first power supply terminal VGH is written into the second node N2 through the turned-on second transistor T2, and the fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned off.

[0417] In this stage, the signals at the first node N1, the third node N3, the fourth node N4, and the fifth node N5 are all low-level signals, the signal at the second node N2 is high-level signal, the signal at the cascade output signal terminal OUT1 is low-level signal, and the signal at the drive output signal terminal OUT2 is high-level signal.

[0418] In the third stage S23, the signal at the first clock signal terminal CK is a low level signal, the signals at the signal input terminal IN, the second clock signal terminal CB and the mask signal terminal MS are high level signals, the first transistor T1 is turned on, and the fifth transistor T5 and the thirteenth transistor T13 are turned off.

[0419] The first transistor T1 is turned on, and the high-level signal of the signal input terminal IN is written into the first node N1. The high-level signal of the first node N1 is written into the third node N3 through the turned-on eighth transistor T8. The seventh transistor T7 is turned off. Under the coupling effect of the first capacitor C1, the signal of the cascade output signal terminal OUT becomes a high-level signal. The high-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the turned-on fifteenth transistor T15. The twelfth transistor T12 is turned off, and the high-level signal of the second clock signal terminal CB cannot be written into the fifth node N5. Under the coupling effect of the sixth capacitor C6, the signal of the fifth node N5 becomes a high-level signal. The tenth transistor T10 is turned off, and the high-level signal of the masked signal terminal MS cannot be written into the drive output signal terminal OUT2. Under the coupling effect of the fifth capacitor C5, the signal of the drive output signal terminal OUT2 becomes a high-level signal. The signal at the first node N1 is a high-level signal, the second transistor T2 and the ninth transistor T9 are disconnected, and the second end of the third capacitor C3 is floating. Due to the high-level signal at the second clock signal terminal CB, the signal at the second end of the third capacitor C3 is a high-level signal under the coupling effect of the third capacitor C3. The third transistor T3 is disconnected, and the second capacitor C2 is discharged, so that the signal at the second node N2 remains a high-level signal in the previous stage. The high-level signal at the first power supply terminal VGH cannot be written to the second node N2 through the conductive second transistor T2. The fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are disconnected.

[0420] In this stage, the signals of the first node N1, the second node N2, the third node N3, the fourth node N4 and the fifth node N5 are all high-level signals, the signal of the cascade output signal terminal OUT1 is a high-level signal, driving the output signal terminal OUT2 to float and maintain the high-level signal of the previous stage.

[0421] In the fourth stage S24, the signal at the second clock signal terminal CB is a low level signal, the signals at the signal input terminal IN, the first clock signal terminal CK and the mask signal terminal MS are high level signals, the first transistor T1 is turned off, and the fifth transistor T5 and the thirteenth transistor T13 are turned on.

[0422] The first transistor T1 is disconnected, so that the high-level signal of the signal input terminal IN cannot be written into the first node N1. The signal of the first node N1 maintains the high-level signal of the previous stage. The high-level signal of the first node N1 is written into the third node N3 through the conductive eighth transistor T8. The seventh transistor T7 is disconnected, and the low-level signal of the second clock signal terminal CB cannot be written into the cascade output signal terminal OUT1. The high-level signal of the first node N1 or the third node N3 is written into the fourth node N4 through the conductive fifteenth transistor T15. The twelfth transistor T12 is disconnected, and the low-level signal of the second clock signal terminal CB cannot be written into the fifth node N5. The tenth transistor T10 is disconnected. The signal at the first node N1 is a high-level signal, the second transistor T2 and the ninth transistor T9 are disconnected, and the second end of the third capacitor C3 is floating. Due to the low-level signal of the signal at the second clock signal terminal CB, the signal at the second end of the third capacitor C3 is a low-level signal under the coupling effect of the third capacitor C3. The third transistor T3 is turned on, and the low-level signal at the second clock signal terminal CB is written to the second node N2. The fourth transistor T4, the sixth transistor T6, the eleventh transistor T11, and the fourteenth transistor T14 are turned on, and the high-level signal of the first power supply terminal VGH is written to the cascade output signal terminal OUT1, the drive output signal terminal OUT2, the node connecting the fourth transistor T4 and the fifth transistor T5, and the node connecting the thirteenth transistor T13 and the fourteenth transistor T14. Since the fourth transistor T4 and the fifth transistor T5 are turned on, the high-level signal of the first power supply terminal VGH is written into the first node N1, so that the signal of the first node N1 remains at a high-level signal. Since the thirteenth transistor T13 and the fourteenth transistor T14 are turned on, the high-level signal of the first power supply terminal VGH is written into the fifth node N5, so that the signal of the fifth node N5 remains at a high-level signal.

[0423] In this stage, the signals at the first node N1, the third node N3, the fourth node N4 and the fifth node N5 are all high level signals, the signal at the second node N2 is low level signal, and the signals at the cascade output signal terminal OUT1 and the drive output signal terminal OUT2 are high level signals.

[0424] An embodiment of the present disclosure further provides a shift register driving method, which is configured to drive the shift register provided by any of the aforementioned embodiments, and the method includes:

[0425] The cascade output subcircuit provides the signal of the first power supply terminal or the second clock signal terminal to the cascade output signal terminal under the control of the signals of the signal input terminal, the first clock signal terminal, the second clock signal terminal and the second power supply terminal.

[0426] The node control subcircuit provides a signal to the driving output subcircuit under the control of signals from the cascade output subcircuit, the first power supply terminal, the second power supply terminal and the first control input signal terminal.

[0427] The driver output subcircuit provides the signal of the first power supply terminal or the second control input signal terminal to the driver output signal terminal under the control of the signals of the cascade output subcircuit and the node control subcircuit.

[0428] An embodiment of the present disclosure further provides a gate driving circuit, comprising: a plurality of shift registers provided by any one of the aforementioned embodiments.

[0429] In an exemplary embodiment, the cascade output signal terminal of at least one stage of the shift register is electrically connected to the signal input terminal of at least one stage of the shift register.

[0430] An embodiment of the present disclosure further provides a display device, comprising: the gate driving circuit provided by any one of the aforementioned embodiments.

[0431] In an exemplary embodiment, the display device may further include: sub-pixels arranged in an array, a plurality of first scan signal lines, and a plurality of data signal lines. At least one sub-pixel includes the pixel driving circuit shown in Figures 2A and 2B, and the pixel driving circuit of at least one sub-pixel includes a write transistor electrically connected to the first scan signal line and the data signal line, respectively.

[0432] In an exemplary embodiment, the drive output signal terminal of at least one shift register stage is electrically connected to a first scan signal line connected to at least one pixel driving circuit. Specifically, the signal output by the drive output signal terminal of the shift register in the present disclosure is configured to control whether a write transistor is turned on, thereby controlling the writing of a data voltage of the data signal line into the pixel driving circuit.

[0433] In an exemplary embodiment, the display device may further include: a plurality of second reset signal lines and a plurality of second initial signal lines, wherein at least one subpixel is electrically connected to each of the second reset signal lines and the second initial signal line. The pixel driving circuit of the at least one subpixel further includes an anode reset transistor, wherein the anode reset transistor is electrically connected to each of the second reset signal lines and the second initial signal line connected to the subpixel.

[0434] The driving output signal terminal of at least one stage of the shift register is electrically connected to the second reset signal line connected to at least one row of pixel driving circuits.

[0435] In an exemplary embodiment, the first scan signal line and the second reset signal line connected to at least one row of pixel driving circuits are independently provided, or the second reset signal line connected to at least one row of pixel driving circuits is the same signal line as the first scan signal line connected to the next row of pixel driving circuits. FIG2A illustrates an example in which the first scan signal line and the second reset signal line connected to at least one row of pixel driving circuits are independently provided, while FIG2B illustrates an example in which the second reset signal line connected to at least one row of pixel driving circuits is the same signal line as the first scan signal line connected to the next row of pixel driving circuits.

[0436] The driving output signal terminal of at least one stage of the shift register is electrically connected to the first scanning signal line connected to at least one row of pixel driving circuits.

[0437] In an exemplary embodiment, the display substrate provided by the present disclosure can be used in a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0438] The drawings of the embodiments of the present disclosure only involve the structures involved in the embodiments of the present disclosure, and other structures may refer to general designs.

[0439] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0440] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A shift register comprising: cascade output subcircuit, driver output subcircuit and node control subcircuit; The cascade output sub-circuit is electrically connected to the signal input terminal, the first clock signal terminal, the second clock signal terminal, the first power supply terminal, the second power supply terminal and the cascade output signal terminal, respectively, and is configured to provide the signal of the first power supply terminal or the second clock signal terminal to the cascade output signal terminal under the control of the signals of the signal input terminal, the first clock signal terminal, the second clock signal terminal and the second power supply terminal; The node control subcircuit is electrically connected to the cascade output subcircuit, the driver output subcircuit, the first power supply terminal, the second power supply terminal, and the first control input signal terminal, respectively, and is configured to provide a signal to the driver output subcircuit under the control of signals from the cascade output subcircuit, the first power supply terminal, the second power supply terminal, and the first control input signal terminal; The driver output subcircuit is electrically connected to the cascade output subcircuit, the node control subcircuit, the first power supply terminal, the second control input signal terminal and the driver output signal terminal, respectively, and is configured to provide a signal from the first power supply terminal or the second control input signal terminal to the driver output signal terminal under the control of signals from the cascade output subcircuit and the node control subcircuit; The first control input signal terminal includes: a second clock signal terminal, the second control input signal terminal includes: a mask signal terminal, or the first control input signal terminal includes: a second clock signal terminal and a mask signal terminal, and the second control input signal terminal includes: a second clock signal terminal.

2. The shift register according to claim 1, wherein: The shift register is provided in a display device, the content displayed by the display device includes a plurality of display frames, and the display mode of the display device includes: a first display mode and a second display mode, and the refresh rate of the first display mode is greater than the refresh rate of the second display mode; In the first display mode, the signal at the cascade output signal terminal and the signal at the drive output signal terminal of the shift register are the same; In the second display mode, the signal at the cascade output signal terminal and the signal at the drive output signal terminal of the shift register are inverted signals at least partially.

3. The shift register according to claim 1, wherein: The cascade output subcircuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitor and a second capacitor; The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node; The control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the second node; A control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is electrically connected to the second power supply terminal, and a second electrode of the third transistor is electrically connected to the second node; The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor; The control electrode of the fifth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first node; The control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the cascade output signal terminal; The control electrode of the seventh transistor is electrically connected to the third node, the first electrode of the seventh transistor is electrically connected to the second clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the cascade output signal terminal; a control electrode of the eighth transistor electrically connected to the second power supply terminal, a first electrode of the eighth transistor electrically connected to the first node, and a second electrode of the eighth transistor electrically connected to the third node; A first end of the first capacitor is electrically connected to the third node, and a second end of the first capacitor is electrically connected to the cascade output signal terminal; A first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the first power supply end.

4. The shift register according to claim 1, wherein: The cascade output subcircuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitor, a second capacitor and a third capacitor; The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node; The control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the second power supply terminal, and the second electrode of the second transistor is electrically connected to the second node; The control electrode of the third transistor is electrically connected to the first end of the third capacitor, the first electrode of the third transistor is electrically connected to the second clock signal end, and the second electrode of the third transistor is electrically connected to the second node; The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the second power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor; The control electrode of the fifth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first node; The control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the cascade output signal terminal; The control electrode of the seventh transistor is electrically connected to the third node, the first electrode of the seventh transistor is electrically connected to the second clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the cascade output signal terminal; a control electrode of the eighth transistor electrically connected to the second power supply terminal, a first electrode of the eighth transistor electrically connected to the first node, and a second electrode of the eighth transistor electrically connected to the third node; a control electrode of the ninth transistor electrically connected to the first node, a first electrode of the ninth transistor electrically connected to the second power supply terminal, and a second electrode of the ninth transistor electrically connected to the first terminal of the third capacitor; A first end of the first capacitor is electrically connected to the third node, and a second end of the first capacitor is electrically connected to the cascade output signal terminal; A first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the first power supply terminal; The second end of the third capacitor is electrically connected to the second clock signal end.

5. The shift register according to claim 3 or 4, wherein: The cascade output sub-circuit further includes: a fourth capacitor; A first end of the fourth capacitor is electrically connected to the first power supply end, and a second end of the fourth capacitor is electrically connected to the cascade output signal end. The shift register according to claim 1 , wherein: The first control input signal terminal includes: a second clock signal terminal and a mask signal terminal, and the second control input signal terminal includes: a second clock signal terminal; The cascade output subcircuit is provided with a first node, a second node and a third node; The node control subcircuit is electrically connected to the first node, the second node, the mask signal terminal, the second clock signal terminal, the first power terminal, the second power terminal, and the fifth node, respectively, and is configured to provide a signal from the first power terminal or the mask signal terminal to the fifth node under the control of signals from the first node, the second node, the mask signal terminal, the second clock signal terminal, and the second power terminal; The drive output sub-circuit is electrically connected to the second node, the fifth node, the second clock signal terminal, the first power supply terminal and the drive output signal terminal, respectively, and is configured to provide a signal from the first power supply terminal or the second clock signal terminal to the drive output signal terminal under the control of the signals of the second node and the fifth node.

7. The shift register according to claim 6, wherein: The drive output sub-circuit includes: a tenth transistor, an eleventh transistor and a fifth capacitor; the node control sub-circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a sixth capacitor; The control electrode of the tenth transistor is electrically connected to the fifth node, the first electrode of the tenth transistor is electrically connected to the second clock signal terminal, and the second electrode of the tenth transistor is electrically connected to the drive output signal terminal; The control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the driving output signal terminal; The control electrode of the twelfth transistor is electrically connected to the fourth node, the first electrode of the twelfth transistor is electrically connected to the masking signal terminal, and the second electrode of the twelfth transistor is electrically connected to the fifth node; a control electrode of the thirteenth transistor electrically connected to the second clock signal terminal, a first electrode of the thirteenth transistor electrically connected to the second electrode of the fourteenth transistor, and a second electrode of the thirteenth transistor electrically connected to the fifth node; The control electrode of the fourteenth transistor is electrically connected to the second node, and the first electrode of the fourteenth transistor is electrically connected to the first power supply terminal; a control electrode of the fifteenth transistor electrically connected to the second power supply terminal, a first electrode of the fifteenth transistor electrically connected to the first node, and a second electrode of the fifteenth transistor electrically connected to the fourth node; A first end of the fifth capacitor is electrically connected to the fifth node, and a second end of the fifth capacitor is electrically connected to the driving output signal terminal; A first end of the sixth capacitor is electrically connected to the fourth node, and a second end of the sixth capacitor is electrically connected to the fifth node.

8. The shift register according to claim 1, wherein: The first control input signal terminal includes: a second clock signal terminal, and the second control input signal terminal includes: a mask signal terminal; The cascade output subcircuit is provided with a first node, a second node and a third node; The node control subcircuit is electrically connected to the first node, the second node, the second clock signal terminal, the first power terminal, the second power terminal, and the fifth node, respectively, and is configured to provide a signal from the first power terminal or the second clock signal terminal to the fifth node under the control of the signals from the first node, the second node, the second clock signal terminal, and the second power terminal; The drive output sub-circuit is electrically connected to the second node, the fifth node, the first power supply terminal, the masking signal terminal and the drive output signal terminal, respectively, and is configured to provide a signal from the first power supply terminal or the masking signal terminal to the drive output signal terminal under the control of signals configured as the second node and the fifth node.

9. The shift register according to claim 8, wherein: The drive output sub-circuit includes: a tenth transistor, an eleventh transistor and a fifth capacitor; the node control sub-circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a sixth capacitor; The control electrode of the tenth transistor is electrically connected to the fifth node, the first electrode of the tenth transistor is electrically connected to the masking signal terminal, and the second electrode of the tenth transistor is electrically connected to the driving output signal terminal; The control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the driving output signal terminal; a control electrode of the twelfth transistor electrically connected to the fourth node, a first electrode of the twelfth transistor electrically connected to the second clock signal terminal, and a second electrode of the twelfth transistor electrically connected to the fifth node; a control electrode of the thirteenth transistor electrically connected to the second clock signal terminal, a first electrode of the thirteenth transistor electrically connected to the second electrode of the fourteenth transistor, and a second electrode of the thirteenth transistor electrically connected to the fifth node; The control electrode of the fourteenth transistor is electrically connected to the second node, and the first electrode of the fourteenth transistor is electrically connected to the first power supply terminal; a control electrode of the fifteenth transistor electrically connected to the second power supply terminal, a first electrode of the fifteenth transistor electrically connected to the first node, and a second electrode of the fifteenth transistor electrically connected to the fourth node; A first end of the fifth capacitor is electrically connected to the fifth node, and a second end of the fifth capacitor is electrically connected to the driving output signal terminal; A first end of the sixth capacitor is electrically connected to the fourth node, and a second end of the sixth capacitor is electrically connected to the fifth node.

10. The shift register according to claim 1, wherein: The first control input signal terminal includes: a second clock signal terminal and a mask signal terminal, and the second control input signal terminal includes: a second clock signal terminal; The cascade output subcircuit is provided with a first node, a second node and a third node; The node control subcircuit is electrically connected to the second node, the third node, the mask signal terminal, the second clock signal terminal, the first power terminal, the second power terminal, and the fifth node, respectively, and is configured to provide a signal from the first power terminal or the mask signal terminal to the fifth node under the control of signals from the second node, the third node, the mask signal terminal, the second clock signal terminal, and the second power terminal; The drive output sub-circuit is electrically connected to the second node, the fifth node, the second clock signal terminal, the first power supply terminal and the drive output signal terminal, respectively, and is configured to provide a signal from the first power supply terminal or the second clock signal terminal to the drive output signal terminal under the control of the signals of the second node and the fifth node.

11. The shift register according to claim 10, wherein: The drive output sub-circuit includes: a tenth transistor, an eleventh transistor and a fifth capacitor; the node control sub-circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a sixth capacitor; The control electrode of the tenth transistor is electrically connected to the fifth node, the first electrode of the tenth transistor is electrically connected to the second clock signal terminal, and the second electrode of the tenth transistor is electrically connected to the drive output signal terminal; The control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the driving output signal terminal; The control electrode of the twelfth transistor is electrically connected to the fourth node, the first electrode of the twelfth transistor is electrically connected to the masking signal terminal, and the second electrode of the twelfth transistor is electrically connected to the fifth node; a control electrode of the thirteenth transistor electrically connected to the second clock signal terminal, a first electrode of the thirteenth transistor electrically connected to the second electrode of the fourteenth transistor, and a second electrode of the thirteenth transistor electrically connected to the fifth node; The control electrode of the fourteenth transistor is electrically connected to the second node, and the first electrode of the fourteenth transistor is electrically connected to the first power supply terminal; a control electrode of the fifteenth transistor electrically connected to the second power supply terminal, a first electrode of the fifteenth transistor electrically connected to the third node, and a second electrode of the fifteenth transistor electrically connected to the fourth node; A first end of the fifth capacitor is electrically connected to the fifth node, and a second end of the fifth capacitor is electrically connected to the driving output signal terminal; A first end of the sixth capacitor is electrically connected to the fourth node, and a second end of the sixth capacitor is electrically connected to the fifth node.

12. The shift register according to claim 1, wherein: The first control input signal terminal includes: a second clock signal terminal, and the second control input signal terminal includes: a mask signal terminal; The cascade output subcircuit is provided with a first node, a second node and a third node; The node control subcircuit is electrically connected to the second node, the third node, the second clock signal terminal, the first power terminal, the second power terminal, and the fifth node, respectively, and is configured to provide a signal from the first power terminal or the second clock signal terminal to the fifth node under the control of signals from the second node, the third node, the second clock signal terminal, and the second power terminal; The drive output sub-circuit is electrically connected to the second node, the fifth node, the first power supply terminal, the masking signal terminal and the drive output signal terminal, respectively, and is configured to provide a signal from the first power supply terminal or the masking signal terminal to the drive output signal terminal under the control of signals configured as the second node and the fifth node.

13. The shift register according to claim 12, wherein: The drive output sub-circuit includes: a tenth transistor, an eleventh transistor and a fifth capacitor; the node control sub-circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a sixth capacitor; The control electrode of the tenth transistor is electrically connected to the fifth node, the first electrode of the tenth transistor is electrically connected to the masking signal terminal, and the second electrode of the tenth transistor is electrically connected to the driving output signal terminal; The control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the driving output signal terminal; a control electrode of the twelfth transistor electrically connected to the fourth node, a first electrode of the twelfth transistor electrically connected to the second clock signal terminal, and a second electrode of the twelfth transistor electrically connected to the fifth node; a control electrode of the thirteenth transistor electrically connected to the second clock signal terminal, a first electrode of the thirteenth transistor electrically connected to the second electrode of the fourteenth transistor, and a second electrode of the thirteenth transistor electrically connected to the fifth node; The control electrode of the fourteenth transistor is electrically connected to the second node, and the first electrode of the fourteenth transistor is electrically connected to the first power supply terminal; a control electrode of the fifteenth transistor electrically connected to the second power supply terminal, a first electrode of the fifteenth transistor electrically connected to the third node, and a second electrode of the fifteenth transistor electrically connected to the fourth node; A first end of the fifth capacitor is electrically connected to the fifth node, and a second end of the fifth capacitor is electrically connected to the driving output signal terminal; A first end of the sixth capacitor is electrically connected to the fourth node, and a second end of the sixth capacitor is electrically connected to the fifth node.

14. The shift register according to claim 1, wherein: The cascade output subcircuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitor and a second capacitor; the drive output subcircuit includes: a tenth transistor, an eleventh transistor and a fifth capacitor; the node control subcircuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a sixth capacitor; The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node; The control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the second node; A control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is electrically connected to the second power supply terminal, and a second electrode of the third transistor is electrically connected to the second node; The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor; The control electrode of the fifth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first node; The control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the cascade output signal terminal; The control electrode of the seventh transistor is electrically connected to the third node, the first electrode of the seventh transistor is electrically connected to the second clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the cascade output signal terminal; a control electrode of the eighth transistor electrically connected to the second power supply terminal, a first electrode of the eighth transistor electrically connected to the first node, and a second electrode of the eighth transistor electrically connected to the third node; a control electrode of the tenth transistor electrically connected to the fifth node, a first electrode of the tenth transistor electrically connected to one of the masking signal terminal and the second clock signal terminal, and a second electrode of the tenth transistor electrically connected to the driving output signal terminal; The control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the driving output signal terminal; A control electrode of the twelfth transistor is electrically connected to the fourth node, a first electrode of the twelfth transistor is electrically connected to the other of the mask signal terminal and the second clock signal terminal, and a second electrode of the twelfth transistor is electrically connected to the fifth node; a control electrode of the thirteenth transistor electrically connected to the second clock signal terminal, a first electrode of the thirteenth transistor electrically connected to the second electrode of the fourteenth transistor, and a second electrode of the thirteenth transistor electrically connected to the fifth node; The control electrode of the fourteenth transistor is electrically connected to the second node, and the first electrode of the fourteenth transistor is electrically connected to the first power supply terminal; a control electrode of the fifteenth transistor electrically connected to the second power supply terminal, a first electrode of the fifteenth transistor electrically connected to one of the first node and the third node, and a second electrode of the fifteenth transistor electrically connected to the fourth node; A first end of the first capacitor is electrically connected to the third node, and a second end of the first capacitor is electrically connected to the cascade output signal terminal; A first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the first power supply terminal; A first end of the fifth capacitor is electrically connected to the fifth node, and a second end of the fifth capacitor is electrically connected to the driving output signal terminal; A first end of the sixth capacitor is electrically connected to the fourth node, and a second end of the sixth capacitor is electrically connected to the fifth node.

15. The shift register according to claim 1, wherein: The cascade output subcircuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitor, a second capacitor, and a fourth capacitor; the drive output subcircuit includes: a tenth transistor, an eleventh transistor, and a fifth capacitor; and the node control subcircuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitor; The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node; The control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the first clock signal terminal, and the second electrode of the second transistor is electrically connected to the second node; A control electrode of the third transistor is electrically connected to the first clock signal terminal, a first electrode of the third transistor is electrically connected to the second power supply terminal, and a second electrode of the third transistor is electrically connected to the second node; The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the first power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor; The control electrode of the fifth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first node; The control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the cascade output signal terminal; The control electrode of the seventh transistor is electrically connected to the third node, the first electrode of the seventh transistor is electrically connected to the second clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the cascade output signal terminal; a control electrode of the eighth transistor electrically connected to the second power supply terminal, a first electrode of the eighth transistor electrically connected to the first node, and a second electrode of the eighth transistor electrically connected to the third node; a control electrode of the tenth transistor electrically connected to the fifth node, a first electrode of the tenth transistor electrically connected to one of the masking signal terminal and the second clock signal terminal, and a second electrode of the tenth transistor electrically connected to the driving output signal terminal; The control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the driving output signal terminal; A control electrode of the twelfth transistor is electrically connected to the fourth node, a first electrode of the twelfth transistor is electrically connected to the other of the mask signal terminal and the second clock signal terminal, and a second electrode of the twelfth transistor is electrically connected to the fifth node; a control electrode of the thirteenth transistor electrically connected to the second clock signal terminal, a first electrode of the thirteenth transistor electrically connected to the second electrode of the fourteenth transistor, and a second electrode of the thirteenth transistor electrically connected to the fifth node; The control electrode of the fourteenth transistor is electrically connected to the second node, and the first electrode of the fourteenth transistor is electrically connected to the first power supply terminal; a control electrode of the fifteenth transistor electrically connected to the second power supply terminal, a first electrode of the fifteenth transistor electrically connected to one of the first node and the third node, and a second electrode of the fifteenth transistor electrically connected to the fourth node; A first end of the first capacitor is electrically connected to the third node, and a second end of the first capacitor is electrically connected to the cascade output signal terminal; A first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the first power supply terminal; A first end of the fourth capacitor is electrically connected to the first power supply terminal, and a second end of the fourth capacitor is electrically connected to the cascade output signal terminal; A first end of the fifth capacitor is electrically connected to the fifth node, and a second end of the fifth capacitor is electrically connected to the driving output signal terminal; A first end of the sixth capacitor is electrically connected to the fourth node, and a second end of the sixth capacitor is electrically connected to the fifth node.

16. The shift register according to claim 1, wherein: The cascade output subcircuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitor, a second capacitor, and a third capacitor; the drive output subcircuit includes: a tenth transistor, an eleventh transistor, and a fifth capacitor; and the node control subcircuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitor; The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node; The control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the second power supply terminal, and the second electrode of the second transistor is electrically connected to the second node; The control electrode of the third transistor is electrically connected to the first end of the third capacitor, the first electrode of the third transistor is electrically connected to the second clock signal end, and the second electrode of the third transistor is electrically connected to the second node; The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the second power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor; The control electrode of the fifth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first node; The control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the cascade output signal terminal; The control electrode of the seventh transistor is electrically connected to the third node, the first electrode of the seventh transistor is electrically connected to the second clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the cascade output signal terminal; a control electrode of the eighth transistor electrically connected to the second power supply terminal, a first electrode of the eighth transistor electrically connected to the first node, and a second electrode of the eighth transistor electrically connected to the third node; a control electrode of the ninth transistor electrically connected to the first node, a first electrode of the ninth transistor electrically connected to the second power supply terminal, and a second electrode of the ninth transistor electrically connected to the first terminal of the third capacitor; a control electrode of the tenth transistor electrically connected to the fifth node, a first electrode of the tenth transistor electrically connected to one of the masking signal terminal and the second clock signal terminal, and a second electrode of the tenth transistor electrically connected to the driving output signal terminal; The control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the driving output signal terminal; A control electrode of the twelfth transistor is electrically connected to the fourth node, a first electrode of the twelfth transistor is electrically connected to the other of the mask signal terminal and the second clock signal terminal, and a second electrode of the twelfth transistor is electrically connected to the fifth node; a control electrode of the thirteenth transistor electrically connected to the second clock signal terminal, a first electrode of the thirteenth transistor electrically connected to the second electrode of the fourteenth transistor, and a second electrode of the thirteenth transistor electrically connected to the fifth node; The control electrode of the fourteenth transistor is electrically connected to the second node, and the first electrode of the fourteenth transistor is electrically connected to the first power supply terminal; a control electrode of the fifteenth transistor electrically connected to the second power supply terminal, a first electrode of the fifteenth transistor electrically connected to one of the first node and the third node, and a second electrode of the fifteenth transistor electrically connected to the fourth node; A first end of the first capacitor is electrically connected to the third node, and a second end of the first capacitor is electrically connected to the cascade output signal terminal; A first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the first power supply terminal; The second end of the third capacitor is electrically connected to the second clock signal end; A first end of the fifth capacitor is electrically connected to the fifth node, and a second end of the fifth capacitor is electrically connected to the driving output signal terminal; A first end of the sixth capacitor is electrically connected to the fourth node, and a second end of the sixth capacitor is electrically connected to the fifth node.

17. The shift register according to claim 1, wherein: The cascade output sub-circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor; the drive output sub-circuit includes: a tenth transistor, an eleventh transistor, and a fifth capacitor; and the node control sub-circuit includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixth capacitor; The control electrode of the first transistor is electrically connected to the first clock signal terminal, the first electrode of the first transistor is electrically connected to the signal input terminal, and the second electrode of the first transistor is electrically connected to the first node; The control electrode of the second transistor is electrically connected to the first node, the first electrode of the second transistor is electrically connected to the second power supply terminal, and the second electrode of the second transistor is electrically connected to the second node; The control electrode of the third transistor is electrically connected to the first end of the third capacitor, the first electrode of the third transistor is electrically connected to the second clock signal end, and the second electrode of the third transistor is electrically connected to the second node; The control electrode of the fourth transistor is electrically connected to the second node, the first electrode of the fourth transistor is electrically connected to the second power supply terminal, and the second electrode of the fourth transistor is electrically connected to the first electrode of the fifth transistor; The control electrode of the fifth transistor is electrically connected to the second clock signal terminal, and the second electrode of the fifth transistor is electrically connected to the first node; The control electrode of the sixth transistor is electrically connected to the second node, the first electrode of the sixth transistor is electrically connected to the first power supply terminal, and the second electrode of the sixth transistor is electrically connected to the cascade output signal terminal; The control electrode of the seventh transistor is electrically connected to the third node, the first electrode of the seventh transistor is electrically connected to the second clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the cascade output signal terminal; a control electrode of the eighth transistor electrically connected to the second power supply terminal, a first electrode of the eighth transistor electrically connected to the first node, and a second electrode of the eighth transistor electrically connected to the third node; a control electrode of the ninth transistor electrically connected to the first node, a first electrode of the ninth transistor electrically connected to the second power supply terminal, and a second electrode of the ninth transistor electrically connected to the first terminal of the third capacitor; a control electrode of the tenth transistor electrically connected to the fifth node, a first electrode of the tenth transistor electrically connected to one of the masking signal terminal and the second clock signal terminal, and a second electrode of the tenth transistor electrically connected to the driving output signal terminal; The control electrode of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the first power supply terminal, and the second electrode of the eleventh transistor is electrically connected to the driving output signal terminal; A control electrode of the twelfth transistor is electrically connected to the fourth node, a first electrode of the twelfth transistor is electrically connected to the other of the mask signal terminal and the second clock signal terminal, and a second electrode of the twelfth transistor is electrically connected to the fifth node; a control electrode of the thirteenth transistor electrically connected to the second clock signal terminal, a first electrode of the thirteenth transistor electrically connected to the second electrode of the fourteenth transistor, and a second electrode of the thirteenth transistor electrically connected to the fifth node; The control electrode of the fourteenth transistor is electrically connected to the second node, and the first electrode of the fourteenth transistor is electrically connected to the first power supply terminal; a control electrode of the fifteenth transistor electrically connected to the second power supply terminal, a first electrode of the fifteenth transistor electrically connected to one of the first node and the third node, and a second electrode of the fifteenth transistor electrically connected to the fourth node; A first end of the first capacitor is electrically connected to the third node, and a second end of the first capacitor is electrically connected to the cascade output signal terminal; A first end of the second capacitor is electrically connected to the second node, and a second end of the second capacitor is electrically connected to the first power supply terminal; The second end of the third capacitor is electrically connected to the second clock signal end; A first end of the fourth capacitor is electrically connected to the first power supply terminal, and a second end of the fourth capacitor is electrically connected to the cascade output signal terminal; A first end of the fifth capacitor is electrically connected to the fifth node, and a second end of the fifth capacitor is electrically connected to the driving output signal terminal; A first end of the sixth capacitor is electrically connected to the fourth node, and a second end of the sixth capacitor is electrically connected to the fifth node.

18. The shift register according to claim 2, wherein: In the first display mode, the signal at the masking signal end is the first signal; in the second display mode, the signal at the masking signal end is the first signal in at least a portion of the time period and is the second signal in at least a portion of the time period; The time period when the signal of the masked signal terminal is the first signal does not overlap with the time period when the cascade output signal terminal outputs the signal, and the time period when the signal of the masked signal terminal is the second signal at least partially overlaps with the time period when the cascade output signal terminal outputs the signal; A voltage value of at least one of the first signal and the second signal is constant, and the voltage value of the first signal is smaller than the voltage value of the second signal.

19. The shift register according to claim 18, wherein: In the second display mode, a time period during which the cascade output signal terminal outputs a signal is within a time period during which the signal of the masking signal terminal is the second signal.

20. The shift register according to claim 19, wherein: The moment when the signal at the masking signal terminal changes from the first signal to the second signal is before the output time period, wherein the output time period is the time period when the cascade output signal terminal outputs the signal.

21. A gate drive circuit comprising: A plurality of shift registers according to any one of claims 1 to 20; The cascade output signal terminal of at least one stage of the shift register is electrically connected to the signal input terminal of at least one stage of the shift register.

22. A display device comprising: The gate drive circuit according to claim 21.

23. The display device according to claim 22, further comprising: Sub-pixels, a plurality of first scanning signal lines, and a plurality of data signal lines are arranged in an array, and at least one sub-pixel is electrically connected to the first scanning signal line and the data signal line respectively; At least one sub-pixel includes: a pixel driving circuit, the pixel driving circuit of at least one sub-pixel includes: a write transistor, the write transistor being electrically connected to the first scan signal line and the data signal line connected to the sub-pixel; The driving output signal terminal of at least one stage of the shift register is electrically connected to the first scanning signal line connected to at least one row of pixel driving circuits.

24. The display device according to claim 23, further comprising: a plurality of second reset signal lines and a plurality of second initial signal lines, wherein at least one sub-pixel is further electrically connected to the second reset signal line and the second initial signal line respectively; The pixel driving circuit of at least one sub-pixel further includes: an anode reset transistor, wherein the anode reset transistor is electrically connected to the second reset signal line and the second initial signal line connected to the sub-pixel; The driving output signal terminal of at least one stage of the shift register is electrically connected to a second reset signal line connected to at least one row of pixel driving circuits; The first scanning signal line and the second reset signal line connected to at least one row of pixel driving circuits are independently provided, or the second reset signal line connected to at least one row of pixel driving circuits is the same signal line as the first scanning signal line connected to the next row of pixel driving circuits.

25. A method for driving a shift register, configured to drive the shift register according to any one of claims 1 to 20, the method comprising: The cascade output subcircuit provides the signal of the first power supply terminal or the second clock signal terminal to the cascade output signal terminal under the control of the signal of the signal input terminal, the first clock signal terminal, the second clock signal terminal and the second power supply terminal; The node control subcircuit provides a signal to the drive output subcircuit under the control of the signals from the cascade output subcircuit, the first power supply terminal, the second power supply terminal and the first control input signal terminal; The driver output subcircuit provides the signal of the first power supply terminal or the second control input signal terminal to the driver output signal terminal under the control of the signals of the cascade output subcircuit and the node control subcircuit.

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