Driving circuit, driving method, and display device

Abstract

A driving circuit, a driving method, and a display device. The driving circuit comprises a first control circuit (11), a first energy storage circuit (10), a second control circuit, (12), and a drive reset circuit (13). Under the control of the potential of a control node (QB1), the first control circuit (11) controls the potential of a first node (QB). Under the control of the potential of the control node (QB1), the second control circuit (12) controls the connection or disconnection between a first intermediate node (P1) and a first voltage end (V1), and under the control of an input signal, the second control circuit (12) controls the connection or disconnection between the first intermediate node (P1) and the control node (QB1). Under the control of the potential of a reset control node (SR), the drive reset circuit (13) resets a driving signal outputted by a driving signal output end (OT). The reset control node (SR) is electrically connected to the first node (QB). The driving circuit can prevent the potential of the control node (QB1) from dropping due to electric leakage, and ensure that the first control circuit (11) is turned on, such that the potential of the first node (QB) is pulled up to a high voltage, thereby enabling the drive reset circuit (13) to reset the driving signal.

Description

Driving circuit, driving method and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese Patent Application No. 202410346751.2 filed in China on March 25, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a driving circuit, a driving method and a display device. Background Art

[0004] In the display field, especially in OLED (organic light-emitting diode) displays, oxides are currently widely used in medium and large-sized OLED displays due to their good uniformity. However, oxide TFTs (thin-film transistors) are depletion-mode TFTs, so they can have a negative threshold voltage, which can cause the driver circuit to fail due to leakage. Summary of the Invention

[0005] The main purpose of the present disclosure is to provide a driving circuit, a driving method and a display device to solve the problem that the existing driving circuit fails due to leakage.

[0006] In one aspect, an embodiment of the present disclosure provides a driving circuit, comprising a first control circuit, a first energy storage circuit, a second control circuit, and a driving reset circuit;

[0007] The first control circuit is electrically connected to the control node and the first node respectively, and is configured to control the potential of the first node under the control of the potential of the control node;

[0008] A first end of the first energy storage circuit is electrically connected to the first clock signal end, a second end of the first energy storage circuit is electrically connected to the control node, and the first energy storage circuit is used to store electrical energy;

[0009] The second control circuit is electrically connected to the control node, the first voltage terminal, the input terminal, and the first intermediate node, respectively, and is configured to control the connection or disconnection between the intermediate node and the first voltage terminal under the control of the potential of the control node, and control the connection or disconnection between the first intermediate node and the control node under the control of the input signal provided by the input terminal;

[0010] The driving reset circuit is electrically connected to the reset control node and the driving signal output terminal respectively, and is used to reset the driving signal output by the driving signal output terminal under the potential control of the reset control node;

[0011] The reset control node is electrically connected to the first node.

[0012] Optionally, the first control circuit is further electrically connected to the first clock signal terminal, and is configured to control the potential of the first node according to a first clock signal provided by the first clock signal terminal under the control of the potential of the control node;

[0013] The second control circuit is further electrically connected to the second voltage terminal, and is configured to control the connection or disconnection between the first intermediate node and the second voltage terminal under the control of the input signal.

[0014] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a third control circuit;

[0015] The reset control node is electrically connected to the first node through the third control circuit;

[0016] The control end of the third control circuit is electrically connected to the first clock signal end, and the third control circuit is used to control the connection or disconnection between the first node and the reset control node under the control of the first clock signal.

[0017] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a third control circuit;

[0018] The reset control node is electrically connected to the first node through the third control circuit;

[0019] The third control circuit is electrically connected to the first control terminal, the first node, the reset control node, the second intermediate node and the third voltage terminal, respectively, and is used to control the connection or disconnection between the second intermediate node and the third voltage terminal under the control of the potential of the reset control node, and to control the connection or disconnection between the first node and the second intermediate node, and to control the connection or disconnection between the second intermediate node and the reset control node under the control of the first control signal provided by the first control terminal.

[0020] Optionally, the first control terminal is a first clock signal terminal, a first high voltage terminal or a second high voltage terminal;

[0021] The third voltage terminal is the first high voltage terminal or the second high voltage terminal;

[0022] The first voltage terminal is a first high voltage terminal or a second high voltage terminal.

[0023] Optionally, the first control circuit is used to control the connection or disconnection between the first clock signal terminal and the first node under the control of the potential of the control node.

[0024] Optionally, the first control circuit is also electrically connected to the third intermediate node and the fourth voltage terminal, respectively, and is used to control the connection or disconnection between the third intermediate node and the fourth voltage terminal under the control of the potential of the first node, control the connection or disconnection between the first clock signal terminal and the third intermediate node under the control of the potential of the control node, and control the connection or disconnection between the third intermediate node and the first node under the control of the potential of the control node.

[0025] Optionally, the driving circuit described in at least one embodiment of the present disclosure further includes a fourth control circuit;

[0026] The fourth control circuit is electrically connected to the second node, the fifth voltage terminal and the first node respectively, and is used to control the connection or disconnection between the first node and the fifth voltage terminal under the control of the potential of the second node.

[0027] Optionally, the driving circuit described in at least one embodiment of the present disclosure further includes a fourth control circuit;

[0028] The fourth control circuit is electrically connected to the second node, the fifth voltage terminal and the reset control node respectively, and is used to control the connection or disconnection between the reset control node and the fifth voltage terminal under the control of the potential of the second node.

[0029] Optionally, the driving circuit described in at least one embodiment of the present disclosure further includes a fourth control circuit;

[0030] The fourth control circuit is electrically connected to the second node, the sixth voltage terminal, the fourth intermediate node, the seventh voltage terminal and the first node, respectively, and is used to control the connection or disconnection between the fourth intermediate node and the seventh voltage terminal under the control of the potential of the first node, and to control the connection or disconnection between the first node and the fourth intermediate node and the connection or disconnection between the fourth intermediate node and the sixth voltage terminal under the control of the potential of the second node.

[0031] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a carry output circuit, a carry reset circuit and a driving output circuit;

[0032] The carry output circuit is electrically connected to the output control node, the first high voltage terminal and the carry signal output terminal respectively, and is used to control the connection or disconnection between the carry signal output terminal and the first high voltage terminal under the control of the potential of the output control node;

[0033] The carry reset circuit is electrically connected to the reset control node, the first low voltage terminal and the carry signal output terminal respectively, and is used to control the connection or disconnection between the carry signal output terminal and the first low voltage terminal under the control of the potential of the reset control node;

[0034] The drive output circuit is electrically connected to the output control node, the second high voltage terminal and the drive signal output terminal respectively, and is used to control the connection or disconnection between the drive signal output terminal and the second high voltage terminal under the control of the potential of the output control node;

[0035] The driving reset circuit is also electrically connected to the second low voltage terminal, and is used to control the connection or disconnection between the driving signal output terminal and the second low voltage terminal under the control of the potential of the reset control node.

[0036] Optionally, the voltage value of the first high voltage signal provided by the first high voltage terminal is greater than the voltage value of the second high voltage signal provided by the second high voltage terminal, and the voltage value of the first low voltage signal provided by the first low voltage terminal is less than the voltage value of the second low voltage signal provided by the second low voltage terminal.

[0037] Optionally, the driving circuit described in at least one embodiment of the present disclosure further includes a driving output circuit;

[0038] The drive output circuit is electrically connected to the output control node, the third high voltage terminal and the drive signal output terminal respectively, and is used to control the connection or disconnection between the drive signal output terminal and the third high voltage terminal under the control of the potential of the output control node;

[0039] The drive reset circuit is also electrically connected to the third low voltage terminal, the output intermediate node and the eighth voltage terminal, respectively, and is used to control the connection or disconnection between the output intermediate node and the eighth voltage terminal under the control of the drive signal provided by the drive signal output terminal, and to control the electrical connection between the drive signal output terminal and the output intermediate node, and to control the connection or disconnection between the output intermediate node and the third low voltage terminal under the control of the potential of the reset control node.

[0040] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a fifth control circuit;

[0041] The fifth control circuit is electrically connected to the second node, the ninth voltage terminal and the output control node respectively, and is used to control the connection or disconnection between the second node and the output control node under the control of a ninth voltage signal provided by the ninth voltage terminal.

[0042] Optionally, the driving circuit according to at least one embodiment of the present disclosure further includes a fifth control circuit;

[0043] The fifth control circuit is electrically connected to the ninth voltage terminal, the tenth voltage terminal, the fifth intermediate node, the second node and the output control node, respectively, and is used to control the connection or disconnection between the fifth intermediate node and the tenth voltage terminal under the control of the potential of the output control node, and to control the connection or disconnection between the second node and the fifth intermediate node and the output control node under the control of the voltage signal provided by the ninth voltage terminal.

[0044] Optionally, the driving circuit described in at least one embodiment of the present disclosure further includes a bootstrap output circuit and an output energy storage circuit;

[0045] The bootstrap output circuit is electrically connected to the output control node, the output clock signal terminal, the bootstrap output terminal, the reset control node, and the fourth low voltage terminal, respectively, and is used to control the connection or disconnection between the bootstrap output terminal and the output clock signal terminal under the control of the potential of the output control node, and to control the connection or disconnection between the bootstrap output terminal and the fourth low voltage terminal under the control of the potential of the reset control node;

[0046] A first terminal of the output energy storage circuit is electrically connected to the output control node, a second terminal of the output energy storage circuit is electrically connected to the bootstrap output terminal, and the output energy storage circuit is used to store electrical energy.

[0047] Optionally, the first high voltage end and the second high voltage end are the same voltage end.

[0048] Optionally, the driving circuit described in at least one embodiment of the present disclosure further includes an input circuit;

[0049] The input circuit is electrically connected to the first clock signal terminal, the input terminal and the second node respectively, and is used to control the connection or disconnection between the input terminal and the second node under the control of the first clock signal provided by the first clock signal terminal.

[0050] Optionally, the first energy storage circuit includes a first capacitor, the second control circuit includes a first transistor and a second transistor, a first end of the first capacitor is electrically connected to the first clock signal end, and a second end of the first capacitor is electrically connected to the control node;

[0051] The gate of the first transistor is electrically connected to the control node, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the first intermediate node;

[0052] A gate of the second transistor is electrically connected to the input terminal, a first electrode of the second transistor is electrically connected to the first intermediate node, and a second electrode of the second transistor is electrically connected to the control node.

[0053] Optionally, the second control circuit further includes a third transistor;

[0054] A gate of the third transistor is electrically connected to the input terminal, a first electrode of the third transistor is electrically connected to the second voltage terminal, and a second electrode of the third transistor is electrically connected to the first intermediate node.

[0055] Optionally, the third control circuit includes a fourth transistor; the gate of the fourth transistor is electrically connected to the first clock signal end, the first electrode of the fourth transistor is electrically connected to the first node, and the second electrode of the fourth transistor is electrically connected to the reset control node.

[0056] Optionally, the third control circuit includes a fourth transistor, a fifth transistor, and a sixth transistor; the gate of the fourth transistor is electrically connected to the first control terminal, the first electrode of the fourth transistor is electrically connected to the first node, and the second electrode of the fourth transistor is electrically connected to the second intermediate node;

[0057] The gate of the fifth transistor is electrically connected to the first control terminal, the first electrode of the fifth transistor is electrically connected to the second intermediate node, and the second electrode of the fifth transistor is electrically connected to the reset control node;

[0058] A gate of the sixth transistor is electrically connected to the reset control node, a first electrode of the sixth transistor is electrically connected to the third voltage terminal, and a second electrode of the sixth transistor is electrically connected to the second intermediate node.

[0059] Optionally, the first control circuit includes a seventh transistor;

[0060] A gate of the seventh transistor is electrically connected to the control node, a first electrode of the seventh transistor is electrically connected to the first clock signal terminal, and a second electrode of the seventh transistor is electrically connected to the first node.

[0061] Optionally, the first control circuit includes a seventh transistor, an eighth transistor and a ninth transistor;

[0062] The gate of the seventh transistor is electrically connected to the control node, the first electrode of the seventh transistor is electrically connected to the first clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the third intermediate node;

[0063] The gate of the eighth transistor is electrically connected to the control node, the first electrode of the eighth transistor is electrically connected to the third intermediate node, and the second electrode of the eighth transistor is electrically connected to the first node;

[0064] A gate of the ninth transistor is electrically connected to the first node, a first electrode of the ninth transistor is electrically connected to the fourth voltage terminal, and a second electrode of the ninth transistor is electrically connected to the third intermediate node.

[0065] Optionally, the fourth control circuit includes a tenth transistor;

[0066] A gate of the tenth transistor is electrically connected to the second node, a first electrode of the tenth transistor is electrically connected to the fifth voltage terminal, and a second electrode of the tenth transistor is electrically connected to the first node.

[0067] Optionally, the fourth control circuit includes a tenth transistor;

[0068] A gate of the tenth transistor is electrically connected to the second node, a first electrode of the tenth transistor is electrically connected to the fifth voltage terminal, and a second electrode of the tenth transistor is electrically connected to the reset control node.

[0069] Optionally, the fourth control circuit includes a tenth transistor, an eleventh transistor and a twelfth transistor;

[0070] The gate of the tenth transistor is electrically connected to the second node, the first electrode of the tenth transistor is electrically connected to the fourth intermediate node, and the second electrode of the tenth transistor is electrically connected to the first node;

[0071] The gate of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the sixth voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the fourth intermediate node;

[0072] A gate of the twelfth transistor is electrically connected to the first node, a first electrode of the twelfth transistor is electrically connected to the seventh voltage terminal, and a second electrode of the twelfth transistor is electrically connected to the fourth intermediate node.

[0073] Optionally, the carry output circuit includes a carry output transistor, the carry reset circuit includes a carry reset transistor, the drive output circuit includes a drive output transistor, and the drive reset circuit includes a drive reset transistor;

[0074] The gate of the carry output transistor is electrically connected to the output control node, the first electrode of the carry output transistor is electrically connected to the first high voltage terminal, and the second electrode of the carry output transistor is electrically connected to the carry signal output terminal;

[0075] The gate of the carry reset transistor is electrically connected to the reset control node, the first electrode of the carry reset transistor is electrically connected to the carry signal output terminal, and the second electrode of the carry reset transistor is electrically connected to the first low voltage terminal;

[0076] The gate of the driving output transistor is electrically connected to the output control node, the first electrode of the driving output transistor is electrically connected to the second high voltage terminal, and the second electrode of the driving output transistor is electrically connected to the driving signal output terminal;

[0077] The gate of the driving reset transistor is electrically connected to the reset control node, the first electrode of the driving reset transistor is electrically connected to the driving signal output terminal, and the second electrode of the driving reset transistor is electrically connected to the second low voltage terminal.

[0078] Optionally, the driving output circuit includes a driving output transistor, and the driving reset circuit includes a first driving reset transistor, a second driving reset transistor and a reset control transistor;

[0079] The gate of the driving output transistor is electrically connected to the output control node, the first electrode of the driving output transistor is electrically connected to the third high voltage terminal, and the second electrode of the driving output transistor is electrically connected to the driving signal output terminal;

[0080] The gate of the first driving reset transistor is electrically connected to the reset control node, the first electrode of the first driving reset transistor is electrically connected to the driving signal output terminal, and the second electrode of the first driving reset transistor is electrically connected to the output intermediate node;

[0081] The gate of the second driving reset transistor is electrically connected to the reset control node, the first electrode of the second driving reset transistor is electrically connected to the output intermediate node, and the second electrode of the first driving reset transistor is electrically connected to the third low voltage terminal;

[0082] The gate of the reset control transistor is electrically connected to the drive signal output terminal, the first electrode of the reset control transistor is electrically connected to the eighth voltage terminal, and the second electrode of the reset control transistor is electrically connected to the output intermediate node.

[0083] Optionally, the fifth control circuit includes a thirteenth transistor;

[0084] A gate of the thirteenth transistor is electrically connected to the ninth voltage terminal, a first electrode of the thirteenth transistor is electrically connected to the second node, and a second electrode of the thirteenth transistor is electrically connected to the output control node.

[0085] Optionally, the fifth control circuit includes a thirteenth transistor, a fourteenth transistor and a fifteenth transistor;

[0086] The gate of the thirteenth transistor is electrically connected to the ninth voltage terminal, the first electrode of the thirteenth transistor is electrically connected to the second node, and the second electrode of the thirteenth transistor is electrically connected to the fifth intermediate node;

[0087] The gate of the fourteenth transistor is electrically connected to the ninth voltage terminal, the first electrode of the fourteenth transistor is electrically connected to the fifth intermediate node, and the second electrode of the fourteenth transistor is electrically connected to the output control node;

[0088] A gate of the fifteenth transistor is electrically connected to the output control node, a first electrode of the fifteenth transistor is electrically connected to the tenth voltage terminal, and a second electrode of the fifteenth transistor is electrically connected to the fifth intermediate node.

[0089] Optionally, the bootstrap output circuit includes a bootstrap output transistor and a bootstrap reset transistor, and the output energy storage circuit includes an output control capacitor;

[0090] The gate of the bootstrap output transistor is electrically connected to the output control node, the first electrode of the bootstrap output transistor is electrically connected to the output clock signal terminal, and the second electrode of the bootstrap output transistor is electrically connected to the bootstrap output terminal;

[0091] The gate of the bootstrap reset transistor is electrically connected to the reset control node, the first electrode of the bootstrap output transistor is electrically connected to the bootstrap output terminal, and the second electrode of the bootstrap output transistor is electrically connected to the fourth low voltage terminal;

[0092] A first end of the output control capacitor is electrically connected to the output control node, a second end of the output control capacitor is electrically connected to the bootstrap output end, and the output energy storage circuit is used to store electrical energy.

[0093] In a second aspect, an embodiment of the present disclosure provides a driving method, which is applied to the above-mentioned driving circuit. The driving method includes:

[0094] The first control circuit controls the potential of the first node according to the first clock signal under the control of the potential of the control node;

[0095] The second control circuit controls the connection or disconnection between the intermediate node and the first voltage terminal under the control of the potential of the control node, and controls the connection or disconnection between the first intermediate node and the control node under the control of the input signal;

[0096] The driving reset circuit resets the driving signal under the control of the potential of the reset control node.

[0097] In a third aspect, an embodiment of the present disclosure provides a display device comprising the above-mentioned driving circuit.

[0098] The driving circuit, driving method, and display device described in the embodiments of the present disclosure can prevent the potential of the control node from becoming low due to leakage, ensure that the first control circuit is turned on, so that the potential of the first node is pulled up to a high voltage, so that the driving reset circuit can reset the driving signal output from the driving signal output end under the control of the potential of the reset control node. BRIEF DESCRIPTION OF THE DRAWINGS

[0099] FIG1 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0100] FIG2 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0101] FIG3 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0102] FIG4 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0103] FIG5 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0104] FIG6 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0105] FIG7 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0106] FIG8 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0107] FIG9 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0108] FIG10 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0109] FIG11 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0110] FIG12 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0111] FIG13 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0112] FIG14 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0113] FIG15 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0114] FIG16 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0115] FIG17 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0116] FIG18 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0117] FIG19 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0118] FIG20 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0119] FIG21 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0120] FIG22 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0121] FIG23 is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0122] FIG24A is a structural diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0123] FIG24B is a circuit diagram of at least one embodiment of a pixel circuit;

[0124] FIG25A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0125] FIG25B is a potential of the first node QB in at least one embodiment of the driving circuit shown in FIG25A;

[0126] FIG25C is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG25A;

[0127] FIG26 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0128] FIG27 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0129] FIG28 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0130] FIG29A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0131] FIG29B is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG29A;

[0132] FIG30 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0133] FIG31 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0134] FIG32 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0135] FIG33 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0136] FIG34A is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0137] FIG34B is an operation timing diagram of at least one embodiment of the driving circuit shown in FIG34A;

[0138] FIG35 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure;

[0139] FIG36 is a circuit diagram of a driving circuit according to at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0140] The following will be combined with the accompanying drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present disclosure.

[0141] The transistors used in all embodiments of the present disclosure may be thin film transistors, field effect transistors, or other devices with the same characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of the transistor except the gate, one electrode is referred to as the first electrode and the other electrode is referred to as the second electrode.

[0142] In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first electrode may be a drain electrode, and the second electrode may be a source electrode; or, the first electrode may be a source electrode, and the second electrode may be a drain electrode.

[0143] As shown in FIG1 , the driving circuit according to at least one embodiment of the present disclosure includes a first control circuit 11 , a first energy storage circuit 10 , a second control circuit 12 , and a driving reset circuit 13 ;

[0144] The first control circuit 11 is electrically connected to the control node QB1 and the first node QB, and is configured to control the potential of the first node QB under the control of the potential of the control node QB1;

[0145] A first end of the first energy storage circuit 10 is electrically connected to the first clock signal terminal CK, a second end of the first energy storage circuit 10 is electrically connected to the control node QB1, and the first energy storage circuit is used to store electrical energy;

[0146] The second control circuit 12 is electrically connected to the control node QB1, the first voltage terminal V1, the input terminal I1, and the first intermediate node P1, respectively, and is configured to control the connection or disconnection between the first intermediate node P1 and the first voltage terminal V1 under the control of the potential of the control node QB1, and control the connection or disconnection between the first intermediate node P1 and the control node QB1 under the control of the input signal provided by the input terminal I1;

[0147] The driving reset circuit 13 is electrically connected to the reset control node SR and the driving signal output terminal OT respectively, and is used to reset the driving signal output by the driving signal output terminal OT under the potential control of the reset control node SR;

[0148] The reset control node SR is electrically connected to the first node QB.

[0149] In at least one embodiment of the driving circuit shown in FIG1 , the driving signal output terminal may be a light-emitting control signal terminal, but is not limited thereto. In a specific implementation, the driving signal output terminal may also be a gate driving signal terminal, a reset control signal terminal, or other types of driving signal output terminals.

[0150] Optionally, the first voltage end may be a first high voltage end or a second high voltage end, but is not limited thereto.

[0151] When at least one embodiment of the driving circuit shown in FIG1 of the present disclosure is in operation, when the potential of the first clock signal provided by the first clock signal terminal CK1 jumps from a low level to a high level, due to the action of the first energy storage circuit 10, the potential of the control node QB1 becomes a high voltage, and the second control circuit 12, under the control of the potential of the control node QB1, controls the connection between the first intermediate node P1 and the first voltage terminal V1 to prevent the potential of the control node QB1 from becoming low due to leakage, thereby ensuring that the first control circuit 11 is turned on, so that the potential of the first node QB is pulled up to a high voltage, thereby driving the reset circuit 13 to reset the driving signal output by the driving signal output terminal OT under the control of the potential of the reset control node SR.

[0152] In at least one embodiment of the present disclosure,

[0153] The second control circuit is further electrically connected to the second voltage terminal, and is configured to control the connection or disconnection between the first intermediate node and the second voltage terminal under the control of the input signal.

[0154] In a specific implementation, the second control circuit may further control the connection or disconnection between the first intermediate node and the second voltage terminal under the control of an input signal.

[0155] Optionally, the second voltage end may be the first low voltage end, but is not limited thereto.

[0156] As shown in FIG2 , in at least one embodiment of the driving circuit shown in FIG1 , the first control circuit 11 is further electrically connected to the first clock signal terminal CK1 and is configured to control the potential of the first node QB1 according to the first clock signal provided by the first clock signal terminal CK1 under the control of the potential of the control node QB1;

[0157] The second control circuit 12 is also electrically connected to the second voltage terminal V2 and is used to control the connection or disconnection between the first intermediate node P1 and the second voltage terminal V2 under the control of the input signal.

[0158] The driving circuit according to at least one embodiment of the present disclosure further includes a third control circuit;

[0159] The reset control node is electrically connected to the first node through the third control circuit;

[0160] The control end of the third control circuit is electrically connected to the first clock signal end, and the third control circuit is used to control the connection or disconnection between the first node and the reset control node under the control of the first clock signal.

[0161] In a specific implementation, the driving circuit may further include a third control circuit, and the reset control node may be electrically connected to the first node through the third control circuit. The third control end circuit controls the connection or disconnection between the first node and the reset control node under the control of the first clock signal.

[0162] As shown in FIG3 , based on at least one embodiment of the driving circuit shown in FIG2 , the driving circuit according to at least one embodiment of the present disclosure further includes a third control circuit 31 ;

[0163] The reset control node SR is electrically connected to the first node QB through the third control circuit 31;

[0164] The control terminal of the third control circuit 31 is electrically connected to the first clock signal terminal CK1 . The third control circuit 31 is configured to control the connection or disconnection between the first node QB and the reset control node SR under the control of the first clock signal.

[0165] At least one embodiment of the driving circuit shown in FIG. 3 of the present disclosure, when in operation, by adding a third control circuit 31 , prevents the potential of the reset control node SR from decreasing due to leakage when the potential of the first clock signal changes from a high level to a low level.

[0166] The driving circuit according to at least one embodiment of the present disclosure further includes a third control circuit;

[0167] The reset control node is electrically connected to the first node through the third control circuit;

[0168] The third control circuit is electrically connected to the first control terminal, the first node, the reset control node, the second intermediate node and the third voltage terminal, respectively, and is used to control the connection or disconnection between the second intermediate node and the third voltage terminal under the control of the potential of the reset control node, and to control the connection or disconnection between the first node and the second intermediate node, and to control the connection or disconnection between the second intermediate node and the reset control node under the control of the first control signal provided by the first control terminal.

[0169] In a specific implementation, the driving circuit may further include a third control circuit, and the reset control node may be electrically connected to the first node through the third control circuit; the third control circuit may control the connection or disconnection between the second intermediate node and the third voltage terminal under the control of the potential of the reset control node, and control the connection or disconnection between the first node and the second intermediate node, and control the connection or disconnection between the second intermediate node and the reset control node under the control of the first control signal.

[0170] Optionally, the third voltage terminal may be the first high voltage terminal or the second high voltage terminal, but is not limited thereto.

[0171] In at least one embodiment of the present disclosure, the first voltage terminal may be the first high voltage terminal or the second high voltage terminal, and the third voltage terminal may be the first high voltage terminal or the second high voltage terminal.

[0172] Optionally, the first voltage terminal and the third voltage terminal may be the same voltage terminal; for example, the first voltage terminal and the third voltage terminal may both be first high voltage terminals, or the first voltage terminal and the third voltage terminal may both be second high voltage terminals.

[0173] Optionally, the first voltage terminal may be a different voltage terminal from the third voltage terminal; for example, the first voltage terminal may be a first high voltage terminal, and the third voltage terminal may be a second high voltage terminal; or, the first voltage terminal may be a second high voltage terminal, and the third voltage terminal may be the first high voltage terminal.

[0174] In at least one embodiment of the present disclosure, the third voltage terminal may also be a third high voltage terminal, the third high voltage terminal may be different from the first high voltage terminal, and the third high voltage terminal may be different from the second high voltage terminal.

[0175] As shown in FIG4 , based on at least one embodiment of the driving circuit shown in FIG2 , the driving circuit according to at least one embodiment of the present disclosure further includes a third control circuit 31 ;

[0176] The reset control node is electrically connected to the first node QB through the third control circuit 31;

[0177] The third control circuit 31 is electrically connected to the first control terminal S1, the first node QB, the reset control node SR, the second intermediate node P2 and the third voltage terminal V3, respectively, and is used to control the connection or disconnection between the second intermediate node P2 and the third voltage terminal V3 under the control of the potential of the reset control node SR, and to control the connection or disconnection between the first node QB and the second intermediate node P2, and to control the connection or disconnection between the second intermediate node P2 and the reset control node SR under the control of the first control signal provided by the first control terminal S1.

[0178] When at least one embodiment of the driving circuit shown in FIG4 of the present disclosure is in operation, when the potential of the reset control node SR is a high voltage, the third control circuit 31 controls the connection between the second intermediate node P2 and the third voltage terminal V3 under the control of the potential of the reset control node SR, so that the potential of the second intermediate node P2 is a high voltage, thereby preventing the potential of the reset control node SR from decreasing due to leakage.

[0179] In at least one embodiment of the driving circuit shown in FIG. 4 , the first control terminal S1 may be the first clock signal terminal CK1 , the first high voltage terminal, or the second high voltage terminal, but is not limited thereto.

[0180] At least one embodiment of the driving circuit shown in FIG4 of the present disclosure is based on at least one embodiment of the driving circuit shown in FIG2 and further includes a third control circuit 31. However, in at least one embodiment of the present disclosure, at least one embodiment of the driving circuit shown in FIG4 of the present disclosure can be based on at least one embodiment of the driving circuit shown in FIG1 and further includes a third control circuit 31.

[0181] Optionally, the first control terminal is a first clock signal terminal, a first high voltage terminal or a second high voltage terminal;

[0182] The third voltage terminal is the first high voltage terminal or the second high voltage terminal;

[0183] The first voltage terminal is a first high voltage terminal or a second high voltage terminal.

[0184] In at least one embodiment of the present disclosure, the first control circuit is configured to control the connection or disconnection between the first clock signal terminal and the first node under the control of the potential of the control node.

[0185] In a specific implementation, the first control circuit may control the connection or disconnection between the first clock signal terminal and the first node under the control of the potential of the control node, so as to control the potential of the first node.

[0186] In at least one embodiment of the present disclosure, the first control circuit is also electrically connected to the third intermediate node and the fourth voltage terminal, respectively, and is used to control the connection or disconnection between the third intermediate node and the fourth voltage terminal under the control of the potential of the first node, control the connection or disconnection between the first clock signal terminal and the third intermediate node under the control of the potential of the control node, and control the connection or disconnection between the third intermediate node and the one node under the control of the potential of the control node.

[0187] In a specific implementation, the first control circuit can control the connection or disconnection between the third intermediate node and the fourth voltage terminal under the control of the potential of the first node, control the connection or disconnection between the first clock signal terminal and the third intermediate node under the control of the potential of the control node, and control the connection or disconnection between the third intermediate node and the first node.

[0188] Optionally, the fourth voltage terminal may be the first high voltage terminal or the second high voltage terminal, but is not limited thereto.

[0189] In at least one embodiment of the present disclosure, the first voltage terminal may be the first high voltage terminal or the second high voltage terminal, and the fourth voltage terminal may be the first high voltage terminal or the second high voltage terminal.

[0190] Optionally, the first voltage terminal and the fourth voltage terminal may be the same voltage terminal; for example, the first voltage terminal and the fourth voltage terminal may both be first high voltage terminals, or the first voltage terminal and the fourth voltage terminal may both be second high voltage terminals.

[0191] Optionally, the first voltage terminal may be a different voltage terminal from the fourth voltage terminal; for example, the first voltage terminal may be a first high voltage terminal, and the fourth voltage terminal may be a second high voltage terminal; or, the first voltage terminal may be a second high voltage terminal, and the fourth voltage terminal may be the first high voltage terminal.

[0192] In at least one embodiment of the present disclosure, the fourth voltage terminal may also be a fourth high voltage terminal, the fourth high voltage terminal may be different from the first high voltage terminal, and the fourth high voltage terminal may be different from the second high voltage terminal.

[0193] As shown in Figure 5, based on at least one embodiment of the driving circuit shown in Figure 4, the first control circuit 11 can also be electrically connected to the third intermediate node P3 and the fourth voltage terminal V4, respectively, to control the connection or disconnection between the third intermediate node P3 and the fourth voltage terminal V4 under the control of the potential of the first node QB, control the connection or disconnection between the first clock signal terminal CK1 and the third intermediate node P3 under the control of the potential of the control node QB1, and control the connection or disconnection between the third intermediate node P3 and the first node QB under the control of the potential of the control node QB1.

[0194] When at least one embodiment of the driving circuit shown in FIG5 of the present disclosure is in operation, when the potential of the first node QB is a high voltage, the first control circuit 11 controls the connection between the third intermediate node P3 and the fourth voltage terminal V4 under the control of the potential of the first node QB, so that the potential of the third intermediate node P3 is a high voltage, thereby preventing the potential of the first node QB from decreasing due to leakage, and facilitating maintaining the high potential of the first node QB.

[0195] The driving circuit according to at least one embodiment of the present disclosure further includes a fourth control circuit;

[0196] The fourth control circuit is electrically connected to the second node, the fifth voltage terminal and the first node respectively, and is used to control the connection or disconnection between the first node and the fifth voltage terminal under the control of the potential of the second node.

[0197] Optionally, the fifth voltage end may be the first low voltage end, but is not limited thereto.

[0198] In a specific implementation, the driving circuit may further include a fourth control circuit, which controls the connection or disconnection between the first node and the fifth voltage terminal under the control of the potential of the second node.

[0199] As shown in FIG6 , based on at least one embodiment of the driving circuit shown in FIG3 , the driving circuit according to at least one embodiment of the present disclosure further includes a fourth control circuit 61 ;

[0200] The fourth control circuit 61 is electrically connected to the second node Q1, the fifth voltage terminal V5 and the first node QB respectively, and is used to control the connection or disconnection between the first node QB and the fifth voltage terminal V5 under the control of the potential of the second node Q1.

[0201] At least one embodiment of the driving circuit shown in FIG6 of the present disclosure is based on at least one embodiment of the driving circuit shown in FIG3 and additionally includes a fourth control circuit 61; in at least one embodiment of the present disclosure, at least one embodiment of the driving circuit shown in FIG6 of the present disclosure can be based on at least one embodiment of the driving circuit shown in FIG1 or FIG2 and additionally includes a fourth control circuit 61.

[0202] As shown in FIG7 , based on at least one embodiment of the driving circuit shown in FIG4 , the driving circuit according to at least one embodiment of the present disclosure further includes a fourth control circuit 61 ;

[0203] The fourth control circuit 61 is electrically connected to the second node Q1, the fifth voltage terminal V5 and the first node QB respectively, and is used to control the connection or disconnection between the first node QB and the fifth voltage terminal V5 under the control of the potential of the second node Q1.

[0204] As shown in FIG8 , based on at least one embodiment of the driving circuit shown in FIG5 , the driving circuit according to at least one embodiment of the present disclosure further includes a fourth control circuit 61 ;

[0205] The fourth control circuit 61 is electrically connected to the second node Q1, the fifth voltage terminal V5 and the first node QB respectively, and is used to control the connection or disconnection between the first node QB and the fifth voltage terminal V5 under the control of the potential of the second node Q1.

[0206] The driving circuit according to at least one embodiment of the present disclosure further includes a fourth control circuit;

[0207] The fourth control circuit is electrically connected to the second node, the fifth voltage terminal and the reset control node respectively, and is used to control the connection or disconnection between the reset control node and the fifth voltage terminal under the control of the potential of the second node.

[0208] In a specific implementation, the driving circuit may further include a fourth control circuit, which controls the connection or disconnection between the reset control node and the fifth voltage terminal under the control of the potential of the second node to control the potential of the reset control node.

[0209] As shown in FIG9 , based on at least one embodiment of the driving circuit shown in FIG3 , the driving circuit according to at least one embodiment of the present disclosure further includes a fourth control circuit 61 ;

[0210] The fourth control circuit 61 is electrically connected to the second node Q1, the fifth voltage terminal V5 and the reset control node SR respectively, and is used to control the connection or disconnection between the reset control node SR and the fifth voltage terminal V5 under the control of the potential of the second node Q1.

[0211] At least one embodiment of the driving circuit shown in FIG9 of the present disclosure is based on at least one embodiment of the driving circuit shown in FIG3 and additionally includes a fourth control circuit 61; in at least one embodiment of the present disclosure, at least one embodiment of the driving circuit shown in FIG9 of the present disclosure can be based on at least one embodiment of the driving circuit shown in FIG1 or FIG2 and additionally includes a fourth control circuit 61.

[0212] The driving circuit according to at least one embodiment of the present disclosure further includes a fourth control circuit;

[0213] The fourth control circuit is electrically connected to the second node, the sixth voltage terminal, the fourth intermediate node, the seventh voltage terminal and the first node, respectively, and is used to control the connection or disconnection between the fourth intermediate node and the seventh voltage terminal under the control of the potential of the first node, and to control the connection or disconnection between the first node and the fourth intermediate node and the connection or disconnection between the fourth intermediate node and the sixth voltage terminal under the control of the potential of the second node.

[0214] In a specific implementation, the driving circuit may further include a fourth control circuit, which controls the connection or disconnection between the fourth intermediate node and the seventh voltage terminal under the control of the potential of the first node, and controls the connection or disconnection between the first node and the fourth intermediate node and the connection or disconnection between the fourth intermediate node and the sixth voltage terminal under the control of the potential of the second node.

[0215] Optionally, the seventh voltage end may be the first high voltage end or the second high voltage end, but is not limited thereto.

[0216] When the driving circuit described in at least one embodiment of the present disclosure is in operation, when the potential of the first node is a high voltage, the fourth control circuit, under the control of the potential of the first node, controls the connection between the fourth intermediate node and the seventh voltage terminal, so that the potential of the fourth intermediate node is a high voltage, thereby preventing the potential of the first node from decreasing due to leakage.

[0217] Optionally, the sixth voltage end may be the first low voltage end, but is not limited thereto.

[0218] In at least one embodiment of the present disclosure, the first voltage terminal may be the first high voltage terminal or the second high voltage terminal, and the seventh voltage terminal may be the first high voltage terminal or the second high voltage terminal.

[0219] Optionally, the first voltage terminal and the fourth voltage terminal may be the same voltage terminal; for example, the first voltage terminal and the seventh voltage terminal may both be first high voltage terminals, or the first voltage terminal and the seventh voltage terminal may both be second high voltage terminals.

[0220] Optionally, the first voltage terminal may be a different voltage terminal from the seventh voltage terminal; for example, the first voltage terminal may be a first high voltage terminal, and the seventh voltage terminal may be a second high voltage terminal; or, the first voltage terminal may be a second high voltage terminal, and the seventh voltage terminal may be a first high voltage terminal.

[0221] In at least one embodiment of the present disclosure, the seventh voltage terminal may also be a fifth high voltage terminal, the fifth high voltage terminal may be different from the first high voltage terminal, and the fifth high voltage terminal may be different from the second high voltage terminal.

[0222] As shown in FIG10 , based on at least one embodiment of the driving circuit shown in FIG5 , the driving circuit according to at least one embodiment of the present disclosure further includes a fourth control circuit 61 ;

[0223] The fourth control circuit 61 is electrically connected to the second node Q1, the sixth voltage terminal V6, the fourth intermediate node P4, the seventh voltage terminal V7 and the first node QB, respectively, and is used to control the connection or disconnection between the fourth intermediate node P4 and the seventh voltage terminal V7 under the control of the potential of the first node QB, and to control the connection or disconnection between the first node QB and the fourth intermediate node P4 under the control of the potential of the second node Q1, and to control the connection or disconnection between the fourth intermediate node P4 and the sixth voltage terminal V6.

[0224] The driving circuit according to at least one embodiment of the present disclosure further includes a carry output circuit, a carry reset circuit and a driving output circuit;

[0225] The carry output circuit is electrically connected to the output control node, the first high voltage terminal and the carry signal output terminal respectively, and is used to control the connection or disconnection between the carry signal output terminal and the first high voltage terminal under the control of the potential of the output control node;

[0226] The carry reset circuit is electrically connected to the reset control node, the first low voltage terminal and the carry signal output terminal respectively, and is used to control the connection or disconnection between the carry signal output terminal and the first low voltage terminal under the control of the potential of the reset control node;

[0227] The drive output circuit is electrically connected to the output control node, the second high voltage terminal and the drive signal output terminal respectively, and is used to control the connection or disconnection between the drive signal output terminal and the second high voltage terminal under the control of the potential of the output control node;

[0228] The driving reset circuit is also electrically connected to the second low voltage terminal, and is used to control the connection or disconnection between the driving signal output terminal and the second low voltage terminal under the control of the potential of the reset control node.

[0229] In a specific implementation, the drive circuit may further include a carry output circuit, a carry reset circuit and a drive output circuit; the carry output circuit and the carry reset circuit may control the carry output under the control of the potential of the output control node and the potential of the reset control node; the drive output circuit controls the connection or disconnection between the drive signal output terminal and the second high voltage terminal under the control of the potential of the output control node.

[0230] In at least one embodiment of the present disclosure, the voltage value of the first high voltage signal provided by the first high voltage terminal is greater than the voltage value of the second high voltage signal provided by the second high voltage terminal, and the voltage value of the first low voltage signal provided by the first low voltage terminal is less than the voltage value of the second low voltage signal provided by the second low voltage terminal.

[0231] In a specific implementation, the voltage value of the first high voltage signal is greater than the voltage value of the second high voltage signal, and the voltage value of the first low voltage signal is less than the voltage value of the second low voltage signal. By lowering the voltage value of the second high voltage signal, it can be ensured that when the potential of the output control node is pulled low, the drive signal output end can correctly output the drive signal.

[0232] The driving circuit according to at least one embodiment of the present disclosure further includes a driving output circuit;

[0233] The drive output circuit is electrically connected to the output control node, the third high voltage terminal and the drive signal output terminal respectively, and is used to control the connection or disconnection between the drive signal output terminal and the third high voltage terminal under the control of the potential of the output control node;

[0234] The drive reset circuit is also electrically connected to the third low voltage terminal, the output intermediate node and the eighth voltage terminal, respectively, and is used to control the connection or disconnection between the output intermediate node and the eighth voltage terminal under the control of the drive signal provided by the drive signal output terminal, and to control the electrical connection between the drive signal output terminal and the output intermediate node, and to control the connection or disconnection between the output intermediate node and the third low voltage terminal under the control of the potential of the reset control node.

[0235] Optionally, the eighth voltage end may be the first high voltage end or the second high voltage end, but is not limited thereto.

[0236] In a specific implementation, the drive circuit may further include a drive output circuit; the drive output circuit controls the connection or disconnection between the drive signal output terminal and the third high voltage terminal under the control of the potential of the output control node. When the drive signal output terminal outputs a high voltage signal, the drive reset circuit controls the connection between the output intermediate node and the eighth voltage terminal under the control of the drive signal, so that the potential of the output intermediate node is a high voltage, thereby preventing the potential of the drive signal from decreasing due to leakage.

[0237] In at least one embodiment of the present disclosure, the first voltage terminal may be the first high voltage terminal or the second high voltage terminal, and the eighth voltage terminal may be the first high voltage terminal or the second high voltage terminal.

[0238] Optionally, the first voltage terminal and the eighth voltage terminal may be the same voltage terminal; for example, the first voltage terminal and the eighth voltage terminal may both be first high voltage terminals, or the first voltage terminal and the eighth voltage terminal may both be second high voltage terminals.

[0239] Optionally, the first voltage terminal may be a different voltage terminal from the eighth voltage terminal; for example, the first voltage terminal may be a first high voltage terminal, and the eighth voltage terminal may be a second high voltage terminal; or, the first voltage terminal may be a second high voltage terminal, and the eighth voltage terminal may be the first high voltage terminal.

[0240] In at least one embodiment of the present disclosure, the eighth voltage terminal may also be a sixth high voltage terminal, the sixth high voltage terminal may be different from the first high voltage terminal, and the sixth high voltage terminal may be different from the second high voltage terminal.

[0241] The driving circuit according to at least one embodiment of the present disclosure further includes a fifth control circuit;

[0242] The fifth control circuit is electrically connected to the second node, the ninth voltage terminal and the output control node respectively, and is used to control the connection or disconnection between the second node and the output control node under the control of a ninth voltage signal provided by the ninth voltage terminal.

[0243] In a specific implementation, the driving circuit may further include a fifth control circuit, which controls the connection or disconnection between the second node and the output control node under the control of a ninth voltage signal provided by a ninth voltage terminal.

[0244] Optionally, the ninth voltage end may be the first high voltage end, but is not limited thereto.

[0245] As shown in FIG11 , based on at least one embodiment of the driving circuit shown in FIG6 , the driving circuit according to at least one embodiment of the present disclosure further includes a fifth control circuit 110 , a carry output circuit 111 , a carry reset circuit 112 , and a driving output circuit 113 ;

[0246] The fifth control circuit 110 is electrically connected to the second node Q1, the ninth voltage terminal V9, and the output control node Q, respectively, and is configured to control the connection or disconnection between the second node Q1 and the output control node Q under the control of a ninth voltage signal provided by the ninth voltage terminal V9;

[0247] The carry output circuit 111 is electrically connected to the output control node Q, the first high voltage terminal VGH1 and the carry signal output terminal CR, respectively, and is used to control the connection or disconnection between the carry signal output terminal CR and the first high voltage terminal VGH1 under the control of the potential of the output control node Q;

[0248] The carry reset circuit 112 is electrically connected to the reset control node SR, the first low voltage terminal VGL1, and the carry signal output terminal CR, respectively, and is used to control the connection or disconnection between the carry signal output terminal CR and the first low voltage terminal VGL1 under the control of the potential of the reset control node SR;

[0249] The drive output circuit 113 is electrically connected to the output control node Q, the second high voltage terminal VGH2 and the drive signal output terminal OT, respectively, and is used to control the connection or disconnection between the drive signal output terminal OT and the second high voltage terminal VGH2 under the control of the potential of the output control node Q;

[0250] The driving reset circuit 13 is also electrically connected to the second low voltage terminal VGL2 and is used to control the connection or disconnection between the driving signal output terminal OT and the second low voltage terminal VGL2 under the control of the potential of the reset control node SR.

[0251] As shown in FIG12 , based on at least one embodiment of the driving circuit shown in FIG7 , the driving circuit according to at least one embodiment of the present disclosure further includes a fifth control circuit 110 , a carry output circuit 111 , a carry reset circuit 112 , and a driving output circuit 113 ;

[0252] The fifth control circuit 110 is electrically connected to the second node Q1, the ninth voltage terminal V9, and the output control node Q, respectively, and is configured to control the connection or disconnection between the second node Q1 and the output control node Q under the control of a ninth voltage signal provided by the ninth voltage terminal V9;

[0253] The carry output circuit 111 is electrically connected to the output control node Q, the first high voltage terminal VGH1 and the carry signal output terminal CR, respectively, and is used to control the connection or disconnection between the carry signal output terminal CR and the first high voltage terminal VGH1 under the control of the potential of the output control node Q;

[0254] The carry reset circuit 112 is electrically connected to the reset control node SR, the first low voltage terminal VGL1, and the carry signal output terminal CR, respectively, and is used to control the connection or disconnection between the carry signal output terminal CR and the first low voltage terminal VGL1 under the control of the potential of the reset control node SR;

[0255] The drive output circuit 113 is electrically connected to the output control node Q, the second high voltage terminal VGH2 and the drive signal output terminal OT, respectively, and is used to control the connection or disconnection between the drive signal output terminal OT and the second high voltage terminal VGH2 under the control of the potential of the output control node Q;

[0256] The driving reset circuit 13 is also electrically connected to the second low voltage terminal VGL2 and is used to control the connection or disconnection between the driving signal output terminal OT and the second low voltage terminal VGL2 under the control of the potential of the reset control node SR.

[0257] As shown in FIG13 , based on at least one embodiment of the driving circuit shown in FIG8 , the driving circuit according to at least one embodiment of the present disclosure further includes a fifth control circuit 110 , a carry output circuit 111 , a carry reset circuit 112 , and a driving output circuit 113 ;

[0258] The fifth control circuit 110 is electrically connected to the second node Q1, the ninth voltage terminal V9, and the output control node Q, respectively, and is configured to control the connection or disconnection between the second node Q1 and the output control node Q under the control of a ninth voltage signal provided by the ninth voltage terminal V9;

[0259] The carry output circuit 111 is electrically connected to the output control node Q, the first high voltage terminal VGH1 and the carry signal output terminal CR, respectively, and is used to control the connection or disconnection between the carry signal output terminal CR and the first high voltage terminal VGH1 under the control of the potential of the output control node Q;

[0260] The carry reset circuit 112 is electrically connected to the reset control node SR, the first low voltage terminal VGL1, and the carry signal output terminal CR, respectively, and is used to control the connection or disconnection between the carry signal output terminal CR and the first low voltage terminal VGL1 under the control of the potential of the reset control node SR;

[0261] The drive output circuit 113 is electrically connected to the output control node Q, the second high voltage terminal VGH2 and the drive signal output terminal OT, respectively, and is used to control the connection or disconnection between the drive signal output terminal OT and the second high voltage terminal VGH2 under the control of the potential of the output control node Q;

[0262] The driving reset circuit 13 is also electrically connected to the second low voltage terminal VGL2 and is used to control the connection or disconnection between the driving signal output terminal OT and the second low voltage terminal VGL2 under the control of the potential of the reset control node SR.

[0263] As shown in FIG14 , based on at least one embodiment of the driving circuit shown in FIG9 , the driving circuit according to at least one embodiment of the present disclosure further includes a fifth control circuit 110 and a driving output circuit 113 ;

[0264] The fifth control circuit 110 is electrically connected to the second node Q1, the ninth voltage terminal V9, and the output control node Q, respectively, and is configured to control the connection or disconnection between the second node Q1 and the output control node Q under the control of a ninth voltage signal provided by the ninth voltage terminal V9;

[0265] The drive output circuit 113 is electrically connected to the output control node Q, the second high voltage terminal VGH2 and the drive signal output terminal OT, respectively, and is used to control the connection or disconnection between the drive signal output terminal OT and the second high voltage terminal VGH2 under the control of the potential of the output control node Q;

[0266] The driving reset circuit 13 is also electrically connected to the second low voltage terminal VGL2 and is used to control the connection or disconnection between the driving signal output terminal OT and the second low voltage terminal VGL2 under the control of the potential of the reset control node SR.

[0267] As shown in FIG15 , based on at least one embodiment of the driving circuit shown in FIG10 , the driving circuit according to at least one embodiment of the present disclosure further includes a fifth control circuit 110 and a driving output circuit 113 ;

[0268] The fifth control circuit 110 is electrically connected to the second node Q1, the ninth voltage terminal V9, and the output control node Q, respectively, and is configured to control the connection or disconnection between the second node Q1 and the output control node Q under the control of a ninth voltage signal provided by the ninth voltage terminal V9;

[0269] The drive output circuit 113 is electrically connected to the output control node Q, the third high voltage terminal VGH3 and the drive signal output terminal OT, respectively, and is used to control the connection or disconnection between the drive signal output terminal OT and the third high voltage terminal VGH3 under the control of the potential of the output control node Q;

[0270] The driving reset circuit 13 is also electrically connected to the third low voltage terminal VGL3, the output intermediate node P0 and the eighth voltage terminal V8, respectively, and is used to control the connection or disconnection between the output intermediate node P0 and the eighth voltage terminal V8 under the control of the driving signal provided by the driving signal output terminal OT, and to control the electrical connection between the driving signal output terminal OT and the output intermediate node P0, and to control the connection or disconnection between the output intermediate node P0 and the third low voltage terminal VGL3 under the control of the potential of the reset control node SR.

[0271] Optionally, the third high voltage end may be the first high voltage end, and the third low voltage end may be the first low voltage end, but the present invention is not limited thereto.

[0272] As shown in FIG16 , based on at least one embodiment of the driving circuit shown in FIG10 , the driving circuit according to at least one embodiment of the present disclosure further includes a fifth control circuit 110 and a driving output circuit 113 ;

[0273] The fifth control circuit 110 is electrically connected to the second node Q1, the ninth voltage terminal V9, and the output control node Q, respectively, and is configured to control the connection or disconnection between the second node Q1 and the output control node Q under the control of a ninth voltage signal provided by the ninth voltage terminal V9;

[0274] The drive output circuit 113 is electrically connected to the output control node Q, the second high voltage terminal VGH2 and the drive signal output terminal OT, respectively, and is used to control the connection or disconnection between the drive signal output terminal OT and the second high voltage terminal VGH2 under the control of the potential of the output control node Q;

[0275] The driving reset circuit 13 is also electrically connected to the second low voltage terminal VGL2 and is used to control the connection or disconnection between the driving signal output terminal OT and the second low voltage terminal VGL2 under the control of the potential of the reset control node SR.

[0276] The driving circuit according to at least one embodiment of the present disclosure further includes a fifth control circuit;

[0277] The fifth control circuit is electrically connected to the ninth voltage terminal, the tenth voltage terminal, the fifth intermediate node, the second node and the output control node, respectively, and is used to control the connection or disconnection between the fifth intermediate node and the tenth voltage terminal under the control of the potential of the output control node, and to control the connection or disconnection between the second node and the fifth intermediate node and the output control node under the control of the voltage signal provided by the ninth voltage terminal.

[0278] Optionally, the tenth voltage terminal may be the first high voltage terminal or the second high voltage terminal, and the ninth voltage terminal may be the first high voltage terminal, but is not limited thereto.

[0279] In a specific implementation, the driving circuit may further include a fifth control circuit, which controls the connection or disconnection between the fifth intermediate node and the tenth voltage terminal under the control of the potential of the output control node, controls the connection or disconnection between the second node and the fifth intermediate node under the control of the voltage signal provided by the ninth voltage terminal, and controls the connection or disconnection between the fifth intermediate node and the output control node.

[0280] When the driving circuit described in at least one embodiment of the present disclosure is in operation, when the potential of the output control node is a high voltage, the fifth control circuit, under the control of the potential of the output control node, controls the connection between the fifth intermediate node and the tenth voltage terminal, so that the potential of the fifth intermediate node is a high voltage, thereby preventing the potential of the output control node from becoming low due to leakage.

[0281] As shown in FIG17 , based on at least one embodiment of the driving circuit shown in FIG7 , the driving circuit according to at least one embodiment of the present disclosure further includes a fifth control circuit 110 , a carry output circuit 111 , a carry reset circuit 112 , and a driving output circuit 113 ;

[0282] the fifth control circuit is electrically connected to the ninth voltage terminal V9, the tenth voltage terminal V10, the fifth intermediate node P5, the second node Q1, and the output control node Q, respectively, and is configured to control the connection or disconnection between the fifth intermediate node P5 and the tenth voltage terminal V10 under the control of the potential of the output control node Q, and to control the connection or disconnection between the second node Q1 and the fifth intermediate node P5 and the connection or disconnection between the fifth intermediate node P5 and the output control node Q under the control of the voltage signal provided by the ninth voltage terminal V9;

[0283] The carry output circuit 111 is electrically connected to the output control node Q, the first high voltage terminal VGH1 and the carry signal output terminal CR, respectively, and is used to control the connection or disconnection between the carry signal output terminal CR and the first high voltage terminal VGH1 under the control of the potential of the output control node Q;

[0284] The carry reset circuit 112 is electrically connected to the reset control node SR, the first low voltage terminal VGL1, and the carry signal output terminal CR, respectively, and is used to control the connection or disconnection between the carry signal output terminal CR and the first low voltage terminal VGL1 under the control of the potential of the reset control node SR;

[0285] The drive output circuit 113 is electrically connected to the output control node Q, the second high voltage terminal VGH2 and the drive signal output terminal OT, respectively, and is used to control the connection or disconnection between the drive signal output terminal OT and the second high voltage terminal VGH2 under the control of the potential of the output control node Q;

[0286] The driving reset circuit 13 is also electrically connected to the second low voltage terminal VGL2 and is used to control the connection or disconnection between the driving signal output terminal OT and the second low voltage terminal VGL2 under the control of the potential of the reset control node SR.

[0287] The driving circuit according to at least one embodiment of the present disclosure further includes a bootstrap output circuit and an output energy storage circuit;

[0288] The bootstrap output circuit is electrically connected to the output control node, the output clock signal terminal, the bootstrap output terminal, the reset control node, and the fourth low voltage terminal, respectively, and is used to control the connection or disconnection between the bootstrap output terminal and the output clock signal terminal under the control of the potential of the output control node, and to control the connection or disconnection between the reset control node and the fourth low voltage terminal under the control of the potential of the reset control node;

[0289] A first terminal of the output energy storage circuit is electrically connected to the output control node, a second terminal of the output energy storage circuit is electrically connected to the bootstrap output terminal, and the output energy storage circuit is used to store electrical energy.

[0290] In a specific implementation, the driving circuit may further include a bootstrap output circuit and an output energy storage circuit; the bootstrap output circuit controls the connection or disconnection between the bootstrap output terminal and the output clock signal terminal under the control of the potential of the output control node, and controls the connection or disconnection between the bootstrap output terminal and the fourth low voltage terminal under the control of the potential of the reset control node.

[0291] Optionally, the fourth low voltage end may be the first low voltage end, but is not limited thereto.

[0292] As shown in FIG18 , based on at least one embodiment of the driving circuit shown in FIG11 , the driving circuit according to at least one embodiment of the present disclosure further includes a bootstrap output circuit 161 and an output energy storage circuit 160 ;

[0293] The bootstrap output circuit 161 is electrically connected to the output control node Q, the output clock signal terminal CLKO, the bootstrap output terminal OD, the reset control node SR, and the fourth low voltage terminal VGL4, respectively, and is used to control the connection or disconnection between the bootstrap output terminal OD and the output clock signal terminal CLKO under the control of the potential of the output control node Q, and to control the connection or disconnection between the bootstrap output terminal OD and the fourth low voltage terminal VGL4 under the control of the potential of the reset control node SR;

[0294] A first terminal of the output energy storage circuit 160 is electrically connected to the output control node Q, and a second terminal of the output energy storage circuit 160 is electrically connected to the bootstrap output terminal OD. The output energy storage circuit 160 is used to store electrical energy.

[0295] When at least one embodiment of the driving circuit shown in FIG18 of the present disclosure is in operation, at the rising edge of the output clock signal provided at the output clock signal terminal CLKO, the potential of the output control node Q is bootstrapped and pulled up by the bootstrap pull-up effect of the output energy storage circuit 160, thereby ensuring carry output and drive output.

[0296] Optionally, the first high voltage end and the second high voltage end are the same voltage end.

[0297] In at least one embodiment of the driving circuit shown in FIG. 18 of the present disclosure, since the potential of the output control node Q is bootstrapped, the first high voltage terminal and the second high voltage terminal can be set to the same voltage terminal.

[0298] The driving circuit according to at least one embodiment of the present disclosure further includes an input circuit;

[0299] The input circuit is electrically connected to the first clock signal terminal, the input terminal and the second node respectively, and is used to control the connection or disconnection between the input terminal and the second node under the control of the first clock signal provided by the first clock signal terminal.

[0300] In a specific implementation, the driving circuit may further include an input circuit, and the input circuit controls the connection or disconnection between the input terminal and the second node under the control of a first clock signal.

[0301] As shown in FIG19 , based on at least one embodiment of the driving circuit shown in FIG11 , the driving circuit according to at least one embodiment of the present disclosure further includes an input circuit 171 , a second energy storage circuit 172 , and a third energy storage circuit 173 ;

[0302] The input circuit 171 is electrically connected to the first clock signal terminal CK1, the input terminal I1 and the second node Q1 respectively, and is used to control the connection or disconnection between the input terminal I1 and the second node Q1 under the control of the first clock signal provided by the first clock signal terminal CK1;

[0303] The second energy storage circuit 172 is electrically connected to the output control node Q and the carry signal output terminal CR respectively, and is used to store electrical energy;

[0304] The third energy storage circuit 173 is electrically connected to the reset control node SR and the first low voltage terminal VGL1 respectively, and is used for storing electrical energy.

[0305] In at least one embodiment of the driving circuit shown in Figures 19-21, the driving circuit includes an input circuit 171, a second energy storage circuit 172 and a third energy storage circuit 173; however, in at least one embodiment of the present disclosure, the driving circuit may include at least one of the input circuit 171, the second energy storage circuit 172 and the third energy storage circuit 173.

[0306] As shown in FIG20 , based on at least one embodiment of the driving circuit shown in FIG12 , the driving circuit according to at least one embodiment of the present disclosure further includes an input circuit 171 , a second energy storage circuit 172 , and a third energy storage circuit 173 ;

[0307] The input circuit 171 is electrically connected to the first clock signal terminal CK1, the input terminal I1 and the second node Q1 respectively, and is used to control the connection or disconnection between the input terminal I1 and the second node Q1 under the control of the first clock signal provided by the first clock signal terminal CK1;

[0308] The second energy storage circuit 172 is electrically connected to the output control node Q and the carry signal output terminal CR respectively, and is used to store electrical energy;

[0309] The third energy storage circuit 173 is electrically connected to the reset control node SR and the first low voltage terminal VGL1 respectively, and is used for storing electrical energy.

[0310] As shown in FIG21 , based on at least one embodiment of the driving circuit shown in FIG13 , the driving circuit according to at least one embodiment of the present disclosure further includes an input circuit 171 , a second energy storage circuit 172 , and a third energy storage circuit 173 ;

[0311] The input circuit 171 is electrically connected to the first clock signal terminal CK1, the input terminal I1 and the second node Q1 respectively, and is used to control the connection or disconnection between the input terminal I1 and the second node Q1 under the control of the first clock signal provided by the first clock signal terminal CK1;

[0312] The second energy storage circuit 172 is electrically connected to the output control node Q and the carry signal output terminal CR respectively, and is used to store electrical energy;

[0313] The third energy storage circuit 173 is electrically connected to the reset control node SR and the first low voltage terminal VGL1 respectively, and is used for storing electrical energy.

[0314] As shown in FIG22 , based on at least one embodiment of the driving circuit shown in FIG14 , the driving circuit according to at least one embodiment of the present disclosure further includes an input circuit 171 , a second energy storage circuit 172 , and a third energy storage circuit 173 ;

[0315] The input circuit 171 is electrically connected to the first clock signal terminal CK1, the input terminal I1 and the second node Q1 respectively, and is used to control the connection or disconnection between the input terminal I1 and the second node Q1 under the control of the first clock signal provided by the first clock signal terminal CK1;

[0316] The second energy storage circuit 172 is electrically connected to the output control node Q and the drive signal output terminal OT respectively, and is used to store electrical energy;

[0317] The third energy storage circuit 173 is electrically connected to the reset control node SR and the second low voltage terminal VGL2 respectively, and is used for storing electrical energy.

[0318] As shown in FIG23 , based on at least one embodiment of the driving circuit shown in FIG17 , the driving circuit according to at least one embodiment of the present disclosure further includes an input circuit 171 , a second energy storage circuit 172 , and a third energy storage circuit 173 ;

[0319] The input circuit 171 is electrically connected to the first clock signal terminal CK1, the input terminal I1 and the second node Q1 respectively, and is used to control the connection or disconnection between the input terminal I1 and the second node Q1 under the control of the first clock signal provided by the first clock signal terminal CK1;

[0320] The second energy storage circuit 172 is electrically connected to the output control node Q and the carry signal output terminal CR respectively, and is used to store electrical energy;

[0321] The third energy storage circuit 173 is electrically connected to the reset control node SR and the first low voltage terminal VGL1 respectively, and is used for storing electrical energy.

[0322] As shown in FIG24A , based on at least one embodiment of the driving circuit shown in FIG18 , the driving circuit according to at least one embodiment of the present disclosure further includes an input circuit 171 and a third energy storage circuit 173 ;

[0323] The input circuit 171 is electrically connected to the first clock signal terminal CK1, the input terminal I1 and the second node Q1 respectively, and is used to control the connection or disconnection between the input terminal I1 and the second node Q1 under the control of the first clock signal provided by the first clock signal terminal CK1;

[0324] The third energy storage circuit 173 is electrically connected to the reset control node SR and the first low voltage terminal VGL1 respectively, and is used for storing electrical energy.

[0325] In at least one embodiment of the present disclosure, the driving signal output terminal may be a light-emitting control signal output terminal, which may be used to provide a light-emitting control signal to the pixel circuit, but is not limited thereto.

[0326] As shown in FIG24B , at least one embodiment of the pixel circuit may include a driving transistor T0 , a first light emission control transistor TE1 , a second light emission control transistor TE2 , a data writing transistor TD , a compensation control transistor TC , and an organic light emitting diode O1 ;

[0327] The gate of TE1 is electrically connected to the light emitting control terminal E1, the drain of TE1 is electrically connected to the power supply voltage terminal VDD, and the source of TE1 is electrically connected to the drain of T0;

[0328] The gate of TE2 is electrically connected to the light emitting control terminal E1, the drain of TE2 is electrically connected to the source of T0, the anode of the source of TE2 is electrically connected to O1, and the cathode of O1 is electrically connected to the low level terminal VSS;

[0329] The gate of TD is electrically connected to the gate line GT, the source of TD is electrically connected to the data line DT, and the drain of TD is electrically connected to the drain of T0;

[0330] The gate of TC is electrically connected to the gate line GT, the source of TC is electrically connected to the gate of T0, and the drain of TC is electrically connected to the source of T0.

[0331] In at least one embodiment of the pixel circuit shown in FIG. 24B , all transistors may be n-type transistors, but the present invention is not limited thereto.

[0332] In at least one embodiment of the present disclosure, the driving signal output terminal can be a light-emitting control signal output terminal, which can be used to provide a light-emitting control signal for the gate of TE1 and the gate of TE2 in at least one embodiment of the pixel circuit shown in Figure 24B, but is not limited to this.

[0333] In at least one embodiment of the driving circuit shown in FIG. 25A to FIG. 36 of the present disclosure, the driving signal output terminal is a light-emitting control signal output terminal.

[0334] Optionally, the first energy storage circuit includes a first capacitor, and the second control circuit includes a first transistor and a second transistor; a first end of the first capacitor is electrically connected to the first clock signal end, and a second end of the first capacitor is electrically connected to the control node;

[0335] The gate of the first transistor is electrically connected to the control node, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the first intermediate node;

[0336] A gate of the second transistor is electrically connected to the input terminal, a first electrode of the second transistor is electrically connected to the first intermediate node, and a second electrode of the second transistor is electrically connected to the control node.

[0337] In all embodiments of the present disclosure, the first energy storage circuit may include a first capacitor, the second control circuit may include a first transistor and a second transistor, and the structure of the first energy storage circuit and the structure of the second control circuit may be as shown above.

[0338] Optionally, the second control circuit further includes a third transistor;

[0339] A gate of the third transistor is electrically connected to the input terminal, a first electrode of the third transistor is electrically connected to the second voltage terminal, and a second electrode of the third transistor is electrically connected to the first intermediate node.

[0340] In all embodiments of the present disclosure, the second control circuit may include a third transistor, and the structure of the second control circuit may be as shown above.

[0341] Optionally, the third control circuit includes a fourth transistor; the gate of the fourth transistor is electrically connected to the first clock signal end, the first electrode of the fourth transistor is electrically connected to the first node, and the second electrode of the fourth transistor is electrically connected to the reset control node.

[0342] In all embodiments of the present disclosure, the third control circuit may include a fourth transistor, and the structure of the third control circuit may be as shown above.

[0343] Optionally, the third control circuit includes a fourth transistor, a fifth transistor, and a sixth transistor; the gate of the fourth transistor is electrically connected to the first control terminal, the first electrode of the fourth transistor is electrically connected to the first node, and the second electrode of the fourth transistor is electrically connected to the second intermediate node;

[0344] The gate of the fifth transistor is electrically connected to the first control terminal, the first electrode of the fifth transistor is electrically connected to the second intermediate node, and the second electrode of the fifth transistor is electrically connected to the reset control node;

[0345] A gate of the sixth transistor is electrically connected to the reset control node, a first electrode of the sixth transistor is electrically connected to the third voltage terminal, and a second electrode of the sixth transistor is electrically connected to the second intermediate node.

[0346] In all embodiments of the present disclosure, the third control circuit may include a fourth transistor, a fifth transistor, and a sixth transistor, and the structure of the third control circuit may be as shown above.

[0347] Optionally, the first control circuit includes a seventh transistor;

[0348] A gate of the seventh transistor is electrically connected to the control node, a first electrode of the seventh transistor is electrically connected to the first clock signal terminal, and a second electrode of the seventh transistor is electrically connected to the first node.

[0349] In all embodiments of the present disclosure, the first control circuit may include a seventh transistor, and the structure of the first control circuit may be as shown above.

[0350] Optionally, the first control circuit includes a seventh transistor, an eighth transistor and a ninth transistor;

[0351] The gate of the seventh transistor is electrically connected to the control node, the first electrode of the seventh transistor is electrically connected to the first clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the third intermediate node;

[0352] The gate of the eighth transistor is electrically connected to the control node, the first electrode of the eighth transistor is electrically connected to the third intermediate node, and the second electrode of the eighth transistor is electrically connected to the first node;

[0353] A gate of the ninth transistor is electrically connected to the first node, a first electrode of the ninth transistor is electrically connected to the fourth voltage terminal, and a second electrode of the ninth transistor is electrically connected to the third intermediate node.

[0354] In all embodiments of the present disclosure, the first control circuit may include a seventh transistor, an eighth transistor, and a ninth transistor, and the structure of the first control circuit may be as shown above.

[0355] Optionally, the fourth control circuit includes a tenth transistor;

[0356] A gate of the tenth transistor is electrically connected to the second node, a first electrode of the tenth transistor is electrically connected to the fifth voltage terminal, and a second electrode of the tenth transistor is electrically connected to the first node.

[0357] In all embodiments of the present disclosure, the fourth control circuit may include a tenth transistor, and the structure of the fourth control circuit may be as shown above.

[0358] Optionally, the fourth control circuit includes a tenth transistor;

[0359] A gate of the tenth transistor is electrically connected to the second node, a first electrode of the tenth transistor is electrically connected to the fifth voltage terminal, and a second electrode of the tenth transistor is electrically connected to the reset control node.

[0360] In all embodiments of the present disclosure, the fourth control circuit may include a tenth transistor, and the structure of the fourth control circuit may be as shown above.

[0361] Optionally, the fourth control circuit includes a tenth transistor, an eleventh transistor and a twelfth transistor;

[0362] The gate of the tenth transistor is electrically connected to the second node, the first electrode of the tenth transistor is electrically connected to the fourth intermediate node, and the second electrode of the tenth transistor is electrically connected to the first node;

[0363] The gate of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the sixth voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the fourth intermediate node;

[0364] A gate of the twelfth transistor is electrically connected to the first node, a first electrode of the twelfth transistor is electrically connected to the seventh voltage terminal, and a second electrode of the twelfth transistor is electrically connected to the fourth intermediate node.

[0365] In all embodiments of the present disclosure, the fourth control circuit may include a tenth transistor, an eleventh transistor, and a twelfth transistor, and the structure of the fourth control circuit may be as shown above.

[0366] Optionally, the carry output circuit includes a carry output transistor, the carry reset circuit includes a carry reset transistor, the drive output circuit includes a drive output transistor, and the drive reset circuit includes a drive reset transistor;

[0367] The gate of the carry output transistor is electrically connected to the output control node, the first electrode of the carry output transistor is electrically connected to the first high voltage terminal, and the second electrode of the carry output transistor is electrically connected to the carry signal output terminal;

[0368] The gate of the carry reset transistor is electrically connected to the reset control node, the first electrode of the carry reset transistor is electrically connected to the carry signal output terminal, and the second electrode of the carry reset transistor is electrically connected to the first low voltage terminal;

[0369] The gate of the driving output transistor is electrically connected to the output control node, the first electrode of the driving output transistor is electrically connected to the second high voltage terminal, and the second electrode of the driving output transistor is electrically connected to the driving signal output terminal;

[0370] The gate of the driving reset transistor is electrically connected to the reset control node, the first electrode of the driving reset transistor is electrically connected to the driving signal output terminal, and the second electrode of the driving reset transistor is electrically connected to the second low voltage terminal.

[0371] In all embodiments of the present disclosure, the carry output circuit includes a carry output transistor, the carry reset circuit includes a carry reset transistor, the drive output circuit includes a drive output transistor, and the drive reset circuit includes a drive reset transistor; the structure of the carry output circuit may be as shown above, the structure of the carry reset circuit may be as shown above, the structure of the drive output circuit may be as shown above, and the structure of the drive reset circuit may be as shown above. Optionally, the drive output circuit includes a drive output transistor, and the drive reset circuit includes a first drive reset transistor, a second drive reset transistor, and a reset control transistor;

[0372] The gate of the driving output transistor is electrically connected to the output control node, the first electrode of the driving output transistor is electrically connected to the third high voltage terminal, and the second electrode of the driving output transistor is electrically connected to the driving signal output terminal;

[0373] The gate of the first driving reset transistor is electrically connected to the reset control node, the first electrode of the first driving reset transistor is electrically connected to the driving signal output terminal, and the second electrode of the first driving reset transistor is electrically connected to the output intermediate node;

[0374] The gate of the second driving reset transistor is electrically connected to the reset control node, the first electrode of the second driving reset transistor is electrically connected to the output intermediate node, and the second electrode of the first driving reset transistor is electrically connected to the third low voltage terminal;

[0375] The gate of the reset control transistor is electrically connected to the drive signal output terminal, the first electrode of the reset control transistor is electrically connected to the eighth voltage terminal, and the second electrode of the reset control transistor is electrically connected to the output intermediate node.

[0376] In all embodiments of the present disclosure, the drive output circuit includes a drive output transistor, and the drive reset circuit includes a first drive reset transistor, a second drive reset transistor and a reset control transistor; the structure of the drive output circuit can be as shown above, and the structure of the drive reset circuit can be as shown above.

[0377] Optionally, the fifth control circuit includes a thirteenth transistor;

[0378] A gate of the thirteenth transistor is electrically connected to the ninth voltage terminal, a first electrode of the thirteenth transistor is electrically connected to the second node, and a second electrode of the thirteenth transistor is electrically connected to the output control node.

[0379] In all embodiments of the present disclosure, the fifth control circuit may include a thirteenth transistor, and the structure of the fifth control circuit may be as shown above.

[0380] Optionally, the fifth control circuit includes a thirteenth transistor, a fourteenth transistor and a fifteenth transistor;

[0381] The gate of the thirteenth transistor is electrically connected to the ninth voltage terminal, the first electrode of the thirteenth transistor is electrically connected to the second node, and the second electrode of the thirteenth transistor is electrically connected to the fifth intermediate node;

[0382] The gate of the fourteenth transistor is electrically connected to the ninth voltage terminal, the first electrode of the fourteenth transistor is electrically connected to the fifth intermediate node, and the second electrode of the fourteenth transistor is electrically connected to the output control node;

[0383] A gate of the fifteenth transistor is electrically connected to the output control node, a first electrode of the fifteenth transistor is electrically connected to the tenth voltage terminal, and a second electrode of the fifteenth transistor is electrically connected to the fifth intermediate node.

[0384] In all embodiments of the present disclosure, the fifth control circuit may include a thirteenth transistor, a fourteenth transistor, and a fifteenth transistor, and the structure of the fifth control circuit may be as shown above.

[0385] Optionally, the bootstrap output circuit includes a bootstrap output transistor and a bootstrap reset transistor, and the output energy storage circuit includes an output control capacitor;

[0386] The gate of the bootstrap output transistor is electrically connected to the output control node, the first electrode of the bootstrap output transistor is electrically connected to the output clock signal terminal, and the second electrode of the bootstrap output transistor is electrically connected to the bootstrap output terminal;

[0387] The gate of the bootstrap reset transistor is electrically connected to the reset control node, the first electrode of the bootstrap output transistor is electrically connected to the bootstrap output terminal, and the second electrode of the bootstrap output transistor is electrically connected to the fourth low voltage terminal;

[0388] A first end of the output control capacitor is electrically connected to the output control node, a second end of the output control capacitor is electrically connected to the bootstrap output end, and the output energy storage circuit is used to store electrical energy.

[0389] In all embodiments of the present disclosure, the bootstrap output circuit includes a bootstrap output transistor and a bootstrap reset transistor, and the output energy storage circuit includes an output control capacitor; the structure of the bootstrap output circuit can be as shown above, and the structure of the output energy storage circuit can be as shown above.

[0390] In at least one embodiment of the driving circuit shown in FIG. 25A to FIG. 36 , the driving signal output terminal is a light-emitting control signal output terminal, but the present invention is not limited thereto.

[0391] As shown in FIG25A , based on at least one embodiment of the driving circuit shown in FIG11 , the first energy tank circuit includes a first capacitor C1, and the second control circuit includes a first transistor T1 and a second transistor T2; a first end of the first capacitor C1 is electrically connected to the first clock signal terminal CK1, and a second end of the first capacitor C1 is electrically connected to the control node QB1;

[0392] The gate of the first transistor T1 is electrically connected to the control node QB1, the source of the first transistor T1 is electrically connected to the second high voltage terminal VGH2, and the drain of the first transistor T1 is electrically connected to the first intermediate node P1;

[0393] The gate of the second transistor T2 is electrically connected to the input terminal I1, the source of the second transistor T2 is electrically connected to the first intermediate node P1, and the drain of the second transistor T2 is electrically connected to the control node QB1;

[0394] The second control circuit further includes a third transistor T3;

[0395] The gate of the third transistor T3 is electrically connected to the input terminal I1, the source of the third transistor T3 is electrically connected to the first low voltage terminal VGL1, and the drain of the third transistor T3 is electrically connected to the first intermediate node P1;

[0396] The third control circuit includes a fourth transistor T4;

[0397] The gate of the fourth transistor T4 is electrically connected to the first clock signal terminal CK1, the source of the fourth transistor T4 is electrically connected to the first node QB, and the drain of the fourth transistor T4 is electrically connected to the reset control node SR;

[0398] The first control circuit includes a seventh transistor T7;

[0399] A gate of the seventh transistor T7 is electrically connected to the control node QB1 , a source of the seventh transistor T7 is electrically connected to the first clock signal terminal CK1 , and a drain of the seventh transistor T7 is electrically connected to the first node QB.

[0400] The fourth control circuit includes a tenth transistor T10;

[0401] The gate of the tenth transistor T10 is electrically connected to the second node Q1, the source of the tenth transistor T10 is electrically connected to the first low voltage terminal VGL1, and the drain of the tenth transistor T10 is electrically connected to the first node QB;

[0402] The carry output circuit includes a carry output transistor TR1, the carry reset circuit includes a carry reset transistor TR2, the drive output circuit includes a drive output transistor TP1, and the drive reset circuit includes a drive reset transistor TP2;

[0403] The gate of the carry output transistor TR1 is electrically connected to the output control node Q, the source of the carry output transistor TR1 is electrically connected to the first high voltage terminal VGH1, and the drain of the carry output transistor TR1 is electrically connected to the carry signal output terminal CR;

[0404] The gate of the carry reset transistor TR2 is electrically connected to the reset control node SR, the source of the carry reset transistor TR2 is electrically connected to the carry signal output terminal CR, and the drain of the carry reset transistor TR2 is electrically connected to the first low voltage terminal VGL1;

[0405] The gate of the driving output transistor TP1 is electrically connected to the output control node Q, the source of the driving output transistor TP1 is electrically connected to the second high voltage terminal VGH2, and the second electrode of the driving output transistor TP1 is electrically connected to the light emitting control signal output terminal EM;

[0406] The gate of the driving reset transistor TP2 is electrically connected to the reset control node SR, the source of the driving reset transistor TP2 is electrically connected to the light emitting control signal output terminal EM, and the drain of the driving reset transistor TP2 is electrically connected to the second low voltage terminal VGL2;

[0407] The fifth control circuit includes a thirteenth transistor T13;

[0408] The gate of the thirteenth transistor T13 is electrically connected to the first high voltage terminal VGH1, the source of the thirteenth transistor T13 is electrically connected to the second node Q1, and the drain of the thirteenth transistor T13 is electrically connected to the output control node Q;

[0409] The input circuit includes a sixteenth transistor T16;

[0410] The gate of the sixteenth transistor T16 is electrically connected to the first clock signal terminal CK1, the source of the sixteenth transistor T16 is electrically connected to the input terminal I1, and the drain of the sixteenth transistor T16 is electrically connected to the second node Q1;

[0411] At least one embodiment of the driving circuit shown in FIG. 25A of the present disclosure may further include a second capacitor C2 and a third capacitor C3;

[0412] The first end of C2 is electrically connected to the output control node Q, and the second end of C2 is electrically connected to the carry signal output terminal CR;

[0413] A first end of C3 is electrically connected to the reset control node SR, and a second end of C3 is electrically connected to the first low voltage end VGL1.

[0414] In at least one embodiment shown in FIG. 25A , the first voltage terminal is the second high voltage terminal VGH2 , the second voltage terminal is the first low voltage terminal VGL1 , the fifth voltage terminal is the first low voltage terminal VGL1 , and the ninth voltage terminal is the first high voltage terminal VGH1 .

[0415] In at least one embodiment shown in FIG. 25A , all transistors are n-type transistors, but the present invention is not limited thereto.

[0416] In at least one embodiment shown in FIG. 25A , the source of T1 may be replaced by being electrically connected to the first high voltage terminal VGH1 .

[0417] In at least one embodiment of the driving circuit shown in FIG25A , the second control circuit includes a first transistor T1 , a second transistor T2 , and a third transistor T3 ;

[0418] When the potential of QB1 is high, T2 is turned on, and the second high voltage terminal VGH2 is connected to P1, preventing the potential of QB1 from being pulled down due to leakage, ensuring that T7 is turned on, so that the potential of QB is pulled up to a high voltage, so that CR and EM can correctly output low voltage signals.

[0419] In at least one embodiment of the driving circuit shown in FIG. 25A , T4 is provided. When the potential of the first clock signal provided by CK1 changes from a high level to a low level, the presence of T4 prevents the potential of SR from decreasing due to leakage.

[0420] In at least one embodiment of the present disclosure, the voltage value of the first high voltage signal provided by the first high voltage terminal VGH1 may be greater than the voltage value of the second high voltage signal provided by the second high voltage terminal VGH2. For example, the voltage value of the first high voltage signal may be 17V, and the voltage value of the second high voltage signal may be 14V.

[0421] The voltage value of the first low voltage signal provided by the first low voltage terminal VGL1 may be lower than the voltage value of the second low voltage signal provided by the second low voltage terminal VGL2; for example, the voltage value of the first low voltage signal may be -17V, and the voltage value of the second low voltage signal may be -14V.

[0422] In at least one embodiment of the present disclosure, the voltage value of the first high voltage signal may be greater than or equal to 11V and less than or equal to 17V, and the voltage value of the second high voltage signal may be greater than or equal to 9V and less than or equal to 15V;

[0423] The voltage value of the first low voltage signal may be greater than or equal to -17V and less than or equal to -11V, and the voltage value of the second low voltage signal may be greater than or equal to -15V and less than or equal to -9V;

[0424] But it is not limited to this.

[0425] In at least one embodiment of the present disclosure, the voltage value of the second high voltage signal is set to be relatively low, so that even if the potential of Q is relatively low, EM can normally output the light emitting control signal to ensure that the pixel circuit can operate normally.

[0426] In at least one embodiment of the present disclosure, the voltage value of the first low voltage signal may be equal to the voltage value of the second low voltage signal;

[0427] The voltage value of the first high voltage signal may be equal to the voltage value of the second high voltage signal;

[0428] But it is not limited to this.

[0429] FIG. 25B shows the potential of QB when the threshold voltage of the transistor is negatively biased to −3 V in at least one embodiment of the driving circuit shown in FIG. 25A .

[0430] In FIG25B , the horizontal axis represents time t, with a unit of s (seconds); the vertical axis represents the potential of QB, with a unit of V (volts).

[0431] As shown in FIG25C , when at least one embodiment of the driving circuit shown in FIG25A of the present disclosure is in operation, a driving cycle may include an input phase S1, a first interval phase S01, a second interval phase S02, an output phase S2, an output reset phase S3, and an output cutoff phase S4, which are arranged in sequence;

[0432] In the input phase S1, CK1 provides a high voltage signal, I1 provides a low voltage signal, T16 is turned on, Q1 is connected to I1, and the potential of Q1 is low. T13 is turned on, and the potential of Q is low. The potential of QB1 becomes high due to the bootstrap pull-up of C1. T7 is turned on, QB is connected to CK1, and the potential of QB is high. T4 is turned on, and the potential of SR is high. TR2 and TP2 are both turned on, and CR and EM both output low voltage signals. T2 is turned on, and P1 is connected to VGH2.

[0433] In the first interval phase S01, the potential of the first clock signal provided by CK1 changes from a high voltage to a low voltage. Due to the action of C1, the potential of QB1 jumps to a low voltage, T7 is turned off, and the potential of QB remains at a high voltage.

[0434] In the second interval phase S02, I1 provides a high voltage signal, T3 and T1 are turned on, the potential of QB1 is a low voltage, T7 is turned off, and the potential of QB is maintained at a high voltage;

[0435] In the first interval phase S01 and the second interval phase S02, the potential of QB is high, CK1 provides a low voltage signal, T4 is turned off, the potential of SR is maintained at a high voltage, TR2 and TP2 are both turned on, and CR and EM both output low voltage signals;

[0436] In the output phase S2, when CK1 provides a high voltage signal and I1 provides a high voltage signal, T16 is turned on, Q1 is connected to I1, and the potential of Q1 is high voltage; T10 is turned on, QB is connected to VGL1, and the potential of QB is low voltage; T13 is turned on, and the potential of Q is high voltage; TR1 and TP1 are turned on, CR and EM both output high voltage signals; T3 and T1 are turned on, and the potential of QB1 is low voltage;

[0437] In the output reset phase S3, CK1 provides a high voltage signal, I1 provides a low voltage signal, T16 is turned on, Q1 is connected to I1, the potential of Q1 is low voltage, T13 is turned on, and the potential of Q is a low voltage signal;

[0438] In the output reset phase S3, when the first clock signal provided by CK1 jumps from a low voltage to a high voltage, the potential of QB1 is high, QB is connected to CK1, and the potential of QB is high; TR2 and TP2 are turned on, CR and EM both output low voltage signals; T2 is turned on, and P1 is connected to VGH2;

[0439] In the output cutoff stage S4, the potential of Q1 and the potential of Q are low voltage, the potential of QB and the potential of QB1 are high voltage, TR2 and TP2 are open, CR and EM both output low voltage signals; T2 is turned on, and P1 is connected to VGH2;

[0440] During the output cutoff phase S4, due to the action of C1, the potential of QB changes with the potential of the first clock signal provided by CK1. When the potential of QB1 and the potential of CK1 are high, T7 turns on, causing the potential of QB to be high. When the potential of QB1 is low, T7 turns off, and the potential of QB remains high. As shown in Figure 26, based on at least one embodiment of the drive circuit shown in Figure 12, the first energy storage circuit includes a first capacitor C1, the second control circuit includes a first transistor T1 and a second transistor T2, and the drive reset circuit includes a third transistor T3; the first end of the first capacitor C1 is electrically connected to the first clock signal terminal CK1, and the second end of the first capacitor C1 is electrically connected to the control node QB1.

[0441] The gate of the first transistor T1 is electrically connected to the control node QB1, the source of the first transistor T1 is electrically connected to the second high voltage terminal VGH2, and the drain of the first transistor T1 is electrically connected to the first intermediate node P1;

[0442] The gate of the second transistor T2 is electrically connected to the input terminal I1, the source of the second transistor T2 is electrically connected to the first intermediate node P1, and the drain of the second transistor T2 is electrically connected to the control node QB1;

[0443] The third control circuit includes a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6;

[0444] The gate of the fourth transistor T4 is electrically connected to the first high voltage terminal VGH1, the source of the fourth transistor T4 is electrically connected to the first node QB, and the drain of the fourth transistor T4 is electrically connected to the second intermediate node P2;

[0445] The gate of the fifth transistor T5 is electrically connected to the first high voltage terminal VGH1, the source of the fifth transistor T5 is electrically connected to the second intermediate node P2, and the drain of the fifth transistor T5 is electrically connected to the reset control node SR;

[0446] The gate of the sixth transistor T6 is electrically connected to the reset control node SR, the source of the sixth transistor T6 is electrically connected to the second high voltage terminal VGH2, and the drain of the sixth transistor T6 is electrically connected to the second intermediate node P2;

[0447] The third control circuit includes a fourth transistor T4;

[0448] The gate of the fourth transistor T4 is electrically connected to the first clock signal terminal CK1, the source of the fourth transistor T4 is electrically connected to the first node QB, and the drain of the fourth transistor T4 is electrically connected to the reset control node SR;

[0449] The first control circuit includes a seventh transistor T7;

[0450] A gate of the seventh transistor T7 is electrically connected to the control node QB1 , a source of the seventh transistor T7 is electrically connected to the first clock signal terminal CK1 , and a drain of the seventh transistor T7 is electrically connected to the first node QB.

[0451] The fourth control circuit includes a tenth transistor T10;

[0452] The gate of the tenth transistor T10 is electrically connected to the second node Q1, the source of the tenth transistor T10 is electrically connected to the first low voltage terminal VGL1, and the drain of the tenth transistor T10 is electrically connected to the first node QB;

[0453] The carry output circuit includes a carry output transistor TR1, the carry reset circuit includes a carry reset transistor TR2, the drive output circuit includes a drive output transistor TP1, and the drive reset circuit includes a drive reset transistor TP2;

[0454] The gate of the carry output transistor TR1 is electrically connected to the output control node Q, the source of the carry output transistor TR1 is electrically connected to the first high voltage terminal VGH1, and the drain of the carry output transistor TR1 is electrically connected to the carry signal output terminal CR;

[0455] The gate of the carry reset transistor TR2 is electrically connected to the reset control node SR, the source of the carry reset transistor TR2 is electrically connected to the carry signal output terminal CR, and the drain of the carry reset transistor TR2 is electrically connected to the first low voltage terminal VGL1;

[0456] The gate of the driving output transistor TP1 is electrically connected to the output control node Q, the source of the driving output transistor TP1 is electrically connected to the second high voltage terminal VGH2, and the second electrode of the driving output transistor TP1 is electrically connected to the light emitting control signal output terminal EM;

[0457] The gate of the driving reset transistor TP2 is electrically connected to the reset control node SR, the source of the driving reset transistor TP2 is electrically connected to the light emitting control signal output terminal EM, and the drain of the driving reset transistor TP2 is electrically connected to the second low voltage terminal VGL2;

[0458] The fifth control circuit includes a thirteenth transistor T13;

[0459] The gate of the thirteenth transistor T13 is electrically connected to the first high voltage terminal VGH1, the source of the thirteenth transistor T13 is electrically connected to the second node Q1, and the drain of the thirteenth transistor T13 is electrically connected to the output control node Q;

[0460] The input circuit includes a sixteenth transistor T16;

[0461] The gate of the sixteenth transistor T16 is electrically connected to the first clock signal terminal CK1, the source of the sixteenth transistor T16 is electrically connected to the input terminal I1, and the drain of the sixteenth transistor T16 is electrically connected to the second node Q1;

[0462] At least one embodiment of the driving circuit shown in FIG26 of the present disclosure may further include a second capacitor C2 and a third capacitor C3;

[0463] The first end of C2 is electrically connected to the output control node Q, and the second end of C2 is electrically connected to the carry signal output terminal CR;

[0464] A first end of C3 is electrically connected to the reset control node SR, and a second end of C3 is electrically connected to the first low voltage end VGL1.

[0465] In at least one embodiment shown in Figure 26, the first voltage terminal is the second high voltage terminal VGH2, the second voltage terminal is the first low voltage terminal VGL1, the fifth voltage terminal is the first low voltage terminal VGL1, the ninth voltage terminal is the first high voltage terminal VGH1, the first control terminal is the first high voltage terminal VGH1, and the third voltage terminal is the second high voltage terminal VGH2.

[0466] In at least one embodiment shown in FIG. 26 , all transistors are n-type transistors;

[0467] The first control terminal may be replaced by a first clock signal terminal CK1;

[0468] But it is not limited to this.

[0469] In at least one embodiment shown in FIG. 26 , the source of T1 may be replaced by being electrically connected to the first high voltage terminal VGH1 , and the source of T6 may be replaced by being electrically connected to the first high voltage terminal VGH1 .

[0470] In at least one embodiment of the driving circuit shown in FIG26 , the second control circuit includes a first transistor T1 , a second transistor T2 , and a third transistor T3 ;

[0471] When the potential of the first clock signal provided by CK1 jumps from a low level to a high level, the potential of QB1 becomes a high voltage due to the action of C1, T2 is turned on, and the second high voltage terminal VGH2 is connected to P1, preventing the potential of QB1 from being pulled low due to leakage. This ensures that T7 is turned on, so that the potential of QB is pulled up to a high voltage, so that CR and EM can correctly output low-voltage signals.

[0472] In at least one embodiment of the driving circuit shown in Figure 26, the third control circuit includes a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6; when the potential of SR is a high voltage, T6 is turned on, and P2 is connected to the second high voltage terminal VGH2 to prevent the potential of SR from becoming low due to leakage of the transistor.

[0473] As shown in FIG27 , based on at least one embodiment of the driving circuit shown in FIG13 , the first energy tank circuit includes a first capacitor C1, the second control circuit includes a first transistor T1 and a second transistor T2, and the driving reset circuit includes a third transistor T3; a first end of the first capacitor C1 is electrically connected to the first clock signal terminal CK1, and a second end of the first capacitor C1 is electrically connected to the control node QB1;

[0474] The gate of the first transistor T1 is electrically connected to the control node QB1, the source of the first transistor T1 is electrically connected to the second high voltage terminal VGH2, and the drain of the first transistor T1 is electrically connected to the first intermediate node P1;

[0475] The gate of the second transistor T2 is electrically connected to the input terminal I1, the source of the second transistor T2 is electrically connected to the first intermediate node P1, and the drain of the second transistor T2 is electrically connected to the control node QB1;

[0476] The third control circuit includes a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6;

[0477] The gate of the fourth transistor T4 is electrically connected to the first high voltage terminal VGH1, the source of the fourth transistor T4 is electrically connected to the first node QB, and the drain of the fourth transistor T4 is electrically connected to the second intermediate node P2;

[0478] The gate of the fifth transistor T5 is electrically connected to the first high voltage terminal VGH1, the source of the fifth transistor T5 is electrically connected to the second intermediate node P2, and the drain of the fifth transistor T5 is electrically connected to the reset control node SR;

[0479] The gate of the sixth transistor T6 is electrically connected to the reset control node SR, the source of the sixth transistor T6 is electrically connected to the second high voltage terminal VGH2, and the drain of the sixth transistor T6 is electrically connected to the second intermediate node P2;

[0480] The third control circuit includes a fourth transistor T4;

[0481] The gate of the fourth transistor T4 is electrically connected to the first clock signal terminal CK1, the source of the fourth transistor T4 is electrically connected to the first node QB, and the drain of the fourth transistor T4 is electrically connected to the reset control node SR;

[0482] The first control circuit includes a seventh transistor T7, an eighth transistor T8 and a ninth transistor T9;

[0483] The gate of the seventh transistor T7 is electrically connected to the control node QB1, the source of the seventh transistor T7 is electrically connected to the first clock signal terminal CK1, and the drain of the seventh transistor T7 is electrically connected to the third intermediate node P3;

[0484] The gate of the eighth transistor T8 is electrically connected to the control node QB1, the source of the eighth transistor T8 is electrically connected to the third intermediate node P3, and the drain of the eighth transistor T8 is electrically connected to the first node QB;

[0485] The gate of the ninth transistor T9 is electrically connected to the first node QB, the source of the ninth transistor T9 is electrically connected to the second high voltage terminal VGH2, and the second electrode of the ninth transistor is electrically connected to the third intermediate node P3;

[0486] The fourth control circuit includes a tenth transistor T10;

[0487] The gate of the tenth transistor T10 is electrically connected to the second node Q1, the source of the tenth transistor T10 is electrically connected to the first low voltage terminal VGL1, and the drain of the tenth transistor T10 is electrically connected to the first node QB;

[0488] The carry output circuit includes a carry output transistor TR1, the carry reset circuit includes a carry reset transistor TR2, the drive output circuit includes a drive output transistor TP1, and the drive reset circuit includes a drive reset transistor TP2;

[0489] The gate of the carry output transistor TR1 is electrically connected to the output control node Q, the source of the carry output transistor TR1 is electrically connected to the first high voltage terminal VGH1, and the drain of the carry output transistor TR1 is electrically connected to the carry signal output terminal CR;

[0490] The gate of the carry reset transistor TR2 is electrically connected to the reset control node SR, the source of the carry reset transistor TR2 is electrically connected to the carry signal output terminal CR, and the drain of the carry reset transistor TR2 is electrically connected to the first low voltage terminal VGL1;

[0491] The gate of the driving output transistor TP1 is electrically connected to the output control node Q, the source of the driving output transistor TP1 is electrically connected to the second high voltage terminal VGH2, and the second electrode of the driving output transistor TP1 is electrically connected to the light emitting control signal output terminal EM;

[0492] The gate of the driving reset transistor TP2 is electrically connected to the reset control node SR, the source of the driving reset transistor TP2 is electrically connected to the light emitting control signal output terminal EM, and the drain of the driving reset transistor TP2 is electrically connected to the second low voltage terminal VGL2;

[0493] The fifth control circuit includes a thirteenth transistor T13;

[0494] The gate of the thirteenth transistor T13 is electrically connected to the first high voltage terminal VGH1, the source of the thirteenth transistor T13 is electrically connected to the second node Q1, and the drain of the thirteenth transistor T13 is electrically connected to the output control node Q;

[0495] The input circuit includes a sixteenth transistor T16;

[0496] The gate of the sixteenth transistor T16 is electrically connected to the first clock signal terminal CK1, the source of the sixteenth transistor T16 is electrically connected to the input terminal I1, and the drain of the sixteenth transistor T16 is electrically connected to the second node Q1;

[0497] At least one embodiment of the driving circuit shown in FIG27 of the present disclosure may further include a second capacitor C2 and a third capacitor C3;

[0498] The first end of C2 is electrically connected to the output control node Q, and the second end of C2 is electrically connected to the carry signal output terminal CR;

[0499] A first end of C3 is electrically connected to the reset control node SR, and a second end of C3 is electrically connected to the first low voltage end VGL1.

[0500] In at least one embodiment shown in Figure 27, the first voltage terminal is the second high voltage terminal VGH2, the second voltage terminal is the first low voltage terminal VGL1, the fifth voltage terminal is the first low voltage terminal VGL1, the ninth voltage terminal is the first high voltage terminal VGH1, the first control terminal is the first high voltage terminal VGH1, the third voltage terminal is the second high voltage terminal VGH2, and the fourth voltage terminal is the second high voltage terminal VGH2.

[0501] In at least one embodiment shown in FIG. 27 , all transistors are n-type transistors, but the present invention is not limited thereto.

[0502] In at least one embodiment shown in FIG. 27 , the source of T1 may be replaced by being electrically connected to the first high voltage terminal VGH1 , the source of T6 may be replaced by being electrically connected to the first high voltage terminal VGH1 , and the source of T9 may be replaced by being electrically connected to the first high voltage terminal VGH1 .

[0503] In at least one embodiment of the driving circuit shown in FIG27 , the second control circuit includes a first transistor T1 , a second transistor T2 , and a third transistor T3 ;

[0504] When the potential of the first clock signal provided by CK1 jumps from a low level to a high level, the potential of QB1 becomes a high voltage due to the action of C1, T2 is turned on, and the second high voltage terminal VGH2 is connected to P1, preventing the potential of QB1 from being pulled low due to leakage. This ensures that T7 is turned on, so that the potential of QB is pulled up to a high voltage, so that CR and EM can correctly output low-voltage signals.

[0505] In at least one embodiment of the driving circuit shown in Figure 27, the third control circuit includes a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6; when the potential of SR is a high voltage, T6 is turned on, and P2 is connected to the second high voltage terminal VGH2 to prevent the potential of SR from becoming low due to leakage of the transistor.

[0506] In at least one embodiment of the driving circuit shown in FIG27 , the first control circuit includes a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9; when the potential of QB is a high voltage, T9 is turned on, and P3 is connected to the second high voltage terminal VGH2, so that the potential of QB does not become low due to leakage.

[0507] As shown in FIG28 , based on at least one embodiment of the driving circuit shown in FIG16 , the first energy tank circuit includes a first capacitor C1, the second control circuit includes a first transistor T1 and a second transistor T2, and the driving reset circuit includes a third transistor T3; a first end of the first capacitor C1 is electrically connected to the first clock signal terminal CK1, and a second end of the first capacitor C1 is electrically connected to the control node QB1;

[0508] The gate of the first transistor T1 is electrically connected to the control node QB1, the source of the first transistor T1 is electrically connected to the second high voltage terminal VGH2, and the drain of the first transistor T1 is electrically connected to the first intermediate node P1;

[0509] The gate of the second transistor T2 is electrically connected to the input terminal I1, the source of the second transistor T2 is electrically connected to the first intermediate node P1, and the drain of the second transistor T2 is electrically connected to the control node QB1;

[0510] The third control circuit includes a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6;

[0511] The gate of the fourth transistor T4 is electrically connected to the first high voltage terminal VGH1, the source of the fourth transistor T4 is electrically connected to the first node QB, and the drain of the fourth transistor T4 is electrically connected to the second intermediate node P2;

[0512] The gate of the fifth transistor T5 is electrically connected to the first high voltage terminal VGH1, the source of the fifth transistor T5 is electrically connected to the second intermediate node P2, and the drain of the fifth transistor T5 is electrically connected to the reset control node SR;

[0513] The gate of the sixth transistor T6 is electrically connected to the reset control node SR, the source of the sixth transistor T6 is electrically connected to the second high voltage terminal VGH2, and the drain of the sixth transistor T6 is electrically connected to the second intermediate node P2;

[0514] The third control circuit includes a fourth transistor T4;

[0515] The gate of the fourth transistor T4 is electrically connected to the first clock signal terminal CK1, the source of the fourth transistor T4 is electrically connected to the first node QB, and the drain of the fourth transistor T4 is electrically connected to the reset control node SR;

[0516] The first control circuit includes a seventh transistor T7, an eighth transistor T8 and a ninth transistor T9;

[0517] The gate of the seventh transistor T7 is electrically connected to the control node QB1, the source of the seventh transistor T7 is electrically connected to the first clock signal terminal CK1, and the drain of the seventh transistor T7 is electrically connected to the third intermediate node P3;

[0518] The gate of the eighth transistor T8 is electrically connected to the control node QB1, the source of the eighth transistor T8 is electrically connected to the third intermediate node P3, and the drain of the eighth transistor T8 is electrically connected to the first node QB;

[0519] The gate of the ninth transistor T9 is electrically connected to the first node QB, the source of the ninth transistor T9 is electrically connected to the second high voltage terminal VGH2, and the second electrode of the ninth transistor is electrically connected to the third intermediate node P3;

[0520] The fourth control circuit includes a tenth transistor T10, an eleventh transistor T11 and a twelfth transistor T12;

[0521] The gate of the tenth transistor T10 is electrically connected to the second node Q1, the source of the tenth transistor T10 is electrically connected to the fourth intermediate node P4, and the drain of the tenth transistor T10 is electrically connected to the first node QB;

[0522] The gate of the eleventh transistor T11 is electrically connected to the second node Q1, the source of the eleventh transistor T11 is electrically connected to the first low voltage terminal VGL1, and the drain of the eleventh transistor T11 is electrically connected to the fourth intermediate node P4;

[0523] The gate of the twelfth transistor T12 is electrically connected to the first node QB, the source of the twelfth transistor T12 is electrically connected to the second high voltage terminal VGH2, and the drain of the twelfth transistor T12 is electrically connected to the fourth intermediate node P4;

[0524] The carry output circuit includes a carry output transistor TR1, the carry reset circuit includes a carry reset transistor TR2, the drive output circuit includes a drive output transistor TP1, and the drive reset circuit includes a drive reset transistor TP2;

[0525] The gate of the carry output transistor TR1 is electrically connected to the output control node Q, the source of the carry output transistor TR1 is electrically connected to the first high voltage terminal VGH1, and the drain of the carry output transistor TR1 is electrically connected to the carry signal output terminal CR;

[0526] The gate of the carry reset transistor TR2 is electrically connected to the reset control node SR, the source of the carry reset transistor TR2 is electrically connected to the carry signal output terminal CR, and the drain of the carry reset transistor TR2 is electrically connected to the first low voltage terminal VGL1;

[0527] The gate of the driving output transistor TP1 is electrically connected to the output control node Q, the source of the driving output transistor TP1 is electrically connected to the second high voltage terminal VGH2, and the second electrode of the driving output transistor TP1 is electrically connected to the light emitting control signal output terminal EM;

[0528] The gate of the driving reset transistor TP2 is electrically connected to the reset control node SR, the source of the driving reset transistor TP2 is electrically connected to the light emitting control signal output terminal EM, and the drain of the driving reset transistor TP2 is electrically connected to the second low voltage terminal VGL2;

[0529] The fifth control circuit includes a thirteenth transistor T13;

[0530] The gate of the thirteenth transistor T13 is electrically connected to the first high voltage terminal VGH1, the source of the thirteenth transistor T13 is electrically connected to the second node Q1, and the drain of the thirteenth transistor T13 is electrically connected to the output control node Q;

[0531] The input circuit includes a sixteenth transistor T16;

[0532] The gate of the sixteenth transistor T16 is electrically connected to the first clock signal terminal CK1, the source of the sixteenth transistor T16 is electrically connected to the input terminal I1, and the drain of the sixteenth transistor T16 is electrically connected to the second node Q1;

[0533] At least one embodiment of the driving circuit shown in FIG28 of the present disclosure may further include a second capacitor C2 and a third capacitor C3;

[0534] The first end of C2 is electrically connected to the output control node Q, and the second end of C2 is electrically connected to the carry signal output terminal CR;

[0535] A first end of C3 is electrically connected to the reset control node SR, and a second end of C3 is electrically connected to the first low voltage end VGL1.

[0536] In at least one embodiment shown in Figure 28, the first voltage terminal is the second high voltage terminal VGH2, the second voltage terminal is the first low voltage terminal VGL1, the fifth voltage terminal is the first low voltage terminal VGL1, the ninth voltage terminal is the first high voltage terminal VGH1, the first control terminal is the first high voltage terminal VGH1, the third voltage terminal is the second high voltage terminal VGH2, the fourth voltage terminal is the second high voltage terminal VGH2, the sixth voltage terminal is the first low voltage terminal VGL1, and the seventh voltage terminal is the second high voltage terminal VGH2.

[0537] In at least one embodiment shown in FIG. 28 , all transistors are n-type transistors, but the present invention is not limited thereto.

[0538] In at least one embodiment shown in FIG. 28 , the source of T1 may be replaced by being electrically connected to the first high voltage terminal VGH1, the source of T6 may be replaced by being electrically connected to the first high voltage terminal VGH1, the source of T9 may be replaced by being electrically connected to the first high voltage terminal VGH1, and the source of T12 may be replaced by being electrically connected to the first high voltage terminal VGH1.

[0539] In at least one embodiment of the driving circuit shown in FIG28 , the second control circuit includes a first transistor T1 , a second transistor T2 , and a third transistor T3 ;

[0540] When the potential of the first clock signal provided by CK1 jumps from a low level to a high level, the potential of QB1 becomes a high voltage due to the action of C1, T2 is turned on, and the second high voltage terminal VGH2 is connected to P1, preventing the potential of QB1 from being pulled low due to leakage. This ensures that T7 is turned on, so that the potential of QB is pulled up to a high voltage, so that CR and EM can correctly output low-voltage signals.

[0541] In at least one embodiment of the driving circuit shown in Figure 28, the third control circuit includes a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6; when the potential of SR is a high voltage, T6 is turned on, and P2 is connected to the second high voltage terminal VGH2 to prevent the potential of SR from becoming low due to leakage of the transistor.

[0542] In at least one embodiment of the driving circuit shown in FIG28 , the first control circuit includes a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9; when the potential of QB is a high voltage, T9 is turned on, and P3 is connected to the second high voltage terminal VGH2, so that the potential of QB does not become low due to leakage.

[0543] In at least one embodiment of the driving circuit shown in FIG28 , the fourth control circuit includes a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12; when the potential of QB is a high voltage, T12 is turned on to connect P4 to VGH2, thereby preventing the potential of QB from becoming low due to leakage of the transistor.

[0544] As shown in FIG29A , based on at least one embodiment of the driving circuit shown in FIG15 , the first energy tank circuit includes a first capacitor C1, the second control circuit includes a first transistor T1 and a second transistor T2, and the driving reset circuit includes a third transistor T3; a first end of the first capacitor C1 is electrically connected to the first clock signal terminal CK1, and a second end of the first capacitor C1 is electrically connected to the control node QB1;

[0545] The gate of the first transistor T1 is electrically connected to the control node QB1, the source of the first transistor T1 is electrically connected to the second high voltage terminal VGH2, and the drain of the first transistor T1 is electrically connected to the first intermediate node P1;

[0546] The gate of the second transistor T2 is electrically connected to the input terminal I1, the source of the second transistor T2 is electrically connected to the first intermediate node P1, and the drain of the second transistor T2 is electrically connected to the control node QB1;

[0547] The third control circuit includes a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6;

[0548] The gate of the fourth transistor T4 is electrically connected to the first high voltage terminal VGH1, the source of the fourth transistor T4 is electrically connected to the first node QB, and the drain of the fourth transistor T4 is electrically connected to the second intermediate node P2;

[0549] The gate of the fifth transistor T5 is electrically connected to the first high voltage terminal VGH1, the source of the fifth transistor T5 is electrically connected to the second intermediate node P2, and the drain of the fifth transistor T5 is electrically connected to the reset control node SR;

[0550] The gate of the sixth transistor T6 is electrically connected to the reset control node SR, the source of the sixth transistor T6 is electrically connected to the second high voltage terminal VGH2, and the drain of the sixth transistor T6 is electrically connected to the second intermediate node P2;

[0551] The third control circuit includes a fourth transistor T4;

[0552] The gate of the fourth transistor T4 is electrically connected to the first clock signal terminal CK1, the source of the fourth transistor T4 is electrically connected to the first node QB, and the drain of the fourth transistor T4 is electrically connected to the reset control node SR;

[0553] The first control circuit includes a seventh transistor T7, an eighth transistor T8 and a ninth transistor T9;

[0554] The gate of the seventh transistor T7 is electrically connected to the control node QB1, the source of the seventh transistor T7 is electrically connected to the first clock signal terminal CK1, and the drain of the seventh transistor T7 is electrically connected to the third intermediate node P3;

[0555] The gate of the eighth transistor T8 is electrically connected to the control node QB1, the source of the eighth transistor T8 is electrically connected to the third intermediate node P3, and the drain of the eighth transistor T8 is electrically connected to the first node QB;

[0556] The gate of the ninth transistor T9 is electrically connected to the first node QB, the source of the ninth transistor T9 is electrically connected to the second high voltage terminal VGH2, and the second electrode of the ninth transistor is electrically connected to the third intermediate node P3;

[0557] The fourth control circuit includes a tenth transistor T10, an eleventh transistor T11 and a twelfth transistor T12;

[0558] The gate of the tenth transistor T10 is electrically connected to the second node Q1, the source of the tenth transistor T10 is electrically connected to the fourth intermediate node P4, and the drain of the tenth transistor T10 is electrically connected to the first node QB;

[0559] The gate of the eleventh transistor T11 is electrically connected to the second node Q1, the source of the eleventh transistor T11 is electrically connected to the first low voltage terminal VGL1, and the drain of the eleventh transistor T11 is electrically connected to the fourth intermediate node P4;

[0560] The gate of the twelfth transistor T12 is electrically connected to the first node QB, the source of the twelfth transistor T12 is electrically connected to the second high voltage terminal VGH2, and the drain of the twelfth transistor T12 is electrically connected to the fourth intermediate node P4;

[0561] The driving output circuit includes a driving output transistor TP1;

[0562] The gate of the driving output transistor TP1 is electrically connected to the output control node Q, the source of the driving output transistor TP1 is electrically connected to the first high voltage terminal VGH1, and the second electrode of the driving output transistor TP1 is electrically connected to the light emitting control signal output terminal EM;

[0563] The driving reset circuit includes a first driving reset transistor TP21, a second driving reset transistor TP22 and a reset control transistor TP0;

[0564] The gate of the first driving reset transistor TP21 is electrically connected to the reset control node SR, the source of the first driving reset transistor TP21 is electrically connected to the light emitting control signal output terminal EM, and the drain of the first driving reset transistor TP21 is electrically connected to the output intermediate node P0;

[0565] The gate of the second driving reset transistor TP22 is electrically connected to the reset control node SR, the source of the second driving reset transistor TP22 is electrically connected to the output intermediate node P0, and the drain of the second driving reset transistor P22 is electrically connected to the first low voltage terminal VGL1;

[0566] The gate of the reset control transistor TP0 is electrically connected to the light emitting control signal output terminal EM, the source of the reset control transistor TP0 is electrically connected to the second high voltage terminal VGH2, and the drain of the reset control transistor TP0 is electrically connected to the output intermediate node P0;

[0567] The fifth control circuit includes a thirteenth transistor T13;

[0568] The gate of the thirteenth transistor T13 is electrically connected to the first high voltage terminal VGH1, the source of the thirteenth transistor T13 is electrically connected to the second node Q1, and the drain of the thirteenth transistor T13 is electrically connected to the output control node Q;

[0569] The input circuit includes a sixteenth transistor T16;

[0570] The gate of the sixteenth transistor T16 is electrically connected to the first clock signal terminal CK1, the source of the sixteenth transistor T16 is electrically connected to the input terminal I1, and the drain of the sixteenth transistor T16 is electrically connected to the second node Q1;

[0571] At least one embodiment of the driving circuit shown in FIG. 29A of the present disclosure may further include a second capacitor C2 and a third capacitor C3;

[0572] The first end of C2 is electrically connected to the output control node Q, and the second end of C2 is electrically connected to the carry signal output terminal CR;

[0573] A first end of C3 is electrically connected to the reset control node SR, and a second end of C3 is electrically connected to the first low voltage end VGL1.

[0574] In at least one embodiment shown in Figure 29A, the first voltage terminal is the second high voltage terminal VGH2, the second voltage terminal is the first low voltage terminal VGL1, the fifth voltage terminal is the first low voltage terminal VGL1, the ninth voltage terminal is the first high voltage terminal VGH1, the first control terminal is the first high voltage terminal VGH1, the third voltage terminal is the second high voltage terminal VGH2, the fourth voltage terminal is the second high voltage terminal VGH2, the sixth voltage terminal is the first low voltage terminal VGL1, and the seventh voltage terminal is the second high voltage terminal VGH2; the third high voltage terminal is the first high voltage terminal VGH1, the third low voltage terminal is the first low voltage terminal VGL1, and the eighth voltage terminal is the second high voltage terminal VGH2.

[0575] In at least one embodiment shown in FIG. 29A , the source of T1 may be replaced by being electrically connected to the first high voltage terminal VGH1, the source of T6 may be replaced by being electrically connected to the first high voltage terminal VGH1, the source of T9 may be replaced by being electrically connected to the first high voltage terminal VGH1, the source of T12 may be replaced by being electrically connected to the first high voltage terminal VGH1, and the source of TP0 may be replaced by being electrically connected to the first high voltage terminal VGH1.

[0576] In at least one embodiment of the driving circuit shown in FIG29A , the second control circuit includes a first transistor T1 , a second transistor T2 , and a third transistor T3 ;

[0577] When the potential of the first clock signal provided by CK1 jumps from a low level to a high level, the potential of QB1 becomes a high voltage due to the action of C1, T2 is turned on, and the second high voltage terminal VGH2 is connected to P1, preventing the potential of QB1 from being pulled low due to leakage. This ensures that T7 is turned on, so that the potential of QB is pulled up to a high voltage, so that CR and EM can correctly output low-voltage signals.

[0578] In at least one embodiment of the driving circuit shown in FIG29A , the third control circuit includes a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6; when the potential of SR is a high voltage, T6 is turned on, and P2 is connected to the second high voltage terminal VGH2 to prevent the potential of SR from becoming low due to leakage of the transistor.

[0579] In at least one embodiment of the driving circuit shown in FIG29A , the first control circuit includes a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9; when the potential of QB is a high voltage, T9 is turned on, and P3 is connected to the second high voltage terminal VGH2, so that the potential of QB does not become low due to leakage.

[0580] In at least one embodiment of the driving circuit shown in FIG29A , the fourth control circuit includes a tenth transistor T10, an eleventh transistor T11, and a twelfth transistor T12; when the potential of QB is a high voltage, T12 is turned on to connect P4 to VGH2, thereby preventing the potential of QB from becoming low due to leakage of the transistor.

[0581] The driving reset circuit includes a first driving reset transistor TP21, a second driving reset transistor TP22 and a reset control transistor TP0; when EM outputs a high voltage signal, TP0 is turned on to connect P0 with VGH2, preventing the potential of the light-emitting control signal output by EM from becoming low due to transistor leakage.

[0582] As shown in FIG29B , when at least one embodiment of the driving circuit shown in FIG29A of the present disclosure is in operation, a driving cycle may include an input phase S1, a first interval phase S01, a second interval phase S02, an output phase S2, an output reset phase S3, and an output cutoff phase S4, which are arranged in sequence;

[0583] In the input phase S1, CK1 provides a high voltage signal, I1 provides a low voltage signal, T16 is turned on, Q1 is connected to I1, the potential of Q1 is low, T13 is turned on, the potential of Q is low; the potential of QB1 becomes high due to the bootstrap pull-up of C1, T7 and T8 are turned on, QB is connected to CK1, the potential of QB is high; T4 and T5 are turned on, the potential of SR is high; TP21 and TP22 are turned on, and EM outputs a low voltage signal;

[0584] In the first interval phase S01, the potential of the first clock signal provided by CK1 changes from a high voltage to a low voltage. Due to the action of C1, the potential of QB1 jumps to a low voltage, T7 and T8 are turned off, and the potential of QB remains at a high voltage.

[0585] In the second interval phase S02, I1 provides a high voltage signal, T3 and T1 are turned on, the potential of QB1 is a low voltage, T7 and T8 are turned off, and the potential of QB is maintained at a high voltage;

[0586] In the first interval stage S01 and the second interval stage S02, the potential of QB is high voltage, T4 and T5 are turned on, the potential of SR is high voltage, TP21 and TP22 are turned on, and EM outputs a low voltage signal;

[0587] In the output phase S2, when CK1 provides a high voltage signal and I1 provides a high voltage signal, T16 is turned on, Q1 is connected to I1, and the potential of Q1 is high voltage; T10 and T11 are turned on, QB is connected to VGL1, and the potential of QB is low voltage; T13 is turned on, and the potential of Q is high voltage; TP1 is turned on, and EM outputs a high voltage signal; T3 and T1 are turned on, and the potential of QB1 is low voltage; T4 and T5 are turned on, SR is connected to QB, and the potential of SR is low voltage;

[0588] In the output reset phase S3, CK1 provides a high voltage signal, I1 provides a low voltage signal, T16 is turned on, Q1 is connected to I1, the potential of Q1 is low voltage, T13 is turned on, and the potential of Q is a low voltage signal;

[0589] In the output reset phase S3, when the first clock signal provided by CK1 jumps from a low voltage to a high voltage, the potential of QB1 is high, T7 and T8 are turned on, QB is connected to CK1, and the potential of QB is high; T4 and T5 are turned on, the potential of SR is high; TP21 and TP22 are turned on, and EM outputs a low voltage signal;

[0590] In the output cutoff stage S4, the potential of Q1 and the potential of Q are low voltage, the potential of QB and the potential of QB1 are high voltage, TP2 is open, and EM outputs a low voltage signal;

[0591] In the output cut-off stage S4, due to the action of C1, the potential of QB changes with the potential of the first clock signal provided by CK1. When the potential of QB1 and the potential of CK1 are high voltages, T7 and T8 are turned on, so that the potential of QB is high voltage; when the potential of QB1 is low voltage, T7 and T8 are turned off, and the potential of QB is maintained at a high voltage.

[0592] The difference between at least one embodiment of the driving circuit shown in FIG30 and at least one embodiment of the driving circuit shown in FIG25A is that: the drive circuit does not include a carry output circuit and a carry reset circuit; the second control circuit includes a second transistor T1;

[0593] The gate of the first transistor T1 is electrically connected to the input terminal I1, the source of the first transistor T1 is electrically connected to the low voltage terminal VGL, and the drain of the first transistor T1 is electrically connected to the control node QB1;

[0594] The source of the tenth transistor T10 is electrically connected to the low voltage terminal VGL, and the drain of the tenth transistor T10 is electrically connected to the reset control node SR;

[0595] The source of TP1 is electrically connected to the high voltage terminal VGH, and the drain of TP2 is electrically connected to the low voltage terminal VGL;

[0596] The gate of T13 is electrically connected to the high voltage terminal VGH;

[0597] The second end of C2 is electrically connected to EM, and the second end of C3 is electrically connected to the low voltage terminal VGL.

[0598] At least one embodiment of the driving circuit shown in FIG30 is provided with T4 during operation. When the potential of the first clock signal provided by CK1 changes from a high level to a low level, the presence of T4 prevents the potential of SR from decreasing due to leakage.

[0599] The difference between at least one embodiment of the driving circuit shown in FIG31 and at least one embodiment of the driving circuit shown in FIG30 is as follows:

[0600] The drain of T10 is electrically connected to QB.

[0601] At least one embodiment of the driving circuit shown in FIG31 is provided with T4 during operation. When the potential of the first clock signal provided by CK1 changes from a high level to a low level, the presence of T4 prevents the potential of SR from decreasing due to leakage.

[0602] At least one embodiment of the driving circuit shown in FIG32 and at least one embodiment of the driving circuit shown in FIG26 are as follows:

[0603] The gate of T4 and the gate of T5 are both electrically connected to CK1.

[0604] The difference between at least one embodiment of the driving circuit shown in FIG33 and at least one embodiment of the driving circuit shown in FIG26 is as follows:

[0605] The fifth control circuit includes a thirteenth transistor T13, a fourteenth transistor T14 and a fifteenth transistor T15;

[0606] The gate of the thirteenth transistor T13 is electrically connected to the first high voltage terminal VGH1, the source of the thirteenth transistor T13 is electrically connected to the second node Q1, and the drain of the thirteenth transistor T13 is electrically connected to the fifth intermediate node P5;

[0607] The gate of the fourteenth transistor T14 is electrically connected to the first high voltage terminal VGH1, the source of the fourteenth transistor T14 is electrically connected to the fifth intermediate node P5, and the drain of the fourteenth transistor T14 is electrically connected to the output control node Q;

[0608] A gate of the fifteenth transistor T15 is electrically connected to the output control node Q, a source of the fifteenth transistor T15 is electrically connected to the first high voltage terminal VGH1 , and a drain of the fifteenth transistor T15 is electrically connected to the fifth intermediate node P5 .

[0609] In at least one embodiment of the driving circuit shown in FIG. 33 , the ninth voltage terminal is the first high voltage terminal VGH1 , and the tenth voltage terminal is the first high voltage terminal VGH2 .

[0610] In at least one embodiment shown in FIG. 33 , the source of T1 may be replaced by being electrically connected to the first high voltage terminal VGH1 , the source of T6 may be replaced by being electrically connected to the first high voltage terminal VGH1 , and the source of T15 may be replaced by being electrically connected to the second high voltage terminal VGH2 .

[0611] In at least one embodiment of the driving circuit shown in FIG33 , the second control circuit includes a first transistor T1 , a second transistor T2 , and a third transistor T3 ;

[0612] When the potential of the first clock signal provided by CK1 jumps from a low level to a high level, the potential of QB1 becomes a high voltage due to the action of C1, T2 is turned on, and the second high voltage terminal VGH2 is connected to P1, preventing the potential of QB1 from being pulled low due to leakage. This ensures that T7 is turned on, so that the potential of QB is pulled up to a high voltage, so that CR and EM can correctly output low-voltage signals.

[0613] In at least one embodiment of the driving circuit shown in Figure 33, the third control circuit includes a fourth transistor T4, a fifth transistor T5 and a sixth transistor T6; when the potential of SR is a high voltage, T6 is turned on, and P2 is connected to the second high voltage terminal VGH2 to prevent the potential of SR from becoming low due to leakage of the transistor.

[0614] In at least one embodiment of the driving circuit shown in Figure 33, the fifth control circuit includes a thirteenth transistor T13, a fourteenth transistor T14 and a fifteenth transistor T15; when the potential of Q is a high voltage, T15 is turned on, and P5 is connected to the first high voltage terminal VGH1 to prevent the potential of Q from becoming low due to leakage.

[0615] The difference between at least one embodiment of the driving circuit shown in FIG34A and at least one embodiment of the driving circuit shown in FIG25A is as follows:

[0616] It also includes a bootstrap output circuit and an output energy storage circuit, but does not include the second capacitor C2; the bootstrap output circuit includes a bootstrap output transistor TD1 and a bootstrap reset transistor TD2, and the output energy storage circuit includes an output control capacitor C0;

[0617] The gate of the bootstrap output transistor TD1 is electrically connected to the output control node Q, the source of the bootstrap output transistor TD1 is electrically connected to the second clock signal terminal CK2, and the drain of the bootstrap output transistor TD is electrically connected to the bootstrap output terminal OD;

[0618] The gate of the bootstrap reset transistor TD2 is electrically connected to the reset control node SR, the source of the bootstrap output transistor TD2 is electrically connected to the bootstrap output terminal OD, and the drain of the bootstrap output transistor TD2 is electrically connected to the first low voltage terminal VGL1;

[0619] A first end of the output control capacitor C0 is electrically connected to the output control node Q, and a second end of the output control capacitor C0 is electrically connected to the bootstrap output terminal OD.

[0620] In at least one embodiment of the driving circuit shown in FIG. 34A , the output clock signal terminal is the second clock signal terminal CK2 , and the fourth low voltage terminal is the first low voltage terminal VGL1 .

[0621] As shown in FIG34B , when at least one embodiment of the driving circuit shown in FIG34 of the present disclosure is in operation, a driving cycle may include an input phase S1, a first interval phase S01, a second interval phase S02, an output phase S2, an output reset phase S3, and an output cutoff phase S4, which are arranged in sequence;

[0622] In the input phase S1, CK1 provides a high voltage signal, I1 provides a low voltage signal, T16 is turned on, Q1 is connected to I1, and the potential of Q1 is low voltage. T13 is turned on, and the potential of Q is low voltage. The potential of QB1 becomes high voltage due to the bootstrap pull-up of C1. T7 is turned on, QB is connected to CK1, and the potential of QB is high voltage. T4 is turned on, and the potential of SR is high voltage. TD2, TR2, and TP2 are all turned on, and OD, CR, and EM all output low voltage signals.

[0623] In the first interval phase S01, the potential of the first clock signal provided by CK1 changes from a high voltage to a low voltage. Due to the action of C1, the potential of QB1 jumps to a low voltage, T7 is turned off, and the potential of QB remains at a high voltage.

[0624] In the second interval phase S02, I1 provides a high voltage signal, T3 and T1 are turned on, the potential of QB1 is low, T7 is turned off, and the potential of QB is maintained at a high voltage. In the output phase S2, when CK1 provides a high voltage signal and I1 provides a high voltage signal, T16 is turned on, Q1 and I1 are connected, and the potential of Q1 is high. T10 is turned on, QB is connected to VGL1, and the potential of QB is low. T13 is turned on, and the potential of Q is high. TD1, TR1, and TP1 are turned on, and CR and EM both output high voltage signals. T3 and T1 are turned on, and the potential of QB1 is low.

[0625] In the output phase S2, when the potential of the second clock signal provided by CK2 is increased from a low voltage to a high voltage, the potential of the bootstrap signal output by OD is increased from a low voltage to a high voltage, and the potential of Q is bootstrapped by C0, which is conducive to the correct output of the light-emitting control signal by EM;

[0626] In the output reset phase S3, CK1 provides a high voltage signal, I1 provides a low voltage signal, T16 is turned on, Q1 is connected to I1, the potential of Q1 is low voltage, T13 is turned on, and the potential of Q is a low voltage signal;

[0627] In the output reset phase S3, when the first clock signal provided by CK1 jumps from a low voltage to a high voltage, the potential of QB1 is high, QB is connected to CK1, and the potential of QB is high; TD2, TR2, and TP2 are turned on, CR and EM both output low voltage signals; CK2 provides a low voltage signal, and OD outputs a low voltage signal;

[0628] In the output cutoff stage S4, the potential of Q1 and the potential of Q are low voltage, the potential of QB and the potential of QB1 are high voltage, TR2 and TP2 are open, CR and EM both output low voltage signals; PD2 is open, and OD outputs a low voltage signal;

[0629] In the output cut-off stage S4, due to the action of C1, the potential of QB changes with the potential of the first clock signal provided by CK1. When the potential of QB1 and the potential of CK1 are high voltages, T7 is turned on, so that the potential of QB is high voltage; when the potential of QB1 is low voltage, T7 is turned off, and the potential of QB is maintained at a high voltage.

[0630] In at least one embodiment of the driving circuit shown in FIG34A of the present disclosure, in the output stage, the potential of the output control node Q is bootstrapped and pulled up by the second clock signal provided by C0 and the second clock signal terminal CK2, so that the EM can correctly output the light-emitting control signal.

[0631] When at least one embodiment of the driving circuit shown in FIG. 34A of the present disclosure is in operation, the high voltage duration of the input signal provided by I1 may be greater than or equal to 1T, where 1T is the period of the first clock signal.

[0632] In at least one embodiment of the present disclosure, the driving module may include a multi-stage driving circuit;

[0633] The gate of the sixteenth transistor T16 in the odd-numbered stage driving circuit may be electrically connected to the first clock signal terminal CK1, and the source of the bootstrap output transistor TD1 in the odd-numbered stage driving circuit may be electrically connected to the second clock signal terminal CK2;

[0634] A gate of the sixteenth transistor T16 in the even-numbered stage driving circuit may be electrically connected to the second clock signal terminal CK2 , and a source of the bootstrap output transistor TD1 in the even-numbered stage driving circuit may be electrically connected to the first clock signal terminal CK2 .

[0635] In at least one embodiment of the present disclosure, when the driving module includes a first clock signal terminal CK1 and a second clock signal terminal CK2, and the gate of the sixteenth transistor T16 in the odd-level driving circuit can be electrically connected to the first clock signal terminal CK1, and the gate of the sixteenth transistor T16 in the even-level driving circuit can be electrically connected to the second clock signal terminal CK2, the driving circuit may not include a bootstrap output transistor and a bootstrap reset transistor, and the source of the carry output transistor in the odd-level driving circuit can be set to be electrically connected to the second clock signal terminal, and the source of the carry output transistor in the even-level driving circuit can be set to be electrically connected to the first clock signal terminal.

[0636] The difference between at least one embodiment of the driving circuit shown in FIG35 and at least one embodiment of the driving circuit shown in FIG34A is as follows:

[0637] The source of the bootstrap output transistor TD1 is electrically connected to the clock signal output terminal CKD.

[0638] In at least one embodiment of the driving circuit shown in FIG35 , the output clock signal terminal is a clock signal output terminal CKD, and CKD may be a clock signal terminal other than CK1 and CK2.

[0639] During operation of at least one embodiment of the driver circuit shown in FIG35 of the present disclosure, during the output phase, the potential of the clock signal provided by CKD jumps from a low voltage to a high voltage at least once, so that the potential of Q is automatically bootstrapped. The differences between at least one embodiment of the driver circuit shown in FIG36 and at least one embodiment of the driver circuit shown in FIG34 are as follows:

[0640] The source of TP1 is electrically connected to the first high voltage terminal VGH1;

[0641] The source of T1 is electrically connected to the first high voltage terminal VGH1 .

[0642] The driving method described in the embodiment of the present disclosure is applied to the above-mentioned driving circuit, and the driving method includes:

[0643] The first control circuit controls the potential of the first node according to the first clock signal under the control of the potential of the control node;

[0644] The second control circuit controls the connection or disconnection between the intermediate node and the first voltage terminal under the control of the potential of the control node, and controls the connection or disconnection between the first intermediate node and the control node under the control of the input signal;

[0645] The driving reset circuit resets the driving signal under the control of the potential of the reset control node.

[0646] The display device described in the embodiment of the present disclosure includes the above-mentioned driving circuit.

[0647] The above is a preferred embodiment of the present disclosure. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles described in the present disclosure. These improvements and modifications should also be regarded as the scope of protection of the present disclosure.

Claims

1. A driving circuit comprising a first control circuit, a first energy storage circuit, a second control circuit and a driving reset circuit; The first control circuit is electrically connected to the control node and the first node respectively, and is configured to control the potential of the first node under the control of the potential of the control node; A first end of the first energy storage circuit is electrically connected to the first clock signal end, a second end of the first energy storage circuit is electrically connected to the control node, and the first energy storage circuit is used to store electrical energy; The second control circuit is electrically connected to the control node, the first voltage terminal, the input terminal, and the first intermediate node, respectively, and is configured to control the connection or disconnection between the intermediate node and the first voltage terminal under the control of the potential of the control node, and control the connection or disconnection between the first intermediate node and the control node under the control of the input signal provided by the input terminal; The driving reset circuit is electrically connected to the reset control node and the driving signal output terminal respectively, and is used to reset the driving signal output by the driving signal output terminal under the potential control of the reset control node; The reset control node is electrically connected to the first node.

2. The driving circuit according to claim 1, wherein: The first control circuit is further electrically connected to the first clock signal terminal, and is configured to control the potential of the first node according to a first clock signal provided by the first clock signal terminal under the control of the potential of the control node; The second control circuit is further electrically connected to the second voltage terminal, and is configured to control the connection or disconnection between the first intermediate node and the second voltage terminal under the control of the input signal.

3. The driving circuit according to claim 1, wherein: Also comprising a third control circuit; The reset control node is electrically connected to the first node through the third control circuit; The control end of the third control circuit is electrically connected to the first clock signal end, and the third control circuit is used to control the connection or disconnection between the first node and the reset control node under the control of the first clock signal.

4. The driving circuit according to claim 1, wherein: Also comprising a third control circuit; The reset control node is electrically connected to the first node through the third control circuit; The third control circuit is electrically connected to the first control terminal, the first node, the reset control node, the second intermediate node and the third voltage terminal, respectively, and is used to control the connection or disconnection between the second intermediate node and the third voltage terminal under the control of the potential of the reset control node, and to control the connection or disconnection between the first node and the second intermediate node, and to control the connection or disconnection between the second intermediate node and the reset control node under the control of the first control signal provided by the first control terminal.

5. The driving circuit according to claim 4, wherein: The first control terminal is a first clock signal terminal, a first high voltage terminal or a second high voltage terminal; The third voltage terminal is the first high voltage terminal or the second high voltage terminal; The first voltage terminal is a first high voltage terminal or a second high voltage terminal.

6. The driving circuit according to any one of claims 1 to 5, wherein: The first control circuit is used to control the connection or disconnection between the first clock signal terminal and the first node under the control of the potential of the control node.

7. The driving circuit according to any one of claims 1 to 5, wherein: The first control circuit is also electrically connected to the third intermediate node and the fourth voltage terminal respectively, and is used to control the connection or disconnection between the third intermediate node and the fourth voltage terminal under the control of the potential of the first node, control the connection or disconnection between the first clock signal terminal and the third intermediate node under the control of the potential of the control node, and control the connection or disconnection between the third intermediate node and the first node under the control of the potential of the control node.

8. The driving circuit according to any one of claims 1 to 5, wherein: Also comprising a fourth control circuit; The fourth control circuit is electrically connected to the second node, the fifth voltage terminal and the first node respectively, and is used to control the connection or disconnection between the first node and the fifth voltage terminal under the control of the potential of the second node.

9. The driving circuit according to any one of claims 1 to 5, wherein: Also comprising a fourth control circuit; The fourth control circuit is electrically connected to the second node, the fifth voltage terminal and the reset control node respectively, and is used to control the connection or disconnection between the reset control node and the fifth voltage terminal under the control of the potential of the second node.

10. The driving circuit according to any one of claims 1 to 5, wherein: Also comprising a fourth control circuit; The fourth control circuit is electrically connected to the second node, the sixth voltage terminal, the fourth intermediate node, the seventh voltage terminal and the first node, respectively, and is used to control the connection or disconnection between the fourth intermediate node and the seventh voltage terminal under the control of the potential of the first node, and to control the connection or disconnection between the first node and the fourth intermediate node and the connection or disconnection between the fourth intermediate node and the sixth voltage terminal under the control of the potential of the second node.

11. The driving circuit according to claim 3 or 4, wherein: It also includes a carry output circuit, a carry reset circuit and a drive output circuit; The carry output circuit is electrically connected to the output control node, the first high voltage terminal and the carry signal output terminal respectively, and is used to control the connection or disconnection between the carry signal output terminal and the first high voltage terminal under the control of the potential of the output control node; The carry reset circuit is electrically connected to the reset control node, the first low voltage terminal and the carry signal output terminal respectively, and is used to control the connection or disconnection between the carry signal output terminal and the first low voltage terminal under the control of the potential of the reset control node; The drive output circuit is electrically connected to the output control node, the second high voltage terminal and the drive signal output terminal respectively, and is used to control the connection or disconnection between the drive signal output terminal and the second high voltage terminal under the control of the potential of the output control node; The driving reset circuit is also electrically connected to the second low voltage terminal, and is used to control the connection or disconnection between the driving signal output terminal and the second low voltage terminal under the control of the potential of the reset control node.

12. The driving circuit according to claim 11, wherein: The voltage value of the first high voltage signal provided by the first high voltage terminal is greater than the voltage value of the second high voltage signal provided by the second high voltage terminal, and the voltage value of the first low voltage signal provided by the first low voltage terminal is less than the voltage value of the second low voltage signal provided by the second low voltage terminal.

13. The driving circuit according to claim 1, wherein: Also included is a driver output circuit; The drive output circuit is electrically connected to the output control node, the third high voltage terminal and the drive signal output terminal respectively, and is used to control the connection or disconnection between the drive signal output terminal and the third high voltage terminal under the control of the potential of the output control node; The drive reset circuit is also electrically connected to the third low voltage terminal, the output intermediate node and the eighth voltage terminal, respectively, and is used to control the connection or disconnection between the output intermediate node and the eighth voltage terminal under the control of the drive signal provided by the drive signal output terminal, and to control the electrical connection between the drive signal output terminal and the output intermediate node, and to control the connection or disconnection between the output intermediate node and the third low voltage terminal under the control of the potential of the reset control node.

14. The driving circuit according to any one of claims 11 to 13, wherein: Also included is a fifth control circuit; The fifth control circuit is electrically connected to the second node, the ninth voltage terminal and the output control node respectively, and is used to control the connection or disconnection between the second node and the output control node under the control of a ninth voltage signal provided by the ninth voltage terminal.

15. The driving circuit according to any one of claims 11 to 13, wherein: Also included is a fifth control circuit; The fifth control circuit is electrically connected to the ninth voltage terminal, the tenth voltage terminal, the fifth intermediate node, the second node and the output control node, respectively, and is used to control the connection or disconnection between the fifth intermediate node and the tenth voltage terminal under the control of the potential of the output control node, and to control the connection or disconnection between the second node and the fifth intermediate node and the output control node under the control of the voltage signal provided by the ninth voltage terminal.

16. The driving circuit according to claim 11, wherein: It also includes a bootstrap output circuit and an output energy storage circuit; The bootstrap output circuit is electrically connected to the output control node, the output clock signal terminal, the bootstrap output terminal, the reset control node, and the fourth low voltage terminal, respectively, and is used to control the connection or disconnection between the bootstrap output terminal and the output clock signal terminal under the control of the potential of the output control node, and to control the connection or disconnection between the bootstrap output terminal and the fourth low voltage terminal under the control of the potential of the reset control node; A first terminal of the output energy storage circuit is electrically connected to the output control node, a second terminal of the output energy storage circuit is electrically connected to the bootstrap output terminal, and the output energy storage circuit is used to store electrical energy.

17. The driving circuit according to claim 16, wherein: The first high voltage terminal and the second high voltage terminal are the same voltage terminal.

18. The driving circuit according to any one of claims 1 to 5, wherein: Also includes input circuitry; The input circuit is electrically connected to the first clock signal terminal, the input terminal and the second node respectively, and is used to control the connection or disconnection between the input terminal and the second node under the control of the first clock signal provided by the first clock signal terminal.

19. The driving circuit according to claim 1, wherein: The first energy storage circuit includes a first capacitor, the second control circuit includes a first transistor and a second transistor, a first end of the first capacitor is electrically connected to the first clock signal end, and a second end of the first capacitor is electrically connected to the control node; The gate of the first transistor is electrically connected to the control node, the first electrode of the first transistor is electrically connected to the first voltage terminal, and the second electrode of the first transistor is electrically connected to the first intermediate node; A gate of the second transistor is electrically connected to the input terminal, a first electrode of the second transistor is electrically connected to the first intermediate node, and a second electrode of the second transistor is electrically connected to the control node.

20. The driving circuit according to claim 2, wherein: The second control circuit further includes a third transistor; A gate of the third transistor is electrically connected to the input terminal, a first electrode of the third transistor is electrically connected to the second voltage terminal, and a second electrode of the third transistor is electrically connected to the first intermediate node.

21. The driving circuit according to claim 3, wherein: The third control circuit includes a fourth transistor; a gate of the fourth transistor is electrically connected to the first clock signal terminal, a first electrode of the fourth transistor is electrically connected to the first node, and a second electrode of the fourth transistor is electrically connected to the reset control node.

22. The driving circuit according to claim 4, wherein: The third control circuit includes a fourth transistor, a fifth transistor, and a sixth transistor; the gate of the fourth transistor is electrically connected to the first control terminal, the first electrode of the fourth transistor is electrically connected to the first node, and the second electrode of the fourth transistor is electrically connected to the second intermediate node; The gate of the fifth transistor is electrically connected to the first control terminal, the first electrode of the fifth transistor is electrically connected to the second intermediate node, and the second electrode of the fifth transistor is electrically connected to the reset control node; A gate of the sixth transistor is electrically connected to the reset control node, a first electrode of the sixth transistor is electrically connected to the third voltage terminal, and a second electrode of the sixth transistor is electrically connected to the second intermediate node.

23. The driving circuit according to claim 6, wherein: The first control circuit includes a seventh transistor; A gate of the seventh transistor is electrically connected to the control node, a first electrode of the seventh transistor is electrically connected to the first clock signal terminal, and a second electrode of the seventh transistor is electrically connected to the first node.

24. The driving circuit according to claim 7, wherein: The first control circuit includes a seventh transistor, an eighth transistor and a ninth transistor; The gate of the seventh transistor is electrically connected to the control node, the first electrode of the seventh transistor is electrically connected to the first clock signal terminal, and the second electrode of the seventh transistor is electrically connected to the third intermediate node; The gate of the eighth transistor is electrically connected to the control node, the first electrode of the eighth transistor is electrically connected to the third intermediate node, and the second electrode of the eighth transistor is electrically connected to the first node; A gate of the ninth transistor is electrically connected to the first node, a first electrode of the ninth transistor is electrically connected to the fourth voltage terminal, and a second electrode of the ninth transistor is electrically connected to the third intermediate node.

25. The driving circuit according to claim 8, wherein: The fourth control circuit includes a tenth transistor; A gate of the tenth transistor is electrically connected to the second node, a first electrode of the tenth transistor is electrically connected to the fifth voltage terminal, and a second electrode of the tenth transistor is electrically connected to the first node.

26. The driving circuit according to claim 9, wherein: The fourth control circuit includes a tenth transistor; A gate of the tenth transistor is electrically connected to the second node, a first electrode of the tenth transistor is electrically connected to the fifth voltage terminal, and a second electrode of the tenth transistor is electrically connected to the reset control node.

27. The driving circuit according to claim 10, wherein: The fourth control circuit includes a tenth transistor, an eleventh transistor and a twelfth transistor; The gate of the tenth transistor is electrically connected to the second node, the first electrode of the tenth transistor is electrically connected to the fourth intermediate node, and the second electrode of the tenth transistor is electrically connected to the first node; The gate of the eleventh transistor is electrically connected to the second node, the first electrode of the eleventh transistor is electrically connected to the sixth voltage terminal, and the second electrode of the eleventh transistor is electrically connected to the fourth intermediate node; A gate of the twelfth transistor is electrically connected to the first node, a first electrode of the twelfth transistor is electrically connected to the seventh voltage terminal, and a second electrode of the twelfth transistor is electrically connected to the fourth intermediate node.

28. The driving circuit according to claim 11, wherein: The carry output circuit includes a carry output transistor, the carry reset circuit includes a carry reset transistor, the drive output circuit includes a drive output transistor, and the drive reset circuit includes a drive reset transistor; The gate of the carry output transistor is electrically connected to the output control node, the first electrode of the carry output transistor is electrically connected to the first high voltage terminal, and the second electrode of the carry output transistor is electrically connected to the carry signal output terminal; The gate of the carry reset transistor is electrically connected to the reset control node, the first electrode of the carry reset transistor is electrically connected to the carry signal output terminal, and the second electrode of the carry reset transistor is electrically connected to the first low voltage terminal; The gate of the driving output transistor is electrically connected to the output control node, the first electrode of the driving output transistor is electrically connected to the second high voltage terminal, and the second electrode of the driving output transistor is electrically connected to the driving signal output terminal; The gate of the driving reset transistor is electrically connected to the reset control node, the first electrode of the driving reset transistor is electrically connected to the driving signal output terminal, and the second electrode of the driving reset transistor is electrically connected to the second low voltage terminal.

29. The driving circuit according to claim 13, wherein: The driving output circuit includes a driving output transistor, and the driving reset circuit includes a first driving reset transistor, a second driving reset transistor and a reset control transistor; The gate of the driving output transistor is electrically connected to the output control node, the first electrode of the driving output transistor is electrically connected to the third high voltage terminal, and the second electrode of the driving output transistor is electrically connected to the driving signal output terminal; The gate of the first driving reset transistor is electrically connected to the reset control node, the first electrode of the first driving reset transistor is electrically connected to the driving signal output terminal, and the second electrode of the first driving reset transistor is electrically connected to the output intermediate node; The gate of the second driving reset transistor is electrically connected to the reset control node, the first electrode of the second driving reset transistor is electrically connected to the output intermediate node, and the second electrode of the first driving reset transistor is electrically connected to the third low voltage terminal; The gate of the reset control transistor is electrically connected to the drive signal output terminal, the first electrode of the reset control transistor is electrically connected to the eighth voltage terminal, and the second electrode of the reset control transistor is electrically connected to the output intermediate node.

30. The driving circuit according to claim 14, wherein: The fifth control circuit includes a thirteenth transistor; A gate of the thirteenth transistor is electrically connected to the ninth voltage terminal, a first electrode of the thirteenth transistor is electrically connected to the second node, and a second electrode of the thirteenth transistor is electrically connected to the output control node.

31. The driving circuit according to claim 15, wherein: The fifth control circuit includes a thirteenth transistor, a fourteenth transistor and a fifteenth transistor; The gate of the thirteenth transistor is electrically connected to the ninth voltage terminal, the first electrode of the thirteenth transistor is electrically connected to the second node, and the second electrode of the thirteenth transistor is electrically connected to the fifth intermediate node; The gate of the fourteenth transistor is electrically connected to the ninth voltage terminal, the first electrode of the fourteenth transistor is electrically connected to the fifth intermediate node, and the second electrode of the fourteenth transistor is electrically connected to the output control node; A gate of the fifteenth transistor is electrically connected to the output control node, a first electrode of the fifteenth transistor is electrically connected to the tenth voltage terminal, and a second electrode of the fifteenth transistor is electrically connected to the fifth intermediate node.

32. The driving circuit according to claim 16, wherein: The bootstrap output circuit includes a bootstrap output transistor and a bootstrap reset transistor, and the output energy storage circuit includes an output control capacitor; The gate of the bootstrap output transistor is electrically connected to the output control node, the first electrode of the bootstrap output transistor is electrically connected to the output clock signal terminal, and the second electrode of the bootstrap output transistor is electrically connected to the bootstrap output terminal; The gate of the bootstrap reset transistor is electrically connected to the reset control node, the first electrode of the bootstrap output transistor is electrically connected to the bootstrap output terminal, and the second electrode of the bootstrap output transistor is electrically connected to the fourth low voltage terminal; A first end of the output control capacitor is electrically connected to the output control node, a second end of the output control capacitor is electrically connected to the bootstrap output end, and the output energy storage circuit is used to store electrical energy.

33. A driving method, applied to the driving circuit according to any one of claims 1 to 32, the driving method comprising: The first control circuit controls the potential of the first node according to the first clock signal under the control of the potential of the control node; The second control circuit controls the connection or disconnection between the intermediate node and the first voltage terminal under the control of the potential of the control node, and controls the connection or disconnection between the first intermediate node and the control node under the control of the input signal; The driving reset circuit resets the driving signal under the control of the potential of the reset control node.

34. A display device comprising the driving circuit according to any one of claims 1 to 32.

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