Processor table lookup method, processor, device, and readable medium

Abstract

The present disclosure provides a processor table lookup method, a processor, a device, and a readable medium. The processor table lookup method is applied to any hardware thread in a processor, and the hardware thread comprises at least two processes. The processor table lookup method comprises: in each execution of a parallel table lookup, obtaining a target process corresponding to a table lookup key value, wherein the target process is an idle process among the at least two processes; calling the target process to perform a table lookup on the basis of the table lookup key value, and updating the state of the target process to waiting for a table lookup result to be returned; and upon detecting return information of a table lookup result, updating the state of the target process to an idle state and saving the table lookup result.

Description

Processor table lookup method, processor, device and readable medium

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent application claims priority to Chinese patent application 202410367200.4 filed with the State Intellectual Property Office of China on March 28, 2024, and the disclosure of this Chinese patent application is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to the field of processor technology, and in particular to a processor table lookup method, a processor, a device, and a readable medium. Background Art

[0004] A network processor is a programmable processor specialized for network packet processing and is used for a variety of communications tasks. Network processors contain multiple microengines (MEs). When an ME issues instructions to access a coprocessor or external memory, it spends a significant amount of time waiting for the results to be returned. To efficiently utilize this idle time, hardware multithreading is often employed.

[0005] The process of implementing table lookup functionality in a network processor through hardware multithreading technology is roughly as follows: the key values ​​required for table lookup are saved in the key-value memory (KEY_MEM) through microcode; a table lookup request is then issued to the table lookup engine through a specific table lookup command; each time a table lookup request is issued, the hardware automatically switches threads, and the switched thread waits for the table lookup result to return before continuing to execute subsequent instructions. Summary of the Invention

[0006] Embodiments of the present disclosure provide a processor table lookup method, a processor, a device, and a readable medium.

[0007] A first aspect of an embodiment of the present disclosure provides a table lookup method for a processor, which is applied to any hardware thread in the processor, and the hardware thread includes at least two processes. The method includes: each time a parallel table lookup is executed, obtaining a target process corresponding to a table lookup key value, wherein the target process is an idle process among the at least two processes; calling the target process to perform a table lookup according to the table lookup key value, and updating the state of the target process to a state of waiting for the table lookup result to be returned; and when the return information of the table lookup result is monitored, updating the state of the target process to an idle state and saving the table lookup result.

[0008] A second aspect of an embodiment of the present disclosure provides a processor, which includes at least two hardware threads, and any hardware thread of the at least two hardware threads includes at least two processes, wherein any hardware thread of the at least two processes is configured to: obtain a target process corresponding to a table lookup key value each time a parallel table lookup is executed, wherein the target process is an idle process among the at least two processes; call the target process to perform a table lookup according to the table lookup key value, and update the state of the target process to a waiting result return state; when monitoring the return information of the table lookup result, update the state of the target process to an idle state and save the table lookup result.

[0009] A third aspect of an embodiment of the present disclosure provides an electronic device, comprising: at least one processor; a memory on which at least one program is stored, wherein when the at least one program is executed by the at least one processor, the at least one processor implements the method described in the first aspect; and at least one I / O interface connected between the at least one processor and the memory, and configured to implement information interaction between the at least one processor and the memory.

[0010] A fourth aspect of the embodiments of the present disclosure provides a computer-readable medium having a computer program stored thereon, which implements the method described in the first aspect when the program is executed by a processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] FIG1 is a schematic diagram of an application environment of a table lookup method for a processor provided by an embodiment of the present disclosure;

[0012] FIG2 is a schematic diagram of an application environment of a table lookup method for a processor provided by an embodiment of the present disclosure;

[0013] FIG3 is a schematic diagram of a thread state machine provided in an embodiment of the present disclosure;

[0014] FIG4 is a flowchart of a table lookup method of a processor provided by an embodiment of the present disclosure;

[0015] FIG5 is a schematic diagram of a hardware thread parallel table lookup process provided in an embodiment of the present disclosure;

[0016] FIG6 is a schematic diagram of another process of hardware thread parallel table lookup provided in an embodiment of the present disclosure;

[0017] FIG7 is a schematic diagram comparing the execution effects of a parallel table lookup and a non-parallel table lookup provided in an embodiment of the present disclosure;

[0018] FIG8 is a schematic structural diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] The following describes the specific embodiments of the present disclosure in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure and are not intended to limit the present disclosure.

[0020] As used in this disclosure, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0021] The terms used in the present disclosure are only used to describe specific embodiments and are not intended to limit the present disclosure.As used in the present disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0022] When the terms “comprising” and / or “made of” are used in the present disclosure, it specifies the existence of the stated features, integers, steps, operations, elements and / or components, but does not preclude the existence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0023] Unless otherwise defined, all terms (including technical and scientific terms) used in this disclosure have the same meanings as those commonly understood by those skilled in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning unless expressly defined in this disclosure.

[0024] In the process of implementing the present disclosure, the inventors discovered that in the hardware multi-threading technology of the network processor, the thread will be switched after the operation of searching the external memory is triggered, and the thread will be switched back after the search result is returned, and subsequent instructions will continue to be executed through the thread, thereby shielding the table access delay through a large number of parallel thread switches.

[0025] For a single thread, instructions are executed sequentially and table lookup requests are issued serially. After issuing a table lookup request, you must wait for the table lookup result to be returned before issuing the next table lookup request.

[0026] Because each table lookup triggers a thread switch, frequent thread switching can lead to performance loss when there are numerous table lookup requests. Furthermore, if the latency of a single table lookup is too large, exceeding the range that can be masked by other threads, this can lead to a lack of available threads, causing a pipeline stall. For a short period of time, no instructions can be processed in the pipeline, resulting in performance degradation.

[0027] Based on this, an embodiment of the present disclosure provides a table lookup method for a processor. The application environment of the table lookup method for a processor is shown in Figures 1 and 2. When executing a table lookup instruction, a network processor with a hardware multi-threaded structure accesses external memory through a table lookup engine. The micro-engine (ME) of the network processor includes multiple hardware threads, represented as hardware threads 1 to N in Figure 1 and threads 0 to N in Figure 2. Each of the multiple hardware threads includes a table lookup key-value memory, a table lookup result memory, a table lookup process status register, and a thread state machine. The multiple hardware threads share a core pipeline, a thread controller, and a table lookup engine.

[0028] The core pipeline is used to parse and execute instructions, and write data into the table lookup key-value memory according to the instructions, read data from the table lookup result memory, or operate the table lookup process status register.

[0029] The lookup key value memory is used to store the spliced ​​lookup key values.

[0030] The table lookup result memory is used to store the table lookup results returned by the table lookup engine.

[0031] The table lookup process status register is used to store a flag, which is used to indicate whether the table lookup result of the process corresponding to the parallel table lookup is returned.

[0032] The thread state machine is used to record the current state of the hardware thread. The thread state machine is controlled by microcode execution and table lookup return status.

[0033] The thread controller is used to control hardware thread switching and authorization according to the thread state machine.

[0034] The table lookup engine is used to access external memory.

[0035] An embodiment of the present disclosure provides a table lookup method for a processor. The method can be applied to any hardware thread in the processor. The hardware thread includes at least two processes. One of the processes is called when executing a table lookup instruction, and the other process is called when executing another table lookup instruction. Parallel table lookup is achieved through multiple processes.

[0036] In the embodiment of the present disclosure, a thread state machine of a hardware thread is defined. FIG3 is a schematic diagram of the thread state machine. The thread state machine of the hardware thread is initially in an idle (IDLE) state and switches to a ready (RDY) state after receiving instruction authorization.

[0037] The disclosed embodiment also defines a table lookup result check instruction, namely the CHKRSP instruction, which is a pre-defined special instruction used to check the table lookup results of the parallel table lookup and control the hardware thread switching. The instruction includes a keyword, represented as PROCESS_ID_MASK, which is used to represent the identifier of the specified target process. These specified target processes are processes that need to pay attention to whether the table lookup results are returned.

[0038] In the RDY state, the hardware thread fetches instructions through the kernel pipeline for data processing. If a parallel table lookup instruction is executed, the hardware thread does not switch and remains in the RDY state. If a CHKRSP instruction is executed, and the table lookup result for the designated target process corresponding to the CHKRSP instruction has been returned, the hardware thread does not switch and remains in the RDY state. If a CHKRSP instruction is executed, and the table lookup result for the designated target process corresponding to the CHKRSP instruction has not been fully returned, the hardware thread switches to the WAIT state, waiting for the result of each designated target process to be returned before being triggered by the instruction to enter the RDY state.

[0039] In the WAIT state, if the table lookup result is a table lookup failure, the state is switched to the IDLE state and the message processing is completed.

[0040] It should be noted that the thread state machine for controlling hardware threads may have many other variations, but at least includes the above three states.

[0041] FIG4 is a flowchart of a table lookup method for a processor provided by an embodiment of the present disclosure. The table lookup method for a processor is applied to any hardware thread and mainly includes the following steps 401 and 402 .

[0042] In step 401, each time a parallel table lookup is performed, a target process corresponding to the table lookup key value is obtained, wherein the target process is an idle process among the at least two processes included in any hardware thread; the target process is called to perform a table lookup according to the table lookup key value, and the state of the target process is updated to a state of waiting for the table lookup result to be returned.

[0043] In some embodiments, the table lookup method further includes: when the hardware thread is in an idle state, converting the hardware thread from the idle state to the ready state through instruction authorization, and executing a parallel table lookup instruction to start the parallel table lookup.

[0044] In an exemplary embodiment, a thread controller grants an instruction to an idle hardware thread, causing the hardware thread to transition from the idle state to the ready state. When executing a parallel table lookup instruction, the core pipeline initiates a parallel table lookup based on the instruction and saves the concatenated table lookup key value to a table lookup key value memory.

[0045] In an exemplary embodiment, the parallel table lookup instruction may be predefined, and the parallel table lookup instruction may carry an identifier of a specified process and / or carry tag information for indicating a parallel table lookup.

[0046] When the parallel table lookup instruction carries the identifier of a designated process, the kernel pipeline can verify whether the designated process is in an idle state through the table lookup process status register of the hardware thread. If it is in an idle state, the kernel pipeline provides the table lookup key value to the hardware thread while also carrying the identifier of the process, so that the hardware thread performs a table lookup through the process. If it is not in an idle state (i.e., waiting for a result to be returned), the kernel pipeline can prompt the hardware thread to re-designate the process.

[0047] When the parallel table lookup instruction carries tag information for indicating a parallel table lookup but does not carry the identifier of a specified process, the kernel pipeline checks the table lookup process status register of the hardware thread and selects a process in an idle state based on the table lookup process status register; while providing the table lookup key value to the hardware thread, the kernel pipeline carries the identifier of the process so that the hardware thread performs a table lookup through the process.

[0048] In an exemplary embodiment, a dedicated thread switching instruction is predefined, defined as SRH_SWITCH, and is controlled by a microcode writer. The thread switching instruction forces the current hardware thread to be suspended and controls other hardware threads to switch from the IDLE state to the RDY state; the microcode writer controls by adding a flag bit in the thread switching instruction to indicate whether the table lookup instruction switches the hardware thread. When the flag bit indicates not to switch the hardware thread, each time the hardware thread executes the table lookup instruction, a table lookup is performed through the corresponding process, and the hardware thread is not switched after the table lookup instruction is issued. After all the table lookup instructions are completed, the hardware thread is switched by executing a separate hardware thread switching instruction, and after all the table lookup results of the hardware thread are returned, the instruction execution continues without switching the hardware thread.

[0049] In step 402, when the return information of the table lookup result is monitored, the state of the target process is updated to the idle state and the table lookup result is saved.

[0050] In some embodiments, the table lookup method also includes: obtaining a table lookup result check instruction by a hardware thread, the table lookup result check instruction carries an identifier of a specified target process, obtaining the status of the target process corresponding to the identifier of the specified target process, and judging whether to switch the hardware thread based on the status of the target process corresponding to the identifier of the specified target process.

[0051] In an exemplary embodiment, obtaining the status of the target process corresponding to the identifier of the specified target process includes: obtaining the status of the target process corresponding to the identifier of the specified target process from the table lookup process status register of the hardware thread, and the table lookup process status register stores a flag indicating whether the table lookup result corresponding to the process identifier is returned.

[0052] In some embodiments, whether to switch the hardware thread is determined based on the state of the target process corresponding to the identifier of the specified target process, including: when the state of at least one of the specified target processes is a waiting result return state, switching the hardware thread to a waiting state to switch other hardware threads; when the state of each of the specified target processes is an idle state, the hardware thread continues to execute the next instruction.

[0053] It should be noted that when the state of at least one specified target process is the waiting result return state, it indicates that the hardware thread has not yet returned the table lookup result, and the hardware thread is switched from the RDY state to the WAIT state so that the kernel pipeline authorizes other hardware threads in the RDY state to continue executing instructions, avoiding wasting time waiting for the result to be returned, thereby improving processor efficiency.

[0054] When the status of each designated target process is idle, it indicates that the hardware thread currently has an idle process that can be used to execute a new table lookup instruction, and there is no need to perform hardware thread switching to avoid performance degradation caused by hardware thread switching.

[0055] In some embodiments, calling the target process to perform a table lookup based on the table lookup key value includes: generating a table lookup request by a hardware thread, the table lookup request including the table lookup key value and an identifier of the target process; and sending the table lookup request to a table lookup engine through the target process.

[0056] In some embodiments, the hardware thread updates the state of the target process to an idle state when monitoring the return information of the table lookup result, including: when the hardware thread monitors the return information of the table lookup result, the state of the target process is updated to an idle state according to the identifier of the target process included in the return information of the table lookup result.

[0057] It should be noted that by carrying the identifier of the target process in the table lookup request, when the table lookup engine obtains the table lookup result, the table lookup result can be matched with the identifier of the target process, so that the hardware thread can modify the table lookup process status register according to the identifier of the target process corresponding to the table lookup result, and save the table lookup result to the correct storage location.

[0058] In some embodiments, saving the table lookup result includes: obtaining an identifier of the target process from the return information of the table lookup result, obtaining a table lookup key value according to the identifier of the target process, and saving the table lookup result according to a storage location corresponding to the table lookup key value.

[0059] In an exemplary embodiment, an offset corresponding to a lookup key value is pre-configured. When a hardware thread obtains a lookup result corresponding to a lookup key value, a storage location in a lookup result memory is determined based on the offset corresponding to the lookup key value, and the lookup result is saved to the storage location. The offset corresponding to the lookup key value is an offset of a designated storage location in the lookup result memory corresponding to the lookup key value. The offset is superimposed on the designated storage location in the lookup result memory to obtain the storage location corresponding to the lookup result of the lookup key value.

[0060] In some embodiments, after saving the table lookup result, the table lookup method further includes: updating the state of the target process to an idle state.

[0061] It should be noted that the status of the process in the table lookup process status register includes an idle state and a waiting result return state, wherein the idle state indicates that the table lookup result has been returned.

[0062] In one embodiment, the process of parallel table lookup in a single hardware thread is illustrated with reference to FIG5 and FIG6 , which mainly includes the following steps 1 to 6.

[0063] In step 1, the network processor loads the message into the core pipeline and triggers the hardware thread to execute the microcode instruction through the message to authorize the hardware thread to perform the instruction.

[0064] In step 2, the hardware thread obtains the parallel table lookup instruction through the kernel pipeline, obtains the spliced ​​table lookup key value from the table lookup key value memory, clears the table lookup process status register corresponding to the process through the identifier (PROCESS_ID number) of the process specified in the parallel table lookup instruction, and calls the process to issue a table lookup instruction to the table lookup engine based on the table lookup key value without switching the hardware thread; the table lookup process status register is used to store information indicating whether the table lookup result is returned.

[0065] In order to avoid reusing the same process when initiating parallel table lookups multiple times, it is necessary to verify the identifier of the process that initiates the table lookup, that is, to check whether the table lookup process status register of the process is in the waiting result return state. If it is in the waiting result return state, the process is refused to be used and a prompt is given. If it is in the return state, the process is continued to be used for table lookup.

[0066] In step 3, the hardware thread continues to execute instructions. It can execute ordinary instructions other than table lookup instructions, or it can continue to execute parallel table lookup instructions, and pre-configure the storage location corresponding to each table lookup key value to save the table lookup result returned by the process corresponding to the table lookup key value to avoid the table lookup results from overwriting each other.

[0067] In step 4, the hardware thread executes the CHKRSP instruction to determine whether to switch the hardware thread.

[0068] The hardware thread determines whether to switch the hardware thread through the decoding logic of the core pipeline based on the identifier of the specified process carried in the PROCESS_ID_MASK keyword in the CHKRSP instruction and the table lookup process status register of the specified process; if the table lookup process status register indicates that the table lookup result of the specified process has not been returned, it is necessary to switch the hardware thread and switch the hardware thread to the WAIT state to wait for the table lookup result to be returned; if the table lookup process status register indicates that the table lookup result of the specified process has been returned, the hardware thread remains in the RDY state to continue executing the next instruction.

[0069] In step 5, when the hardware thread detects that the table lookup result is returned, it determines the offset based on the table lookup key value corresponding to the table lookup result, writes the table lookup result to the corresponding position of the table lookup result memory based on the offset, waits for the kernel pipeline to access it, and simultaneously completes the update operation of the table lookup process status register of the corresponding process to indicate that the table lookup result has been returned.

[0070] If the hardware thread is in the WAIT state and the table lookup results of all processes in the process specified in the CHKRSP instruction are returned, it is ready to execute the next instruction and wait for the hardware thread to be authorized by the instruction to enter the RDY state to continue execution; otherwise, it continues to wait for the table lookup result to return.

[0071] The actual execution order of steps 4 and 5 is determined by the table lookup delay.

[0072] In step 6, the core pipeline reads the table lookup result from the table lookup result memory and continues processing.

[0073] The table lookup method for a processor provided by the embodiments of the present disclosure sets multiple processes in a hardware thread. Multiple table lookup tasks can be executed in parallel through the multiple processes. One process is used to execute a table lookup task. When the table lookup task of the process is not completed, another process is started to execute the next table lookup task. There is no need to switch hardware threads. In this way, within one hardware thread, multiple table lookup instructions can be processed in the time taken for a single lookup instruction, thereby improving the execution efficiency of the processor pipeline, expanding the processing resources for table lookup instructions, improving processor performance, and avoiding performance losses caused by frequent switching of hardware threads.

[0074] Figure 7 shows a comparison of the execution performance of parallel and non-parallel table lookups. The non-parallel table lookup waits for the lookup result to return starting at cycle 2 and cannot process instructions before cycle N. The parallel table lookup continues executing instructions after cycle 2. If the result of table lookup 2 is returned before cycle N, the behavior of table lookup 2 can be completely overwritten. Table lookup latency is typically much greater than the processing latency of non-table lookup instructions. The return time of multiple parallel table lookups can be approximated as the longest table lookup latency. This shows that parallel table lookups significantly improve performance.

[0075] In the processor table lookup method provided by the embodiment of the present disclosure, the control of hardware thread switching can be achieved through the defined CHKRSP instruction, which is beneficial for microcode personnel to fully utilize network processor resources, reasonably encode, and improve network processor performance by optimizing encoding.

[0076] The steps of the various methods above are divided only for clarity of description. During implementation, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this disclosure. Adding insignificant modifications or introducing insignificant designs to the algorithm or process without changing the core design of the algorithm and process are all within the scope of protection of this disclosure.

[0077] A processor is provided in an embodiment of the present disclosure, wherein the processor includes at least two hardware threads, and each hardware thread includes at least two processes. The specific implementation of the processor can be found in the relevant description of the method embodiment, which will not be repeated here.

[0078] Any hardware thread is used to obtain the target process corresponding to the table lookup key value each time a parallel table lookup is executed; wherein the target process is an idle process among at least two processes; the target process is called to perform a table lookup according to the table lookup key value, and the state of the target process is updated to a waiting result return state; when the return information of the table lookup result is monitored, the state of the target process is updated to an idle state and the table lookup result is saved.

[0079] The functions or modules included in the apparatus provided in the embodiments of the present disclosure can be used to execute the method described in the method embodiments. The specific implementation and technical effects thereof can be referred to the description of the above method embodiments, and will not be repeated here for the sake of brevity.

[0080] It should be noted that all modules involved in this embodiment are logical modules. In actual applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, to highlight the innovations of this disclosure, this embodiment does not include units that are not closely related to solving the technical problems proposed by this disclosure. However, this does not mean that other units do not exist in this embodiment.

[0081] 8 , an embodiment of the present disclosure provides an electronic device, comprising: at least one processor 801; a memory 802 on which at least one program is stored, and when the at least one program is executed by the at least one processor, the at least one processor implements the above method; and at least one I / O interface 803, connected between the processor and the memory, and configured to implement information interaction between the processor and the memory.

[0082] The processor 801 is a device with data processing capabilities, including but not limited to a central processing unit (CPU); the memory 802 is a device with data storage capabilities, including but not limited to random access memory (RAM, more specifically SDRAM, DDR, etc.), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), and flash memory (FLASH); the I / O interface (read-write interface) 803 is connected between the processor 801 and the memory 802, and can realize information exchange between the processor 801 and the memory 802, including but not limited to a data bus (Bus), etc.

[0083] In some embodiments, the processor 801 , the memory 802 , and the I / O interface 803 are connected to each other via a bus, and further connected to other components of the computing device.

[0084] This embodiment further provides a computer-readable medium on which a computer program is stored. When the program is executed by a processor, the method provided in this embodiment is implemented. To avoid repeated description, the specific steps of the method are not repeated here.

[0085] It will be appreciated by those skilled in the art that all or some of the steps, systems, and functional modules / units in the methods applied for above may be implemented as software, firmware, hardware, and appropriate combinations thereof. In hardware implementations, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed by several physical components in cooperation. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software may be distributed on a computer-readable medium, which may include a computer storage medium (or non-transitory medium) and a communication medium (or temporary medium). As is well known to those skilled in the art, the term computer storage medium includes volatile and non-volatile, removable, and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store the desired information and can be accessed by a computer. In addition, it is well known to those skilled in the art that communication media typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0086] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0087] Those skilled in the art will understand that although some embodiments described herein include certain features included in other embodiments but not other features, the combination of features from different embodiments is meant to be within the scope of the present embodiment and to form different embodiments.

[0088] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A table lookup method for a processor, applied to any hardware thread in the processor, wherein the hardware thread includes at least two processes, the method comprising: In each case of executing a parallel table lookup, obtaining a target process corresponding to the table lookup key value, wherein the target process is an idle process among the at least two processes; Calling the target process to perform a table lookup according to the table lookup key value, and updating the state of the target process to a state of waiting for a table lookup result to be returned; and When the return information of the table lookup result is monitored, the state of the target process is updated to the idle state and the table lookup result is saved.

2. The method according to claim 1, further comprising: When the hardware thread is in an idle state, the hardware thread is converted from the idle state to the ready state through instruction authorization, and a parallel table lookup instruction is executed to start the parallel table lookup.

3. The method according to claim 1, further comprising: Obtain an instruction for checking a table lookup result, wherein the instruction for checking a table lookup result carries an identifier of a specified target process, obtain the state of the target process corresponding to the identifier of the specified target process, and determine whether to switch the hardware thread based on the state of the target process corresponding to the identifier of the specified target process.

4. The method according to claim 3, wherein: Determining whether to switch the hardware thread according to the state of the target process corresponding to the identifier of the designated target process includes: When at least one of the designated target processes is in a waiting state for a result to be returned, switching the hardware thread to a waiting state to switch other hardware threads; When the state of each of the designated target processes is an idle state, the hardware thread continues to execute the next instruction.

5. The method according to claim 1, wherein Calling the target process to perform a table lookup according to the table lookup key value includes: generating a table lookup request, wherein the table lookup request includes the table lookup key value and an identifier of the target process; and The table lookup request is sent to a table lookup engine through the target process.

6. The method according to claim 5, wherein: When the return information of the table lookup result is monitored, the state of the target process is updated to an idle state, including: When the return information of the table lookup result is monitored, the state of the target process is updated to an idle state according to the identifier of the target process included in the return information of the table lookup result.

7. The method according to claim 5, wherein: Saving the table lookup result includes: The identifier of the target process is obtained from the return information of the table lookup result, the table lookup key value is obtained according to the identifier of the target process, and the table lookup result is saved according to the storage location corresponding to the table lookup key value.

8. The method according to claim 1, wherein After saving the table lookup result, the method further includes: The state of the target process is updated to the idle state.

9. A processor comprising at least two hardware threads, wherein any one of the at least two hardware threads comprises at least two processes. in, Any hardware thread in the at least two processes is configured to: obtain a target process corresponding to a table lookup key value each time a parallel table lookup is executed, wherein the target process is an idle process among the at least two processes; call the target process to perform a table lookup according to the table lookup key value, and update the state of the target process to a waiting result return state; and when the return information of the table lookup result is monitored, update the state of the target process to the idle state and save the table lookup result.

10. An electronic device comprising: at least one processor; a memory having at least one program stored thereon, wherein when the at least one program is executed by the at least one processor, the at least one processor implements the method according to any one of claims 1 to 8; as well as At least one I / O interface is connected between the at least one processor and the memory and is configured to implement information interaction between the at least one processor and the memory.

11. A computer-readable medium having a computer program stored thereon, wherein when the program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

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