Solid-state imaging element and electronic device

Abstract

The present disclosure relates to a solid-state imaging element and an electronic device that enable further improvement of image quality. The solid-state imaging element is provided with a pixel having: a first capacitor that holds a voltage of a pixel signal of a reset level output from a pixel circuit; a second capacitor that holds a voltage of a pixel signal of a pixel signal level output from the pixel circuit; and a third capacitor one end of which is connected to a connection point where one end of the first capacitor and one end of the second capacitor are connected, and the other end of which is connected to a signal line that supplies a ramp signal, the third capacitor constituting a source follower circuit together with the amplification gate of the pixel circuit. The first capacitor, the second capacitor, and the third capacitor are disposed in the same wiring layer. The present technology can be applied to, for example, a global shutter-type solid-state imaging element using the Voltage-Domain method.

Description

Solid-state imaging device and electronic device

[0001] The present disclosure relates to a solid-state imaging device and an electronic device, and more particularly to a solid-state imaging device and an electronic device that are capable of further improving image quality.

[0002] In recent years, there has been a demand for miniaturization of pixel size in global shutter CMOS (Complementary Metal Oxide Semiconductor) image sensors, which do not cause focal plane distortion during image capture, as the number of pixels increases.

[0003] The voltage-domain method has been proposed as one method for achieving simultaneous charge accumulation in global shutter CMOS image sensors. For example, unlike ordinary CMOS image sensors, a voltage-domain CMOS image sensor has a photodiode and a sample-and-hold circuit in each pixel, and requires the sample-and-hold circuit to have a metal-insulator-metal (MIM) structure to hold the voltage.

[0004] For example, Patent Document 1 discloses an image sensor having an MIM structure for sampling a P-phase signal and an MIM structure for sampling a D-phase signal.

[0005] Japanese Patent Application Laid-Open No. 2022-45912

[0006] Meanwhile, in voltage-domain CMOS image sensors, improvements in image quality are being considered by adopting a method that uses a capacitor in the first-stage source follower, and a new layout that is more efficient, including the capacitor, is required.

[0007] The present disclosure has been made in view of such circumstances, and aims to make it possible to further improve image quality.

[0008] A solid-state imaging device according to one aspect of the present disclosure includes a pixel having a first capacitor that holds the voltage of a pixel signal at a reset level output from a pixel circuit, a second capacitor that holds the voltage of a pixel signal at a pixel signal level output from the pixel circuit, and a third capacitor that has one end connected to a connection point where one end of the first capacitor and one end of the second capacitor are connected and the other end connected to a signal line that supplies a ramp signal, and that forms a source follower circuit together with an amplification gate of the pixel circuit, wherein the first capacitor, the second capacitor, and the third capacitor are arranged in the same wiring layer.

[0009] An electronic device according to one aspect of the present disclosure includes a first capacitor that holds the voltage of a pixel signal at a reset level output from a pixel circuit, a second capacitor that holds the voltage of a pixel signal at a pixel signal level output from the pixel circuit, and a third capacitor that has one end connected to a connection point where one end of the first capacitor and one end of the second capacitor are connected and the other end connected to a signal line that supplies a ramp signal, and that forms a source follower circuit together with an amplification gate of the pixel circuit, and includes a solid-state imaging element in which the first capacitor, the second capacitor, and the third capacitor are arranged in the same wiring layer.

[0010] In one aspect of the present disclosure, a first capacitor holds the voltage of a pixel signal of a reset level output from a pixel circuit, and a second capacitor holds the voltage of a pixel signal of a pixel signal level output from the pixel circuit, and a third capacitor has one end connected to a connection point where one end of the first capacitor and one end of the second capacitor are connected, and the other end connected to a signal line that supplies a ramp signal, and together with an amplification gate of the pixel circuit, a source follower circuit is configured, and the first capacitor, the second capacitor, and the third capacitor are arranged in the same wiring layer.

[0011] 8 is a block diagram showing a configuration example of an embodiment of an imaging device to which the present technology is applied. FIG. 1 is a circuit diagram showing a first configuration example of a pixel. FIG. 2 is a circuit diagram showing a configuration example of a four-pixel sharing structure of the pixel of FIG. 2. FIG. 3 is a diagram showing an example of a planar layout of three capacitors provided in the pixel. FIG. 4 is a diagram showing an example of a cross-sectional structure of three capacitors provided in the pixel. FIG. 5 is a circuit diagram showing a second configuration example of a pixel. FIG. 6 is a diagram showing an example of a planar layout of capacitors. FIG. 7 is a circuit diagram showing a third configuration example of a pixel. FIG. 8 is a circuit diagram showing a configuration example of a four-pixel sharing structure of the pixel of FIG. 9. FIG. 9 is a diagram showing an example of a planar layout of capacitors. FIG. 10 is a circuit diagram showing a fifth configuration example of a pixel. FIG. 11 is a circuit diagram showing a sixth configuration example of a pixel. FIG. 12 is a circuit diagram showing an eighth configuration example of a pixel. FIG. 13 is a circuit diagram showing a ninth configuration example of a pixel. FIG. 14 is a circuit diagram showing a tenth configuration example of a pixel. FIG. 15 is a circuit diagram showing an eleventh configuration example of a pixel. FIG. 16 is a diagram showing a first cross-sectional configuration example of a solid-state imaging element. FIG. 17 is a diagram showing a second cross-sectional configuration example of a solid-state imaging element. FIG. 18 is a diagram showing a third cross-sectional configuration example of a solid-state imaging element. FIG. 10 is a diagram showing a fourth cross-sectional configuration example of a solid-state imaging element. FIG. 11 is a diagram showing an example of a planar layout of three capacitors provided in a pixel configured with a second capacitor arrangement. FIG. 12 is a diagram showing an example of a cross-sectional structure of the second capacitor arrangement. FIG. 13 is a diagram showing an example of a cross-sectional structure of the second capacitor arrangement having a multilayer structure. FIG. 14 is a diagram showing a fifth cross-sectional configuration example of a solid-state imaging element. FIG. 15 is a diagram showing a sixth cross-sectional configuration example of a solid-state imaging element. FIG. 16 is a diagram showing a seventh cross-sectional configuration example of a solid-state imaging element. FIG. 17 is a diagram showing an eighth cross-sectional configuration example of a solid-state imaging element. FIG. 18 is a diagram showing an example of a use in which an image sensor is used.

[0012] Hereinafter, specific embodiments to which the present technology is applied will be described in detail with reference to the drawings.

[0013] <Configuration Example of Imaging Apparatus> FIG. 1 is a block diagram showing a configuration example of an embodiment of an imaging apparatus to which the present technology is applied.

[0014] 1, the imaging device 11 is configured to include an optical system 12, a solid-state imaging element 13, an imaging control circuit 14, a signal processing circuit 15, a monitor 16, and a memory 17. For example, the imaging device 11 can be applied to various electronic devices such as imaging systems such as digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions, and is capable of capturing still images and moving images.

[0015] The optical system 12 is composed of one or more lenses, and collects incident light from the subject that enters the imaging device 11, directs it to the solid-state imaging element 13, and forms an image of the subject on the light-receiving surface (sensor section) of the solid-state imaging element 13.

[0016] The solid-state image sensor 13 captures an image of the subject formed on the light receiving surface via the optical system 12 under the control of the image capture control circuit 14 , and supplies an image signal obtained by the image capture to the signal processing circuit 15 .

[0017] The imaging control circuit 14 controls imaging by the solid-state imaging element 13. For example, the imaging control circuit 14 supplies the solid-state imaging element 13 with an imaging control signal including a vertical synchronization signal VSYNC, which is a periodic signal with a constant frequency (e.g., 60 Hz) indicating the timing of imaging.

[0018] The signal processing circuit 15 performs various signal processing on the image signal output from the solid-state image sensor 13 , and supplies the image data obtained as a result of the processing to a monitor 16 or a memory 17 .

[0019] The monitor 16 displays an image in accordance with the image data supplied from the signal processing circuit 15, and the memory 17 stores (records) the image data supplied from the signal processing circuit 15. If the solid-state imaging device 13 has a communication interface, the image data may be transmitted to an external device.

[0020] The solid-state imaging device 13 includes a pixel array section 21, a timing control circuit 22, a vertical scanning circuit 23, a digital-to-analog converter (DAC) 24, a load complementary metal oxide (MOS) circuit block 25, and a column signal processing circuit 26.

[0021] A plurality of pixels 31 are arranged in an array in the pixel array unit 21. Hereinafter, a group of pixels 31 arranged in the horizontal direction will be referred to as a "row," and a group of pixels 31 arranged in a direction perpendicular to the rows will be referred to as a "column." In the pixel array unit 21, each pixel 31 photoelectrically converts incident light to generate an analog pixel signal, and the pixel signals are output in parallel in the column direction in order for each row selected by the vertical scanning circuit 23.

[0022] The timing control circuit 22 controls the operation timing of each of the vertical scanning circuit 23 , the DAC 24 , and the column signal processing circuit 26 in synchronization with the vertical synchronization signal VSYNC supplied from the imaging control circuit 14 .

[0023] The vertical scanning circuit 23 sequentially selects rows so as to scan in the vertical direction, and supplies various control signals to the pixels 31 provided in each selected row, causing the pixels 31 to output analog pixel signals.

[0024] The DAC 24 generates a sawtooth ramp signal by DA conversion and supplies it to the column signal processing circuit 26 .

[0025] In the load MOS circuit block 25, a MOS transistor (for example, the constant current source 44 in FIG. 2) that supplies a constant current is provided for each column.

[0026] The column signal processing circuit 26 refers to the ramp signal supplied from the DAC 24, performs AD (Analog to Digital) conversion on the analog pixel signals output from the pixels 31 via the load MOS circuit block 25, and removes noise by performing CDS (Correlated Double Sampling) processing on the digital pixel signals.

[0027] Then, image data obtained as a result of the column signal processing circuit 26 performing signal processing on the pixel signals is output from the solid-state imaging device 13 .

[0028] <First Configuration Example of Pixel> A first configuration example of the pixel 31 will be described with reference to FIGS.

[0029] FIG. 2 shows an example of a circuit diagram of a pixel 31 according to the first configuration example.

[0030] As shown in FIG. 2 , the pixel 31 is composed of a pixel circuit 41 that generates a pixel signal corresponding to the amount of incident light, and a sample-and-hold circuit 42 that samples the pixel signal generated in the pixel circuit 41 and holds it at a constant level of voltage, and is connected to a constant current source 44 via a vertical signal line 43.

[0031] The pixel circuit 41 includes a photoelectric conversion unit 51, a transfer gate 52, an FD gate 53, a reset gate 54, a capacitor 55, an amplifier gate 56, and a switch gate 57. The sample-and-hold circuit 42 includes a capacitor 61, a capacitor 62, an SR gate 63, an SD gate 64, an RB gate 65, an amplifier gate 66, a selection gate 67, and a capacitor 68. When the pixel 31 is configured using a semiconductor substrate with a two-layer structure, the pixel circuit 41 is provided on the first semiconductor substrate layer, and the sample-and-hold circuit 42 is provided on the second semiconductor substrate layer. In FIG. 2 , a rectangle illustrated between the pixel circuit 41 and the sample-and-hold circuit 42 represents a connection point where the two semiconductor substrate layers are connected (e.g., a Cu-Cu connection).

[0032] The anode of the photoelectric conversion unit 51 is grounded, and the cathode of the photoelectric conversion unit 51 is connected to the source of the transfer gate 52. The drain of the transfer gate 52 is connected to the source of the FD gate 53 and the gate electrode of the amplifier gate 56, and this connection point is called an FD (Floating Diffusion) node. The drain of the FD gate 53 is connected to the source of the reset gate 54 and one end of the capacitor 55. The drain of the reset gate 54 is connected to a power supply VDD, and the other end of the capacitor 55 is grounded. The drain of the amplifier gate 56 is connected to a power supply AMD, and the source of the amplifier gate 56 is connected to the drain of the switch gate 57. The source of the switch gate 57 is connected to a capacitor 68 of the sample-and-hold circuit 42.

[0033] The connection point between one end of the capacitor 61 and one end of the capacitor 62 is called the V1 node, and the source of the switch gate 57 and one end of the capacitor 68 are connected to this V1 node. The other end of the capacitor 61 is connected to the source of the SR gate 63, and the other end of the capacitor 62 is connected to the source of the SD gate 64. The drains of the SR gate 63 and the SD gate 64 are connected to this connection point, which is called the V2 node. The gate electrode of the amplifier gate 66 and the source of the RB gate 65 are connected to this V2 node. The drain of the RB gate 65 is connected to the power supply VREG, and the drain of the amplifier gate 66 is connected to the power supply VDD. The source of the amplifier gate 66 is connected to the drain of the select gate 67, and the source of the select gate 67 is connected to the vertical signal line 43. The other end of the capacitor 68 is connected to a signal line that supplies a ramp signal RAMP.

[0034] The photoelectric conversion unit 51 is configured by a photodiode that photoelectrically converts incident light that enters the pixel 31, and accumulates the electric charge generated by the photoelectric conversion.

[0035] The transfer gate 52 is driven in accordance with a control signal TRG supplied from the vertical scanning circuit 23, and transfers the charge accumulated in the photoelectric conversion unit 51 to the FD node at the timing when the transfer gate 52 is turned on.

[0036] The FD gate 53 is driven in accordance with a control signal FDG supplied from the vertical scanning circuit 23, and connects a capacitor 55 to the FD node while the transfer gate 52 is on. For example, by connecting the capacitor 55 to the FD node via the FD gate 53, it is possible to increase the storage capacitance that holds the charge transferred from the photoelectric conversion unit 51, and to perform HDR (High Dynamic Range) imaging.

[0037] The reset gate 54 is driven in accordance with a control signal RST supplied from the vertical scanning circuit 23, and when the reset gate 54 is turned on, the charge stored in the capacitor 55 and the charge stored in the FD node via the FD gate 53 are discharged to the power supply VDD and reset.

[0038] The capacitor 55 holds the charge transferred from the photoelectric conversion unit 51 together with the FD node while it is connected to the FD node via the FD gate 53 .

[0039] The amplification gate 56 generates a pixel signal according to the charge stored in the FD node or the charge stored in the FD node and the capacitor 55. The amplification gate 56 forms a source follower circuit together with a capacitor 68 connected via a switch gate 57, and outputs the generated pixel signal to the V1 node.

[0040] The switch gate 57 is driven in accordance with a control signal SW supplied from the vertical scanning circuit 23, and connects the amplifier gate 56 to the V1 node while the switch gate 57 is on. Then, the pixel signal generated in the amplifier gate 56 is output to the V1 node via the switch gate 57.

[0041] The capacitor 61 holds the voltage of the pixel signal (hereinafter also referred to as a P-phase signal) at the reset level at which the FD node is reset, in a signal holding capacitance C. A signal holding node that holds a charge corresponding to the P-phase signal between the capacitor 61 and the SR gate 63 is called a VCR node.

[0042] The capacitor 62 holds, in a signal holding capacitance C, the voltage of a pixel signal (hereinafter also referred to as a D-phase signal) at a pixel signal level corresponding to the charge generated in the photoelectric conversion unit 51 and held in the FD node (or the FD node and capacitor 55). A signal holding node that holds the charge corresponding to the D-phase signal between the capacitor 62 and the SD gate 64 is referred to as a VCD node.

[0043] The SR gate 63 is driven in accordance with a control signal SR supplied from the vertical scanning circuit 23, and when the SR gate 63 is turned on, it connects the VCR node to the V2 node, causing the charge corresponding to the P-phase signal held in the VCR node to be held by the VCR node and the V2 node.

[0044] The SD gate 64 is driven in accordance with a control signal SD supplied from the vertical scanning circuit 23, and when the SD gate 64 is turned on, it connects the VCD node to the V2 node, causing the charge corresponding to the D-phase signal that was held in the VCD node to be held by the VCD node and the V2 node.

[0045] The RB gate 65 is driven in accordance with a control signal RB supplied from the vertical scanning circuit 23, and when the RB gate 65 is turned on, the charges held by the VCR node and the V2 node, as well as the charges held by the VCD node and the V2 node, are discharged to the power supply VREG and reset.

[0046] The amplifier gate 66 generates a P-phase signal, which is a pixel signal corresponding to the charges held by the VCR node and the V2 node, and a D-phase signal, which is a pixel signal corresponding to the charges held by the VCD node and the V2 node. The amplifier gate 66 forms a source follower circuit together with the constant current source 44 connected via a selection gate 67, and outputs the P-phase signal and the D-phase signal to the vertical signal line 43.

[0047] The selection gate 67 is driven in accordance with a control signal SEL supplied from the vertical scanning circuit 23, and while the row is selected as the row from which pixel signals are to be read out and the selection gate 67 is turned on, the amplification gate 66 is connected to the vertical signal line 43. Then, the pixel signals (P-phase signal and D-phase signal) generated in the amplification gate 66 are read out to the vertical signal line 43 via the selection gate 67.

[0048] The capacitor 68 is used as a constant current source that supplies a sink current of a constant current Iconst. to the V1 node as charge is accumulated at a constant rate in accordance with the ramp signal RAMP.

[0049] The solid-state imaging device 13 can employ an MIM structure in which an insulator is sandwiched between an upper electrode and a lower electrode as the capacitors 61, 62, and 68. The global shutter type solid-state imaging device 13 can further improve image quality by employing a Capacitive-Current-Source method in which the MIM structure capacitor 68 is used as a constant current source for the first-stage source follower in a Voltage-Domain system.

[0050] For example, in a conventional circuit structure that does not employ the Capacitive-Current-Source method, there is a concern that variations in transistors may be a factor when writing pixel signals to the MIM structure. In contrast, the solid-state imaging device 13 employing the Capacitive-Current-Source method can suppress variations in transistors by supplying a ramp signal RAMP to the capacitor 68.

[0051] 3, the solid-state imaging device 13 can employ a four-pixel sharing structure in which four pixels 31[0] to 31[3] in a 2x2 array are shared at the V2 node. Note that in the drawings of the four-pixel sharing structure described below, the pixel circuit 41 is not shown. Furthermore, i is used to identify a specific pixel 31 among the multiple pixels 31, and in the four-pixel sharing structure, the individual pixels 31 are distinguished by i=1, 2, 3, 4.

[0052] FIG. 4 shows an example of a planar layout of capacitors 61[i], capacitors 62[i], and capacitors 68[i] included in pixels 31[i] arranged in a 2×2 array.

[0053] 4, a pixel 31[i] is provided with a lower electrode 82[i], a lower electrode 83[i], a ramp signal line 84[i], and an upper electrode 85[i]. In addition, a plurality of MIM holes 81[i] provided in the MIM structure are illustrated by dashed rectangles.

[0054] The capacitor 61[i] is provided in a region where the lower electrode 82[i] and the upper electrode 85[i] overlap when the pixel 31[i] is viewed from above. The capacitor 62[i] is provided in a region where the lower electrode 83[i] and the upper electrode 85[i] overlap when the pixel 31[i] is viewed from above. The capacitor 68[i] is provided in a region where the ramp signal line 84[i] and the upper electrode 85[i] overlap when the pixel 31[i] is viewed from above.

[0055] In the solid-state imaging device 13, a ramp signal line 84[i] for supplying a ramp signal RAMP is arranged to extend in the horizontal direction of the pixel array section 21, and the ramp signal line 84[i] constituting the capacitor 68[i] is shared between the pixels 31[i] arranged side by side in the horizontal direction. In other words, one ramp signal line 84 is commonly used to constitute the capacitor 68 of the pixels 31 arranged side by side in the horizontal direction.

[0056] That is, in pixels 31[0] and 31[1] arranged side by side in the horizontal direction, the ramp signal line 84[0] constituting the capacitor 68[0] and the ramp signal line 84[1] constituting the capacitor 68[1] are shared. Similarly, in pixels 31[2] and 31[3] arranged side by side in the horizontal direction, the ramp signal line 84[2] constituting the capacitor 68[2] and the ramp signal line 84[3] constituting the capacitor 68[3] are shared.

[0057] In this way, the solid-state imaging device 13 can improve the efficiency of its layout by adopting a configuration in which the ramp signal line 84 also serves as the lower electrode of the capacitor 68 for further improving image quality.

[0058] As described above, the capacitors 61, 62, and 68 are connected at the V1 node and can share the single upper electrode 85. This allows the solid-state imaging device 13 to achieve a layout that allows miniaturization of the pixels 31.

[0059] Furthermore, pixel 31 employs a layout in which capacitor 61 and capacitor 62 are disposed adjacent to each other in the horizontal direction, and capacitor 68 is disposed symmetrically with respect to capacitor 61 and capacitor 62. For example, in Fig. 4, a dashed dotted line is shown in the center between capacitor 61 and capacitor 62, and capacitor 68 is disposed symmetrically with respect to this dashed dotted line. This allows the solid-state imaging device 13 to suppress, when reading out pixel signals from pixels 31, the occurrence of an offset between the P-phase signal and the D-phase signal, the occurrence of a difference between the pixel signals of pixels 31 sharing the V2 node, and the like.

[0060] The solid-state imaging element 13 preferably employs a layout in which the capacitors 61, 62, and 68 are arranged in line symmetry between vertically adjacent pixels 31. The solid-state imaging element 13 also preferably employs a layout in which the capacitors 61 and 62 are translationally symmetric (symmetric with respect to parallel movement) between pixels 31 arranged side by side in the horizontal direction.

[0061] 5 shows an example of the cross-sectional structure of the capacitor 61 and the capacitor 62 provided in the pixel 31, and the capacitor 68. Note that the capacitors 61 and 62 have the same cross-sectional structure, and are shown as a common structure in FIG.

[0062] 5, capacitors 61 and 62 are configured such that an insulator 86 is sandwiched between lower electrodes 82 and 83 and an upper electrode 85, and are provided with a plurality of MIM holes 81. Capacitor 68 is configured such that an insulator 86 is sandwiched between a ramp signal line 84 and an upper electrode 85, and is provided with a plurality of MIM holes 81.

[0063] As shown in the figure, the upper electrode 85 is shared by the capacitors 61 and 62 and the capacitor 68. Therefore, it is preferable that the capacitors 61 and 62 and the capacitor 68 are arranged in the same wiring layer that constitutes the solid-state imaging device 13.

[0064] The solid-state imaging device 13 including the pixel 31 configured as described above employs a Capacitive-Current-Source method to suppress transistor variations and further improve image quality. Although the solid-state imaging device 13 has a configuration in which the number of MIM structures is increased compared to conventional configurations, the layout can be made more efficient by using the ramp signal line 84 as the lower electrode of the capacitor 68 and by using a single upper electrode 85 shared by the capacitors 61, 62, and 68. This allows, for example, further miniaturization of the pixel 31.

[0065] <Second Configuration Example of Pixel> A second configuration example of the pixel 31 will be described with reference to FIGS. 6 and 7. FIG.

[0066] Fig. 6 shows an example of a circuit diagram of a pixel 31a, which is the second configuration example. In the pixel 31a shown in Fig. 6, components common to the pixel 31 in Fig. 2 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0067] As shown in FIG. 6, the pixel 31a has a common configuration with the pixel 31 in FIG. 2 in that it is configured by a pixel circuit 41a and a sample-and-hold circuit 42a and is connected to a constant current source 44 via a vertical signal line 43.

[0068] 2 in that it includes a photoelectric conversion unit 51, a transfer gate 52, an FD gate 53, a reset gate 54, a capacitor 55, an amplification gate 56, and a switch gate 57. Furthermore, the pixel circuit 41a is configured to include an overflow gate 58.

[0069] The overflow gate 58 is connected between the photoelectric conversion unit 51 and a power supply VDD, and discharges to the power supply VDD any charge that overflows from the photoelectric conversion unit 51. The overflow gate 58 is driven in accordance with a control signal OFG supplied from the vertical scanning circuit 23, and when the overflow gate 58 is turned on, the charge accumulated in the photoelectric conversion unit 51 is discharged to the power supply VDD to reset the photoelectric conversion unit 51, and exposure of the pixel 31 a begins.

[0070] In addition, in the pixel circuit 41a, the power supply AMD connected to the drain of the amplification gate 56 is configured to be switched between VDD (batch S / H) and VDD-Vft-Vgs (readout) by a switch provided in the peripheral region of the pixel array section 21.

[0071] The sample-and-hold circuit 42 a is configured to include capacitors 61 - 1 and 61 - 2 , capacitors 62 - 1 and 62 - 2 , SR gates 63 - 1 and 63 - 2 , SD gates 64 - 1 and 64 - 2 , an RB gate 65 , an amplification gate 66 , a selection gate 67 , and a capacitor 68 .

[0072] One end of capacitor 61-1, one end of capacitor 61-2, one end of capacitor 62-1, and one end of capacitor 62-2 are connected to the V1 node. The other end of capacitor 61-1 is connected to the source of SR gate 63-1, the other end of capacitor 61-2 is connected to the source of SR gate 63-2, the other end of capacitor 62-1 is connected to the source of SD gate 64-1, and the other end of capacitor 62-2 is connected to the source of SD gate 64-2. The drains of SR gate 63-1, SR gate 63-2, SD gate 64-1, and SD gate 64-2 are connected to the V2 node. The gate electrode of amplifier gate 66 and the source of RB gate 65 are connected to this V2 node. The drain of RB gate 65 is connected to the power supply VREG, and the drain of amplifier gate 66 is connected to the power supply VDD. The source of amplifier gate 66 is connected to the drain of select gate 67, and the source of select gate 67 is connected to the vertical signal line 43. The other end of the capacitor 68 is connected to a signal line that supplies a ramp signal RAMP.

[0073] When performing HDR imaging, pixel 31a configured in this manner can, for example, hold a P-phase signal corresponding to high luminance in capacitor 61-1, hold a D-phase signal corresponding to high luminance in capacitor 62-1, hold a P-phase signal corresponding to low luminance in capacitor 61-2, and hold a D-phase signal corresponding to low luminance in capacitor 62-2.

[0074] FIG. 7 shows an example of a planar layout of the capacitors 61-1 and 61-2, the capacitors 62-1 and 62-2, and the capacitor 68 included in the pixel 31a.

[0075] 7, in a plan view of pixel 31a, capacitor 61-1 is provided in a region where lower electrode 82-1 and upper electrode 85 overlap, and capacitor 61-2 is provided in a region where lower electrode 82-2 and upper electrode 85 overlap. Similarly, in a plan view of pixel 31a, capacitor 62-1 is provided in a region where lower electrode 83-1 and upper electrode 85 overlap, and capacitor 62-2 is provided in a region where lower electrode 83-2 and upper electrode 85 overlap. Furthermore, in a plan view of pixel 31a, capacitor 68 is provided in a region where ramp signal line 84 and upper electrode 85 overlap.

[0076] In this way, in pixel 31a, the upper electrode 85 is shared among five MIM structures, namely, capacitors 61-1 and 61-2, capacitors 62-1 and 62-2, and capacitor 68, thereby making it possible to improve the efficiency of the layout.

[0077] Of course, when capturing an image using HDR, pixel 31 may use two or more luminance levels, high luminance and low luminance, in which case pixel 31 is configured to include two or more capacitors 61 and two or more capacitors 62. Therefore, even in a configuration using five or more MIM structures including capacitor 68, the upper electrode 85 can be shared among all of these MIM structures, thereby improving layout efficiency.

[0078] The voltage-domain global shutter solid-state imaging element 13 having the pixel 31a configured as described above can suppress transistor variations and further improve image quality by adopting the capacitive-current-source method.

[0079] <Third Configuration Example of Pixel> A third configuration example of the pixel 31 will be described with reference to FIGS. 8 to 10. FIG.

[0080] Fig. 8 shows an example of a circuit diagram of a pixel 31b, which is a third configuration example. In the pixel 31b shown in Fig. 8, components common to those of the pixel 31 in Fig. 2 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0081] As shown in FIG. 8, the pixel 31b has a common configuration with the pixel 31 in FIG. 2 in that it is configured with a pixel circuit 41 and a sample-and-hold circuit 42b and is connected to a constant current source 44 via a vertical signal line 43.

[0082] 2 in that it includes a capacitor 61, a capacitor 62, an SR gate 63, an SD gate 64, an RB gate 65, an amplification gate 66, a selection gate 67, and a capacitor 68. In addition, the sample and hold circuit 42b includes a DIFF gate 69.

[0083] 8, the drain of the DIFF gate 69 is connected to a V1 node which is a connection point between the source of the switch gate 57 and one end of the capacitor 61. The source of the DIFF gate 69 is connected to a connection point between one end of the capacitor 62 and one end of the capacitor 68, and this connection point is referred to as a V3 node.

[0084] Furthermore, pixel 31b is provided with DIFF gate 69, which can reduce leakage during periods when pixel signals are held in capacitors 61 and 62. For example, DIFF gate 69 is driven in accordance with a control signal DIFF, and is turned off during a readout standby period after a global operation period, thereby separating capacitors 61 and 62. On the other hand, during a readout period, a complete global operation period, and / or a complete row readout period, DIFF gate 69 is turned on, thereby connecting capacitors 61 and 62.

[0085] Furthermore, as shown in FIG. 9, the solid-state imaging device 13 can employ a four-pixel sharing structure in which four pixels 31b[0] to 31b[3] in a 2×2 array are shared at the V2 node.

[0086] FIG. 10 shows an example of a planar layout of capacitors 61[i], capacitors 62[i], and capacitors 68[i] included in pixels 31b[i] arranged in a 2×2 array.

[0087] 10, a pixel 31b[i] is provided with a lower electrode 82[i], a lower electrode 83[i], a ramp signal line 84[i], and an upper electrode 85[i]. A plurality of MIM holes 81[i] provided in the MIM structure are illustrated by dashed rectangles.

[0088] The capacitor 61[i] is provided in a region where the lower electrode 82[i] and the upper electrode 85-1[i] overlap when the pixel 31b[i] is viewed from above. The capacitor 62[i] is provided in a region where the lower electrode 83[i] and the upper electrode 85-2[i] overlap when the pixel 31b[i] is viewed from above. The capacitor 68[i] is provided in a region where the ramp signal line 84[i] and the upper electrode 85-2[i] overlap when the pixel 31b[i] is viewed from above.

[0089] As described above, capacitor 62 and capacitor 68 are connected at node V3, and can share and use one upper electrode 85-2, thereby improving layout efficiency. Note that in a configuration where DIFF gate 69 is provided, upper electrode 85-1[i] of capacitor 61[i] is not shared.

[0090] The voltage-domain global shutter solid-state imaging element 13 having the pixel 31b configured as described above can suppress transistor variations and further improve image quality by adopting the capacitive-current-source method.

[0091] <Fourth Configuration Example of Pixel> A fourth configuration example of the pixel 31 will be described with reference to FIGS. 11 and 12 .

[0092] Fig. 11 shows an example of a circuit diagram of a pixel 31c, which is a fourth configuration example. In the pixel 31c shown in Fig. 11, components common to the pixel 31 in Fig. 2, the pixel 31a in Fig. 6, and the pixel 31b in Fig. 8 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0093] As shown in FIG. 11, the pixel 31c has a common configuration with the pixel 31 in FIG. 2 in that it is configured by a pixel circuit 41c and a sample-and-hold circuit 42c and is connected to a constant current source 44 via a vertical signal line 43.

[0094] The pixel circuit 41c is configured to include a photoelectric conversion unit 51, a transfer gate 52, an FD gate 53, a reset gate 54, a capacitor 55, an amplification gate 56, a switch gate 57, and an overflow gate 58, similar to the pixel circuit 41a in FIG.

[0095] The sample and hold circuit 42c is configured similarly to the pixel 31a in FIG. 6 in that it includes capacitors 61-1 and 61-2, capacitors 62-1 and 62-2, SR gates 63-1 and 63-2, SD gates 64-1 and 64-2, an RB gate 65, an amplification gate 66, a selection gate 67, and a capacitor 68.

[0096] The sample-and-hold circuit 42c further includes DIFF gates 69-1 and 69-2. The drain of the DIFF gate 69-1 is connected to a V1 node, which is the connection point between the source of the switch gate 57 and one end of the capacitor 61-1. The source of the DIFF gate 69-1 is connected to a connection point between one end of the capacitor 62-1, one end of the capacitor 61-2, and the drain of the DIFF gate 69-2; this connection point is referred to as a V3 node. The source of the DIFF gate 69-2 is connected to a connection point between one end of the capacitor 62-2 and one end of the capacitor 68; this connection point is referred to as a V4 node.

[0097] 6, when performing HDR imaging, the pixel 31c can, for example, hold a P-phase signal corresponding to high luminance in the capacitor 61-1, hold a D-phase signal corresponding to high luminance in the capacitor 62-1, hold a P-phase signal corresponding to low luminance in the capacitor 61-2, and hold a D-phase signal corresponding to low luminance in the capacitor 62-2. Similarly to the pixel 31b of FIG. 8, the pixel 31c is provided with DIFF gates 69-1 and 69-2, thereby reducing leakage during periods when pixel signals are held in the capacitors 61-1 and 61-2 and the capacitors 62-1 and 62-2.

[0098] FIG. 12 shows an example of a planar layout of the capacitors 61-1 and 61-2, the capacitors 62-1 and 62-2, and the capacitor 68 included in the pixel circuit 41c.

[0099] 12, in a plan view of pixel 31c, capacitor 61-1 is provided in the region where lower electrode 82-1 and upper electrode 85-1 overlap, and capacitor 61-2 is provided in the region where lower electrode 82-2 and upper electrode 85-2 overlap. Similarly, in a plan view of pixel 31c, capacitor 62-1 is provided in the region where lower electrode 83-1 and upper electrode 85-3 overlap, and capacitor 62-2 is provided in the region where lower electrode 83-2 and upper electrode 85-4 overlap. Furthermore, in a plan view of pixel 31c, capacitor 68 is provided in the region where ramp signal line 84 and upper electrode 85-4 overlap.

[0100] As described above, the capacitor 62-2 and the capacitor 68 are connected at the V4 node and can share the single upper electrode 85-4, which allows for an efficient layout.

[0101] The global shutter type solid-state imaging element 13 using the voltage-domain method and having the pixel 31c configured as described above can suppress transistor variations by adopting the capacitive-current-source method, thereby further improving image quality.

[0102] <Fifth to Eleventh Configuration Examples of Pixel> Fifth to eleventh configuration examples of the pixel 31 will be described with reference to FIGS.

[0103] Fig. 13 shows an example of a circuit diagram of a pixel 31d, which is a fifth configuration example. In the pixel 31d shown in Fig. 13, components common to the pixel 31 in Fig. 2 and the pixel 31a in Fig. 7 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0104] 13, pixel 31d is configured with a pixel circuit 41d and a sample-and-hold circuit 42d, and has a configuration common to pixel 31 in Fig. 2 in that it is connected to a constant current source 44 via a vertical signal line 43. Like sample-and-hold circuit 42 in Fig. 2, sample-and-hold circuit 42d is configured with capacitor 61, capacitor 62, SR gate 63, SD gate 64, RB gate 65, amplifier gate 66, selection gate 67, and capacitor 68.

[0105] 2 in that it includes a photoelectric conversion unit 51, a transfer gate 52, a reset gate 54, an amplification gate 56, and a switch gate 57. Furthermore, the pixel circuit 41a includes an overflow gate 73 and a CLP gate 74.

[0106] As shown in FIG. 13, the CLP gate 74 is connected in parallel to the amplifier gate 56 and forms a source follower circuit similar to the amplifier gate 56 .

[0107] Similarly, the voltage-domain global shutter solid-state imaging device 13 having the pixel 31d configured in this way can capture images with better image quality.

[0108] Fig. 14 shows an example of a circuit diagram of a pixel 31e, which is a sixth configuration example. In the pixel 31e shown in Fig. 14, components common to those of the pixel 31 in Fig. 2 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0109] As shown in FIG. 14, the pixel 31e has a common configuration with the pixel 31 in FIG. 2 in that it is configured by a pixel circuit 41e and a sample-and-hold circuit 42e and is connected to a constant current source 44 via a vertical signal line 43.

[0110] 2 in that it includes a photoelectric conversion unit 51, a transfer gate 52, an FD gate 53, a reset gate 54, a capacitor 55, and an amplification gate 56, but differs from the pixel circuit 41 in that it does not include a switch gate 57. Note that the pixel circuit 41e differs from the pixel circuit 41 in that the drain of the amplification gate 56, together with the drain of the reset gate 54, is connected to the power supply VDD.

[0111] The sample-and-hold circuit 42 e includes a switch gate 57 , a capacitor 61 , a capacitor 62 , an SR gate 63 , an SD gate 64 , an amplifier gate 66 , a selection gate 67 , and a capacitor 68 .

[0112] The drain of the switch gate 57 is connected to the source of the amplifier gate 56 and one end of a capacitor 68, and this connection point serves as the V1 node. The source of the switch gate 57 is connected to the V2 node, which is connected to the drain of the SR gate 63, the drain of the SD gate 64, and the gate electrode of the amplifier gate 66. The source of the SR gate 63 is connected to one end of a capacitor 61, and the other end of the capacitor 61 is grounded. The source of the SD gate 64 is connected to one end of a capacitor 62, and the other end of the capacitor 62 is grounded. The drain of the amplifier gate 66 is connected to the power supply VDD, and the source of the amplifier gate 66 is connected to the drain of the select gate 67, and the source of the select gate 67 is connected to the vertical signal line 43.

[0113] Similarly, the voltage-domain global shutter solid-state imaging device 13 having the pixel 31e configured in this way can capture images with better image quality.

[0114] Fig. 15 shows an example of a circuit diagram of a pixel 31f, which is a seventh configuration example. In the pixel 31f shown in Fig. 15, components common to the pixel 31 in Fig. 2 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0115] 15, pixel 31f has a configuration common to pixel 31 in Fig. 2 in that it is configured by a pixel circuit 41 and a sample-and-hold circuit 42f. Furthermore, pixel 31f is connected to a constant current source 44-1 via a vertical signal line 43-1, and is connected to a constant current source 44-2 via a vertical signal line 43-2.

[0116] The sample-and-hold circuit 42 f is configured to include a capacitor 61 , a capacitor 62 , an SR gate 63 , an SD gate 64 , an amplification gate 66 - 1 and an amplification gate 66 - 2 , a selection gate 67 - 1 and a selection gate 67 - 2 , and a capacitor 68 .

[0117] The drain of the SR gate 63 is connected to the V1 node, and the source of the SR gate 63 is connected to one end of the capacitor 61 and the gate electrode of the amplifier gate 66-1. The drain of the amplifier gate 66-1 is connected to the power supply VDD, and the source of the amplifier gate 66-1 is connected to the drain of the select gate 67-1, and the source of the select gate 67-1 is connected to the vertical signal line 43-1. The drain of the SD gate 64 is connected to the V1 node, and the source of the SD gate 64 is connected to one end of the capacitor 62 and the gate electrode of the amplifier gate 66-2. The drain of the amplifier gate 66-2 is connected to the power supply VDD, and the source of the amplifier gate 66-2 is connected to the drain of the select gate 67-2, and the source of the select gate 67-2 is connected to the vertical signal line 43-2.

[0118] Similarly, the voltage-domain global shutter solid-state imaging device 13 having the pixels 31f configured in this way can capture images with better image quality.

[0119] Fig. 16 shows an example of a circuit diagram of a pixel 31g, which is an eighth configuration example. In the pixel 31g shown in Fig. 16, components common to the pixel 31 in Fig. 2 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0120] As shown in FIG. 16, a pixel 31g has a configuration common to the pixel 31 in FIG. 2 in that it is composed of a pixel circuit 41 and a sample-and-hold circuit 42g and is connected to a constant current source 44 via a vertical signal line 43.

[0121] The sample-and-hold circuit 42 g includes a capacitor 61 , a capacitor 62 , an SR gate 63 , an SD gate 64 , an amplifier gate 66 , a selection gate 67 , and a capacitor 68 .

[0122] The drain of the SR gate 63 is connected to the V1 node, which is connected to one end of a capacitor 68. The source of the SR gate 63 is connected to one end of a capacitor 61 and one end of a capacitor 62. The other end of the capacitor 62 is connected to the V2 node, which is connected to the drain of the SD gate 64 and the gate electrode of an amplifier gate 66. The drain of the amplifier gate 66 is connected to the power supply VDD, and the source of the amplifier gate 66 is connected to the drain of a select gate 67, which is connected to the vertical signal line 43.

[0123] Similarly, the voltage-domain global shutter solid-state imaging device 13 having the pixels 31g configured in this way can capture images with better image quality.

[0124] Fig. 17 shows an example of a circuit diagram of a pixel 31h, which is a ninth configuration example. In the pixel 31h shown in Fig. 17, components common to the pixel 31 in Fig. 2 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0125] As shown in FIG. 17, a pixel 31h has a common configuration with the pixel 31 in FIG. 2 in that it is configured by a pixel circuit 41h and a sample-and-hold circuit 42h and is connected to a constant current source 44 via a vertical signal line 43.

[0126] The pixel circuit 41h is configured similarly to the pixel circuit 41 of Figure 2 in that it includes a photoelectric conversion unit 51, a transfer gate 52, an FD gate 53, a reset gate 54, a capacitor 55, and an amplification gate 56, but differs from the pixel circuit 41 of Figure 2 in that it does not include a switch gate 57.

[0127] The sample-and-hold circuit 42 h includes a switch gate 57 , a capacitor 61 , a capacitor 62 , an SR gate 63 , an SD gate 64 , an amplifier gate 66 , a selection gate 67 , and a capacitor 68 .

[0128] The drain of the switch gate 57 is connected to the source of the amplifier gate 56 and one end of a capacitor 68, and this connection point serves as the V1 node. The source of the switch gate 57 is connected to the V2 node, which is connected to the drain of the SR gate 63, the drain of the SD gate 64, and the gate electrode of the amplifier gate 66. The source of the SR gate 63 is connected to one end of a capacitor 61, and the other end of the capacitor 61 is grounded. The source of the SD gate 64 is connected to one end of a capacitor 62, and the other end of the capacitor 62 is grounded. The drain of the amplifier gate 66 is connected to the power supply VDD, and the source of the amplifier gate 66 is connected to the drain of the select gate 67, and the source of the select gate 67 is connected to the vertical signal line 43.

[0129] Similarly, the voltage-domain global shutter solid-state imaging device 13 having the pixels 31h configured in this way can capture images with better image quality.

[0130] Fig. 18 shows an example of a circuit diagram of a pixel 31i, which is a tenth configuration example. In the pixel 31i shown in Fig. 18, components common to the pixel 31 in Fig. 2 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0131] As shown in FIG. 18, the pixel 31i has a common configuration with the pixel 31 in FIG. 2 in that it is configured with a pixel circuit 41 and a sample-and-hold circuit 42i and is connected to a constant current source 44 via a vertical signal line 43.

[0132] The sample-and-hold circuit 42 i includes a capacitor 61 , a capacitor 62 , an SR gate 63 , an SD gate 64 , an amplifier gate 66 , a selection gate 67 , and a capacitor 68 .

[0133] The drain of the SR gate 63 is connected to the V1 node, and one end of a capacitor 68 is connected to the V1 node. The source of the SR gate 63 is connected to the drain of the SD gate 64 and one end of the capacitor 61. The source of the SD gate 64 is connected to the gate electrode of the amplifier gate 66 and one end of the capacitor 62. The drain of the amplifier gate 66 is connected to the power supply VDD, and the source of the amplifier gate 66 is connected to the drain of the select gate 67, and the source of the select gate 67 is connected to the vertical signal line 43.

[0134] Similarly, the voltage-domain global shutter solid-state imaging device 13 having the pixels 31i configured in this way can capture images with better image quality.

[0135] Fig. 19 shows an example of a circuit diagram of a pixel 31j, which is an eleventh configuration example. In the pixel 31j shown in Fig. 19, components common to the pixel 31 in Fig. 2 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0136] As shown in FIG. 19, the pixel 31j is configured with a pixel circuit 41 and a sample-and-hold circuit 42j, and has a configuration common to the pixel 31 in FIG. 2 in that it is connected to a constant current source 44 via a vertical signal line 43.

[0137] The sample-and-hold circuit 42 j includes a capacitor 61 , a capacitor 62 , an RB gate 65 , an amplifier gate 66 , a selection gate 67 , and a capacitor 68 .

[0138] One end of the capacitor 61 is connected to the V1 node, and one end of a capacitor 68 is connected to the V1 node. The other end of the capacitor 61 is connected to one end of the capacitor 62, the source of the RB gate 65, and the gate electrode of the amplifier gate 66. The drain of the RB gate 65 is connected to the power supply VREG, and the drain of the amplifier gate 66 is connected to the power supply VDD. The source of the amplifier gate 66 is connected to the drain of the select gate 67, and the source of the select gate 67 is connected to the vertical signal line 43.

[0139] Similarly, the voltage-domain global shutter solid-state imaging device 13 having the pixel 31j configured in this way can capture images with better image quality.

[0140] The pixel 31 may have various configurations other than those shown in FIGS. 13 to 19, as long as it satisfies the layout and the like described above.

[0141] <Example of Cross-Sectional Configuration of Solid-State Imaging Device> An example of the cross-sectional configuration of the solid-state imaging device 13 will be described with reference to FIGS. 20 to 23. FIG.

[0142] FIG. 20 shows a cross-sectional configuration of a solid-state imaging device 13 as a first configuration example.

[0143] As shown in FIG. 20, the solid-state imaging element 13 has a two-layer structure in which a first semiconductor substrate 101 and a second semiconductor substrate 102 are stacked, and a plurality of pixels 31 are arranged in a pixel array section 21.

[0144] The first semiconductor substrate 101 is configured by laminating a wiring layer 112 on a semiconductor layer 111, and an on-chip lens 113 for condensing light for each pixel 31 is laminated on the light-receiving surface side of the semiconductor layer 111.

[0145] The semiconductor layer 111 is provided with a photoelectric conversion unit 51 for each pixel 31, as well as various elements (e.g., transfer gates 52, FD gates 53, etc.) that constitute the pixel circuit 41. The semiconductor layer 111 is also provided with an element isolation unit 121 that optically and electrically isolates adjacent pixels 31 from each other.

[0146] The wiring layer 112 is provided with a plurality of wires and a plurality of through electrodes for electrical connection with the second semiconductor substrate 102 for each pixel 31. Furthermore, in the peripheral region of the wiring layer 112 (the region outside the pixel array section 21), pads 122 used for connecting the solid-state imaging element 13 to the outside are arranged, and openings 123 are provided for wire bonding to the pads 122.

[0147] The second semiconductor substrate 102 is configured by laminating a wiring layer 132 on a semiconductor layer 131 .

[0148] The semiconductor layer 131 is provided with various elements (for example, an SR gate 63, an SD gate 64, etc.) that constitute the sample-and-hold circuit 42. The semiconductor layer 131 is also provided with various elements that constitute a logic circuit that drives the solid-state imaging device 13, for example.

[0149] The wiring layer 132 is provided with a plurality of wires and a plurality of through electrodes for electrical connection with the first semiconductor substrate 101 for each pixel 31. The wiring layer 132 is also provided with an MIM structure 143 for each pixel 31, which constitutes the capacitors 61, 62, and 68 arranged in the same layer.

[0150] The solid-state imaging element 13 having such a stacked structure can be constructed by joining the wiring layer 112 of the first semiconductor substrate 101 and the wiring layer 132 of the second semiconductor substrate 102, as in the configuration example shown in FIG.

[0151] Fig. 21 shows a cross-sectional configuration of a solid-state imaging device 13A as a second configuration example. In the solid-state imaging device 13A shown in Fig. 21, components common to the solid-state imaging device 13 shown in Fig. 20 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0152] 21, the solid-state imaging element 13A has a two-layer structure formed by stacking a first semiconductor substrate 101A and a second semiconductor substrate 102A. In the solid-state imaging element 13A, similar to the solid-state imaging element 13 shown in FIG. 20, a photoelectric conversion unit 51 is provided in the semiconductor layer 111 of the first semiconductor substrate 101A for each pixel 31, and an MIM structure 143 is provided in the wiring layer 132A of the second semiconductor substrate 102A.

[0153] 20 in that the solid-state imaging element 13A is configured by bonding a wiring layer 112A of a first semiconductor substrate 101A and a semiconductor layer 131A of a second semiconductor substrate 102A together. In the solid-state imaging element 13A, a pad 122A is disposed on the wiring layer 132A, and an opening 123A is provided so as to penetrate the first semiconductor substrate 101A and reach the pad 122A.

[0154] Fig. 22 shows a cross-sectional configuration of a solid-state imaging device 13B, which is a third configuration example. In the solid-state imaging device 13B shown in Fig. 22, components common to the solid-state imaging device 13 shown in Fig. 20 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0155] 22, the solid-state imaging element 13B has a three-layer structure in which a first semiconductor substrate 101, a second semiconductor substrate 102, and a third semiconductor substrate 103 are stacked, and is configured by joining a wiring layer 112 of the first semiconductor substrate 101 and a wiring layer 132 of the second semiconductor substrate 102. In other words, the solid-state imaging element 13B has a configuration in which the third semiconductor substrate 103 is stacked on the first semiconductor substrate 101 and the second semiconductor substrate 102, which are configured in the same manner as the solid-state imaging element 13 in FIG.

[0156] For example, in the solid-state imaging device 13B, various elements constituting the pixel circuit 41 are provided on the first semiconductor substrate 101, and various elements constituting the sample-and-hold circuit 42 are provided on the second semiconductor substrate 102. Then, various elements constituting the logic circuit that drives the solid-state imaging device 13 are provided on the third semiconductor substrate 103.

[0157] Fig. 23 shows a cross-sectional configuration of a solid-state imaging device 13C as a fourth configuration example. In the solid-state imaging device 13C shown in Fig. 23, components common to the solid-state imaging device 13 shown in Fig. 20 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0158] 23, the solid-state imaging element 13C has a three-layer structure formed by stacking a first semiconductor substrate 101C, a second semiconductor substrate 102C, and a third semiconductor substrate 103, and is formed by bonding a wiring layer 112C of the first semiconductor substrate 101C to a semiconductor layer 131C of the second semiconductor substrate 102C. In other words, the solid-state imaging element 13C is formed by stacking a third semiconductor substrate 103 on a first semiconductor substrate 101C and a second semiconductor substrate 102C that are configured in the same manner as the first semiconductor substrate 101A and the second semiconductor substrate 102A of the solid-state imaging element 13A in FIG.

[0159] For example, in the solid-state imaging device 13C, various elements constituting the pixel circuit 41 are provided on the first semiconductor substrate 101C, and various elements constituting the sample-and-hold circuit 42 are provided on the second semiconductor substrate 102C. Then, various elements constituting the logic circuit that drives the solid-state imaging device 13 are provided on the third semiconductor substrate 103.

[0160] The solid-state imaging device 13 may employ a layered structure other than the layered structures shown in FIGS.

[0161] <Other Arrangement Examples of Capacitors> Other arrangement examples of the capacitors 61, 62, and 68 included in the above-described pixel 31 (including the pixels 31a to 31j of each configuration example) will be described with reference to FIGS. 24 to 30.

[0162] The pixel 31 described above is configured such that the capacitors 61, 62, and 68 are arranged in the same layer (hereinafter referred to as a first capacitor arrangement) of the wiring layer that constitutes the solid-state imaging element 13. In addition to this first capacitor arrangement, the pixel 31 can also be configured such that the capacitors 61 and 62 are arranged in the same layer and the capacitor 68 is arranged in a different layer from the capacitors 61 and 62, and the capacitors 61, 62, and 68 are arranged in the wiring layer that constitutes the solid-state imaging element 13 so as to overlap when the pixel 31 is viewed in a plane (hereinafter referred to as a second capacitor arrangement).

[0163] Figure 24 shows an example of a planar layout of capacitors 61n[i], capacitors 62n[i], and capacitors 68n[i] provided in pixel 31n[i] of a 2x2 array (see Figure 3) configured with the second capacitor arrangement.

[0164] 24, a pixel 31n[i] is provided with a lower electrode 82n[i], a lower electrode 83n[i], a ramp signal line 84n[i], an upper electrode 85n[i], and a lower electrode 87n[i]. Note that, in FIG. 24, the illustration of a plurality of MIM holes 81 provided in the MIM structure is omitted.

[0165] The capacitor 61n[i] is provided in a region where the lower electrode 82n[i] and the upper electrode 85n[i] overlap in a plan view of the pixel 31n[i]. The capacitor 62n[i] is provided in a region where the lower electrode 83n[i] and the upper electrode 85n[i] overlap in a plan view of the pixel 31n[i]. The capacitor 68n[i] is provided in a region where the ramp signal line 84n[i] and the lower electrode 87n[i] overlap in a plan view of the pixel 31n[i].

[0166] The ramp signal line 84n[i] is used as an upper electrode that constitutes the MIM structure of the capacitor 68n[i], and the ramp signal line 84n[i] that constitutes the capacitor 68n[i] is shared by the pixels 31n[i] that are arranged side by side in the horizontal direction, similar to the ramp signal line 84[i] described above with reference to Fig. 4. That is, one ramp signal line 84n that is arranged to extend in the horizontal direction of the pixel array unit 21 is used in common to constitute the capacitors 68n of the pixels 31n that are arranged side by side in the horizontal direction.

[0167] In the pixel 31n, the capacitor 61n and the capacitor 62n are arranged so as to overlap with the capacitor 68n when the pixel 31n is viewed from above as shown in FIG.

[0168] FIG. 25 shows an example of the cross-sectional structure of the second capacitor arrangement.

[0169] 25, in the second capacitor arrangement, capacitors 61n and 62n are arranged on the same layer, and capacitor 68n is arranged on a different layer from capacitors 61n and 62n. In the example shown, capacitors 61n and 62n are arranged on the lower layer, and capacitor 68n is arranged on the upper layer, but these may be arranged in an interchangeable manner.

[0170] The capacitor 61n is configured so that an insulator 86 is sandwiched between a lower electrode 82n and an upper electrode 85n, and is provided with a plurality of MIM holes 81. The capacitor 62n is configured so that an insulator 86 is sandwiched between a lower electrode 83n and an upper electrode 85n, and is provided with a plurality of MIM holes 81. That is, the upper electrode 85n is shared by the capacitors 61n and 62n.

[0171] The capacitor 68n is configured such that an insulator 86 is sandwiched between a lower electrode 87n and a ramp signal line 84n, and is configured by providing a plurality of MIM holes 81.

[0172] Furthermore, when arranging capacitors 61n, 62n, and 68n on different layers, from the viewpoint of layout efficiency, it is preferable to arrange the wiring connected to the connection point CCC (Cu-Cu Connection) between pixel circuit 41 and sample-and-hold circuit 42 between capacitors 61n, 62n, and 68n. This allows capacitors 61n and 62n arranged on the lower side and capacitor 68n arranged on the upper side to be configured with opposite polarity and symmetrical top-to-bottom. In other words, by adopting a configuration in which upper electrodes 85n constituting capacitors 61n and 62n arranged on the lower side are connected to connection point CCC and lower electrodes 87n constituting capacitors 68n arranged on the upper side are connected to connection point CCC, layout efficiency can be improved.

[0173] The electrodes connected to the connection point CCC may be reversed. In this case, the ramp signal line 84n is used as the lower electrode of the capacitor 68n, the upper electrode of the capacitor 68n is connected to the connection point CCC, and the lower electrode 82n of the capacitor 61n and the lower electrode 83n of the capacitor 62n are connected to the connection point CCC, so that the polarities are symmetrical and opposite to each other.

[0174] As described above, pixel 31n configured with the second capacitor arrangement can increase the capacitance of each of capacitors 61n, 62n, and 68n by arranging them on different layers. In other words, in the first capacitor arrangement described above, capacitors 61, 62, and 68 are arranged on the same layer, which reduces the area for each arrangement, raising concerns about a decrease in capacitance, whereas the second capacitor arrangement can avoid such a decrease in capacitance.

[0175] The pixel 31n can reduce noise generated in the pixel signal by increasing the capacitance of the capacitor 61n and the capacitor 62n that store the pixel signal. The pixel 31n can also reduce variations in the current supplied to the V1 node by increasing the capacitance of the capacitor 68n that stores charge in accordance with the ramp signal RAMP. Therefore, the solid-state imaging device 13 including the pixel 31n can reduce noise and variations, further improving image quality.

[0176] FIG. 26 shows an example of a cross-sectional structure of the second capacitor arrangement having a multi-layer structure.

[0177] 26, capacitors 61m and 62m are arranged in a two-layer structure on the same layer, and capacitor 68m is arranged in a two-layer structure on a layer different from capacitors 61m and 62m. In the example shown, capacitors 61m and 62m are arranged on the lower layer, and capacitor 68m is arranged on the upper layer, but these may be arranged in an interchangeable manner.

[0178] The capacitor 61m has a two-layer structure including a first layer in which an insulator 86 is sandwiched between a lower electrode 82m-1 and an upper electrode 85m-1, and a second layer in which the insulator 86 is sandwiched between a lower electrode 82m-2 and an upper electrode 85m-2, and is provided with a plurality of MIM holes 81. The capacitor 62m has a two-layer structure including a first layer in which an insulator 86 is sandwiched between a lower electrode 83m-1 and an upper electrode 85m-1, and a second layer in which the insulator 86 is sandwiched between a lower electrode 83m-2 and an upper electrode 85m-2, and is provided with a plurality of MIM holes 81. That is, the upper electrode 85m-1 of the first layer is shared by the capacitor 61m and the capacitor 62m, and the upper electrode 85m-2 of the second layer is shared by the capacitor 61m and the capacitor 62m.

[0179] The capacitor 68m is configured with a two-layer structure including a first layer in which an insulator 86 is sandwiched between a lower electrode 87m-1 and a ramp signal line 84m-1, and a second layer in which an insulator 86 is sandwiched between a lower electrode 87m-2 and a ramp signal line 84m-2, and is configured with a plurality of MIM holes 81 provided.

[0180] 25, from the viewpoint of layout efficiency, it is preferable to configure the capacitors 61m and 62m arranged on the lower side and the capacitor 68m arranged on the upper side so that they are symmetrical and have opposite polarities in the vertical direction. That is, by adopting a configuration in which the upper electrodes 85m-1 and 85m-2 constituting the capacitors 61m and 62m arranged on the lower side are connected to the connection point CCC, and the lower electrodes 87m-1 and 87m-2 constituting the capacitor 68m arranged on the upper side are connected to the connection point CCC, layout efficiency can be improved.

[0181] The electrodes connected to the connection point CCC may be interchanged. In this case, the ramp signal line 84m is used as the lower electrode of the capacitor 68m, the upper electrode of the capacitor 68m is connected to the connection point CCC, and the lower electrodes 82m-1 and 82m-2 of the capacitor 61m and the lower electrodes 83m-1 and 83m-1 of the capacitor 62m are connected to the connection point CCC, so that the polarities are symmetrical and opposite to each other.

[0182] In this way, by configuring the capacitors 61m, 62m, and 68m in a two-layer structure, the capacitance of each can be increased by approximately two times, and the image quality of the solid-state imaging device 13 can be improved.

[0183] Of course, the capacitors 61m and 62m may be arranged in a multi-layer structure of two or more layers on the same layer, and the capacitor 68m may be arranged in a multi-layer structure of two or more layers on a different layer from the capacitors 61m and 62m.

[0184] <Example of Cross-Sectional Configuration of Solid-State Imaging Device> An example of the cross-sectional configuration of the solid-state imaging device 13 will be described with reference to FIGS. 27 to 30. FIG.

[0185] Fig. 27 shows a cross-sectional configuration of a solid-state imaging device 13D, which is a fifth configuration example. In the solid-state imaging device 13D shown in Fig. 27, components common to the solid-state imaging device 13 shown in Fig. 20 and the solid-state imaging device 13B shown in Fig. 22 are denoted by the same reference numerals, and detailed descriptions thereof will be omitted.

[0186] As shown in Figure 27, the solid-state imaging element 13D, like the solid-state imaging element 13B in Figure 22, has a three-layer structure formed by stacking a first semiconductor substrate 101, a second semiconductor substrate 102D, and a third semiconductor substrate 103, and is formed by joining a wiring layer 112 on the surface side of the first semiconductor substrate 101 and a wiring layer 132D on the surface side of the second semiconductor substrate 102D.

[0187] The solid-state imaging element 13D is configured such that an MIM structure having a second capacitor arrangement in which capacitors 61 and 62 are arranged in the same layer and capacitor 68 is arranged in a different layer from capacitors 61 and 62 is provided for each pixel 31 in the wiring layer 132D of the second semiconductor substrate 102D.

[0188] Fig. 28 shows a cross-sectional configuration of a solid-state imaging device 13E as a sixth configuration example. In the solid-state imaging device 13E shown in Fig. 28, components common to the solid-state imaging device 13 shown in Fig. 20 and the solid-state imaging device 13C shown in Fig. 23 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0189] As shown in Figure 28, the solid-state imaging element 13E, like the solid-state imaging element 13C in Figure 23, has a three-layer structure formed by stacking a first semiconductor substrate 101E, a second semiconductor substrate 102E, and a third semiconductor substrate 103, and is formed by joining a wiring layer 112E on the front side of the first semiconductor substrate 101E and a semiconductor layer 131E on the back side of the second semiconductor substrate 102E.

[0190] The solid-state imaging element 13E is configured such that an MIM structure having a second capacitor arrangement in which capacitors 61 and 62 are arranged in the same layer and capacitor 68 is arranged in a different layer from capacitors 61 and 62 is provided for each pixel 31 in the wiring layer 132E of the second semiconductor substrate 102E.

[0191] Fig. 29 shows a cross-sectional configuration of a solid-state imaging device 13F, which is a seventh configuration example. In the solid-state imaging device 13F shown in Fig. 29, components common to the solid-state imaging device 13 shown in Fig. 20 and the solid-state imaging device 13B shown in Fig. 22 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0192] As shown in Figure 29, the solid-state imaging element 13F, like the solid-state imaging element 13B in Figure 22, has a three-layer structure formed by stacking a first semiconductor substrate 101, a second semiconductor substrate 102F, and a third semiconductor substrate 103, and is formed by joining a wiring layer 112 on the surface side of the first semiconductor substrate 101 and a wiring layer 132F on the surface side of the second semiconductor substrate 102F.

[0193] The solid-state imaging element 13F is configured such that an MIM structure in which capacitors 61 and 62 are arranged in the same layer is provided for each pixel 31 in a wiring layer 132F of the second semiconductor substrate 102F, and a trench MOS capacitor 133 is provided for each pixel 31 in a semiconductor layer 131F of the second semiconductor substrate 102F.

[0194] The trench MOS capacitor 133 is configured by arranging a MOS (Metal-Oxide-Semiconductor) structure in a deep trench formed in the semiconductor layer 131F. The trench MOS capacitor 133 is provided in place of the capacitor 68 and is used as a capacitance that stores charge in accordance with the ramp signal RAMP. In addition to the trench MOS capacitor 133 as shown in the figure, a MOS capacitor configured by arranging a planar MOS structure in the semiconductor layer 131F may also be used as a capacitance.

[0195] Fig. 30 shows a cross-sectional configuration of a solid-state imaging device 13G as an eighth configuration example. In the solid-state imaging device 13G shown in Fig. 30, components common to the solid-state imaging device 13 shown in Fig. 20 and the solid-state imaging device 13B shown in Fig. 22 are denoted by the same reference numerals, and detailed description thereof will be omitted.

[0196] As shown in Figure 30, the solid-state imaging element 13G, like the solid-state imaging element 13B in Figure 22, has a three-layer structure formed by stacking a first semiconductor substrate 101, a second semiconductor substrate 102G, and a third semiconductor substrate 103, and is formed by joining a wiring layer 112 on the surface side of the first semiconductor substrate 101 and a wiring layer 132 on the surface side of the second semiconductor substrate 102G.

[0197] The solid-state imaging device 13G is configured by providing trench MOS capacitors 133-1 to 133-3 for each pixel 31 in a semiconductor layer 131G of a second semiconductor substrate 102G.

[0198] Trench MOS capacitor 133-1 is provided in place of capacitor 61, and MOS capacitor 133-2 is provided in place of capacitor 62, and each is used as a capacitance for holding a pixel signal. Trench MOS capacitor 133-3 is provided in place of capacitor 68, and is used as a capacitance for storing charge in accordance with ramp signal RAMP. In addition to trench MOS capacitors 133-1 to 133-3 as shown in the figure, a MOS capacitor configured by arranging a planar MOS structure on semiconductor layer 131G may also be used as a capacitance.

[0199] <Example of Use of Image Sensor> FIG. 31 is a diagram showing an example of use of the image sensor (imaging element) described above.

[0200] The image sensor described above can be used in various cases for sensing light such as visible light, infrared light, ultraviolet light, and X-rays, for example, as follows.

[0201] ・Devices for taking images for viewing purposes, such as digital cameras and mobile devices with camera functions. ・Devices for traffic purposes, such as in-vehicle sensors that take images of the front, rear, surroundings, and interior of a car for safe driving such as automatic stopping, and for recognizing the driver's state, surveillance cameras that monitor moving vehicles and roads, and distance measuring sensors that measure distances between vehicles. ・Devices for home appliances such as TVs, refrigerators, and air conditioners that take images of user gestures and operate the device according to those gestures. ・Devices for medical and healthcare purposes, such as endoscopes and devices that take images of blood vessels by receiving infrared light. ・Devices for security purposes, such as surveillance cameras for crime prevention and cameras for person authentication. ・Devices for beauty purposes, such as skin measuring devices that take images of the skin and microscopes that take images of the scalp. ・Devices for sports purposes, such as action cameras and wearable cameras for sports, etc. ・Devices for agricultural purposes, such as cameras to monitor the condition of fields and crops.

[0202] <Examples of Combinations of Configurations> The present technology can also be configured as follows. (1) A solid-state imaging device including a pixel having: a first capacitor that holds a voltage of a pixel signal of a reset level output from a pixel circuit; a second capacitor that holds a voltage of a pixel signal of a pixel signal level output from the pixel circuit; and a third capacitor that has one end connected to a connection point where one end of the first capacitor and one end of the second capacitor are connected and the other end connected to a signal line that supplies a ramp signal, and that forms a source follower circuit together with an amplification gate of the pixel circuit, wherein the first capacitor, the second capacitor, and the third capacitor are arranged in the same wiring layer. (2) The solid-state imaging device according to (1), wherein the third capacitor uses a ramp signal line that supplies the ramp signal as a lower electrode that forms an MIM (Metal Insulator Metal) structure. (3) The solid-state imaging device according to (2), wherein the lower electrode that forms the MIM structure of the third capacitor is used in common between the pixels that are arranged side by side in a direction in which the ramp signal line extends. (4) The solid-state imaging device according to (3), wherein an upper electrode constituting the MIM structure of the third capacitor is shared with upper electrodes constituting the MIM structure of the first capacitor and the second capacitor. (5) The solid-state imaging device according to (4), wherein a plurality of the first capacitors are provided to hold pixel signals at reset levels corresponding to a plurality of brightnesses, and a plurality of the second capacitors are provided to hold pixel signals at pixel signal levels corresponding to a plurality of brightnesses. (6) The solid-state imaging device according to claim 5, wherein the upper electrodes of a plurality of the first capacitors, the upper electrodes of a plurality of the second capacitors, and the upper electrode of the third capacitor are shared. The solid-state imaging device according to (5). (7) The solid-state imaging device according to any of (3) to (6), further comprising: a transistor provided between a first node which is a connection point between the pixel circuit and one end of the first capacitor, and a second node which is a connection point between one end of the second capacitor and one end of the third capacitor.(8) The solid-state imaging element according to (7), wherein an upper electrode constituting the MIM structure of the third capacitor is used in common with an upper electrode constituting the MIM structure of the second capacitor. (9) An electronic device comprising a solid-state imaging element comprising: a first capacitor that holds a voltage of a pixel signal of a reset level output from a pixel circuit, a second capacitor that holds a voltage of a pixel signal of a pixel signal level output from the pixel circuit, and a third capacitor that has one end connected to a connection point where one end of the first capacitor and one end of the second capacitor are connected and the other end connected to a signal line that supplies a ramp signal, and that constitutes a source follower circuit together with an amplification gate of the pixel circuit, wherein the first capacitor, the second capacitor, and the third capacitor are arranged in the same layer of a wiring layer. (10) A solid-state imaging device comprising a pixel having: a first capacitor that holds the voltage of a pixel signal of a reset level output from a pixel circuit; a second capacitor that holds the voltage of a pixel signal of a pixel signal level output from the pixel circuit; and a third capacitor that has one end connected to a connection point where one end of the first capacitor and one end of the second capacitor are connected and the other end connected to a signal line that supplies a ramp signal, and that forms a source follower circuit together with an amplification gate of the pixel circuit, wherein the first capacitor and the second capacitor are arranged in the same layer of a wiring layer, and the third capacitor is arranged in a layer of the wiring layer different from that of the first capacitor and the second capacitor. (11) The solid-state imaging device according to (10), wherein the third capacitor uses a ramp signal line that supplies the ramp signal as an upper electrode that forms an MIM (Metal Insulator Metal) structure. (12) The solid-state imaging device according to (11), wherein the upper electrode that forms the MIM structure of the third capacitor is used in common between the pixels that are arranged side by side in a direction in which the ramp signal line extends. (13) The solid-state imaging device according to (12), wherein the upper electrode constituting the MIM structure of the first capacitor and the second capacitor is shared.(14) The solid-state imaging device according to (12) or (13), wherein a lower electrode constituting the MIM structure of the third capacitor arranged on the upper side and upper electrodes constituting the MIM structures of the first capacitor and the second capacitor arranged on the lower side are connected to a connection point with the pixel circuit. (15) The solid-state imaging device according to any of (10) to (14), wherein the MIM structures constituting the first capacitor and the second capacitor are configured with a multilayer structure of two or more layers, and the MIM structure constituting the third capacitor is configured with a multilayer structure of two or more layers. (16) The solid-state imaging device according to any of (10) to (15), wherein a first semiconductor substrate on which the pixel circuit including a photoelectric conversion unit that performs photoelectric conversion to generate the pixel signal is provided, and a second semiconductor substrate on which a sample and hold circuit that holds the pixel signal is provided are configured with a stacked structure formed by at least stacking, and wherein a front surface side of the first semiconductor substrate and a front surface side of the second semiconductor substrate are bonded, or a back surface side of the first semiconductor substrate and a back surface side of the second semiconductor substrate are bonded. (17) An electronic device having a pixel including: a first capacitor that holds the voltage of a pixel signal of a reset level output from a pixel circuit; a second capacitor that holds the voltage of a pixel signal of a pixel signal level output from the pixel circuit; and a third capacitor that has one end connected to a connection point where one end of the first capacitor and one end of the second capacitor are connected and the other end connected to a signal line that supplies a ramp signal, and that forms a source follower circuit together with an amplification gate of the pixel circuit; wherein the first capacitor and the second capacitor are arranged in the same layer of a wiring layer, and the third capacitor is arranged in a layer of the wiring layer different from that of the first capacitor and the second capacitor.(18) A solid-state imaging device comprising a pixel having: a first capacitor that holds a voltage of a pixel signal of a reset level output from a pixel circuit; a second capacitor that holds a voltage of a pixel signal of a pixel signal level output from the pixel circuit; and a third capacitor that has one end connected to a connection point where one end of the first capacitor and one end of the second capacitor are connected and the other end connected to a signal line that supplies a ramp signal, and that forms a source follower circuit together with an amplification gate of the pixel circuit; wherein a first semiconductor substrate on which the pixel circuit is provided, the first semiconductor substrate including a photoelectric conversion unit that performs photoelectric conversion to generate the pixel signal, and a second semiconductor substrate on which a sample-and-hold circuit that holds the pixel signal is provided, are configured in a stacked structure formed by at least stacking them; and at least one or both of the first capacitor, the second capacitor, and the third capacitor uses a MOS (Metal-Oxide-Semiconductor) capacitor configured by arranging a MOS structure on a semiconductor layer of the second semiconductor substrate. (19) The solid-state imaging device according to (18), wherein the third capacitor is a MOS capacitor, and the first capacitor and the second capacitor have an MIM (Metal Insulator Metal) structure provided in a wiring layer of the second semiconductor substrate.(20) An electronic device having a solid-state imaging element, the solid-state imaging element comprising: a pixel having: a first capacitor that holds the voltage of a pixel signal of a reset level output from a pixel circuit; a second capacitor that holds the voltage of a pixel signal of a pixel signal level output from the pixel circuit; and a third capacitor that has one end connected to a connection point where one end of the first capacitor and one end of the second capacitor are connected and the other end connected to a signal line that supplies a ramp signal, and that forms a source follower circuit together with an amplification gate of the pixel circuit; the solid-state imaging element having a stacked structure formed by stacking at least a first semiconductor substrate on which the pixel circuit is provided, the first semiconductor substrate including a photoelectric conversion unit that performs photoelectric conversion to generate the pixel signal, and a second semiconductor substrate on which a sample-and-hold circuit that holds the pixel signal is provided; and at least one or both of the first capacitor, the second capacitor, and the third capacitor use a MOS (Metal-Oxide-Semiconductor) capacitor that is formed by arranging a MOS structure on a semiconductor layer of the second semiconductor substrate.

[0203] It should be noted that the present embodiment is not limited to the above-described embodiment, and various modifications are possible within the scope of the gist of the present disclosure. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be obtained.

[0204] REFERENCE SIGNS LIST 11 imaging device, 12 optical system, 13 solid-state imaging element, 14 imaging control circuit, 15 signal processing circuit, 16 monitor, 17 memory, 21 pixel array section, 22 timing control circuit, 23 vertical scanning circuit, 24 DAC, 25 load MOS circuit block, 26 column signal processing circuit, 31 pixel, 41 pixel circuit, 42 sample and hold circuit, 43 vertical signal line, 44 constant current source, 51 photoelectric conversion section, 52 transfer gate, 53 FD gate, 54 reset gate, 55 capacitor, 56 amplification gate, 57 switch gate, 61 capacitor, 62 capacitor, 63 SR gate, 64 SD gate, 64, 65 RB gate, 66 amplification gate, 67 selection gate, 68 capacitor

Claims

1. A solid-state imaging device comprising a pixel having: a first capacitor that holds the voltage of a pixel signal of a reset level output from a pixel circuit; a second capacitor that holds the voltage of a pixel signal of a pixel signal level output from the pixel circuit; and a third capacitor that has one end connected to a connection point where one end of the first capacitor and one end of the second capacitor are connected and the other end connected to a signal line that supplies a ramp signal, and that forms a source follower circuit together with an amplification gate of the pixel circuit, wherein the first capacitor, the second capacitor, and the third capacitor are arranged in the same wiring layer.

2. The solid-state imaging device according to claim 1, wherein the third capacitor uses a ramp signal line that supplies the ramp signal as a lower electrode that constitutes an MIM (Metal Insulator Metal) structure.

3. The solid-state imaging device according to claim 2, wherein the pixels arranged side by side in the direction in which the ramp signal line extends share the lower electrode constituting the MIM structure of the third capacitor.

4. A solid-state imaging device according to claim 3, wherein the upper electrode constituting the MIM structure of the third capacitor is used in common with the upper electrodes constituting the MIM structures of the first capacitor and the second capacitor.

5. The solid-state imaging device according to claim 4, wherein a plurality of the first capacitors are provided to hold pixel signals at reset levels corresponding to a plurality of brightness levels, and a plurality of the second capacitors are provided to hold pixel signals at pixel signal levels corresponding to a plurality of brightness levels.

6. The solid-state imaging device according to claim 5, wherein the upper electrodes of the plurality of first capacitors, the upper electrodes of the plurality of second capacitors, and the upper electrode of the third capacitor are shared.

7. The solid-state imaging device according to claim 3, further comprising a transistor provided between a first node which is a connection point between the pixel circuit and one end of the first capacitor, and a second node which is a connection point between one end of the second capacitor and one end of the third capacitor.

8. The solid-state imaging device according to claim 7, wherein the upper electrode constituting the MIM structure of the third capacitor is used in common with the upper electrode constituting the MIM structure of the second capacitor.

9. An electronic device having a solid-state imaging element comprising: a first capacitor that holds the voltage of a pixel signal of a reset level output from a pixel circuit; a second capacitor that holds the voltage of a pixel signal of a pixel signal level output from the pixel circuit; and a third capacitor that has one end connected to a connection point where one end of the first capacitor and one end of the second capacitor are connected and the other end connected to a signal line that supplies a ramp signal, and that forms a source follower circuit together with an amplification gate of the pixel circuit, wherein the first capacitor, the second capacitor, and the third capacitor are arranged in the same wiring layer.

10. A solid-state imaging device comprising a pixel having: a first capacitor that holds the voltage of a pixel signal of a reset level output from a pixel circuit; a second capacitor that holds the voltage of a pixel signal of a pixel signal level output from the pixel circuit; and a third capacitor that has one end connected to a connection point where one end of the first capacitor and one end of the second capacitor are connected and the other end connected to a signal line that supplies a ramp signal, and that forms a source follower circuit together with an amplification gate of the pixel circuit, wherein the first capacitor and the second capacitor are arranged in the same layer of a wiring layer, and the third capacitor is arranged in a layer of the wiring layer different from that of the first capacitor and the second capacitor.

11. The solid-state imaging device according to claim 10, wherein the third capacitor uses a ramp signal line that supplies the ramp signal as an upper electrode that constitutes an MIM (Metal Insulator Metal) structure.

12. The solid-state imaging device according to claim 11, wherein the upper electrode constituting the MIM structure of the third capacitor is used in common by the pixels arranged side by side in the direction in which the ramp signal line extends.

13. The solid-state imaging device according to claim 12, wherein the upper electrode constituting the MIM structure of the first capacitor and the second capacitor is shared.

14. The solid-state imaging device according to claim 12, wherein a lower electrode constituting the MIM structure of the third capacitor arranged on the upper side, and upper electrodes constituting the MIM structure of the first capacitor and the second capacitor arranged on the lower side, are connected to a connection point with the pixel circuit.

15. The solid-state imaging device according to claim 10, wherein the MIM structures constituting the first capacitor and the second capacitor are configured as a multi-layer structure of two or more layers, and the MIM structure constituting the third capacitor is configured as a multi-layer structure of two or more layers.

16. The solid-state imaging device according to claim 10, wherein a first semiconductor substrate on which the pixel circuit including a photoelectric conversion unit that performs photoelectric conversion to generate the pixel signal is provided, and a second semiconductor substrate on which a sample-and-hold circuit that holds the pixel signal is provided are at least stacked to form a laminated structure, and the front surface side of the first semiconductor substrate and the front surface side of the second semiconductor substrate are bonded, or the front surface side of the first semiconductor substrate and the back surface side of the second semiconductor substrate are bonded.

17. An electronic device having a pixel having: a first capacitor that holds the voltage of a pixel signal of a reset level output from a pixel circuit; a second capacitor that holds the voltage of a pixel signal of a pixel signal level output from the pixel circuit; and a third capacitor that has one end connected to a connection point where one end of the first capacitor and one end of the second capacitor are connected and the other end connected to a signal line that supplies a ramp signal, and that forms a source follower circuit together with an amplification gate of the pixel circuit; wherein the first capacitor and the second capacitor are arranged in the same layer of a wiring layer, and the third capacitor is arranged in a layer of the wiring layer different from that of the first capacitor and the second capacitor.

18. A solid-state imaging device comprising a pixel having: a first capacitor that holds the voltage of a pixel signal of a reset level output from a pixel circuit; a second capacitor that holds the voltage of a pixel signal of a pixel signal level output from the pixel circuit; and a third capacitor that has one end connected to a connection point where one end of the first capacitor and one end of the second capacitor are connected and the other end connected to a signal line that supplies a ramp signal, and that forms a source follower circuit together with an amplification gate of the pixel circuit; wherein a first semiconductor substrate on which the pixel circuit is provided, including a photoelectric conversion unit that performs photoelectric conversion to generate the pixel signal, and a second semiconductor substrate on which a sample and hold circuit that holds the pixel signal is provided, are configured in a laminated structure formed by at least laminating one another; and at least one or both of the first capacitor, the second capacitor, and the third capacitor uses a MOS (Metal-Oxide-Semiconductor) capacitor configured by arranging a MOS structure in a semiconductor layer of the second semiconductor substrate.

19. The solid-state imaging device according to claim 18, wherein the third capacitor is a MOS capacitor, and the first capacitor and the second capacitor are configured by an MIM (Metal Insulator Metal) structure provided in a wiring layer of the second semiconductor substrate.

20. An electronic device having a solid-state imaging element, comprising a pixel having: a first capacitor that holds the voltage of a pixel signal of a reset level output from a pixel circuit; a second capacitor that holds the voltage of a pixel signal of a pixel signal level output from the pixel circuit; and a third capacitor that has one end connected to a connection point where one end of the first capacitor and one end of the second capacitor are connected and the other end connected to a signal line that supplies a ramp signal, and that forms a source follower circuit together with an amplification gate of the pixel circuit; wherein the solid-state imaging element is configured in a layered structure formed by at least laminating a first semiconductor substrate on which the pixel circuit is provided, the first semiconductor substrate including a photoelectric conversion unit that performs photoelectric conversion to generate the pixel signal, and a second semiconductor substrate on which a sample-and-hold circuit that holds the pixel signal is provided; and wherein at least one or both of the first capacitor, the second capacitor, and the third capacitor use a MOS (Metal-Oxide-Semiconductor) capacitor configured by arranging a MOS structure in a semiconductor layer of the second semiconductor substrate.

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