Display device

Abstract

Disclosed in one or more embodiments of the present invention is a display device comprising: a substrate; light-emitting elements arranged on the substrate; and a bank layer including bank patterns arranged in an area between the light-emitting elements on a planar surface, wherein each of the bank patterns is a linear first bank pattern extending in correspondence with at least two light-emitting elements arranged in one direction on a planar surface, a linear second bank pattern encompassing at least a portion of one light-emitting element, or a third bank pattern having at least one closed-loop-shaped unit encompassing one light-emitting element.

Description

display device

[0001] One or more embodiments relate to a display device.

[0002] As display devices that visually display electrical signals evolve, a variety of display devices with superior characteristics, such as thinness, weight reduction, and low power consumption, are being introduced. For example, flexible display devices that can be folded or rolled are being introduced. Recently, active research and development is underway on display devices with diverse structures, such as stretchable display devices capable of transforming into various forms.

[0003] One or more embodiments provide a display device that displays high-quality images by reducing the area-specific luminous efficiency and color deviation due to the expansion of the display device. However, these aspects are exemplary and the scope of the present invention is not limited thereby.

[0004] In one or more embodiments of the present invention, a display device is disclosed, comprising: a substrate; light-emitting elements on the substrate; and a bank layer including bank patterns in a region between the light-emitting elements on a plane; wherein the bank patterns are a first linear bank pattern extending corresponding to at least two of the light-emitting elements arranged in one direction on the plane, a second linear bank pattern surrounding at least a portion of one of the light-emitting elements, or a third bank pattern having at least one closed-loop unit surrounding one of the light-emitting elements.

[0005] In one or more embodiments of the present invention, a display device is disclosed, comprising: a substrate; light-emitting elements on the substrate; and a bank layer defining openings corresponding to each of the light-emitting elements, the bank layer including first bank portions and second bank portions respectively disposed between the first bank portions or between the first bank portions and the openings; wherein in a plane, the first bank portions include bank patterns respectively disposed between the light-emitting elements, the bank patterns being a linear first bank pattern extending corresponding to at least two of the light-emitting elements arranged in one direction in the plane, a linear second bank pattern surrounding at least a portion of one of the light-emitting elements, or a third bank pattern having at least one closed-loop unit surrounding one of the light-emitting elements.

[0006] According to one or more embodiments of the present invention as described above, a display device capable of displaying high-quality images can be realized by reducing the deviation in luminous efficiency and color by region due to the expansion and contraction of the display device. Of course, the scope of the present invention is not limited by these effects.

[0007] FIG. 1 is a perspective view schematically illustrating a display device according to one or more embodiments of the present invention.

[0008] Figures 2a and 2b are perspective views showing the display device of Figure 1 extended in the first direction.

[0009] Figure 2c is a perspective view showing the display device of Figure 1 extended in the second direction.

[0010] Figure 2d is a perspective view showing the display device of Figure 1 extended in the first direction and the second direction.

[0011] Figure 2e is a perspective view showing the display device of Figure 1 extended in the third direction.

[0012] FIG. 3 is a schematic plan view of a display device according to one or more embodiments of the present invention.

[0013] FIG. 4 is a cross-sectional view schematically illustrating a display area of ​​a display device according to one or more embodiments of the present invention.

[0014] FIGS. 5A to 5C are equivalent circuit diagrams of subpixels of a display device according to one or more embodiments of the present invention, respectively.

[0015] FIGS. 6A and 6B are cross-sectional views schematically illustrating a light emitting element of a display device according to one or more embodiments of the present invention.

[0016] FIG. 7 is a plan view schematically illustrating a bank layer of a display device according to one or more embodiments of the present invention.

[0017] FIG. 8 is a cross-sectional view schematically illustrating a portion of a display device according to one or more embodiments of the present invention, taken along line A-A' of FIG. 7.

[0018] FIGS. 9A, 9B, and 9C are schematic plan views illustrating a bank layer of a display device according to one or more embodiments of the present invention.

[0019] FIG. 10 is a plan view schematically illustrating a bank layer of a display device according to one or more embodiments of the present invention.

[0020] FIG. 11 is a plan view schematically illustrating a bank layer of a display device according to one or more embodiments of the present invention.

[0021] FIG. 12 is a plan view schematically illustrating a bank layer of a display device according to one or more embodiments of the present invention.

[0022] FIG. 13 is a plan view schematically illustrating a bank layer of a display device according to one or more embodiments of the present invention.

[0023] FIG. 14 is a cross-sectional view schematically illustrating a portion of a display device according to one or more embodiments of the present invention, taken along line B-B' of FIG. 13.

[0024] FIGS. 15A to 15C are cross-sectional views schematically illustrating a portion of a display device according to one or more embodiments of the present invention.

[0025] FIGS. 16A to 16C are cross-sectional views schematically illustrating a portion of a display device according to one or more embodiments of the present invention.

[0026] FIG. 17 is a plan view schematically illustrating a display area of ​​a display device according to one or more embodiments of the present invention.

[0027] FIG. 18 is a plan view schematically illustrating a bank layer of a display device according to one or more embodiments of the present invention, and is an enlarged plan view of part C of FIG. 17.

[0028] FIGS. 19A to 19C are schematic plan views illustrating a display device according to one or more embodiments of the present invention.

[0029] FIGS. 20A to 20C are schematic plan views illustrating a display device according to one or more embodiments of the present invention.

[0030] FIGS. 21A to 21D are schematic plan views illustrating a display device according to one or more embodiments of the present invention.

[0031] FIGS. 22A to 22G are perspective views schematically illustrating embodiments of an electronic device including a display device according to one or more embodiments of the present invention.

[0032] The above multiple bank patterns may be spaced apart from each other.

[0033] The above first bank pattern may be at least partially folded.

[0034] The first bank pattern includes a first pattern portion and a second pattern portion extending in different directions, and a connecting portion connecting the first pattern portion and the second pattern portion, and the first pattern portion and the second pattern portion can be arranged alternately.

[0035] The above connecting portion may have a straight or curved shape.

[0036] The above second bank pattern may include a first pattern portion and a second pattern portion extending in different directions.

[0037] The first pattern portion and the second pattern portion may be connected or spaced apart from each other.

[0038] The above third bank pattern may include a plurality of third bank patterns connected to each other.

[0039] The above plurality of light-emitting elements may be inorganic light-emitting diodes.

[0040] The height from the upper surface of the substrate to the upper surface of one of the plurality of second bank portions may be less than the height from the upper surface of the substrate to the upper surface of one of the plurality of first bank portions.

[0041] One of the plurality of second bank portions of the bank layer includes a second-first bank portion and a second-second bank portion, and a height from the upper surface of the substrate to the upper surface of the second-second bank portion may be different from a height from the upper surface of the substrate to the upper surface of the second-first bank portion.

[0042] At least a portion of the bank layer may have a reverse tapered shape in cross-section.

[0043] Aspects of some embodiments of the present invention and methods for achieving them can be more readily understood by reference to the detailed description of the embodiments and the accompanying drawings. The described embodiments are provided by way of example so that this disclosure is thorough and complete, and fully conveys aspects of the present invention to those skilled in the art. Accordingly, processes, elements, and techniques that are redundant, irrelevant to the description of the embodiments, or unnecessary for those skilled in the art to fully understand aspects of the present invention may be omitted. Unless otherwise stated, similar reference numbers, letters, or combinations thereof throughout the accompanying drawings and written description represent similar elements, and thus a repetitive description thereof may be omitted.

[0044] The described embodiments may have various modifications and may be embodied in other forms, and should not be construed as limited to the embodiments described herein. The use of "can," "may," or "may not" when describing an embodiment is intended to encompass one or more embodiments of the present invention.

[0045] A person skilled in the art will understand that the invention encompasses all modifications, equivalents and substitutes within the spirit and technical scope of the invention, taking into account the entirety of the invention, and that each feature of the embodiments of the invention may be partially or wholly combined with one another, and that various technical interconnections and operations are possible, and that each embodiment may be implemented independently of one another, or may be implemented in conjunction with one another unless otherwise stated or implied.

[0046] The relative sizes of elements, layers, and regions in the drawings may be exaggerated for clarity and / or illustrative purposes. In other words, the sizes and thicknesses of elements in the drawings are arbitrarily depicted for convenience of explanation, and the present invention is not limited thereto. Furthermore, the use of crosshatching and / or shading in the accompanying drawings is generally provided to clarify boundaries between adjacent elements. Therefore, the presence or absence of crosshatching or shading does not convey or indicate any preference or requirement for any particular material, material property, dimension, proportion, commonality between the depicted elements, and / or any other characteristic, property, or property of the elements.

[0047] Various embodiments are described herein with reference to cross-sectional illustrations, which are schematic illustrations of embodiments and / or intermediate structures. Therefore, variations in the shapes of the illustrations are expected, for example, due to manufacturing techniques and / or tolerances. Furthermore, any specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of illustrating embodiments in accordance with the concepts of the present invention. Therefore, the embodiments disclosed herein should not be construed as being limited to the depicted shapes of elements, layers, or regions, but should encompass, for example, variations in shape resulting from manufacturing.

[0048] Spatially relative terms such as "beneath," "below," "lower," "lower side," "under," "above," "upper," "over," "higher," "upper side," "side" (e.g., "sidewall"), and the like may be used herein for ease of description to describe one element or feature in relation to another as depicted in the drawings. It will be understood that spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. For example, if the device in the drawings is turned over, an element described as being "below," "beneath," or "under" another element or feature would be positioned "above" the other element or feature. Thus, the example terms "below" or "under" can encompass both the above and below orientations. The device can be positioned in other orientations (e.g., rotated 90 degrees or in other directions) and the spatially relative descriptors used herein should be interpreted accordingly. Similarly, if a first part is described as being positioned "on" a second part, this can indicate that the first part is positioned above.

[0049] Additionally, the phrase "in plan view" means a top view of an object portion, and the phrase "in a schematic cross-section" means a side view of a schematic cross-section obtained by cutting vertically through an object portion. The terms "overlap" or "superimposed" mean that the first object can be above, below, or beside the second object, and vice versa. Furthermore, the term "overlap" can include stack, face, or facing, extending upward, covering, or partially covering, or other appropriate terms that a person of ordinary skill in the art would understand and recognize. The expression "non-overlap" can include meanings such as "apart from," "set apart," or "offset," and other appropriate equivalents that a person of ordinary skill in the art would understand and recognize. The terms "face" and "facing" can mean that the first object can directly or indirectly face the second object. If a third object intervenes between the first and second objects, the first and second objects can still be understood as facing each other, but indirectly opposing each other.

[0050] When an element, layer, region, or component is referred to as being "formed upon," "on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, it will be understood that it may be directly formed upon, connected to, or coupled to the other element, layer, region, or component, or may be indirectly formed upon, connected to, or coupled to the other element, layer, region, or component so that one or more intervening elements, layers, regions, or components may be present. Furthermore, this can collectively mean direct or indirect couplings or connections, and integral or non-integral couplings or connections. For example, when a layer, region, or component is referred to as being "electrically connected to" or "electrically coupled to" another layer, region, or component, it can be directly electrically connected to or coupled to the other layer, region, and / or component, or there may be one or more intervening layers, regions, or components present. The one or more intervening components may include switches, resistors, capacitors, and / or the like. When describing embodiments, the term "connection" refers to an electrical connection unless explicitly described as a direct connection, and "directly connected / directly coupled" or "directly over" means that one component directly connects or couples to or is over another component without any intermediate components.

[0051] Also, in the present specification, when a part of a layer, film, region, plate, etc. is formed on another part, the direction of formation is not limited to upward, and includes forming the part laterally or downwardly. On the other hand, when a part of a layer, film, region, plate, etc. is formed "under" another part, this includes not only the case where the part is "directly under" the other part, but also the case where there is another part between the part and the other part. Meanwhile, other expressions that describe the relationship between components, such as "between," "directly between," or "adjacent" and "directly adjacent," may be interpreted similarly. It will be understood that when an element or layer is referred to as being "between" two elements or layers, it may be the only element or layer between the two elements or layers, or there may be one or more intervening elements or layers.

[0052] For the purposes of this disclosure, when a list of elements is preceded by expressions such as "at least one," "any," or "one or more," they modify the list of elements as a whole and not any individual element of the list. For example, "at least one of X, Y, and Z," "at least one of X, Y, or Z," "at least one selected from the group consisting of X, Y, and Z," and "at least one selected from the group consisting of X, Y, or Z" can be interpreted as X alone, Y alone, Z alone, any combination of two or more of X, Y, and Z, for example, XYZ, XYY, YZ, and ZZ, or any variation thereof. Similarly, the expressions "at least one of A and B" and "at least one of A or B" can include A, B, or A and B. As used herein, "or" generally means "and / or," and the term "and / or" includes any combination of one or more associated listed items. For example, the expression "A and / or B" can include A, B, or A and B. Similarly, expressions such as "at least one," "a number," "one," and other prepositional phrases, when preceding a list of elements, modify the list as a whole and do not modify individual elements in the list. For example, "C to D" means "C or more and D or less," unless otherwise specified.

[0053] The terms "first," "second," "third," and the like may be used to describe various elements, components, regions, layers, and / or sections, but such elements, components, regions, layers, and / or sections should not be limited by these terms. These terms do not imply any particular order, position, or precedence, but are used only to distinguish one element, member, component, region, region, layer, section, or part from another element, member, component, region, region, layer, section, or part. Thus, a first element, component, region, layer, or section described below could be referred to as a second element, component, region, layer, or section without departing from the spirit and scope of this disclosure. Describing an element as being the "first" element may not require or imply the presence of a second element or other elements. The terms "first," "second," and the like may also be used to distinguish different categories or sets of elements. For brevity, the terms "first", "second", etc. may refer to "first category (or first set)", "second category (or second set)", etc., respectively.

[0054] In the embodiments, the x-axis, y-axis, and / or z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the x-axis, y-axis, and z-axis may be perpendicular to each other, or may represent directions other than perpendicular to each other. The same may apply to the first, second, and / or third directions.

[0055] The terminology used herein is for the purpose of describing embodiments only and is not intended to limit the disclosure. As used herein, the singular forms "a" and "an" are intended to include the plural forms as well, and the plural forms are intended to include the singular forms as well, unless the context clearly indicates otherwise.

[0056] It will also be better understood that the terms "comprises," "comprising," "has," "having," "includes," and "comprising" as used herein refer to the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0057] If one or more embodiments can be implemented differently, the order of specific processes may be performed differently from the order described. For example, two processes described in succession may be performed substantially simultaneously or in the reverse order described.

[0058] The terms "substantially," "about," "approximately," and similar terms, as used herein, are used in approximate terms and not in degrees, and are intended to account for the inherent variation in a measured or calculated value that would be recognizable by a person skilled in the art. For example, "substantially" can include a range of + / - 5% of that value. As used herein, "about" or "approximately" is inclusive of the stated value and means that it is within an acceptable range of variation for the particular value as determined by a person skilled in the art, taking into account the measurement in question and the error associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ± 30%, 20%, 10%, or 5% of the stated value. Additionally, use of "may" when describing embodiments of the present disclosure can mean "one or more embodiments of the present disclosure."

[0059] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with the relevant art and / or the context of this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined so herein.

[0060] FIG. 1 is a perspective view schematically illustrating a display device according to one or more embodiments of the present invention. FIGS. 2A and 2B are perspective views illustrating the display device of FIG. 1 extended in a first direction. FIG. 2C is a perspective view illustrating the display device of FIG. 1 extended in a second direction. FIG. 2D is a perspective view illustrating the display device of FIG. 1 extended in the first and second directions. FIG. 2E is a perspective view illustrating the display device of FIG. 1 extended in a third direction.

[0061] Referring to FIG. 1, a display device (1) may include a display area (DA) and a non-display area (NDA). The display area (DA) may include pixels. The display device (1) may provide a corresponding image using light emitted from the pixels. The non-display area (NDA) may be arranged outside the display area (DA). The non-display area (NDA) may entirely surround the display area (DA) (for example, on a plane).

[0062] The display device (1) can be extended or contracted in various directions. The display device (1) can be extended in a first direction (e.g., in the x-direction and / or the -x-direction) by an external force applied by an external object or a user. In one or more embodiments, as illustrated in FIGS. 2A and 2B, the display area (DA) and / or the non-display area (NDA) of the display device (1) can be extended in the first direction (e.g., in the x-direction and / or the -x-direction). For example, as illustrated in FIG. 2A, the display device (1) can be extended along the x-direction and the -x-direction, or as illustrated in FIG. 2B, one side of the display device (1) can be fixed and the display device (1) can be extended along the x-direction.

[0063] The display device (1) can be stretched in a second direction (e.g., the y-direction and / or the -y-direction) by an external force applied by an external object or a user. In one or more embodiments, the display area (DA) and / or the non-display area (NDA) of the display device (1) can be stretched in the y-direction and the -y-direction, as illustrated in FIG. 2C. In one or more other embodiments, one side of the display device (1) can be fixed while being stretched in the y-direction or the -y-direction.

[0064] The display device (1) can be extended in a plurality of directions, for example, a first direction (e.g., the x-direction and / or the -x-direction) and a second direction (e.g., the y-direction and / or the -y-direction) by an external force applied by an external object or a part of a human body. As illustrated in Fig. 2d, the display area (DA) and / or the non-display area (NDA) of the display device (1) can be extended in the ±x-direction and the ±y-direction.

[0065] The display device (1) can be elongated in a third direction (e.g., the z-direction or the -z-direction) by an external force applied by an external object or a part of a human body. In one or more embodiments, FIG. 2e illustrates that a part of the display device (1), for example, a part of the display area (DA), protrudes in the z-direction. In one or more other embodiments, a part of the display device (1), for example, a part of the display area (DA), can protrude along the -z-direction (or recess along the z-direction).

[0066] Although FIGS. 2A to 2E illustrate the display device (1) extending in the first, second, and / or third directions, the present invention is not limited thereto. In one or more other embodiments, the display device (1) may be variously deformed into an irregular shape, such as being bent or twisted along two or more axes.

[0067] FIG. 3 is a schematic plan view of a display device according to one or more embodiments of the present invention.

[0068] Referring to FIG. 3, pixels may be arranged in a display area (DA) of a display device (1). Each pixel may include subpixels that emit light of different colors. Light-emitting elements corresponding to each subpixel may be arranged in the display area (DA). A circuit for providing electrical signals to the light-emitting elements arranged in the display area (DA) and to transistors electrically connected to the light-emitting elements may be located in a non-display area (NDA) surrounding the display area (DA). A gate driving circuit (GDC) may be arranged in a first non-display area (NDA1) and a second non-display area (NDA2) arranged on both sides of the display area (DA). The gate driving circuit (GDC) may include drivers for providing electrical signals to gate electrodes of each of the transistors electrically connected to the light-emitting elements. Although FIG. 3 illustrates that a gate driving circuit (GDC) is disposed in each of the first non-display area (NDA1) and the second non-display area (NDA2), the present invention is not limited thereto. In one or more other embodiments, the gate driving circuit (GDC) may be disposed in either the first non-display area (NDA1) or the second non-display area (NDA2).

[0069] The data drive circuit (DDC) may be disposed in a third non-display area (NDA3) and / or a fourth non-display area (NDA4) connecting the first non-display area (NDA1) and the second non-display area (NDA2). In one or more embodiments, FIG. 3 illustrates that the data drive circuit (DDC) is disposed in the fourth non-display area (NDA4). In one or more other embodiments, the data drive circuit (DDC) may be disposed in each of the third non-display area (NDA3) and the fourth non-display area (NDA4).

[0070] Although Fig. 3 illustrates that the data drive circuit (DDC) is arranged in the fourth non-display area (NDA4) of the display device (1), the present invention is not limited thereto. In one or more other embodiments, the display device (1) may further include a flexible circuit board electrically connected through a terminal portion arranged in the fourth non-display area (NDA4), and the data drive circuit (DDC) may be arranged on the aforementioned flexible circuit board.

[0071] In some embodiments, the elongation rate of the non-display area (NDA) may be equal to or less than the elongation rate of the display area (DA). In one or more embodiments, the elongation rates of the non-display areas (NDAs) may be different for each area. For example, the first non-display area (NDA1), the second non-display area (NDA2), and the third non-display area (NDA3) may have substantially the same elongation rates, but the elongation rate of the fourth non-display area (NDA4) may be less than the elongation rates of each of the first non-display area (NDA1), the second non-display area (NDA2), and the third non-display area (NDA3).

[0072] FIG. 4 is a cross-sectional view schematically illustrating a display area of ​​a display device according to one or more embodiments of the present invention.

[0073] Referring to FIG. 4, the display device (1) may include a substrate (100) and subpixels arranged on a display area (DA) of the substrate (100). Each of the subpixels may include a light-emitting element (LED) and a circuit for driving the light-emitting element (LED) electrically connected thereto, such as a pixel driving circuit (PC). In addition, the display device (1) may include a wiring (WL) electrically connected to the pixel driving circuit (PC). The wiring (WL) may be a signal line (e.g., a gate line, a data line, etc.) for providing an electrical signal to a transistor included in the pixel driving circuit (PC) or a voltage line (e.g., a driving voltage line, an initialization voltage line, etc.) for providing a voltage.

[0074] The substrate (100) may be a stretchable substrate that can expand or contract in a corresponding direction. The substrate (100) may include an insulating material such as glass, quartz, or a polymer resin. The substrate (100) may include an elastomer. The elastomer may include an organic elastomer, an organic-inorganic elastomer, or a combination thereof. For example, the substrate (100) may include a silicone-based elastomer such as polydimethylsiloxane, a styrene-based elastomer, an olefin-based elastomer, polyurethane, or a mixture thereof. The substrate (100) may have a single-layer or multi-layer structure.

[0075] A buffer layer (111) including an inorganic insulating material may be positioned on a substrate (100), and a pixel driver circuit (PC) and a wiring (WL) may be disposed on the buffer layer (111). An insulating layer (IL) including an inorganic insulating material and / or an organic insulating material may be positioned between both the pixel driver circuit (PC) and the wiring (WL) and the light emitting elements (LEDs). The light emitting elements (LEDs) may be positioned on the insulating layer (IL) and may be electrically connected to corresponding pixel driver circuits (PCs). The light emitting elements (LEDs) may emit light of different colors or the same color. In one or more embodiments, the light emitting elements (LEDs) may emit red, green, and blue light, respectively. In some embodiments, the light emitting elements (LEDs) may emit white light. In one or more other embodiments, the light emitting elements (LEDs) may emit red, green, blue, and white light, respectively.

[0076] The encapsulation layer (400) may be positioned on the light emitting element (LED) and may protect the light emitting element (LED) from external force and / or moisture permeation. The encapsulation layer (400) may include an inorganic encapsulation layer and / or an organic encapsulation layer. In some embodiments, the encapsulation layer (400) may include a structure in which an inorganic encapsulation layer including an inorganic insulating material, an organic encapsulation layer including an organic insulating material, and an inorganic encapsulation layer including an inorganic insulating material are sequentially laminated. In one or more other embodiments, the encapsulation layer (400) may include an organic material such as a resin. In some embodiments, the encapsulation layer (400) may include urethane epoxy acrylate. The encapsulation layer (400) may include a photosensitive material, for example, a material such as a photoresist.

[0077] FIGS. 5A to 5C are equivalent circuit diagrams of subpixels of a display device according to one or more embodiments of the present invention, respectively.

[0078] Referring to FIG. 5a, a light emitting element (LED) corresponding to a subpixel is electrically connected to a pixel driver circuit (PC), and the pixel driver circuit (PC) may include a first transistor (T1), a second transistor (T2), and a storage capacitor (Cst). The pixel driver circuit (PC) may be electrically connected to a signal line and a voltage line. The signal line may include a gate line such as a first scan line (SL1) and a data line (DL), and the voltage line may include a first voltage line (VDDL).

[0079] The second transistor (T2) can be electrically connected to the first scan line (SL1) and the data line (DL). The first scan line (SL1) can provide a first scan signal (GW) to a gate electrode of the second transistor (T2). The second transistor (T2) can transmit a data signal (Dm) input from the data line (DL) to the first transistor (T1) according to the first scan signal (GW) input from the first scan line (SL1).

[0080] The storage capacitor (Cst) is electrically connected to the second transistor (T2) and the first voltage line (VDDL), and can store a voltage corresponding to the difference between the voltage received from the second transistor (T2) and the first power voltage (VDD) supplied by the first voltage line (VDDL).

[0081] The first transistor (T1) is a driving transistor and can control a driving current flowing through a light-emitting element (LED). The first transistor (T1) can be connected to a first voltage line (VDDL) and a storage capacitor (Cst). The first transistor (T1) can control a driving current flowing through the light-emitting element (LED) from the first voltage line (VDDL) in response to a voltage value stored in the storage capacitor (Cst). The light-emitting element (LED) can emit light having a corresponding brightness according to the driving current. A first electrode of the light-emitting element (LED) can be electrically connected to the first transistor (T1), and a second electrode can be electrically connected to a second voltage line (VSSL) that supplies a second power voltage (VSS).

[0082] Although FIG. 5a illustrates that the pixel driver circuit (PC) includes two transistors and one storage capacitor, in one or more other embodiments, the pixel driver circuit (PC) may include three or more transistors.

[0083] Referring to FIG. 5b, the pixel driving circuit unit (PC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), and a storage capacitor (Cst).

[0084] The pixel driver circuit (PC) is electrically connected to signal lines and voltage lines. The signal lines may include gate lines such as a first scan line (SL1), a second scan line (SL2), a third scan line (SL3), and an emission control line (EML), and a data line (DL). The voltage lines may include first and second initialization voltage lines (VIL1, VIL2) and a first voltage line (VDDL).

[0085] The first voltage line (VDDL) can transmit the first power voltage (VDD) to the first transistor (T1). The first initialization voltage line (VIL1) can transmit the first initialization voltage (Vint) that initializes the first transistor (T1) to the pixel driver circuit (PC). The second initialization voltage line (VIL2) can transmit the second initialization voltage (Vaint) that initializes the first electrode of the light-emitting element (LED) to the pixel driver circuit (PC).

[0086] The first transistor (T1) may be electrically connected to the first voltage line (VDDL) via the fifth transistor (T5) and may be electrically connected to the light-emitting element (LED) via the sixth transistor (T6). The first transistor (T1) functions as a driving transistor, and receives a data signal (Dm) according to the switching operation of the second transistor (T2) to supply a driving current to the light-emitting element (LED).

[0087] The second transistor (T2) is a data writing transistor and is electrically connected to the first scan line (SL1) and the data line (DL). The second transistor (T2) is electrically connected to the first voltage line (VDDL) via the fifth transistor (T5). The second transistor (T2) is turned on in response to the first scan signal (GW) received through the first scan line (SL1) and performs a switching operation to transmit the data signal (Dm) transmitted to the data line (DL) to the first node (N1).

[0088] The third transistor (T3) is electrically connected to the first scan line (SL1) and is electrically connected to the light-emitting element (LED) via the sixth transistor (T6). The third transistor (T3) can be turned on in response to the first scan signal (GW) received through the first scan line (SL1) to diode-connect the first transistor (T1).

[0089] The fourth transistor (T4) is a first initialization transistor and is electrically connected to the third scan line (SL3) and the first initialization voltage line (VIL1). The fourth transistor (T4) is turned on according to the third scan signal (GI) received through the third scan line (SL3) and transmits the first initialization voltage (Vint) from the first initialization voltage line (VIL1) to the gate electrode of the first transistor (T1) to initialize the voltage of the gate electrode of the first transistor (T1). The third scan signal (GI) may correspond to the first scan signal of another pixel driver circuit unit arranged in the previous row of the corresponding pixel driver circuit unit (PC).

[0090] The fifth transistor (T5) may be a motion control transistor, and the sixth transistor (T6) may be a light-emitting control transistor. The fifth transistor (T5) and the sixth transistor (T6) are electrically connected to the light-emitting control line (EML), and are turned on simultaneously or substantially simultaneously according to the light-emitting control signal (EM) transmitted through the light-emitting control line (EML), thereby forming a current path so that a driving current can flow from the first voltage line (VDDL) toward the light-emitting element (LED).

[0091] The seventh transistor (T7) is a second initialization transistor and can be electrically connected to the second scan line (SL2), the second initialization voltage line (VIL2), and the sixth transistor (T6). The seventh transistor (T7) is turned on according to the second scan signal (GB) transmitted through the second scan line (SL2), and can transmit the second initialization voltage (Vaint) from the second initialization voltage line (VIL2) to the first electrode of the light-emitting element (LED) to initialize the first electrode of the light-emitting element (LED).

[0092] The storage capacitor (Cst) includes a first capacitor electrode (CE1) and a second capacitor electrode (CE2). The first capacitor electrode (CE1) is electrically connected to the gate electrode of the first transistor (T1), and the second capacitor electrode (CE2) is electrically connected to the first voltage line (VDDL). The storage capacitor (Cst) can maintain the voltage applied to the gate electrode of the first transistor (T1) by storing and maintaining a voltage corresponding to the difference between the voltages at both ends of the first voltage line (VDDL) and the gate electrode of the first transistor (T1).

[0093] Referring to FIG. 5c, the pixel driving circuit unit (PC) may include a first transistor (T1), a second transistor (T2), a third transistor (T3), a fourth transistor (T4), a fifth transistor (T5), a sixth transistor (T6), a seventh transistor (T7), an eighth transistor (T8), a ninth transistor (T9), a storage capacitor (Cst), and an auxiliary capacitor (Ca).

[0094] The pixel driver circuit (PC) is electrically connected to signal lines and voltage lines. The signal lines may include gate lines such as a first scan line (SL1), a second scan line (SL2), a third scan line (SL3), and an emission control line (EML), and a data line (DL). The voltage lines may include first and second initialization voltage lines (VIL1, VIL2), a sustain voltage line (VSL), and a first voltage line (VDDL).

[0095] The first voltage line (VDDL) can transmit a first power voltage (VDD) to the first transistor (T1). The first initialization voltage line (VIL1) can transmit a first initialization voltage (Vint) for initializing the first transistor (T1) to the pixel driver circuit (PC). The second initialization voltage line (VIL2) can transmit a second initialization voltage (Vaint) for initializing the first electrode of the light-emitting element (LED) to the pixel driver circuit (PC). The sustain voltage line (VSL) can provide a sustain voltage (VSUS) to the second node (N2), for example, the second capacitor electrode (CE2) of the storage capacitor (Cst), during the initialization period and the data writing period.

[0096] The first transistor (T1) may be electrically connected to the first voltage line (VDDL) via the fifth transistor (T5) and the eighth transistor (T8), and may be electrically connected to the light-emitting element (LED) via the sixth transistor (T6). The first transistor (T1) functions as a driving transistor, and may receive a data signal (Dm) according to the switching operation of the second transistor (T2) to supply a driving current to the light-emitting element (LED).

[0097] The second transistor (T2) is electrically connected to the first scan line (SL1) and the data line (DL), and is electrically connected to the first voltage line (VDDL) via the fifth transistor (T5) and the eighth transistor (T8). The second transistor (T2) is turned on in response to the first scan signal (GW) received through the first scan line (SL1) and performs a switching operation to transmit the data signal (Dm) transmitted to the data line (DL) to the first node (N1).

[0098] The third transistor (T3) is electrically connected to the first scan line (SL1) and is electrically connected to the light-emitting element (LED) via the sixth transistor (T6). The third transistor (T3) is turned on in response to the first scan signal (GW) received through the first scan line (SL1), thereby diode-connecting the first transistor (T1), thereby compensating for the threshold voltage of the first transistor (T1).

[0099] The fourth transistor (T4) is electrically connected to the third scan line (SL3) and the first initialization voltage line (VIL1), and is turned on in response to the third scan signal (GI) transmitted through the third scan line (SL3) to transmit the first initialization voltage (Vint) from the first initialization voltage line (VIL1) to the gate electrode of the first transistor (T1) to initialize the voltage of the gate electrode of the first transistor (T1). The third scan signal (GI) may correspond to the first scan signal of another pixel driving circuit unit arranged in the previous row of the corresponding pixel driving circuit unit (PC).

[0100] The fifth transistor (T5), the sixth transistor (T6), and the eighth transistor (T8) are electrically connected to the emission control line (EML), and are turned on simultaneously or substantially simultaneously in response to the emission control signal (EM) transmitted through the emission control line (EML), thereby forming a current path so that a driving current can flow from the first voltage line (VDDL) toward the light-emitting element (LED).

[0101] The seventh transistor (T7) is a second initialization transistor and can be electrically connected to the second scan line (SL2), the second initialization voltage line (VIL2), and the sixth transistor (T6). The seventh transistor (T7) is turned on in response to the second scan signal (GB) received through the second scan line (SL2) and transmits the second initialization voltage (Vaint) from the second initialization voltage line (VIL2) to the first electrode of the light-emitting element (LED) to initialize the first electrode of the light-emitting element (LED).

[0102] The ninth transistor (T9) can be electrically connected to the second scan line (SL2), the second capacitor electrode (CE2) of the storage capacitor (Cst), and the sustain voltage line (VSL). The ninth transistor (T9) is turned on according to the second scan signal (GB) transmitted through the second scan line (SL2), and can transmit the sustain voltage (VSUS) to the second node (N2), for example, the second capacitor electrode (CE2) of the storage capacitor (Cst), during the initialization section and the data writing section.

[0103] The eighth transistor (T8) and the ninth transistor (T9) may be electrically connected to a second node (N2), for example, a second capacitor electrode (CE2) of a storage capacitor (Cst), respectively. In some embodiments, the eighth transistor (T8) may be turned off and the ninth transistor (T9) may be turned on in an initialization period and a data writing period, and the eighth transistor (T8) may be turned on and the ninth transistor (T9) may be turned off in an emission period. Since the sustain voltage (VSUS) is transmitted to the second node (N2) in the initialization period and the data writing period, the uniformity of the luminance (e.g., LRU, Long Range Uniformity) of the display device according to the voltage drop of the first voltage line (VDDL) may be improved.

[0104] The storage capacitor (Cst) includes a first capacitor electrode (CE1) and a second capacitor electrode (CE2). The first capacitor electrode (CE1) is electrically connected to the gate electrode of the first transistor (T1), and the second capacitor electrode (CE2) is electrically connected to the eighth transistor (T8) and the ninth transistor (T9).

[0105] The auxiliary capacitor (Ca) can be electrically connected to the sixth transistor (T6), the sustain voltage line (VSL), and the first electrode of the light-emitting element (LED). The auxiliary capacitor (Ca) stores and maintains a voltage corresponding to a voltage difference between the first electrode of the light-emitting element (LED) and the sustain voltage line (VSL) while the seventh transistor (T7) and the ninth transistor (T9) are turned on, thereby preventing or reducing the problem of black luminance increasing when the sixth transistor (T6) is turned off.

[0106] FIG. 6A is a cross-sectional view schematically illustrating a light emitting element of a display device according to one or more embodiments of the present invention.

[0107] Referring to FIG. 6A, a light-emitting element (LED, FIG. 4) according to one or more embodiments of the present invention may include an organic light-emitting diode (220) including an organic material. The organic light-emitting diode (220) may include a first electrode (221) positioned on an insulating layer, a second electrode (225) facing the first electrode (221), and a light-emitting layer (223) positioned between the first electrode (221) and the second electrode (225). A first functional layer (222) may be positioned between the first electrode (221) and the light-emitting layer (223), and a second functional layer (224) may be positioned between the light-emitting layer (223) and the second electrode (225).

[0108] A bank layer (BKL) may be positioned on an insulating layer (IL, FIG. 4) on which an organic light-emitting diode (220) is positioned. The edge of the first electrode (221) may be covered by the bank layer (BKL). The bank layer (BKL) may include an opening (B-OP) overlapping the central portion of the first electrode (221).

[0109] The bank layer (BKL) comprises an inorganic material and / or an organic material and may be formed as a single layer or multiple layers. In one or more embodiments, the bank layer (BKL) may comprise a light-shielding material, such as a black matrix material. In one or more embodiments, the bank layer (BKL) may be a light-shielding layer.

[0110] The first electrode (221) may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). In one or more other embodiments, the first electrode (221) may include a reflective layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds thereof. In one or more other embodiments, the first electrode (221) may further include a layer formed of ITO, IZO, ZnO, AZO or In2O3 above / below the aforementioned reflective layer.

[0111] The light-emitting layer (223) may include a polymer or low-molecular organic material that emits light of a corresponding color. The first functional layer (222) may include a hole transport layer (HTL) and / or a hole injection layer (HIL). The second functional layer (224) may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0112] The second electrode (225) may be formed of a conductive material having a low work function. For example, the second electrode (225) may include a (semi-)transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof. Alternatively, the second electrode (225) may further include a layer such as ITO, IZO, ZnO, AZO, or In2O3 on the (semi-)transparent layer including the aforementioned material.

[0113] FIG. 6b is a cross-sectional view schematically illustrating a light emitting element of a display device according to one or more embodiments of the present invention.

[0114] Referring to FIG. 6b, a light emitting element (LED, FIG. 4) according to one or more embodiments of the present invention may include an inorganic light emitting diode (230) including an inorganic material. The inorganic light emitting diode (230) may include a first semiconductor layer (231), a second semiconductor layer (232), an intermediate layer (233) between the first semiconductor layer (231) and the second semiconductor layer (232), a first electrode (235) electrically connected to the first semiconductor layer (231), and a second electrode (238) electrically connected to the second semiconductor layer (232). The first electrode (235) and the second electrode (238) of the inorganic light emitting diode (230) may be electrically connected to a first electrode pad (241) and a second electrode pad (242), respectively, which are disposed on the same layer.

[0115] In one or more embodiments, the inorganic light-emitting diode (230) may be a micro light-emitting diode.

[0116] A bank layer (BPL) may be positioned on an insulating layer (IL, FIG. 4) on which inorganic light-emitting diodes (230) are positioned. The bank layer (BPL) may expose the inorganic light-emitting diodes (230). On a plane, the bank layer (BPL) may include patterns arranged in an area between the inorganic light-emitting diodes (230) or may have openings corresponding to each of the inorganic light-emitting diodes (230).

[0117] FIG. 6b illustrates that the bank layer (BPL) is arranged adjacent to the inorganic light-emitting diode (230) and covers a portion of the first electrode pad (241) and / or a portion of the second electrode pad (242), but the present invention is not limited thereto. In one or more other embodiments, the bank layer (BPL) may be spaced apart from the first electrode pad (241) and the second electrode pad (242).

[0118] The bank layer (BPL) comprises an inorganic material and / or an organic material and may be formed as a single layer or multiple layers. In one or more embodiments, the bank layer (BPL) may comprise a light-shielding material, such as a black matrix material. In one or more embodiments, the bank layer (BPL) may be a light-shielding layer.

[0119] In some embodiments, the first semiconductor layer (231) may include a p-type semiconductor layer. The p-type semiconductor layer may be selected from semiconductor materials having a composition formula of InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), such as GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and may be doped with a p-type dopant such as Mg, Zn, Ca, Sr, or Ba.

[0120] The second semiconductor layer (232) may include, for example, an n-type semiconductor layer. The n-type semiconductor layer may be selected from semiconductor materials having a composition formula of InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), such as GaN, AlN, AlGaN, InGaN, InN, InAlGaN, AlInN, etc., and may be doped with an n-type dopant such as Si, Ge, or Sn.

[0121] The intermediate layer (233) is a region where electrons and holes recombine, and as the electrons and holes recombine, they transition to a lower energy level and can generate light having a corresponding wavelength. The intermediate layer (233) can be formed by including, for example, a semiconductor material having a composition formula of InxAlyGa1-x-yN (0≤x≤1, 0≤y≤1, 0≤x+y≤1), and can be formed as a single quantum well structure or a multi-quantum well structure (MQW). In addition, it may include a quantum wire structure or a quantum dot structure.

[0122] Although FIG. 6b illustrates that the first semiconductor layer (231) includes a p-type semiconductor layer and the second semiconductor layer (232) includes an n-type semiconductor layer, the present invention is not limited thereto. In one or more other embodiments, the first semiconductor layer (231) may include an n-type semiconductor layer and the second semiconductor layer (232) may include a p-type semiconductor layer.

[0123] Fig. 7 is a plan view schematically illustrating a bank layer of a display device according to one or more embodiments of the present invention. Fig. 8 is a cross-sectional view schematically illustrating a portion of a display device according to one or more embodiments of the present invention, taken along line A-A' of Fig. 7. In Figs. 7 and 8, the same reference numerals as in Figs. 4 and 6b denote the same members, and duplicate descriptions thereof will be omitted.

[0124] Fig. 7 illustrates a portion of a display area (DA), in which light-emitting elements (LEDs) may be arranged. In this regard, Fig. 7 illustrates first to third light-emitting elements (LED1, LED2, LED3). The first to third light-emitting elements (LED1, LED2, LED3) may each emit light of a different color. For example, the first light-emitting element (LED1) may emit red light, the second light-emitting element (LED2) may emit blue light, and the third light-emitting element (LED3) may emit green light. In one or more embodiments, the light-emitting elements (LEDs) may be inorganic light-emitting diodes (230).

[0125] In the display area (DA), the first to third light-emitting elements (LED1, LED2, LED3) of red, blue, and green may be repeatedly arranged. In one or more embodiments, the first to third light-emitting elements (LED1, LED2, LED3) may be arranged in a pentile structure, for example, a diamond pentile structure (e.g., a PENTILE™ type or a Diamond Pixel™ type structure, where PENTILE™ and Diamond Pixel™ are registered trademarks of Samsung Display Co., Ltd. of the Republic of Korea), as illustrated in FIG. 7. In one or more other embodiments, the first to third light-emitting elements (LED1, LED2, LED3) may be arranged in various arrangement structures, such as a stripe structure and a delta structure.

[0126] In FIG. 7, the first to third light-emitting elements (LED1, LED2, LED3) are illustrated as having a polygonal shape, for example, a rhombus shape, on a plane, but are not limited thereto, and in one or more other embodiments, the first to third light-emitting elements (LED1, LED2, LED3) may have a curved shape that does not have an edge or corner portion where a straight line meets another straight line on a plane. For example, the first to third light-emitting elements (LED1, LED2, LED3) may have an elliptical shape, a part circular, and a part elliptical on a plane.

[0127] The bank layer (BPL, FIG. 8) may be positioned on an insulating layer (IL) on which light emitting elements (LEDs) are positioned. In a plane, the bank layer (BPL) includes bank patterns (BPs), and the bank patterns (BPs) may be positioned in an area between the light emitting elements (LEDs). The bank patterns (BPs) may be positioned spaced apart from the light emitting elements (LEDs).

[0128] Each of the bank patterns (BP) may be an extended linear pattern corresponding to at least two light emitting elements (LEDs) arranged in one direction (hereinafter referred to as a “first bank pattern”), a linear pattern surrounding at least a portion of one light emitting element (LED) (hereinafter referred to as a “second bank pattern”), or a pattern including at least one closed loop-shaped unit surrounding one light emitting element (LED) (hereinafter referred to as a “third bank pattern”).

[0129] The bank patterns (BP) may include a first pattern (BPa) and a second pattern (BPb). The first pattern (BPa) and the second pattern (BPb) may be arranged spaced apart from each other.

[0130] Each of the first pattern (BPa) and the second pattern (BPb) may be a first bank pattern. As illustrated in FIG. 7, each of the first pattern (BPa) and the second pattern (BPb) may be a linear pattern extending corresponding to (e.g., passing between or beside) at least two light emitting elements (LEDs) arranged in a first direction (e.g., in the x-direction). The first pattern (BPa) and the second pattern (BPb) may generally be spaced apart from each other in a second direction (e.g., in the y-direction) that is substantially perpendicular to the first direction (e.g., in the x-direction). In one or more other embodiments, each of the first pattern (BPa) and the second pattern (BPb) may be a linear pattern extending corresponding to at least two light emitting elements (LEDs) arranged in the second direction (e.g., in the y-direction). The first pattern (BPa) and the second pattern (BPb) may be spaced apart from each other in a first direction (e.g., x direction) that is substantially perpendicular to the second direction (e.g., y direction).

[0131] Each of the first pattern (BPa) and the second pattern (BPb) may be bent at least partially. For example, each of the first pattern (BPa) and the second pattern (BPb) may have a zigzag shape in the longitudinal direction (e.g., the x-direction).

[0132] In other words, the first pattern (BPa) may include a first pattern portion (a1) and a second pattern portion (a2) extending in different directions, respectively. Each of the first pattern portion (a1) and the second pattern portion (a2) may extend so as to be inclined at a corresponding angle with respect to the first direction (e.g., the x-direction). The first pattern (BPa) may include a connecting portion (a3) ​​connecting the first pattern portion (a1) and the second pattern portion (a2).

[0133] The first pattern portion (a1) and the second pattern portion (a2) may be linear and / or curved. In Fig. 7, the first pattern portion (a1) and the second pattern portion (a2) are illustrated as being linear, but in one or more other embodiments, the first pattern portion (a1) and the second pattern portion (a2) may be curved. The connecting portion (a3) ​​may be linear or curved. In Fig. 7, the first pattern portion (a1) and the second pattern portion (a2) are illustrated as being generally linearly connected at the connecting portion (a3), but in one or more other embodiments, the first pattern portion (a1) and the second pattern portion (a2) may be curvedly connected at the connecting portion (a3).

[0134] Similarly, the second pattern (BPb) may include a first pattern portion (b1) and a second pattern portion (b2) extending in different directions. The first pattern portion (b1) and the second pattern portion (b2) may extend at corresponding angles with respect to the first direction (e.g., the x-direction). The second pattern (BPb) may include a connecting portion (b3) connecting the first pattern portion (b1) and the second pattern portion (b2).

[0135] The first pattern portion (b1) and the second pattern portion (b2) may be linear and / or curved. In Fig. 7, the first pattern portion (b1) and the second pattern portion (b2) are generally linear, but in one or more other embodiments, the first pattern portion (b1) and the second pattern portion (b2) may also be curved. The connecting portion (b3) may be linear or curved. In Fig. 7, the first pattern portion (b1) and the second pattern portion (b2) are shown as being linearly connected at the connecting portion (b3), but in one or more other embodiments, the first pattern portion (b1) and the second pattern portion (b2) may be curvedly connected at the connecting portion (b3).

[0136] In one or more embodiments, the angle (θ1) between the first pattern portion (a1) and the second pattern portion (a2) of the first pattern (BPa) may be different from the angle (θ2) between the first pattern portion (b1) and the second pattern portion (b2) of the second pattern (BPb). For example, the angle (θ1) between the first pattern portion (a1) and the second pattern portion (a2) of the first pattern (BPa) may be smaller than the angle (θ2) between the first pattern portion (b1) and the second pattern portion (b2) of the second pattern (BPb). However, the present invention is not limited thereto. In one or more other embodiments, the angle (θ1) between the first pattern portion (a1) and the second pattern portion (a2) of the first pattern (BPa) may be substantially equal to the angle (θ2) between the first pattern portion (b1) and the second pattern portion (b2) of the second pattern (BPb).

[0137] In one or more embodiments, each of the first pattern (BPa) and the second pattern (BPb) may extend continuously to both edges of the display area (DA). However, the present invention is not limited thereto. In one or more other embodiments, each of the first pattern (BPa) and the second pattern (BPb) may include sub-patterns that are arranged to both edges of the display area (DA) but are spaced apart from each other. Each of the sub-patterns may include a linear pattern extending corresponding to at least two light-emitting elements (LEDs).

[0138] The bank patterns (BP) may include a structure in which each of the first pattern (BPa) and the second pattern (BPb) is repeated at regular intervals. For example, the first pattern (BPa) may be arranged between a first row in which the third light-emitting elements (LED3) are arranged and a second row in which the first light-emitting elements (LED1) and the second light-emitting elements (LED2) are arranged in an alternating manner. The second pattern (BPb) may be arranged between a second row in which the first light-emitting elements (LED1) and the second light-emitting elements (LED2) are arranged in an alternating manner and a third row in which the third light-emitting elements (LED3) are arranged. Additionally, the first pattern (BPa) may be arranged between the third row in which the third light-emitting elements (LED3) are arranged and the fourth row in which the first light-emitting elements (LED1) and the second light-emitting elements (LED2) are arranged in an alternating manner, and the second pattern (BPb) may be arranged between the fourth row in which the first light-emitting elements (LED1) and the second light-emitting elements (LED2) are arranged in an alternating manner and the fifth row in which the third light-emitting elements (LED3) are arranged.

[0139] Referring to the laminated structure of FIG. 8, a buffer layer (111) may be positioned on the substrate (100). The buffer layer (111) may prevent or reduce the penetration of impurities from the substrate (100) and provide a flat base surface to the first pixel driving circuit unit (PC1) and the second pixel driving circuit unit (PC2) positioned on the buffer layer (111). The buffer layer (111) may include an organic insulating material and / or an inorganic insulating material and may have a single-layer or multi-layer structure.

[0140] A first pixel driving circuit unit (PC1) and a second pixel driving circuit unit (PC2) may be positioned on the buffer layer (111). The first pixel driving circuit unit (PC1) and the second pixel driving circuit unit (PC2) may each include a thin film transistor (TFT) and a storage capacitor (Cst). The thin film transistor (TFT) may include a semiconductor layer (Act), a gate electrode (GE), a source electrode (SE), and a drain electrode (DE). The storage capacitor (Cst) may include a first capacitor electrode (CE1) and a second capacitor electrode (CE2).

[0141] A semiconductor layer (Act) of a thin film transistor (TFT) may be positioned on the buffer layer (111). The semiconductor layer (Act) may include a channel region and impurity regions arranged on both sides of the channel region. One of the impurity regions arranged on each side of the channel region may correspond to a source region, and the other may correspond to a drain region. The semiconductor layer (Act) may include a semiconductor material. The semiconductor material may be a silicon-based semiconductor material, an oxide-based semiconductor material, a carbon nanotube, or an organic semiconductor material.

[0142] The silicon-based semiconductor material may include amorphous silicon or polysilicon. The oxide-based semiconductor material may include an oxide of at least one material selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce), and / or zinc (Zn). The oxide-based semiconductor material may be In-Ga-Zn-O (IGZO), In-Sn-Zn-O (ITZO), or In-Ga-Sn-Zn-O (IGTZO), which contain a metal such as indium (In), gallium (Ga), and / or tin (Sn) in ZnO.

[0143] Organic semiconductor materials can be either semiconductor low molecular weight materials or semiconductor high molecular weight materials. For example, the organic semiconductor material may be selected from the group consisting of pentacene, tetracene, anthracene, naphthalene, flullerene, alpha-6-thiophene, alpha-4-thiophene, oligo thiophene, perylene, and / or derivatives thereof, rubrene, and / or derivatives thereof, coronene, and / or derivatives thereof, perylenetetra carboxylic diimide, and / or derivatives thereof, perylene tetra carboxylic dianhydride, and / or derivatives thereof, polythiophene, and / or derivatives thereof, polyparaphenylenevinylene, and / or derivatives thereof, polyparaphenylene, and / or derivatives thereof, polyfluoroene, and / or derivatives thereof, polythiophenevinylene, and / or It may be composed of derivatives thereof, polythiophene-heterocyclic aromatic copolymers, and / or derivatives thereof, oligoacenes of naphthalene and derivatives thereof, naphthalene tetra carboxylic acid diimide and / or derivatives thereof, oligothiophenes of alpha-5-thiophene and derivatives thereof, phthalocyanines containing or not containing metals and derivatives thereof, pyromellitic dianhydrides and / or derivatives thereof, pyromellitic diimides and / or derivatives thereof, polyalkylthiophenes, polythienylenevinylenes, copolymers of alkylfluorene units, alkylthiophenes, diketopyrrolopyrrole, and / or derivatives thereof, etc.However, this is an example, and other organic semiconductor materials may be included in the semiconductor layer (Act).

[0144] A first insulating layer (113) may be positioned on the semiconductor layer (Act). The first insulating layer (113) may include an organic insulating material, an inorganic insulating material, or an organic-inorganic insulating material, and may have a single-layer or multi-layer structure.

[0145] A gate electrode (GE) may be positioned on the first insulating layer (113). The gate electrode (GE) may include a conductive material. For example, the gate electrode (GE) and the first capacitor electrode (CE1) may include a metal material such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti). The gate electrode (GE) and the first capacitor electrode (CE1) may have a single-layer or multi-layer structure.

[0146] The gate electrode (GE) and the first capacitor electrode (CE1) of the storage capacitor (Cst) may be provided as an integral unit. However, the present invention is not limited thereto. In one or more other embodiments, the gate electrode (GE) and the first capacitor electrode (CE1) may be provided separately.

[0147] A second insulating layer (115) may be positioned on the gate electrode (GE). The second insulating layer (115) may include an organic insulator, an inorganic insulator, or an organic-inorganic insulator, and may have a single-layer or multi-layer structure.

[0148] A second capacitor electrode (CE2) of a storage capacitor (Cst) may be positioned on the second insulating layer (115). The second capacitor electrode (CE2) may include a conductive material. For example, the second capacitor electrode (CE2) may include a metal material such as molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti). The second capacitor electrode (CE2) may have a single-layer or multi-layer structure.

[0149] The second capacitor electrode (CE2) of the storage capacitor (Cst) can overlap the first capacitor electrode (CE1) with a second insulating layer (115) therebetween. The second insulating layer (115) can function as a dielectric layer of the storage capacitor (Cst).

[0150] A third insulating layer (117) may be positioned on the second capacitor electrode (CE2). The third insulating layer (117) may include an organic insulator, an inorganic insulator, or an organic-inorganic insulator, and may have a single-layer or multi-layer structure.

[0151] A source electrode (SE) and a drain electrode (DE) may be positioned on the third insulating layer (117). The source electrode (SE) and the drain electrode (DE) may include a conductive material such as a metal material, a conductive composite, or a liquid metal material. The source electrode (SE) and the drain electrode (DE) may have a single-layer or multi-layer structure.

[0152] A fourth insulating layer (119) may be positioned on the source electrode (SE) and the drain electrode (DE). The fourth insulating layer (119) may provide a flat base surface for the first light-emitting element (LED1) and the second light-emitting element (LED2) disposed thereon. The fourth insulating layer (119) may include an organic insulating material. The fourth insulating layer (119) may have a single-layer or multi-layer structure.

[0153] The first insulating layer (113), the second insulating layer (115), the third insulating layer (117), and the fourth insulating layer (119) may be included in the insulating layer (IL).

[0154] A first light-emitting element (LED1) and a second light-emitting element (LED2) may be positioned on an insulating layer (IL). The first light-emitting element (LED1) and the second light-emitting element (LED2) may be inorganic light-emitting diodes (230). As described above with reference to FIG. 6b, the inorganic light-emitting diode (230) may include a first semiconductor layer (231), a second semiconductor layer (232), an intermediate layer (233) between the first semiconductor layer (231) and the second semiconductor layer (232), and a first electrode (235) and a second electrode (238) electrically connected to the first semiconductor layer (231) and the second semiconductor layer (232), respectively. The first electrode (235) and the second electrode (238) of the weapon light-emitting diode (230) can be electrically connected to the first electrode pad (241) and the second electrode pad (242), respectively.

[0155] The first light-emitting element (LED1) and the second light-emitting element (LED2) may be electrically connected to the first electrode pad (241) and the second electrode pad (242), respectively, on the fourth insulating layer (119). The first electrode pad (241) may be electrically connected to the first pixel driving circuit unit (PC1) through a contact hole penetrating the third insulating layer (117). The first light-emitting element (LED1) may be electrically connected to the first pixel driving circuit unit (PC1). Similarly, the second light-emitting element (LED2) may be electrically connected to the second pixel driving circuit unit (PC2).

[0156] The bank layer (BPL) is positioned on the fourth insulating layer (119) and may be arranged spaced apart from the first light-emitting element (LED1) and the second light-emitting element (LED2). The bank layer (BPL) may include a first pattern (BPa) and a second pattern (BPb) that are arranged spaced apart from each other.

[0157] FIGS. 9A, 9B, and 9C are schematic plan views illustrating a bank layer of a display device according to one or more embodiments of the present invention. FIGS. 9A to 9C correspond to a modified embodiment of FIG. 7.

[0158] Referring to FIGS. 9A, 9B, and 9C, the bank layer (BPL) may include bank patterns (BP) on a planar surface. The bank patterns (BP) may include a first pattern (BPa) and a second pattern (BPb). The first pattern (BPa) and the second pattern (BPb) may be arranged to be spaced apart from each other.

[0159] The first pattern (BPa) of FIGS. 9a, 9b, and 9c may be a first bank pattern, and the second pattern (BPb) may be a second bank pattern. Below, the second pattern (BPb), which differs from FIG. 7, will be described, and any redundant or similar descriptions will be omitted.

[0160] The first pattern (BPa) can be a linear pattern extending corresponding to at least two light emitting elements (LEDs) arranged in a first direction (e.g., x-direction). The second pattern (BPb) can be a linear pattern surrounding at least a portion of one light emitting element (LED). For example, the second pattern (BPb) can be a preceding pattern extending generally along the first direction (e.g., x-direction) to surround at least a portion of one light emitting element (LED). The first pattern (BPa) and the second pattern (BPb) can be spaced apart from each other in a second direction (e.g., y-direction) that is substantially perpendicular to the first direction (e.g., x-direction). In one or more other embodiments, the first pattern (BPa) can be a linear pattern extending corresponding to at least two light emitting elements (LEDs) arranged in the second direction (e.g., y-direction). The second pattern (BPb) may be a preceding pattern extending along the second direction (e.g., the y direction) to surround at least a portion of one light emitting element (LED). The first pattern (BPa) and the second pattern (BPb) may be spaced apart from each other in a first direction (e.g., the x direction) that is perpendicular to the second direction (e.g., the y direction).

[0161] In one or more embodiments, the second pattern (BPb) may be at least partially bent. The second pattern (BPb) may include a first pattern portion (b1) and a second pattern portion (b2) extending in different directions, respectively. In one or more embodiments, as illustrated in FIG. 9A, the first pattern portion (b1) and the second pattern portion (b2) may be connected to each other. In other words, the second pattern (BPb) may include a connecting portion (b3), and the first pattern portion (b1) and the second pattern portion (b2) may be connected in a straight line or a curved shape at the connecting portion (b3). In one or more other embodiments, as illustrated in FIG. 9B, the first pattern portion (b1) and the second pattern portion (b2) may be spaced apart from each other. In one or more other embodiments, as illustrated in FIG. 9C, the second pattern (BPb) may have a single curved shape as a whole.

[0162] The bank patterns (BP) may include a structure in which each of the first pattern (BPa) and the second pattern (BPb) is repeated at regular intervals. For example, the first pattern (BPa) may be arranged between a first row in which the third light-emitting elements (LED3) are arranged and a second row in which the first light-emitting elements (LED1) and the second light-emitting elements (LED2) are arranged in an alternating manner. The second pattern (BPb) may be arranged between a second row in which the first light-emitting elements (LED1) and the second light-emitting elements (LED2) are arranged in an alternating manner and a third row in which the third light-emitting elements (LED3) are arranged. The second pattern (BPb) may be arranged to surround at least a portion of the first light-emitting element (LED1) or the second light-emitting element (LED2).

[0163] FIG. 10 is a schematic plan view of a bank layer of a display device according to one or more embodiments of the present invention. FIG. 10 corresponds to one or more modified embodiments of FIGS. 7 and 9A, 9B, and 9C.

[0164] Referring to FIG. 10, the bank layer (BPL) on the plane may include bank patterns (BP). The bank patterns (BP) may include a first pattern (BPa) and a second pattern (BPb). The first pattern (BPa) and the second pattern (BPb) may be arranged spaced apart from each other.

[0165] Each of the first pattern (BPa) and the second pattern (BPb) of Fig. 10 may be a second bank pattern. Each of the first pattern (BPa) and the second pattern (BPb) of Fig. 10 may correspond to the second pattern (BPb) of Figs. 9a, 9b, and 9c.

[0166] Each of the first pattern (BPa) and the second pattern (BPb) may be a linear pattern that surrounds at least a portion of one light emitting element (LED). For example, each of the first pattern (BPa) and the second pattern (BPb) may be a preceding pattern extending along a first direction (e.g., an x-direction) to surround at least a portion of one light emitting element (LED). The first pattern (BPa) and the second pattern (BPb) may be spaced apart from each other in a second direction (e.g., a y-direction) that is perpendicular to the first direction (e.g., an x-direction). In one or more other embodiments, each of the first pattern (BPa) and the second pattern (BPb) may be a preceding pattern extending along a second direction (e.g., a y-direction) to surround at least a portion of one light emitting element (LED). The first pattern (BPa) and the second pattern (BPb) may be spaced apart from each other in the first direction (e.g., the x direction) perpendicular to the second direction (e.g., the y direction).

[0167] Each of the first pattern (BPa) and the second pattern (BPb) may be bent at least in part. The first pattern (BPa) may include a first pattern portion (a1) and a second pattern portion (a2) extending in different directions, respectively. In one or more embodiments, as illustrated in FIG. 10, the first pattern (BPa) may include a connecting portion (a3) ​​connecting the first pattern portion (a1) and the second pattern portion (a2). The first pattern portion (a1) and the second pattern portion (a2) of the first pattern (BPa) may be connected in a straight line or a curved shape at the connecting portion (a3). However, the present invention is not limited thereto, and in one or more other embodiments, the first pattern portion (a1) and the second pattern portion (a2) of the first pattern (BPa) may be spaced apart from each other.

[0168] Similarly, the second pattern (BPb) may include a first pattern portion (b1) and a second pattern portion (b2) extending in different directions, respectively. In one or more embodiments, as illustrated in FIG. 10, the second pattern (BPb) may include a connecting portion (b3) connecting the first pattern portion (b1) and the second pattern portion (b2). The first pattern portion (b1) and the second pattern portion (b2) of the second pattern (BPb) may be connected in a straight line or a curved shape at the connecting portion (b3). However, the present invention is not limited thereto. In one or more other embodiments, the first pattern portion (b1) and the second pattern portion (b2) of the second pattern (BPb) may be spaced apart from each other.

[0169] The bank patterns (BP) may include a structure in which the first pattern (BPa) and the second pattern (BPb) are each repeated at regular intervals. For example, as illustrated in FIG. 10, the first pattern (BPa) may be arranged between a first row in which the third light-emitting elements (LED3) are arranged and a second row in which the first light-emitting elements (LED1) and the second light-emitting elements (LED2) are arranged in an alternating manner. The first pattern (BPa) may be arranged to surround at least a portion of the first light-emitting element (LED1) or at least a portion of the second light-emitting element (LED2). The second pattern (BPb) may be arranged between the second row in which the first light-emitting elements (LED1) and the second light-emitting elements (LED2) are arranged in an alternating manner and a third row in which the third light-emitting elements (LED3) are arranged. The second pattern (BPb) may be arranged to surround at least a portion of the first light-emitting element (LED1) or the second light-emitting element (LED2).

[0170] FIGS. 11 and 12 are schematic plan views illustrating a bank layer of a display device according to one or more embodiments of the present invention. FIGS. 11 and 12 correspond to a modified embodiment of FIG. 7.

[0171] Referring to FIG. 11, the bank patterns (BP) may include a first pattern (BPa). The first pattern (BPa) may be a third bank pattern. There may be multiple first patterns (BP), and the first patterns (BPas) may be spaced apart from each other.

[0172] The first pattern (BPa) may be a pattern having at least one closed-loop shaped unit surrounding one light-emitting element (LED). For example, the first pattern (BPa) may be a pattern having closed-loop shaped units (SBPa) surrounding one light-emitting element (LED). FIG. 11 illustrates that the first pattern (BPa) is formed corresponding to light-emitting elements (LEDs) arranged in a first direction (e.g., x-direction), but in one or more other embodiments, the first patterns (BPa) may correspond to light-emitting elements (LEDs) arranged in a second direction (e.g., y-direction).

[0173] In one or more embodiments, each of the units (SBPa) of the first pattern (BPa) may have a polygonal shape. For example, as illustrated in FIG. 11, each of the units (SBPa) of the first pattern (BPa) may have a square shape. Here, the polygonal shape may include a polygonal shape with rounded corners. However, the present invention is not limited thereto, and in one or more other embodiments, each of the units (SBPa) of the first pattern (BPa) may have a circular or oval shape.

[0174] In one or more embodiments, the first pattern (BPa) may extend continuously to both edges of the display area (DA). Alternatively, in one or more other embodiments, the first pattern (BPa) may include sub-patterns that are arranged to both edges of the display area (DA) but are spaced apart from each other. Each of the sub-patterns may be a pattern comprised of closed-loop units surrounding one light-emitting element (LED).

[0175] The bank patterns (BP) may include a structure in which each of the first patterns (BPa) is repeated at regular intervals. For example, as illustrated in FIG. 11, the first patterns (BP) may be arranged in rows in which the first light-emitting elements (LED1) and the second light-emitting elements (LED2) are arranged in an alternating manner. The first patterns (BP) may be spaced apart from each other. Each unit (SBPa) of the first pattern (BP) may surround at least one first light-emitting element (LED1) or at least one second light-emitting element (LED2).

[0176] Referring to FIG. 12, the bank patterns (BP) may include a first pattern (BPa), a second pattern (BPb), and a third pattern (BPc). Each of the first pattern (BPa), the second pattern (BPb), and the third pattern (BPc) may be a third bank pattern.

[0177] Each of the first pattern (BPa), the second pattern (BPb), and the third pattern (BPc) may be a pattern having a single unit in a closed loop shape surrounding one light-emitting element (LED). For example, the first pattern (BPa) may be a pattern in a closed loop shape surrounding one first light-emitting element (LED1), the second pattern (BPb) may be a pattern in a closed loop shape surrounding one second light-emitting element (LED2), and the third pattern (BPc) may be a pattern in a closed loop shape surrounding one third light-emitting element (LED3).

[0178] In one or more embodiments, each of the first pattern (BPa), the second pattern (BPb), and the third pattern (BPc) may have a polygonal, circular, and / or elliptical shape. Here, the polygonal shape may include a polygonal shape with rounded corners. For example, as illustrated in FIG. 12, the first pattern (BPa) and the second pattern (BPb) may have a rectangular shape, and the third pattern (BPc) may have a circular shape.

[0179] The bank patterns (BP) may include first patterns (BPa) each surrounding a first light-emitting element (LED1) of the entire display area (DA), second patterns (BPb) each surrounding a second light-emitting element (LED2), and third patterns (BPc) each surrounding a third light-emitting element (LED3). Unlike FIGS. 9A, 9B, and 9C, FIGS. 10, and 11, the first patterns (BPa), the second patterns (BPb), and the third patterns (BPc) of FIG. 12 may be connected to each other. For example, at least two of the first patterns (BPa), the second patterns (BPb), and / or the third patterns (BPc) may be connected to each other in a form in which their respective planar shapes are in contact with each other.

[0180] As a comparative example, a display device may include a bank layer that is integrally provided corresponding to a display area and defines apertures corresponding to each light-emitting element. In this case, when the display device is stretched, the degree of deformation of the bank layer (e.g., deformation of the apertures of the bank layer) may vary depending on the area within the display area, resulting in a noticeable difference in luminous efficiency and color between areas. Consequently, the display quality of the display device may deteriorate.

[0181] However, the bank layer (BPL) of the display device (1) according to one or more embodiments of the present invention includes bank patterns (BP) arranged in a region between light-emitting elements (LEDs) on a plane, and each of the bank patterns (BP) may be a linear pattern extending in response to at least two light-emitting elements (LEDs) arranged in one direction, a linear pattern surrounding at least a portion of one light-emitting element (LED), or a pattern having at least one closed-loop-shaped unit surrounding one light-emitting element (LED). The bank patterns (BP) may be spaced apart from the light-emitting elements (LEDs). The area of ​​the region where the bank layer (BPL) is arranged may be reduced compared to the bank layer of a comparative example. In addition, since the bank patterns (BP) have the above-described planar shape, the bank layer (BPL) may be more easily stretched. Accordingly, when the display device (1) is stretched, the variation in the degree of deformation of the bank layer (BPL) in each region within the display area (DA) may be reduced. The luminous efficiency and color deviation of each area within the display area (DA) may decrease due to the extension of the display device (1). Accordingly, the display quality of the display device (1) may be improved.

[0182] Fig. 13 is a plan view schematically illustrating a bank layer of a display device according to one or more embodiments of the present invention. Fig. 13 may correspond to one or more modified embodiments of Fig. 7. Fig. 14 is a cross-sectional view schematically illustrating a portion of a display device according to one or more embodiments of the present invention, taken along line B-B' of Fig. 13. In addition, Figs. 15a to 15c are cross-sectional views schematically illustrating a portion of a display device according to one or more embodiments of the present invention, and may correspond to the modified embodiments of Fig. 14.

[0183] Referring to FIG. 13, the bank layer (BPL) defines openings (OP) corresponding to each of the light-emitting elements (LEDs) and may be integrally provided corresponding to the display area (DA). For example, the bank layer (BPL) may define a first opening (OP1) corresponding to the first light-emitting element (LED1), a second opening (OP2) corresponding to the second light-emitting element (LED2), and a third opening (OP3) corresponding to the third light-emitting element (LED3).

[0184] The bank layer (BPL) may include first portions (PT1), second portions (PT2), and third portions (PT3). The first portions (PT1) of the bank layer (BPL) may be portions spaced apart from the openings (OP). The second portions (PT2) and the third portions (PT3) of the bank layer (BPL) may be portions disposed between the openings (OP) and the first portions (PT1) or between the first portions (PT1). Specifically, the second portions (PT2) of the bank layer (BPL) may be portions that contact the openings (OP). The inner surfaces of the second portions (PT2) may define the openings (OP). The third portions (PT3) of the bank layer (BPL) may be portions disposed between the first portions (PT1), or between the first portions (PT1) and the second portions (PT2). The third portions (PT3) of the bank layer (BPL) may connect the first portions (PT1) to each other, or connect the first portions (PT1) and the second portions (PT2) to each other. On a plane, the first portions (PT1) of the bank layer (BPL) may include bank patterns (BP) arranged in an area between the light emitting elements (LEDs). The bank patterns (BP) may correspond to the bank patterns (BP) of FIGS. 7 to 12.

[0185] In one or more embodiments, the first portion (PT1) of the bank layer (BPL) may be a first bank portion. The second portion (PT2) of the bank layer (BPL) may be a second-first bank portion of the second bank portion. The third portion (PT3) of the bank layer (BPL) may be a second-second bank portion of the second bank portion.

[0186] Referring to Fig. 14, an insulating layer (IL) is positioned on a substrate (100), and the insulating layer (IL) may include first to fourth insulating layers (113, 115, 117, 119). A first light-emitting element (LED1) electrically connected to a first pixel driving circuit unit (PC1) and a second light-emitting element (LED2) electrically connected to a second pixel driving circuit unit (PC2) may be positioned on the fourth insulating layer (119), respectively.

[0187] The bank layer (BPL) may be positioned on an insulating layer (IL) on which light-emitting elements (LEDs) are arranged. For example, the bank layer (BPL) may be positioned on a fourth insulating layer (119) on which a first light-emitting element (LED1) and a second light-emitting element (LED2) are positioned, and may define a first opening (OP1) and a second opening (OP2) corresponding to the first light-emitting element (LED1) and the second light-emitting element (LED2), respectively.

[0188] The height (h2) from the upper surface of the substrate (100) to the second portion (PT2) of the bank layer (BPL) may be smaller than the height (h1) from the upper surface of the substrate (100) to the first portion (PT1) of the bank layer (BPL). The height (h2) from the upper surface of the substrate (100) to the second portion (PT2) of the bank layer (BPL) may be substantially equal to or greater than the height from the upper surface of the substrate (100) to the upper surface of the light-emitting element (LED) (e.g., the first light-emitting element (LED)).

[0189] In one or more embodiments, as illustrated in FIG. 14, the height (h2) from the upper surface of the substrate (100) to the second portion (PT2) of the bank layer (BPL) may be substantially equal to the height (h3) from the upper surface of the substrate (100) to the third portion (PT3) of the bank layer (BPL). However, the present invention is not limited thereto. In one or more other embodiments, the height (h2) from the upper surface of the substrate (100) to the second portion (PT2) of the bank layer (BPL) may be different from the height (h3) from the upper surface of the substrate (100) to the third portion (PT3) of the bank layer (BPL). For example, as illustrated in FIG. 15a, the height (h2) from the upper surface of the substrate (100) to the second portion (PT2) of the bank layer (BPL) may be greater than the height (h3) from the upper surface of the substrate (100) to the third portion (PT3) of the bank layer (BPL). In addition, as illustrated in FIG. 15c, the height (h2) from the upper surface of the substrate (100) to the second portion (PT2) of the bank layer (BPL) may be less than the height (h3) from the upper surface of the substrate (100) to the third portion (PT3) of the bank layer (BPL).

[0190] In some embodiments, as illustrated in FIG. 15b, at least a portion of the third portions (PT3) of the bank layer (BPL) may be removed. The removed portions may form openings in the bank layer (BPL). Furthermore, in some embodiments, as illustrated in FIG. 15c, the height (h3) from the upper surface of the substrate (100) to the third portion (PT3) of the bank layer (BPL) may be greater than the height (h1) from the upper surface of the substrate (100) to the first portion (PT1) of the bank layer (BPL).

[0191] A display device (1) according to one or more embodiments of the present invention includes a bank layer (BPL) that is integrally provided corresponding to a display area (DA) and defines openings (OP) respectively corresponding to light-emitting elements (LEDs), wherein the bank layer (BPL) may include portions having different thicknesses in an area excluding the openings (OP). The bank layer (BPL) may include first portions (PT1), second portions (PT2) disposed between the openings and the first portions (PT1), or disposed between the first portions (PT1), and third portions (PT3). On the plane, the first portions (PT1) of the bank layer (BPL) correspond to the bank patterns (BP), and each of the bank patterns (BP) may be a linear pattern extending in response to at least two light emitting elements (LEDs) arranged in one direction, a linear pattern surrounding at least a portion of one light emitting element (LED), or a pattern having at least one closed-loop unit surrounding one light emitting element (LED). At this time, at least a portion of the height (h1) from the upper surface of the substrate (100) to the first portion (PT1) of the bank layer (BPL), a height (h2) from the upper surface of the substrate (100) to the second portion (PT2) of the bank layer (BPL), or a height (h3) from the upper surface of the substrate (100) to the third portion (PT3) of the bank layer (BPL) may be different. For example, the height (h2) from the upper surface of the substrate (100) to the second portion (PT2) of the bank layer (BPL) may be smaller than the height (h1) from the upper surface of the substrate (100) to the first portion (PT1) of the bank layer (BPL).

[0192] According to one or more embodiments of the present invention, the bank layer (BPL) may include portions having different thicknesses in areas excluding openings. For example, the heights of the second portions (PT2) of the bank layer (BPL) may be smaller than the heights of the first portions (PT1), and the second portions (PT2) may be relatively more stretchable. In addition, the first portions (PT1) of the bank layer (BPL) may include the bank patterns (BP) described above on a plane, and may be relatively more stretchable. Therefore, the overall stretchability of the bank layer (BPL) of the present invention may be improved compared to the bank layer of a comparative example in which the thickness is uniform in areas excluding openings. Accordingly, the variation in the degree of deformation of the bank layer (BPL) in each area within the display area (DA) when the display device (1) is stretched may be reduced. The variation in luminous efficiency and color in each area within the display area (DA) due to the stretching of the display device (1) may be reduced. Accordingly, the display quality of the display device (1) can be improved.

[0193] FIGS. 16A to 16C are schematic cross-sectional views illustrating portions of a display device according to one or more embodiments of the present invention. FIGS. 16A to 16C may correspond to one or more modified embodiments of FIGS. 15A and 15C, respectively. In the following, overlapping details will be omitted and the differences will be primarily described.

[0194] Referring to FIGS. 16a to 16c, at least a portion of the bank layer (BPL) in the cross-section may have a shape in which one or both sides are reversely tapered.

[0195] Referring to FIG. 16a, as illustrated in FIG. 15a, the height from the upper surface of the substrate (100) to the second portion (PT2) of the bank layer (BPL) may be greater than the height from the upper surface of the substrate (100) to the third portion (PT3) of the bank layer (BPL). The height from the upper surface of the substrate (100) to the first portion (PT1) of the bank layer (BPL) may be greater than the height from the upper surface of the substrate (100) to the second portion (PT2) of the bank layer (BPL).

[0196] At least some of the first portions (PT1) of the bank layer (BPL) may have a shape in which one or both sides are reversely tapered in cross-section. For example, the upper portion of each of the first portions (PT1) may have a shape in which one side is reversely tapered. An angle (α) formed between the side surface of each of the first portions (PT1) and the upper surface of the adjacent second portion (PT2) may be greater than 0 and less than 90°.

[0197] Referring to FIGS. 16b and 16c, as illustrated in FIG. 15c, the height from the upper surface of the substrate (100) to the third portion (PT3) of the bank layer (BPL) may be greater than the height from the upper surface of the substrate (100) to the first portion (PT1) of the bank layer (BPL). The height from the upper surface of the substrate (100) to the first portion (PT1) of the bank layer (BPL) may be greater than the height from the upper surface of the substrate (100) to the second portion (PT2) of the bank layer (BPL).

[0198] In one or more embodiments, as illustrated in FIGS. 16b and 16c, at least some of the third portions (PT3) of the bank layer (BPL) may have a shape in which one or both sides thereof are reversely tapered in cross-section. For example, the upper portion of each of the third portions (PT3) may have a shape in which one side thereof is reversely tapered. An angle (β) formed between the side surface of each of the third portions (PT3) and the upper surface of the adjacent first portion (PT1) may be greater than 0 and less than 90°.

[0199] In addition, in one or more embodiments, as illustrated in FIG. 16c, at least some of the first portions (PT1) of the bank layer (BPL) may have a shape in which one side is reversely tapered in cross-section. For example, the upper portion of each of the first portions (PT1) may have a shape in which one side is reversely tapered. The angle (α) formed between the side surface of each of the first portions (PT1) and the upper surface of the adjacent second portion (PT2) may be greater than 0 and less than 90°.

[0200] According to one or more embodiments of the present invention, at least a portion of the bank layer (BPL) may have a reverse tapered shape in cross-section. When another layer is positioned on top of the bank layer (BPL), the adhesive strength of the layer positioned on top of the bank layer (BPL) may be increased due to the reverse tapered shape structure included in the bank layer (BPL). The film lifting phenomenon of the layer positioned on top of the bank layer (BPL) may be reduced or prevented.

[0201] Fig. 17 is a plan view schematically illustrating a display area of ​​a display device according to one or more embodiments of the present invention. Fig. 18 is a plan view schematically illustrating a bank layer of a display device according to one or more embodiments of the present invention, and is an enlarged plan view of part C of Fig. 17.

[0202] Referring to FIG. 17, the display area (DA) of the display device (1) may be divided into a plurality of areas. For example, the display area (DA) may include a first area (AR1), a second area (AR2), and a third area (AR3). For example, the second area (AR2) may be arranged to entirely surround the first area (AR1) (e.g., on a plane), and the third area (AR3) may be arranged to entirely surround the second area (AR2) (e.g., on a plane). However, the present invention is not limited thereto. As will be described later, the display area (DA) may be divided into a plurality of areas of various shapes.

[0203] Referring to FIG. 18, the structures of the bank patterns (BPs) of the bank layer (BPL) arranged in each of the first region (AR1) and the second region (AR2) may be different from each other. For example, the structure of the bank patterns (BPs) of FIG. 9c may be applied to the first region (AR1), and the structure of the bank patterns (BPs) of FIG. 9a may be applied to the second region (AR2). Of course, the arrangement structure of the bank patterns (BPs) for each region is exemplary, and various arrangement structures of the bank patterns (BPs) described above with reference to FIGS. 7 to 12 may be applied to each region. The arrangement structure of the bank patterns (BPs) for each region within the display region (DA) may be determined in consideration of the stretching direction of the display device (1) and the film properties of the bank layer (BPL).

[0204] Meanwhile, although it has been described that the arrangement structure of the bank patterns (BP) of the bank layer (BPL) described with reference to FIGS. 7 to 12 may vary for each area of ​​the display area (DA) in FIGS. 17 and 18, the present invention is not limited thereto. The structures of the bank layer (BPL) described with reference to FIGS. 13 to 16c may also be applied differently for each area of ​​the display area (DA).

[0205] FIGS. 19A to 19C are schematic plan views of display devices according to one or more embodiments of the present invention. FIGS. 20A to 20C are schematic plan views of display devices according to one or more embodiments of the present invention. FIGS. 21A to 21D are schematic plan views of display devices according to one or more embodiments of the present invention.

[0206] The display device (1) can be elongated in various directions. The display device (1) can include a display area (DA). Referring to FIGS. 19A to 19C, the display device (1) can be elongated in one direction, for example, in the x direction or the -x direction, by an external force applied by an external object or a user. Referring to FIGS. 20A to 20C, the display device (1) can be elongated in both directions, in the ±x direction or the ±y direction, by an external force applied by an external object or a user. In addition, referring to FIGS. 21A to 21D, the display device (1) can be elongated in a plurality of directions, for example, in the ±x direction and the ±y direction, by an external force applied by an external object or a user. Figures 19a to 21d illustrate the arrangement structure of areas (e.g., first to fourth areas (AR1, AR2, AR3, AR4), or first to fifth areas (AR1, AR2, AR3, AR4, AR5)) within the display area (DA) considering the extension direction of the display device (1). A different bank layer (BPL) structure may be applied to each area.

[0207] FIGS. 22A to 22G are perspective views schematically illustrating embodiments of an electronic device including a display device according to one or more embodiments of the present invention.

[0208] The display device (1) according to the above-described embodiments can be used in various electronic devices capable of providing images. Here, the term "electronic device" refers to a device that uses electricity and can provide a corresponding image.

[0209] Referring to FIG. 22A, a display device according to one or more embodiments of the present invention may be utilized in a wearable electronic device (3100) that can be worn on a part of a user's body. The wearable electronic device (3100) may include a body portion (3110) and a display portion (3120) provided in the body portion (3110). The display device according to embodiments of the present invention may be utilized as the display portion (3120) of the wearable electronic device (3100). As illustrated in FIG. 22A, the wearable electronic device (3100) may be transformable. In one or more embodiments, it may be utilized as a smart watch or a smartphone, depending on the user's selection.

[0210] FIG. 22B illustrates a medical electronic device (3200). In one or more embodiments, the medical electronic device (3200) may include a body portion (3210) and a light-emitting portion (3220). A display device according to embodiments of the present invention may be used as the light-emitting portion (3220) of the medical electronic device (3200). The light-emitting portion (3220) may emit light of a certain wavelength band (e.g., infrared, visible light, etc.) to the patient's body. In one or more embodiments, the body portion (3210) may have a stretchable fiber material and may have a structure that allows the light-emitting portion to be worn on the body of a user.

[0211] FIG. 22C illustrates an educational electronic device (3300). In one or more embodiments, the educational electronic device may include a display unit (3320) provided within a frame (3310). The display unit (3320) may utilize a display device according to embodiments of the present invention. The display unit (3320) may provide an image such as a sea with waves, a snow-covered mountain, or a volcano with flowing lava, wherein the display unit (3320) may expand in the height direction (e.g., the z direction) to reflect the height of the wave, mountain, or volcano. In some embodiments, a portion of the display unit (3320) may sequentially vary in height along the direction of flowing lava to show the movement of lava in three dimensions. The educational electronic device (3300) may include a plurality of pins (or stroke units, 3330) arranged on the back surface of the display unit (3320) so that the display unit (3320) expands in the height direction. The pins (3330) can be implemented to move along a third direction (e.g., the z direction or the -z direction) so that the image displayed on the display unit (3320) has a three-dimensional height. Although Fig. 22c describes an educational electronic device (3300), its use is not limited to any device that provides corresponding image information.

[0212] While the electronic devices illustrated in FIGS. 22A through 22C are described as electronic devices whose shapes can be variable, the present invention is not limited thereto. As described in the embodiments below, display devices according to embodiments of the present invention can be used in electronic devices in which a portion capable of displaying an image (e.g., a screen) is fixed.

[0213] FIG. 22D illustrates a robot (3400) as an electronic device according to one or more embodiments of the present invention. The robot (3400) can recognize movement or objects using a camera unit (3440) and display corresponding images to a user through a display unit (3420, 3430). In some embodiments, since the display devices according to one embodiment of the present invention can extend in various directions as described above, they can be assembled into a body frame having a hemispherical shape, and thus the robot (3400) can include a hemispherical display unit (3420, 3430).

[0214] FIG. 22E illustrates a vehicle display device (3500) as another electronic device according to one or more embodiments of the present invention. The vehicle display device (3500) may include a cluster (3510), a center information display (CID) (3520), and / or a co-driver display. Since the display device according to an embodiment of the present invention can be extended in various directions, it may be used in the cluster (3510), the center information display (CID) (3520), and / or the co-driver display regardless of the shape of the internal frame of the vehicle.

[0215] Although FIG. 22e illustrates that the cluster (3510), the Center Information Display (CID) (3520), and / or the co-driver display are each separate, the present invention is not limited thereto. In one or more other embodiments, two or more selected from the cluster (3510), the Center Information Display (CID) (3520), and the co-driver display may be connected integrally.

[0216] In some embodiments, the vehicle display device (3500) may include a button (3540) capable of displaying a corresponding image. Referring to the enlarged view of FIG. 22E, the hemispherical button (3540) may include an object (3542) that provides a button usability by moving in the z-direction or the -z-direction, and a display device positioned on the object (3542). In some embodiments, when the object (3542) has a three-dimensionally rounded surface, the display device may also have a three-dimensionally rounded surface.

[0217] FIG. 22F illustrates an electronic device (3600) for advertising or display purposes according to one or more embodiments of the present invention. In some embodiments, the electronic device (3600) for advertising or display purposes may be installed on a fixed structure (3610), such as a wall or a pillar. If the structure (3610) includes a recessed surface as illustrated in FIG. 22F, the electronic device (3600) for advertising or display purposes may also be positioned along the recessed surface of the structure (3610). In some embodiments, the electronic device (3600) for advertising or display purposes may be installed on the structure (3610) using a heat shrink film or the like.

[0218] FIG. 22G illustrates an electronic device according to one or more embodiments of the present invention, which is a controller (3700). The controller (3700) may include an image-type button. For example, the controller (3700) may include first to third button areas (3720, 3730, 3740) in which a portion of the display portion (3710) protrudes in the z direction or protrudes in the -z direction (or is sunken in the z direction). In some embodiments, the first and third button areas (3720, 3740) may protrude in the z direction, and the second button area (3730) may protrude in the -z direction (or is sunken in the z direction).

[0219] While the present invention has been described with reference to the embodiments illustrated in the drawings, it will be understood that these are illustrative rather than restrictive. The description of aspects of each embodiment should generally be considered applicable to other similar aspects in other embodiments. While one or more embodiments have been described with reference to the drawings, those skilled in the art will appreciate that various changes in form and detail may be made without departing from the spirit and scope of the claims, and that functional equivalents thereof may be included herein.

Claims

1. Substrate; a plurality of light-emitting elements on the substrate; and A bank layer including a plurality of bank patterns in an area between the plurality of light-emitting elements on a plane; The above multiple bank patterns are, A display device, comprising a first linear bank pattern extending in correspondence with at least two of the plurality of light-emitting elements arranged in one direction on a plane, a second linear bank pattern surrounding at least a portion of one of the plurality of light-emitting elements, or a third linear bank pattern having at least one closed-loop unit surrounding one of the plurality of light-emitting elements.

2. In paragraph 1, The above multiple bank patterns are spaced apart from each other, display device.

3. In paragraph 1, A display device wherein the first bank pattern is at least partially folded.

4. In paragraph 3, The first bank pattern includes a first pattern portion and a second pattern portion extending in different directions, and a connecting portion connecting the first pattern portion and the second pattern portion, A display device in which the first pattern portion and the second pattern portion are arranged alternately.

5. In paragraph 4, A display device wherein the above connecting portion has a straight or curved shape.

6. In paragraph 1, A display device, wherein the second bank pattern includes a first pattern portion and a second pattern portion extending in different directions.

7. In paragraph 6, A display device wherein the first pattern portion and the second pattern portion are connected or spaced apart from each other.

8. In paragraph 1, A display device, wherein the third bank pattern includes a plurality of third bank patterns connected to each other.

9. In paragraph 1, A display device wherein the above plurality of light-emitting elements are inorganic light-emitting diodes.

10. Substrate; a plurality of light-emitting elements on the substrate; and A bank layer defining a plurality of openings corresponding to each of the plurality of light-emitting elements, and including a plurality of first bank portions, and a plurality of second bank portions respectively disposed between the plurality of first bank portions, or between the plurality of first bank portions and the plurality of openings; On the plane, the plurality of first bank portions include a plurality of bank patterns each arranged between the plurality of light-emitting elements, The above multiple bank patterns are, A display device, comprising a first linear bank pattern extending in correspondence with at least two of the plurality of light-emitting elements arranged in one direction on a plane, a second linear bank pattern surrounding at least a portion of one of the plurality of light-emitting elements, or a third linear bank pattern having at least one closed-loop unit surrounding one of the plurality of light-emitting elements.

11. In paragraph 10, A display device, wherein the height from the upper surface of the substrate to the upper surface of one of the plurality of second bank portions is smaller than the height from the upper surface of the substrate to the upper surface of one of the plurality of first bank portions.

12. In paragraph 10, One of the plurality of second bank portions of the above bank layer includes a second-first bank portion and a second-second bank portion, A display device, wherein the height from the upper surface of the substrate to the upper surface of the 2-2 bank portion is different from the height from the upper surface of the substrate to the upper surface of the 2-1 bank portion.

13. In paragraph 10, The above multiple bank patterns are spaced apart from each other, display device.

14. In paragraph 10, A display device wherein the first bank pattern is at least partially folded.

15. In paragraph 14, The first bank pattern includes a first pattern portion and a second pattern portion extending in different directions, and a connecting portion connecting the first pattern portion and the second pattern portion, A display device in which the first pattern portion and the second pattern portion are arranged alternately.

16. In paragraph 15, A display device wherein the above connecting portion has a straight or curved shape.

17. In paragraph 10, A display device, wherein the second bank pattern includes a first pattern portion and a second pattern portion extending in different directions.

18. In paragraph 17, A display device wherein the first pattern portion and the second pattern portion are connected or spaced apart from each other.

19. In paragraph 10, A display device, wherein the third bank pattern includes a plurality of third bank patterns connected to each other.

20. In paragraph 10, A display device, wherein at least a portion of the bank layer has a reverse tapered shape in cross-section.

Images