Display device, light-emitting device, and method for manufacturing display device

Abstract

Provided are a display device, a light-emitting element, and a method for manufacturing the display device. The display device may comprise: a substrate on which a pixel electrode is disposed; a light-emitting element disposed on the pixel electrode and including an element rod and a contact electrode disposed on one surface and a side surface of the element rod; a connection electrode electrically connecting the contact electrode and the pixel electrode; and a common electrode disposed on the light-emitting element. The element rod may comprise: a first element rod which includes a first semiconductor layer and an active layer and of which a side surface has a first inclination angle; a second element rod which is disposed on the first element rod and of which a side surface has a second inclination angle; and a third element rod which is disposed on the second element rod and of which a side surface has a third inclination angle.

Description

Display device, light-emitting element and method for manufacturing display device

[0001] The present invention relates to a display device, a light-emitting element and a method for manufacturing the display device.

[0002] As the information society develops, demand for display devices for displaying images is increasing in various forms. Display devices can be flat panel displays such as liquid crystal displays (LCDs), field emission displays (FEDs), and light emitting displays (LEDs).

[0003] The light-emitting display device may include an organic light-emitting display device including an organic light-emitting diode element as a light-emitting element, and an ultra-small light-emitting display device including a micro light-emitting diode element (hereinafter referred to as a micro light-emitting element) as a light-emitting element. Since the ultra-small light-emitting diode element is made of an inorganic material, it has the advantage of having a longer lifespan due to fewer deterioration issues compared to an organic light-emitting diode element.

[0004] The problem to be solved by the present invention is to provide a display device, a light-emitting element, and a method for manufacturing the display device that can prevent a short between a common electrode and a contact electrode.

[0005] The tasks of the present invention are not limited to the technical tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the description below.

[0006] According to one embodiment of the present invention for solving the above problem, a display device includes a substrate on which a pixel electrode is arranged, a light-emitting element disposed on the pixel electrode, the light-emitting element including a device rod and a contact electrode disposed on one surface and a side surface of the device rod, a connection electrode electrically connecting the contact electrode and the pixel electrode, and a common electrode disposed on the light-emitting element, wherein the device rod includes a first device rod including a first semiconductor layer and an active layer and a side surface having a first inclination angle, a second device rod disposed on the first device rod and having a second inclination angle, and a third device rod disposed on the second device rod and having a third inclination angle, and the light-emitting element may further include a first protective layer disposed on one surface and a side surface of the first device rod and a side surface of the second device rod, a reflective layer disposed on the second protective layer and disposed on one surface and a side surface of the first device rod and a side surface of the second device rod, and a second protective layer disposed on an edge of the side surface of the second device rod, the side surface of the third device rod, and an upper surface of the third device rod.

[0007] In one embodiment, the contact electrode may be disposed on one side of the first element load on the reflective layer and may extend to a side of the first element load and a side of the second element load.

[0008] In one embodiment, the contact electrode is disposed between the reflective layer and the second protective layer on the second element load side, and one end of the reflective layer can be completely surrounded by the first protective layer and the contact electrode on the second element load side.

[0009] In one embodiment, the first protective layer, the reflective layer, and the contact electrode may not be disposed on a side surface of the third element load.

[0010] In one embodiment, the third semiconductor layer may have a rough structure.

[0011] In one embodiment, the second protective layer may be disposed at the edge of the uneven structure of the third semiconductor layer.

[0012] In one embodiment, the second protective layer may become thinner toward the inside from the upper surface of the third semiconductor layer.

[0013] In one embodiment, the display device further includes an organic pattern layer disposed on the pixel electrode and disposed on a lower surface of the light-emitting element, and the connection electrode may be disposed on one surface of the pixel electrode, a side surface of the organic pattern layer, and a side surface of a first contact electrode of the light-emitting element.

[0014] In one embodiment, the first protective layer has one or more openings defined in one surface of the first element load, and the contact electrode can be electrically connected to the element load exposed by the openings.

[0015] In one embodiment, the contact electrode may have higher conductivity and lower reflectivity than the reflective layer.

[0016] In one embodiment, the second slope angle may be smaller than the first slope angle and the third slope angle.

[0017] In one embodiment, the second inclination angle may be greater than or equal to 60 degrees and greater than or equal to 80 degrees.

[0018] In one embodiment, the second element load may have a wider width toward the third element load, and the width of the third element load may be wider than the width of the first element load.

[0019] According to one embodiment, a light-emitting device may include a device rod in which a first semiconductor layer, an active layer, a second semiconductor layer, and a third semiconductor layer are sequentially stacked, and which is divided into a first device rod, a second device rod, and a third device rod according to an inclination angle, a first protective layer disposed on one surface and a side surface of the first device rod and on the side surface of the second device rod, a reflective layer disposed on the second protective layer and on one surface and a side surface of the first device rod and on the side surface of the second device rod, a contact electrode disposed on one surface of the first device rod on the reflective layer and extending to the side surface of the first device rod and the side surface of the second device rod, and a second protective layer disposed on the edge of the side surface of the second device rod, the side surface of the third device rod, and the upper surface of the third device rod.

[0020] In one embodiment, the third semiconductor layer has a rough structure, and the second protective layer can be disposed at an edge of the rough structure of the third semiconductor layer.

[0021] In one embodiment, the second protective layer may become thinner toward the inside from the upper surface of the third semiconductor layer.

[0022] In one embodiment, the second inclination angle is smaller than the first inclination angle and the third inclination angle, and the second inclination angle may be greater than or equal to 60 degrees and greater than or equal to 80 degrees.

[0023] According to one embodiment, a method for manufacturing a display device includes the steps of forming a third semiconductor material layer, a second semiconductor material layer, an active material layer, and a first semiconductor material layer on a growth substrate, etching the active material layer and the first semiconductor material layer using a first mask to form a first element rod having a first inclination angle, etching the second semiconductor material layer and the third semiconductor material layer using a second mask to form a second element rod having a second inclination angle, forming a first protective layer, a reflective layer, and a contact electrode covering the third semiconductor material layer, the second semiconductor material layer, the active material layer, and the first semiconductor material layer, etching a portion of the second element rod using a third mask to form a third element rod having a third inclination angle, and forming a second protective layer disposed on a side surface of the second element rod and a side surface of the third element rod, wherein the second protective layer may extend from the side surface of the third element rod and be disposed between an edge gap between the third element rod and the protective layer.

[0024] A method for manufacturing a display device according to one embodiment may include a step of transferring a light-emitting element including the first element load, the second element load, and the third element load to a circuit board having a pixel electrode, and a step of forming a connection electrode connecting the contact electrode and the pixel electrode.

[0025] In one embodiment, the step of transferring the light-emitting element to a circuit board having a pixel electrode may include the step of forming an organic pattern layer as an adhesive layer on the pixel electrode, the step of arranging a plurality of light-emitting elements on the organic pattern layer, and the step of fixing the light-emitting elements by curing the organic pattern layer.

[0026] Specific details of other embodiments are included in the detailed description and drawings.

[0027] According to the display device and its manufacturing method according to the embodiments, a short between a common electrode and a contact electrode can be minimized.

[0028] The effects according to the embodiments are not limited to those exemplified above, and more diverse effects are included in this specification.

[0029] Figure 1 is a perspective view showing a display device according to one embodiment.

[0030] FIG. 2 is a layout diagram showing a display device according to one embodiment.

[0031] FIG. 3 is a block diagram showing a display device according to one embodiment.

[0032] Fig. 4 is an equivalent circuit diagram showing a sub-pixel according to one embodiment.

[0033] FIG. 5 is a layout diagram showing pixels of a display area according to one embodiment.

[0034] FIG. 6 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I1-I1' of FIG. 5 according to one embodiment.

[0035] FIG. 7 is a cross-sectional view showing in detail an example of area A of FIG. 6 according to one embodiment.

[0036] FIG. 8 is a cross-sectional view showing in detail an example of area A of FIG. 6 according to another embodiment.

[0037] FIG. 9 is a cross-sectional view showing in detail an example of area A of FIG. 6 according to another embodiment.

[0038] FIG. 10 is a layout diagram showing pixels of a display area according to one embodiment.

[0039] Fig. 11 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I2-I2' of Fig. 10.

[0040] Figure 12 is a cross-sectional view showing in detail an example of area B of Figure 11.

[0041] Fig. 13 is a flowchart showing a method for manufacturing a display device according to one embodiment.

[0042] FIGS. 14 to 22 are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment.

[0043] Figure 23 is a drawing showing in detail an example of area C of Figure 22.

[0044] FIGS. 24 to 29 are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment.

[0045] FIG. 30 is an exemplary drawing showing a smartwatch including a display device according to one embodiment.

[0046] FIG. 31 is an exemplary drawing showing a virtual reality device including a display device according to one embodiment.

[0047] FIGS. 32 and 33 are exemplary drawings showing a virtual reality device including a display device according to one embodiment.

[0048] FIG. 34 is an exemplary drawing showing an automobile instrument panel and center fascia including display devices according to one embodiment.

[0049] FIG. 35 is an exemplary drawing showing a transparent display device including a display device according to one embodiment.

[0050] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0051] When elements or layers are referred to as being "on" another element or layer, this includes both cases where the other element or layer is directly on top of the other element or layer, or where the other layer or layer is interposed therebetween. Like reference numerals refer to like elements throughout the specification. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments are illustrative and therefore the present invention is not limited to the matters illustrated.

[0052] The individual features of the various embodiments of the present invention can be partially or fully combined or combined with one another, enabling various technically feasible interconnections and operations. Each embodiment may be implemented independently of the others, or may be implemented together in a related manner.

[0053] Specific embodiments are described below with reference to the attached drawings.

[0054] Figure 1 is a perspective view showing a display device according to one embodiment.

[0055] Referring to FIG. 1, the display device (10) is a device that displays a moving image or a still image, and can be used as a display screen for various products such as a mobile phone, a smart phone, a tablet personal computer, a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation system, an Ultra Mobile PC (UMPC), etc., as well as a television, a laptop, a monitor, a billboard, an Internet of Things (IOT) device, etc.

[0056] The display device (10) may be a light-emitting display device such as an organic light-emitting display device (OLED) using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and an ultra-small light-emitting display device using an ultra-small light-emitting diode (micro or nano light emitting diode (micro LED or nano LED)). Hereinafter, the display device (10) is described mainly as an ultra-small light-emitting display device, but the present invention is not limited thereto. Meanwhile, for the convenience of explanation, an ultra-small light-emitting diode is described as a light-emitting element below.

[0057] The display device (10) includes a display panel (100), a display driving circuit (250), a circuit board (300), and a power supply circuit (500).

[0058] The display panel (100) may be formed as a rectangular plane having a short side in a first direction (DR1) and a long side in a second direction (DR2) intersecting the first direction (DR1). The corner where the short side in the first direction (DR1) and the long side in the second direction (DR2) meet may be formed to be rounded or formed at a right angle so as to have an appropriate curvature (for example, a predetermined curvature). The plane shape of the display panel (100) is not limited to a square, and may be formed in another polygonal, circular, or oval shape. The display panel (100) may be formed flat, but is not limited thereto. For example, the display panel (100) may include a curved portion formed at the left and right ends and having a constant curvature or a varying curvature. In addition, the display panel (100) may be formed flexibly so as to be bent, curved, folded, or rolled.

[0059] The substrate (SUB in FIG. 6) of the display panel (100) may include a main area (MA) and a sub area (SBA).

[0060] The main area (MA) may include a display area (DA) that displays an image and a non-display area (NDA) that is arranged around the display area (DA) along the edge or periphery of the display area (DA). The display area (DA) may include a plurality of pixels that display an image. Each of the pixels may include a plurality of sub-pixels. For example, each of the pixels may include a first sub-pixel that emits a first light, a second sub-pixel that emits a second light, and a third sub-pixel that emits a third light, but the embodiments of the present specification are not limited thereto.

[0061] The sub-area (SBA) may protrude in a second direction (DR2) from one side of the main area (MA). In FIG. 1, the sub-area (SBA) is illustrated as being unfolded, but the sub-area (SBA) may be bent, in which case it may be disposed on the lower surface of the display panel (100). When the sub-area (SBA) is bent, it may overlap with the main area (MA) in the third direction (DR3), which is the thickness direction of the display panel (100). A display driving circuit (250) may be disposed in the sub-area (SBA).

[0062] The display driving circuit (250) can generate signals and voltages for driving the display panel (100). The display driving circuit (250) can be formed as an integrated circuit (IC) and attached to the display panel (100) using a COG (chip on glass) method, a COP (chip on plastic) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit (250) can be attached to the circuit board (300) using a COF (chip on film) method.

[0063] The circuit board (300) may be attached to one end of the sub-area (SBA) of the display panel (100). As a result, the circuit board (300) may be electrically connected to the display panel (100) and the display driving circuit (250). The display panel (100) and the display driving circuit (250) may receive digital video data, timing signals, and driving voltages through the circuit board (300). The circuit board (300) may be a flexible film such as a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a chip on film (COF).

[0064] The power supply circuit (500) can generate multiple panel driving voltages according to an external power voltage. The power supply circuit (500) can be formed as an integrated circuit (IC) and attached to a circuit board (300) using a COF method.

[0065] Fig. 2 is a layout diagram showing a display device according to one embodiment. Fig. 2 illustrates that the sub-area (SBA) is unfolded rather than bent.

[0066] Referring to FIG. 2, the display panel (100) may include a main area (MA) and a sub area (SBA).

[0067] The main area (MA) may include a display area (DA) that displays an image and a non-display area (NDA) surrounding the display area (DA). The display area (DA) may occupy most of the area of ​​the main area (MA). The display area (DA) may be positioned at the center of the main area (MA).

[0068] The display area (DA) includes a plurality of pixels (PX) for displaying an image, and each of the plurality of pixels (PX) may include a plurality of sub-pixels (SPX). A pixel (PX) may be defined as a sub-pixel group that is the smallest unit capable of expressing white gradation.

[0069] A non-display area (NDA) may be positioned adjacent to a display area (DA). The non-display area (NDA) may be an area outside the display area (DA). The non-display area (NDA) may be positioned to surround the display area (DA). The non-display area (NDA) may be an edge area of ​​the display panel (100).

[0070] The first scan driver (SDC1) and the second scan driver (SDC2) may be disposed in a non-display area (NDA). The first scan driver (SDC1) may be disposed on one side (for example, the left side) of the display panel (100), and the second scan driver (SDC2) may be disposed on the other side (for example, the right side) of the display panel, but is not limited thereto. Each of the first scan driver (SDC1) and the second scan driver (SDC2) may be electrically connected to the display driver circuit (250) via scan fan out lines. Each of the first scan driver (SDC1) and the second scan driver (SDC2) may receive a scan control signal from the display driver circuit (250), generate scan signals according to the scan control signal, and output the scan signals to the scan lines.

[0071] The sub-area (SBA) may protrude from one side of the main area (MA) in a second direction (DR2). The length of the sub-area (SBA) in the second direction (DR2) may be shorter than the length of the main area (MA) in the second direction (DR2). The length of the sub-area (SBA) in the first direction (DR1) may be shorter than the length of the main area (MA) in the first direction (DR1) or may be substantially the same as the length of the main area (MA) in the first direction (DR1). The sub-area (SBA) may be curved and may be disposed at a lower portion of the display panel (100). In this case, the sub-area (SBA) may overlap the main area (MA) in the third direction (DR3).

[0072] The sub-area (SBA) may include a connection area (CA), a pad area (PA), and a bending area (BA).

[0073] The connection area (CA) is an area that protrudes in the second direction (DR2) from one side of the main area (MA). One side of the connection area (CA) may be in contact with the non-display area (NDA) of the main area (MA), and the other side of the connection area (CA) may be in contact with the bending area (BA).

[0074] The pad area (PA) is an area where pads (PD) and a display driving circuit (250) are arranged. The display driving circuit (250) can be attached to the driving pads of the pad area (PA) using a conductive adhesive such as an anisotropic conductive film. The circuit board (300) can be attached to the pads (PD) of the pad area (PA) using a conductive adhesive such as an anisotropic conductive film. One side of the pad area (PA) can be in contact with the bending area (BA).

[0075] The bending area (BA) is a bending area. When the bending area (BA) is bent, the pad area (PA) can be positioned below the connection area (CA) and below the main area (MA). The bending area (BA) can be positioned between the connection area (CA) and the pad area (PA). One side of the bending area (BA) can be in contact with the connection area (CA), and the other side of the bending area (BA) can be in contact with the pad area (PA).

[0076] FIG. 3 is a block diagram showing a display device according to one embodiment.

[0077] Referring to FIG. 3, the display area (DA) includes a plurality of pixels (PX), a plurality of scan lines (SL), a plurality of emission control lines (EL), and a plurality of data lines (DL).

[0078] A plurality of pixels (PX) may be arranged in a matrix form in a first direction (DR1) and a second direction (DR2). For example, the plurality of pixels (PX) may be arranged along rows and columns of the matrix along the first direction (DR1) and the second direction (DR2). A plurality of scan lines (SL) and a plurality of emission control lines (EL) may extend in the first direction (DR1) and be arranged in the second direction (DR2). A plurality of data lines (DL) may extend in the second direction (DR2) and be arranged in the first direction (DR1). The plurality of scan lines (SL) include a plurality of write scan lines (GWL), a plurality of initialization scan lines (GIL), and a plurality of bias scan lines (GBL).

[0079] Each of the plurality of sub-pixels (SPX) can be connected to any one of the plurality of write scan lines (GWL), any one of the plurality of initialization scan lines (GIL), any one of the plurality of bias scan lines (GBL), any one of the plurality of emission control lines (EL), and any one of the plurality of data lines (DL). In one embodiment, each sub-pixel (SPX) can be connected to any one of the plurality of control scan lines. Each of the plurality of sub-pixels (SPX) can receive a data voltage of a data line (DL) according to a write scan signal of a write scan line (GWL), and can emit light through a light-emitting element according to the data voltage.

[0080] The non-display area (NDA) includes a first scan driver (SDC1), a second scan driver (SDC2), and a display driver circuit (250).

[0081] Each of the first scan driving unit (SDC1) and the second scan driving unit (SDC2) may include a write scan signal output unit (611), an initialization scan signal output unit (612), a bias scan signal output unit (613), and an emission control signal output unit (614). Each of the write scan signal output unit (611), the initialization scan signal output unit (612), the bias scan signal output unit (613), and the emission control signal output unit (614) may receive a scan timing control signal (SCS) from a timing control circuit (251).

[0082] The write scan signal output unit (611) can generate write scan signals according to the scan timing control signal (SCS) of the timing control circuit (251) and sequentially output them to write scan lines (GWL).

[0083] The initialization scan signal output unit (612) can generate initialization scan signals according to a scan timing control signal (SCS) and sequentially output them to initialization scan lines (GIL).

[0084] The bias scan signal output unit (613) can generate bias scan signals according to a scan timing control signal (SCS) and sequentially output them to bias scan lines (GBL). The light emission control signal output unit (614) can generate light emission control signals according to a scan timing control signal (SCS) and sequentially output them to light emission control lines (EL).

[0085] The display driving circuit (250) includes a timing control circuit (251) and a data driving circuit (252).

[0086] The data driving circuit (252) can receive digital video data (DATA) and a data timing control signal (DCS) from the timing control circuit (251). The data driving circuit (252) converts the digital video data (DATA) into analog data voltages according to the data timing control signal (DCS) and outputs the converted data voltages to the data lines (DL). In this case, the sub-pixels (SPX) are selected by the write scan signals of the first scan driving unit (SDC1) and the second scan driving unit (SDC2), and the data voltages can be supplied to the selected sub-pixels (SPX).

[0087] The timing control circuit (251) can receive digital video data (DATA) and timing signals from the outside. The timing control circuit (251) can generate a scan timing control signal (SCS) and a data timing control signal (DCS) for controlling the display panel (100) according to the timing signals. The timing control circuit (400) can output the scan timing control signal (SCS) to the first scan driving unit (SDC1) and the second scan driving unit (SDC2). The timing control circuit (251) can output digital video data (DATA) and a data timing control signal (DCS) to the data driving circuit (252).

[0088] The power supply circuit (500) can generate a plurality of panel driving voltages according to a power voltage supplied from an external source. For example, the power supply circuit (500) can generate a first power voltage (VDD), a second power voltage (VSS), a third power voltage (VINT), and a fourth power voltage (VAINT) and supply them to the display panel (100).

[0089] Fig. 4 is an equivalent circuit diagram showing a sub-pixel according to one embodiment.

[0090] Referring to FIG. 4, a sub-pixel (SPX) according to one embodiment may be connected to scan lines (GWL, GIL, GBL), an emission control line (EL), and a data line (DL). For example, the sub-pixel (SPX) may be connected to a write scan line (GWL), an initialization scan line (GIL), a bias scan line (GBL), an emission control line (EL), and a data line (DL).

[0091] A sub-pixel (SPX) according to one embodiment includes a driving transistor (DT), switch elements, a capacitor (C1), and a light-emitting element (LE1). The switch elements include first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6).

[0092] A driving transistor (DT) includes a gate electrode, a first electrode, and a second electrode. The driving transistor (DT) controls a drain-source current (Ids, hereinafter referred to as “driving current”) flowing between the first electrode and the second electrode according to a data voltage applied to the gate electrode.

[0093] The light emitting element (LE1) may be a micro light emitting diode.

[0094] The light-emitting element (LE1) emits light according to the driving current (Ids). The amount of light emitted by the light-emitting element (LE) may be proportional to the driving current (Ids). The anode electrode of the light-emitting element (LE) may be connected to the first electrode of the fourth transistor (ST4) and the second electrode of the sixth transistor (ST6), and the cathode electrode may be connected to the second power line (VSL) to which the second power voltage is applied.

[0095] A capacitor (C1) is formed between the gate electrode of the driving transistor (DT) and a first power line (VDL) to which a first power voltage is applied. The first power voltage may be a voltage of a higher level than the second power voltage. One electrode of the capacitor (C1) may be connected to the gate electrode of the driving transistor (DT), and the other electrode may be connected to the first power line (VDL).

[0096] As shown in Fig. 4, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) can all be formed as p-type MOSFETs. In this case, the active layers of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) can be formed of polysilicon.

[0097] The gate electrode of the first transistor (ST1) and the gate electrode of the second transistor (ST2) may be connected to a write scan line (GWL), the gate electrode of the third transistor (ST3) may be connected to an initialization scan line (GIL), and the gate electrode of the fourth transistor (ST4) may be connected to a bias scan line (GBL). The gate electrodes of the fifth transistor (ST5) and the sixth transistor (ST6) may be connected to an emission line (EL). Since the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, and ST6) are formed of p-type MOSFETs, they may be turned on when a scan signal of a gate low voltage and an emission control signal are applied to the initialization scan line (GIL), the write scan line (GWL), the bias scan line (GBL), and the emission line (EL), respectively. One electrode of the third transistor (ST3) may be connected to a first initialization voltage line (VIL) to which a third power supply voltage (VINT of FIG. 3) is applied, and one electrode of the fourth transistor (ST4) may be connected to a second initialization voltage line (VAIL) to which a fourth power supply voltage (VAINT of FIG. 3) is applied. The third power supply voltage (VINT of FIG. 3) and the fourth power supply voltage (VAINT of FIG. 3) may be different voltages. In addition, the third power supply voltage (VINT of FIG. 3) and the fourth power supply voltage (VAINT of FIG. 3) may be a voltage at a lower level than the first power supply voltage (VDD) and a voltage at a higher level than the second power supply voltage (VSS).

[0098] Alternatively, the driving transistor (DT), the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) may be formed as p-type MOSFETs, and the first transistor (ST1) and the third transistor (ST3) may be formed as n-type MOSFETs. In this case, the active layers of each of the driving transistor (DT), the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) formed as p-type MOSFETs may be formed of polysilicon, and the active layers of each of the first transistor (ST1) and the third transistor (ST3) formed as n-type MOSFETs may be formed of oxide semiconductors. In addition, since the first transistor (ST1) and the third transistor (ST3) are formed as n-type MOSFETs, the first transistor (ST1) may be turned on when a scan signal of a gate high voltage is applied, and the third transistor (ST3) may be turned on when an initialization scan signal of a gate high voltage is applied. In comparison, the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) are formed as p-type MOSFETs, and thus can be turned on when a scan signal of a gate low voltage and a light emission control signal are applied.

[0099] Alternatively, when the fourth transistor (ST4) is formed as an n-type MOSFET and the remaining transistors (DT, ST1, ST2, ST3, ST5, ST6) are formed as p-type MOSFETs, the active layer of the fourth transistor (ST4) may be formed of an oxide semiconductor, and the active layers of each of the remaining transistors (DT, ST1, ST2, ST3, ST5, ST6) may be formed of polysilicon. In addition, the fourth transistor (ST4) may be turned on when a scan signal of a gate high voltage is applied, whereas the remaining transistors (DT, ST1, ST2, ST3, ST5, ST6) may be turned on when a scan signal of a gate low voltage and a light emission control signal are applied.

[0100] Alternatively, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) may all be formed as n-type MOSFETs. In this case, the active layers of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) are formed of an oxide semiconductor and can be turned on when a scan signal of a gate high voltage and a light emission control signal are applied.

[0101] FIG. 5 is a layout diagram showing pixels of a display area according to one embodiment.

[0102] Referring to FIG. 5, each of the plurality of pixels (PX) of the display area (DA) may include three sub-pixels (SPX1, SPX2, SPX3), but the embodiment of the present specification is not limited thereto and may include four sub-pixels. When each of the plurality of pixels (PX) includes three sub-pixels (SPX1, SPX2, SPX3), it may include a first sub-pixel (SPX1), a second sub-pixel (SPX2), and a third sub-pixel (SPX3).

[0103] A plurality of pixels (PX) can be arranged in a matrix form. In each of the plurality of pixels (PX), a first sub-pixel (SPX1), a second sub-pixel (SPX2), and a third sub-pixel (SPX3) can be arranged in a first direction (DR1).

[0104] When each of the plurality of pixels (PX) includes three sub-pixels (SPX1, SPX2, SPX3), the first sub-pixel (SPX1) can emit light of a first color, the second sub-pixel (SPX2) can emit light of a second color, and the third sub-pixel (SPX3) can emit light of a third color. Here, the light of the first color may be light in a red wavelength band, the light of the second color may be light in a green wavelength band, and the light of the third color may be light in a blue wavelength band. For example, the blue wavelength band may refer to a wavelength band in which the main peak wavelength of the light is included in a wavelength band of approximately 370 nm to 460 nm, the green wavelength band may refer to a wavelength band in which the main peak wavelength of the light is included in a wavelength band of approximately 480 nm to 560 nm, and the red wavelength band may refer to a wavelength band in which the main peak wavelength of the light is included in a wavelength band of approximately 600 nm to 750 nm.

[0105] Alternatively, when each of the plurality of pixels (PX) includes four sub-pixels, the first sub-pixel may emit light of a first color, the second and fourth sub-pixels may emit light of a second color, and the third sub-pixel may emit light of a third color. Alternatively, the first sub-pixel may emit light of a first color, the second sub-pixel may emit light of a second color, the third sub-pixel may emit light of a third color, and the fourth sub-pixel may emit light of a fourth color. In this case, the light of the fourth color may be white light.

[0106] The first sub-pixel (SPX1) includes a first pixel electrode (PXE1), a plurality of light-emitting elements (LEs), and a first light conversion layer (QDL1). The second sub-pixel (SPX2) includes a second pixel electrode (PXE2), a plurality of light-emitting elements (LEs), and a second light conversion layer (QDL2). The third sub-pixel (SPX3) includes a third pixel electrode (PXE3), a plurality of light-emitting elements (LEs), and a light-transmitting layer (TPL).

[0107] Each of the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) may have a rectangular planar shape having a short side in the first direction (DR1) and a long side in the second direction (DR2).

[0108] The light emitting element (LE) may have a rectangular planar shape having a short side in a first direction (DR1) and a long side in a second direction (DR2).

[0109] The light emitting element (LE) may include a device load (LD of FIG. 7) that is divided into a first device load (LD1 of FIG. 7), a second device load (LD2 of FIG. 7), and a third device load (LD3 of FIG. 7), as described below. The first device load (LD1), the second device load (LD2), and the third device load (LD3) each follow the planar shape of the light emitting element (LE). For example, the first device load (LD1), the second device load (LD2), and the third device load (LD3) may have a rectangular planar shape having a short side in a first direction (DR1) and a long side in a second direction (DR2).

[0110] The length of the short side (LD2-2) of the element rod (LD) is about 13 µm to 11 µm, and the length of the long side (LD2-1) is about 20 µm to 22 µm, and may be 23 µm to 26 µm. In addition, the length of the short side (LD1-1) of the first element rod (LD) is about 6 µm to 7 µm, and the length of the long side (LD1-2) may be 20 µm to 22 µm, but this is merely exemplary and is not limiting.

[0111] The area of ​​the first sub-pixel (SPX1), the area of ​​the second sub-pixel (SPX2), and the area of ​​the third sub-pixel (SPX3) can be set according to the light conversion efficiency of the first light conversion layer (QDL1) and the light conversion efficiency of the second light conversion layer (QDL2). That is, the lower the light conversion efficiency, the larger the area of ​​the sub-pixel can be.

[0112] For example, as shown in FIG. 5, when the light conversion efficiency of the second light conversion layer (QDL2) is lower than the light conversion efficiency of the first light conversion layer (QDL1), the area of ​​the second pixel electrode (PXE2) may be larger than the area of ​​the first pixel electrode (PXE1), and the area of ​​the first pixel electrode (PXE1) may be larger than the area of ​​the third pixel electrode (PXE3).

[0113] Each of the pixel electrodes (PXE1, PXE2, PXE3) can be electrically connected to at least one transistor through a pixel connection hole (CT1 / CT2 / CT3). For example, each of the pixel electrodes (PXE1, PXE2, PXE3) can be electrically connected to a second electrode of a fourth transistor (ST4 of FIG. 4) and a second electrode of a sixth transistor (ST6 of FIG. 4) of the corresponding sub-pixel.

[0114] A plurality of light emitting elements (LEs) may be arranged on each of the pixel electrodes (PXE1, PXE2, PXE3). The same number of light emitting elements (LEs) may be arranged on each of the pixel electrodes (PXE1, PXE2, PXE3). For example, one light emitting element (LE) may be arranged on each of the pixel electrodes (PXE1, PXE2, PXE3). The plurality of light emitting elements (LEs) may emit light of a third color, i.e., light in a blue wavelength band, but the embodiments of the present specification are not limited thereto. When the light-emitting element (LE) of the first sub-pixel (SPX1) emits light of a first color, the light-emitting element (LE) of the second sub-pixel (SPX2) emits light of a second color, and the light-emitting element (LE) of the third sub-pixel (SPX3) emits light of a third color, the light conversion layers (QDL1, QDL2) and the light transmitting layer (TPL) may be omitted.

[0115] The first light conversion layer (QDL1) can completely overlap the first pixel electrode (PXE1) and the plurality of light emitting elements (LEs) of the first sub-pixel (SPX1). The area of ​​the first light conversion layer (QDL1) can be larger than the area of ​​the first pixel electrode (PXE1). The first light conversion layer (QDL1) can convert or shift the peak wavelength of incident light into light of another specific peak wavelength and emit the light. For example, the first light conversion layer (QDL1) can convert or shift third light emitted from the plurality of light emitting elements (LEs) of the first sub-pixel (SPX1) into first light.

[0116] The second light conversion layer (QDL2) can completely overlap the second pixel electrode (PXE2) and the plurality of light emitting elements (LEs) of the second sub-pixel (SPX2). The area of ​​the second light conversion layer (QDL2) can be larger than the area of ​​the second pixel electrode (PXE2). The second light conversion layer (QDL2) can convert or shift the peak wavelength of incident light into light of another specific peak wavelength and emit the light. For example, the second light conversion layer (QDL2) can convert or shift third light emitted from the plurality of light emitting elements (LEs) of the second sub-pixel (SPX2) into second light.

[0117] The light transmitting layer (TPL) can completely overlap the third pixel electrode (PXE3) and the plurality of light emitting elements (LEs) of the third sub-pixel (SPX3). The light transmitting layer (TPL) can directly transmit incident light. For example, the light transmitting layer (TPL) can directly transmit third light emitted from the plurality of light emitting elements (LEs) of the third sub-pixel (SPX3).

[0118] Fig. 6 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I1-I1' of Fig. 5 according to one embodiment. Fig. 7 is a cross-sectional view showing in detail an example of area A of Fig. 6 according to one embodiment. Figs. 8 and 9 are cross-sectional views showing in detail an example of area A of Fig. 6 according to another embodiment.

[0119] Referring to FIGS. 6 and 7, the substrate (SUB) may be made of an insulating material such as glass or a polymer resin. If the substrate (SUB) is made of a polymer resin, it may be a flexible substrate that can be stretched. The polymer resin may be an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0120] A barrier film (BR) may be disposed on the substrate (SUB). The barrier film (BR) is a film for protecting transistors of a thin film transistor layer (TFTL) from moisture penetrating through the substrate (SUB) which is vulnerable to moisture permeation. The barrier film (BR) may be formed of a plurality of inorganic films alternately laminated. For example, the barrier film (BR) may be formed as a multi-film in which one or more inorganic films of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer are alternately laminated.

[0121] A thin film transistor (TFT1) may be arranged on the barrier film (BR). The thin film transistor (TFT1) may be either the fourth transistor (ST4) or the sixth transistor (ST6) illustrated in FIG. 4. The thin film transistor (TFT1) may include a first active layer (ACT1) and a first gate electrode (G1).

[0122] A first active layer (ACT1) of a thin film transistor (TFT1) may be disposed on the barrier film (BR). The first active layer (ACT1) of the thin film transistor (TFT1) may include polycrystalline silicon, single-crystalline silicon, low-temperature polycrystalline silicon, or amorphous silicon. Alternatively, the first active layer (ACT1) of the thin film transistor (TFT1) may be formed of an oxide semiconductor including IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)), or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0123] The first active layer (ACT1) may include a first channel region (CHA1), a first source region (S1), and a first drain region (D1). The first channel region (CHA1) may be a region overlapping the first gate electrode (G1) in a third direction (DR3) that is a thickness direction of the substrate (SUB). The first source region (S1) may be disposed on one side of the first channel region (CHA1), and the first drain region (D1) may be disposed on the other side of the first channel region (CHA1). The first source region (S1) and the first drain region (D1) may be regions that do not overlap the first gate electrode (G1) in the third direction (DR3). The first source region (S1) and the first drain region (D1) may be regions in which ions are doped into a semiconductor material to have conductivity.

[0124] A first gate insulating film (131) may be disposed on the first channel region (CHA1), the first source region (S1), the first drain region (D1), and the barrier film (BR) of the thin film transistor (TFT1).

[0125] A first gate metal layer may be disposed on the first gate insulating film (131). The first gate metal layer may include a first gate electrode (G1) of a thin film transistor (TFT1) and a first capacitor electrode (CAE1). The first gate electrode (G1) may overlap the first active layer (ACT1) in the third direction (DR3). Although FIG. 6 illustrates that the first gate electrode (G1) and the first capacitor electrode (CAE1) are disposed apart from each other (e.g., spaced apart), the first gate electrode (G1) and the first capacitor electrode (CAE1) may be connected to each other.

[0126] A second gate insulating film (132) may be disposed on the first gate electrode (G1), the first capacitor electrode (CAE1), and the first gate insulating film (131) of the thin film transistor (TFT1).

[0127] A second gate metal layer may be disposed on the second gate insulating film (132). The second gate metal layer may include a second capacitor electrode (CAE2). The second capacitor electrode (CAE2) may overlap the first capacitor electrode (CAE1) of the thin film transistor (TFT1) in the third direction (DR3). Since the second gate insulating film (132) has a predetermined dielectric constant, a capacitor (C1 in FIG. 4) may be formed by the first capacitor electrode (CAE1), the second capacitor electrode (CAE2), and the second gate insulating film (132) disposed therebetween.

[0128] A first interlayer insulating film (141) may be placed on the second capacitor electrode (CAE2) and the second gate insulating film (132).

[0129] A first data metal layer may be disposed on a first interlayer insulating film (141). The first data metal layer may include a first source connection electrode (PCE1). The first source connection electrode (PCE1) may be connected to a first drain region (D1) of a first active layer (ACT1) through a first source contact hole (PCT1) penetrating the first gate insulating film (131), the second gate insulating film (132), and the first interlayer insulating film (141).

[0130] A first organic film (160) may be placed on the first interlayer insulating film (141) and the first source connection electrode (PCE1) to flatten the step caused by the thin film transistor (TFT1).

[0131] A second data metal layer may be disposed on the first organic film (160). The second data metal layer may include a second source connection electrode (PCE2). The second source connection electrode (PCE2) may be connected to the first source connection electrode (PCE1) through a second pixel contact hole (PCT2) penetrating the first organic film (160).

[0132] A second organic film (180) may be placed on the second source connection electrode (PCE2) and the first organic film (160).

[0133] The barrier film (BR), the first gate insulating film (131), the second gate insulating film (132), and the first interlayer insulating film (141) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0134] The first gate metal layer, the second gate metal layer, the first data metal layer, and the second data metal layer may be formed as a single layer or multiple layers made of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0135] The first organic film (160) and the second organic film (180) can be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0136] A light-emitting element layer may be arranged on the second organic film (180). The light-emitting element layer may include pixel electrodes (PXE1, PXE2, PXE3), a common electrode (CE), light-emitting elements (LE), and an organic layer (190).

[0137] A pixel electrode layer may be placed on the second organic film (180).

[0138] The pixel electrode layer may include pixel electrodes (PXE1, PXE2, PXE3). The pixel electrode layer may be formed as a single layer or multiple layers made of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). For example, in order to lower the resistance of each of the pixel electrodes (PXE1, PXE2, PXE3), the pixel electrode layer may be made of copper (Cu) having a low surface resistance.

[0139] An organic layer (210) (hereinafter, referred to as an organic pattern layer to distinguish it from the organic film (180, 190) that is fully disposed on the lower structure) may be disposed on each of the pixel electrodes (PXE1, PXE2, PXE3). The organic pattern layer (210) temporarily fixes or adheres the plurality of light emitting elements (LEs) to prevent the plurality of light emitting elements (LEs) from tilting and falling over or falling over during the process of transferring the plurality of light emitting elements (LEs) to the display panel. That is, the organic pattern layer (210) may be a film for temporarily adhering the plurality of light emitting elements (LEs) onto each of the pixel electrodes (PXE1, PXE2, PXE3). To facilitate the temporary adhesion, the thickness of the organic pattern layer (210) may be greater than the thickness of each of the pixel electrodes (PXE1, PXE2, PXE3).

[0140] The organic pattern layer (210) may be a photosensitive organic film such as a photoresist. Alternatively, the organic pattern layer (210) may be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0141] The organic pattern layer (210) can be placed on the lower surface of the contact electrode (CTE).

[0142] A plurality of light emitting elements (LE) may be arranged on an organic pattern layer (210). In Fig. 6, it is exemplified that each of the plurality of light emitting elements (LE) is a vertical type micro LED extending in a third direction (DR3). The vertical type micro LED refers to an LED having a structure in which a first semiconductor layer (SEM1), an active layer (MQW), a second semiconductor layer (SEM2), and a third semiconductor layer (USE) are sequentially arranged in the third direction (DR3), which is a vertical direction.

[0143] Each of the plurality of light emitting elements (LE) may be formed of an inorganic material such as gallium nitride (GaN). Each of the plurality of light emitting elements (LE) may have a length in a first direction (DR1), a length in a second direction (DR2), and a length in a third direction (DR3) of several to several hundred μm, respectively. For example, each of the plurality of light emitting elements (LE) may have a length in the first direction (DR1), a length in the second direction (DR2), and a length in the third direction (DR3) of approximately 100 μm or less, respectively.

[0144] Each of the light emitting elements (LE) may include a current spreading layer (CSL), a first semiconductor layer (SEM1), an active layer (MQW), a second semiconductor layer (SEM2), a third semiconductor layer (USE), an outer covering layer (OSL), and a contact electrode (CTE). In one embodiment, each of the light emitting elements (LE) may omit the current spreading layer (CSL).

[0145] The current spreading layer (CSL) is placed on the contact electrode (CTE) and is a layer for increasing light extraction efficiency. It can be formed of a transparent conductive oxide (TCO) such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide) to transmit light.

[0146] A first semiconductor layer (SEM1) may be disposed on a current spreading layer (CSL) (or on a first contact electrode (CTE1) if the current spreading layer (CSL) is omitted), an active layer (MQW) may be disposed on the first semiconductor layer (SEM1), a second semiconductor layer (SEM2) may be disposed on the active layer (MQW), and a third semiconductor layer (USE) may be disposed on the second semiconductor layer (SEM2).

[0147] The first semiconductor layer (SEM1) may be formed of GaN doped with a first conductivity type dopant (e.g., a p-type dopant) such as Mg, Zn, Ca, Sr, or Ba.

[0148] The first semiconductor layer (SEM1) may be electrically connected to the pixel electrode (PXE) of each sub-pixel (SPX). For example, the first semiconductor layer (SEM1) may be electrically connected to the pixel electrode (PXE) of each sub-pixel (SPX) through a current spreading layer (CSL) and a contact electrode (CTE).

[0149] The active layer (MQW) can be disposed on the first semiconductor layer (SEM1). The active layer (MQW) can emit light by the combination of electron-hole pairs in response to an electric signal applied through the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2).

[0150] The active layer (MQW) may include a material having a single or multiple quantum well structure. When the active layer (MQW) includes a material having a multiple quantum well structure, it may have a structure in which a plurality of well layers and barrier layers are alternately stacked. In this case, the well layers may be formed of InGaN, and the barrier layer may be formed of GaN or AlGaN, but is not limited thereto. Alternatively, the active layer (MQW) may have a structure in which a semiconductor material having a large band gap energy and a semiconductor material having a small band gap energy are alternately stacked, or may include different group III to group V semiconductor materials depending on the wavelength of the emitted light.

[0151] When the active layer (MQW) includes InGaN, the color of the emitted light may vary depending on the content of indium (In). For example, as the content of indium (In) increases, the wavelength band of the light emitted by the active layer may shift toward a red wavelength band, and as the content of indium (In) decreases, the wavelength band of the light emitted by the active layer may shift toward a blue wavelength band. For example, the content of indium (In) in the active layer (MQW) of the light-emitting element (LE) that emits the third light (light in the blue wavelength band) may be approximately 10 wt% to 20 wt%.

[0152] The second semiconductor layer (SEM2) may be disposed on the active layer (MQW). The second semiconductor layer (SEM2) may be doped with a second conductivity type dopant, such as Si, Ge, Sn, etc. For example, the second semiconductor layer (SEM2) may be n-GaN doped with n-type Si.

[0153] An electron blocking layer may be positioned between the first semiconductor layer (SEM1) and the active layer (MQW). The electron blocking layer may be a layer that suppresses or prevents excessive electrons from flowing into the active layer (MQW). For example, the electron blocking layer may be AlGaN or p-AlGaN doped with p-type Mg. The electron blocking layer may be omitted.

[0154] The superlattice layer may be positioned between the active layer (MQW) and the second semiconductor layer (SEM2). The superlattice layer may be a layer for relieving stress between the second semiconductor layer (SEM2) and the active layer (MQW). For example, the superlattice layer may be formed of InGaN or GaN. The superlattice layer may be omitted.

[0155] The third semiconductor layer (USE) may have a rough structure on its upper surface. For example, the third semiconductor layer (USE) may be an undoped semiconductor grown on a patterned sapphire substrate (PSS). The third semiconductor layer (USE) may be an undoped material, either n-type or p-type. In an exemplary embodiment, the third semiconductor layer (SEM3) may be at least one of undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, but is not limited thereto.

[0156] The current spreading layer (CSL), first semiconductor layer (SEM1), active layer (MQW), second semiconductor layer (SEM2), and third semiconductor layer (USE) of the light emitting element (LE) can be referred to as the element load (LD).

[0157] The element load (LD) may include a first element load (LD1), a second element load (LD2), and a third element load (LE3) that are distinguished according to changes in the inclination angle of the side surface.

[0158] The first element load (LD1) may include a first side wall (SS1) having a first inclination angle (θ1). The first inclination angle (θ1) of the first side wall (SS1) may be formed at 90 degrees as illustrated in FIGS. 7 to 9, but is not limited thereto. For example, the first inclination angle (θ1) may be 70 degrees or more and less than 90 degrees. The first inclination angle (θ1) is an angle between an extension of a contact surface of the second semiconductor layer (SEM2) and the first element load (LD1) and the second element load (LD2) and the first side wall (SS1) of the first element load (LD1).

[0159] The height of the first element load (LD1) may be the lowest among the three element loads (LD1, LD2, LD3). That is, the height of the first element load (LD1) is lower than the height of the second element load (LD2) and the height of the third element load (LD3).

[0160] The first element load (LD1) may include a first semiconductor layer (SEM1) and an active layer (MQW).

[0161] The second element load (LD2) is placed on the first element load (LD1).

[0162] The height of the second element load (LD2) may be the highest among the three element loads (LD1, LD2, LD3).

[0163] The second element load (LD2) may include a second side wall (SS2) having a second inclination angle (θ2). The second inclination angle (θ2) of the second side wall (SS2) may be 60 degrees or more and 80 degrees or less. In addition, the second inclination angle (θ2) may be smaller than the first inclination angle (θ1). Therefore, the second side wall (SS2) may be formed with a constant taper. The second element load (LD2) becomes wider as it goes upward, that is, as it goes toward the third element load (LE3). The second inclination angle (θ2) is an angle between an extension of a contact surface of the second element load (LD2) and the third element load (LD3) and the second side wall (SS2) of the second element load (LD2).

[0164] As shown in Fig. 8, the areas of the surfaces where the first element load (LD1) and the second element load (LD2) face each other may be identical, but are not limited thereto.

[0165] As shown in Fig. 9, the areas of the surfaces where the first element load (LD1) and the second element load (LD2) face each other may not be equal to each other, so that the side surfaces of the first element load (LD1) and the second element load (LD2) may be formed to have a step.

[0166] The second element load (LD2) may include a second semiconductor layer (SEM2).

[0167] A third element load (LD3) may be placed on the second element load (LD2). The third element load (LD3) may include a third side wall (SS3) having a third inclination angle (θ3). The third inclination angle (θ3) of the third side wall (SS3) may be formed at 90 degrees as illustrated in FIG. 7, but is not limited thereto. For example, the third inclination angle (θ3) may be 70 degrees or more and less than 90 degrees.

[0168] The third element load (LD3) may include a portion of the third semiconductor layer (USE). In another embodiment, the third element load (LD3) may include a portion of the second semiconductor layer (SEM2) and the third semiconductor layer (USE).

[0169] When the total height of the element loads (LD) is 6 µm, the height of the first element load (LD1) may be in the range of 0.5 µm to 1.2 µm, the height of the second element load (LD2) may be in the range of 2.3 µm to 2.7 µm, and the height of the third element load (LD3) may be in the range of 1.5 µm to 2.3 µm, but this is for illustrative purposes only and is not limited thereto.

[0170] Each of the plurality of light emitting elements (LEs) can be grown and formed on a semiconductor substrate such as a silicon substrate or a sapphire substrate. The plurality of light emitting elements (LEs) can be transferred directly from the semiconductor substrate onto the pixel electrodes (PXE1, PXE2, PXE3) of the display panel (100). Alternatively, the plurality of light emitting elements (LEs) can be transferred onto the pixel electrodes (PXE1, PXE2, PXE3) of the display panel (100) through an electrostatic method using an electrostatic head or a stamp method using an elastic polymer material such as PDMS or silicon as a transfer substrate.

[0171] The outer layer (OSL) may be disposed on one surface of the first element load (LD1), a side surface of the first element load (LD1), a side surface of the second element load (LD2), and a side surface of the third element load (LD3). For example, the outer layer (OSL) may be disposed on one surface of the current spreading layer (CSL) and side surfaces of the current spreading layer (CSL), the first semiconductor layer (SEM1), the second semiconductor layer (SEM2), the active layer (MQW), and the third semiconductor layer (USE). The outer layer (OSL) may include a first passivation layer (INS1), a first reflective layer (RF1), and a second passivation layer (INS2).

[0172] The first protective layer (INS1) and the second protective layer (INS2) may include materials having insulating properties, for example, inorganic insulating materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (AlxOy), aluminum nitride (AlN), etc.

[0173] The first protective layer (INS1) can be disposed on one side of the current spreading layer (CSL) and on the side surfaces of the current spreading layer (CSL), the first semiconductor layer (SEM1), the second semiconductor layer (SEM2), the active layer (MQW), and the third semiconductor layer (USE).

[0174] The first protective layer (INS1) may include one or more openings on one surface of the current spreading layer (CSL). For example, the first protective layer (INS1) may include a first opening (OP1) and a second opening (OP2) that are spaced apart from each other.

[0175] At least a portion of the current spreading layer (CSL) may be exposed by the first opening (OP1) and the second opening (OP2).

[0176] In one embodiment, the first protective layer (INS1) may be formed of a single film or multiple films of materials having insulating properties. The first protective layer (INS1) may prevent an electrical short circuit that may occur when the active layer (MQW) is in direct contact with an electrode through which an electrical signal is transmitted to the device load (LD). In addition, since the first protective layer (INS1) protects the outer surface (e.g., the outer peripheral surface) of the device load (LD) including the active layer (MQW), it may reduce or prevent a decrease in luminous efficiency.

[0177] The first reflective layer (RF1) may be arranged on the first protective layer (INS1) to surround one side (LD-B) of the element load (LD) and the side surfaces of the first element load (LD1) and the second element load (LD2). The first reflective layer (RF1) may not be arranged on the side surface of the third element load (LD).

[0178] The first reflective layer (RF1) may include a metallic material that is conductive and has a high light reflectivity (e.g., a reflectivity of 90% or more). The first reflective layer (RF1) may include, for example, aluminum (Al), chromium (Cr), or silver (Ag), and may be formed of a single layer or multiple layers including an alloy thereof. The multiple layers may be, for example, two layers of titanium / copper, two layers of titanium / aluminum, two layers of nickel / aluminum, or two layers of a silver / aluminum-silicon alloy. The first reflective layer (RF1) allows light emitted from the light-emitting element (LE) to be emitted upward.

[0179] The first reflective layer (RF1) may employ, but is not limited to, omnidirectional reflectors (hereinafter referred to as ODRs). An omnidirectional reflector refers to a reflector that maintains high reflectivity over a wide wavelength range and wide angle of incidence. The first reflective layer (RF1) may have a reflectivity of 90% or more within the visible range.

[0180] The contact electrode (CTE) may be disposed on the entire lower surface and side surface of the first element load (LD1) and the side surface of the second element load (LDE2) on the first reflective layer (RF1). The contact electrode (CTE) may be formed to cover one end of the first reflective layer (RF1) disposed on the side surface of the second element load (LD2).

[0181] One end of the contact electrode (CTE) may be arranged in a straight line with the third element load (LD3) and the side surface, but is not limited thereto. For example, as illustrated in FIG. 9, the third element load (LD3) and the side surface may be arranged further outward than one end of the contact electrode (CTE). When the third element load (LD3) and the side surface are arranged further outward than one end of the contact electrode (CTE), the height of the third element load (LD3) may be further reduced.

[0182] The contact electrode (CTE) can contact the current spreading layer (CSL) exposed by the first opening (OP1) and the second opening (OP). If the current spreading layer (CSL) is omitted, the contact electrode (CTE) can contact the first semiconductor layer (SEM1).

[0183] The contact electrode (CTE) is disposed on the outermost surface of one side of the first element load (LD1), and thus may be disposed on the organic pattern layer (210). The contact electrode (CTE) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0184] The second protective layer (INS2) may be disposed on at least a portion of a side surface of the element load (LD). For example, the second protective layer (INS2) may be disposed on the side surface of the second element load (LD2) and on the third element load (LD3), and may extend from the side surface of the third element load (LD3) to be disposed at least partially on an upper surface of the third element load (LD3). For example, the second protective layer (INS2) may be disposed on an edge of the upper surface of the third element load (LD3). The second protective layer (INS2) may be disposed along a protrusion on the upper surface of the third element load (LD3). The second protective layer (INS2) may be disposed so as to become thinner from the outer side to the inner side of the upper surface of the third element load (LD3).

[0185] Accordingly, in a plan view (e.g., a top view), the contact area (CTA) between the third element load (LD3) and the common electrode (CE) may be smaller than the area (LD3A) of the third element load (LD3). In addition, in a plan view, the area of ​​the third element load (LD3) may be the same as the area of ​​the light emitting element (LE), and thus, the contact area (CTA) between the third element load (LD3) and the common electrode (CE) may be the same as the area of ​​the third element load (LD3).

[0186] The second protective layer (INS2) can cover and protect one end of the first contact electrode (CTE).

[0187] The connection electrode (BE) connects the contact electrode (CTE) of the light-emitting element (LE) and one of the pixel electrodes (PXE1, PXE2, PXE3). The connection electrode (BE) can be connected to one of the pixel electrodes (PXE1, PXE2, PXE3) exposed through a connection hole penetrating the organic pattern layer (210). In addition, the connection electrode (BE) can be disposed on the upper surface of the organic pattern layer (210) and the side surface of the contact electrode (CTE). In addition, the connection electrode (BE) can be disposed on a part of the side surface of the light-emitting element (LE). For example, the connection electrode (BE) can be disposed on the contact electrode (CTE) of the side surface of the first element load (LD1).

[0188] The connecting electrode (BE) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, the connecting electrode (BE) may be made of a transparent conductive material (TCO), such as indium tin oxide (ITO) and indium zinc oxide (IZO), which can transmit light.

[0189] The third organic layer (190) may be arranged to cover a portion of a side surface of the plurality of light-emitting elements (LE). In addition, the third organic layer (190) may be arranged to cover the connection electrode (BE).

[0190] The upper surface of each of the plurality of light emitting elements (LEs) may be exposed without being covered by the third organic layer (190).

[0191] The third organic layer (190) can be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0192] A common electrode (CE) may be disposed on the upper surface of each of the plurality of light emitting elements (LE) and the upper surface of the third organic layer (190). The common electrode (CE) may be a common layer formed in common on the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3). The common electrode (CE) may be made of a transparent metal material (TCO, Transparent Conductive Material), such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide), which can transmit light.

[0193] Meanwhile, the pixel electrodes (PXE1, PXE2, PXE3) may be referred to as anode electrodes or first electrodes, and the common electrode (CE) may be referred to as cathode electrodes or second electrodes.

[0194] The first capping layer (CAP1) can be disposed on the common electrode (CE).

[0195] A light-shielding layer (BM), a first light conversion layer (QDL1), a second light conversion layer (QDL2), and a light-transmitting layer (TPL) may be disposed on a first capping layer (CAP1). The first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light-transmitting layer (TPL) may be formed by the partitioning of the light-shielding layer (BM). Therefore, in the first sub-pixel (SPX1), the first light conversion layer (QDL1) may be disposed on the first capping layer (CAP1), in the second sub-pixel (SPX2), the second light conversion layer (QDL2) may be disposed on the first capping layer (CAP1), and in the third sub-pixel (SPX3), the light-transmitting layer (TPL) may be disposed on the first capping layer (CAP1). The light-shielding layer (BM) may not overlap with a plurality of light-emitting elements (LE).

[0196] The first light conversion layer (QDL1) can convert a portion of the third light (light in the blue wavelength band) incident from the light emitting element (LE) into first light (light in the red wavelength band). The first light conversion layer (QDL1) can include a first base resin (BRS1) and a first wavelength conversion particle (WCP1). The first base resin (BRS1) can include a light-transmitting organic material. The first wavelength conversion particle (WCP1) can convert a portion of the third light (light in the blue wavelength band) incident from the light emitting element (LE) into first light (light in the red wavelength band).

[0197] The second light conversion layer (QDL2) can convert a portion of the third light (light in the blue wavelength band) incident from the light emitting element (LE) into second light (light in the green wavelength band). It can include a second base resin (BRS2) and second wavelength conversion particles (WCP2). The second base resin (BRS2) can include a light-transmitting organic material. The second wavelength conversion particles (WCP2) can convert a portion of the third light (light in the blue wavelength band) incident from the light emitting element (LE) into second light (light in the green wavelength band).

[0198] The optically transparent layer (TPL) may include a light-transmitting organic material.

[0199] For example, the first base resin (BRS1), the second base resin (BRS2), and the light transmitting layer (TPL) may include an epoxy resin, an acrylic resin, a cardo resin, or an imide resin. The first and second wavelength conversion particles (WCP1, WCP2) may be quantum dots (QDs), quantum rods, fluorescent materials, or phosphorescent materials.

[0200] The light-blocking layer (BM) may include a first light-blocking layer (BM1) and a second light-blocking layer (BM2) that are sequentially laminated. The length of the first light-blocking layer (BM1) in the first direction (DR1) or the length of the second direction (DR2) may be wider than the length of the second light-blocking layer (BM2) in the first direction (DR1) or the length of the second light-blocking layer (BM2) in the second direction (DR2). The first light-blocking layer (BM1) and the second light-blocking layer (BM2) may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The first light-blocking layer (BM1) and the second light-blocking layer (BM2) may include a light-blocking material to prevent light from a light-emitting element (LE) of a sub-pixel from propagating to an adjacent sub-pixel. For example, the first shading layer (BM1) and the second shading layer (BM2) may include an inorganic black pigment such as carbon black or an organic black pigment.

[0201] The second capping layer (CAP2) may be disposed on the first capping layer (CAP1) and the light-shielding layer (BM). The second capping layer (CAP2) may be disposed on the side surface and the upper surface of the light-shielding layer (BM). That is, the second capping layer (CAP2) may be disposed on the side surface of the first light-shielding layer (BM1) and the side surface and the upper surface of the second light-shielding layer (BM2).

[0202] The second reflective layer (RF2) may be disposed between the light-shielding layer (BM) and the first light conversion layer (QDL1), between the light-shielding layer (BM) and the second light conversion layer (QDL2), and between the light-shielding layer (BM) and the light-transmitting layer (TPL). The second reflective layer (RF2) may be disposed on a second capping layer (CAP2) disposed on a side surface of the first light-shielding layer (BM1) and a side surface of the second light-shielding layer (BM2). The second reflective layer (RF2) serves to reflect light that propagates in a lateral direction in the first light-conversion layer (QDL1), the second light-conversion layer (QDL2), and the light-transmitting layer (TPL).

[0203] The second reflective layer (RF2) may include a metal material with a high reflectivity, such as aluminum (Al). The thickness of the second reflective layer (RF2) may be approximately 0.1 μm.

[0204] Alternatively, the second reflective layer (RF2) may include M pairs of first and second layers having different refractive indices (M is an integer greater than or equal to 2) to function as distributed Bragg reflectors (DBRs). In this case, the M first layers and the M second layers may be arranged alternately. The first and second layers may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0205] The third capping layer (CAP3) can be disposed on the second capping layer (CAP2), the second reflective layer (RF2), the first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light transmitting layer (TPL).

[0206] The first capping layer (CAP1), the second capping layer (CAP2), and the third capping layer (CAP3) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light transmitting layer (TPL) may be encapsulated by the first capping layer (CAP1), the second capping layer (CAP2), and the third capping layer (CAP3).

[0207] A fourth organic film (193) may be disposed on the third capping layer (CAP3). A plurality of color filters (CF1, CF2, CF3) may be disposed on the fourth organic film (193). The plurality of color filters (CF1, CF2, CF3) may include first color filters (CF1), second color filters (CF2), and third color filters (CF3).

[0208] The first color filter (CF1) arranged in the first sub-pixel (SPX1) can transmit the first light (light in the red wavelength band) and absorb or block the third light (light in the blue wavelength band). Therefore, the first color filter (CF1) can transmit the first light (light in the red wavelength band) converted by the first light conversion layer (QDL1) among the third light (light in the blue wavelength band) emitted from the light-emitting element (LE), and absorb or block the third light (light in the blue wavelength band) not converted by the first light conversion layer (QDL1). Therefore, the first sub-pixel (SPX1) can emit the first light (light in the red wavelength band).

[0209] The second color filter (CF2) arranged in the second sub-pixel (SPX2) can transmit the second light (light in the green wavelength band) and absorb or block the third light (light in the blue wavelength band). Therefore, the second color filter (CF2) can transmit the second light (light in the green wavelength band) converted by the second light conversion layer (QDL2) among the third light (light in the blue wavelength band) emitted from the light-emitting element (LE), and absorb or block the third light (light in the blue wavelength band) not converted by the second light conversion layer (QDL2). Therefore, the second sub-pixel (SPX2) can emit the second light (light in the green wavelength band).

[0210] The third color filter (CF3) arranged in the third sub-pixel (SPX3) can transmit the third light (light in the blue wavelength band). Therefore, the third color filter (CF3) can transmit the third light (light in the blue wavelength band) emitted from the light-emitting element (LE) passing through the light-transmitting layer (TPL). Therefore, the third sub-pixel (SPX3) can emit the third light (light in the blue wavelength band).

[0211] The first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) overlapping in the third direction (DR3) can overlap with the light-shielding layer (BM) in the third direction (DR3).

[0212] A fifth organic film (194) for planarization may be placed on multiple color filters (CF1, CF2, CF3).

[0213] The fourth organic film (193) and the fifth organic film (194) can be formed of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0214] According to one embodiment, the second protective layer (INS2) is arranged to cover one end of the contact electrode (CTE), thereby preventing a short between the pixel electrode (PXE) and the common electrode (CE).

[0215] FIG. 10 is a layout diagram showing pixels of a display area according to one embodiment.

[0216] The embodiment of FIG. 10 differs from the embodiment of FIG. 5 in that the first sub-pixel (SPX1) additionally includes a first common electrode (CE1), the second sub-pixel (SPX2) additionally includes a second common electrode (CE2), the third sub-pixel (SPX3) additionally includes a third common electrode (CE3), and the light-emitting element (LE) is a flip-type micro LED. In the embodiment of FIG. 10, descriptions overlapping with those of the embodiment of FIG. 5 are omitted.

[0217] Referring to FIG. 10, each of the pixel electrodes (PXE1, PXE2, PXE3) and the common electrodes (CE1, CE2, CE3) may have a rectangular planar shape. The area of ​​the first pixel electrode (PXE1) may be the same as the area of ​​the first common electrode (CE1), the area of ​​the second pixel electrode (PXE2) may be the same as the area of ​​the second common electrode (CE2), and the area of ​​the third pixel electrode (PXE3) may be the same as the area of ​​the third common electrode (CE3), but the embodiments of the present specification are not limited thereto.

[0218] In the first sub-pixel (SPX1), the first pixel electrode (PXE1) and the first common electrode (CE1) may be arranged to be spaced apart from each other in the second direction (DR2). In the second sub-pixel (SPX2), the second pixel electrode (PXE2) and the second common electrode (CE2) may be arranged to be spaced apart from each other in the second direction (DR2). In the third sub-pixel (SPX3), the third pixel electrode (PXE3) and the third common electrode (CE3) may be arranged to be spaced apart from each other in the second direction (DR2).

[0219] The first common electrode (CE1) can be connected to a second power line (VSL) to which a second driving voltage (VSS) is applied through a first common connection hole (CT4). The second common electrode (CE2) can be connected to the second power line (VSL) through a second common connection hole (CT5). The third common electrode (CE3) can be connected to the second power line (VSL) through a third common connection hole (CT6). Therefore, the second driving voltage (VSS) can be applied to each of the common electrodes (CE1, CE2, and CE3).

[0220] Fig. 11 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I2-I2' of Fig. 10. Fig. 12 is a cross-sectional view showing in detail an example of area B of Fig. 11.

[0221] The embodiments of FIGS. 11 and 12 differ from the embodiments of FIGS. 6 and 7 in that the light emitting element (LE) is a flip-type micro LED. In the embodiments of FIGS. 11 and 12, descriptions that overlap with those of the embodiments of FIGS. 6 and 7 are omitted.

[0222] Referring to FIGS. 11 and 12, the light-emitting element (LE) may be a flip-type micro LED. The flip-type micro LED refers to an LED in which contact electrodes (CTE1, CTE2) are formed on one surface (e.g., the lower surface) of the light-emitting element (LE).

[0223] A pixel electrode layer including pixel electrodes (PXE1, PXE2, PXE3) and common electrodes (CE1, CE2, CE3) may be disposed on a second organic film (180).

[0224] Each of the light emitting elements (LE) may include a current spreading layer (CSL), a first semiconductor layer (SEM1), an active layer (MQW), a second semiconductor layer (SEM2), a third semiconductor layer (USE), and an outer layer (OSL). In one embodiment, each of the light emitting elements (LE) may omit the current spreading layer (CSL). In one embodiment, each of the light emitting elements (LE) may further include contact electrodes (CTE1, CTE2). For example, the first contact electrode (CTE1) may be electrically connected to the current spreading layer (CSL), and the second contact electrode (CTE2) may further include a second contact electrode (CTE2) that contacts the first contact electrode (CTE1) and the second semiconductor layer (SEM2). In one embodiment, when the current spreading layer (CSL) is omitted, the first contact electrode (CTE1) may be electrically connected to the first semiconductor layer (SEM1).

[0225] A light emitting element (LE) has a groove (HCTE) penetrating a current spreading layer (CSL), a first semiconductor layer (SEM1), and an active layer (MQW) on one surface and exposing a second semiconductor layer (SEM2). A second contact electrode (CTE) can be electrically connected to the second semiconductor layer (SEM2) through the groove (HCTE) formed penetrating the current spreading layer (CSL), the first semiconductor layer (SEM1), the active layer (MQW), and the second semiconductor layer (SEM2).

[0226] An outer skin layer (OSL) may be disposed on one surface and a side surface of the element load (LD). The outer skin layer (OSL) may include a first protective layer (INS1), a first reflective layer (RF1), and a second protective layer (INS2).

[0227] The first protective layer (INS1) may include a first opening (OP1) and a second opening (OP2) on one surface of the first element load (LD1). The first opening (OP1) and the second opening (OP2) may be spaced apart from each other. The first opening (OP1) may be disposed on one surface of the first element load (LD1), and the second opening (OP2) may be disposed to overlap the bottom of the groove (HCTE). For example, the second semiconductor layer (SEM2) may be exposed by the second opening (OP2) of the first protective layer (INS1) overlapping the groove (HCTE).

[0228] The first reflective layer (RF1) may include a first-first reflective layer (RF1-1) and a first-second reflective layer (RF1-2). In addition, one end of the first-first reflective layer (RF1-1) and the first-second reflective layer (RF1-2) may be spaced apart from each other. The first-first reflective layer (RF1-1) and the first-second reflective layer (RF1-2) are not electrically connected.

[0229] In one embodiment, the first-first reflective layer (RF1-1) may be disposed on the current spreading layer (CSL) exposed through the first opening (OP1) of the first protective layer (INS1). In one embodiment, the first-first reflective layer (RF1-1) is electrically connected to the current spreading layer (CSL).

[0230] In one embodiment, the first-second reflective layer (RF1-2) is disposed on the second semiconductor layer (SEM2) exposed through the second opening (OP2) of the first protective layer (INS1) and may extend to the side of the groove (HCTE). The first-second reflective layer (RF1-2) is electrically connected to the second semiconductor layer (SEM2) through the second contact electrode (CTE).

[0231] In one embodiment, the first contact electrode (CTE1) may be disposed on the pixel electrode (PXE) of each sub-pixel (SPX) (e.g., with an organic pattern layer (210) inserted therebetween). For example, the first contact electrode (CTE1) may be disposed between the pixel electrode (PXE) of each sub-pixel (SPX) and the light emitting element (LE).

[0232] The first contact electrode (CTE1) is arranged along the first reflective layer (RF1), for example, the 1-1 reflective layer (RF1-1), on the first reflective layer (RF1). One end of the first contact electrode (CTE1) is arranged on one surface of the light-emitting element (LE) and is electrically connected to the current spreading layer (CSL) through the first opening (OP1). In one embodiment, the 1-1 reflective layer (RF1-1) may be electrically connected to the current spreading layer (CSL) through the first contact electrode (CTE1) on the first opening (OP1). One end of the first contact electrode (CTE1) may be arranged to extend along the side surface of the light-emitting element (LE) and cover the 1-1 reflective layer (RF1-1).

[0233] The first contact electrode (CTE1) can electrically connect the first semiconductor layer (SEM1) of the light-emitting element (LE) to the pixel electrode (PXE) of each sub-pixel (SPX) via the first connection electrode (BE1) described below.

[0234] The second contact electrode (CTE2) may be disposed on the common electrode (CE) of each sub-pixel (SPX) (e.g., with an organic pattern layer (210) inserted therebetween). For example, the second contact electrode (CTE2) may be disposed between the common electrode (CE) of each sub-pixel (SPX) and the light-emitting element (LE). The second contact electrode (CTE2) is disposed on the first reflective layer (RF1) to follow the first reflective layer (RF1), for example, the first-second reflective layer (RF1-2). One end of the second contact electrode (CTE2) may be disposed on one surface of the light-emitting element (LE) and may extend to the side surface of the groove (HCTE). The second contact electrode (CTE2) is electrically connected to the second semiconductor layer (SEM2) through the second opening (OP2). In one embodiment, the first-second reflective layer (RF1-2) may be electrically connected to the second semiconductor layer (SEM2) through the second contact electrode (CTE2) on the second opening (OP2). One end of the second contact electrode (CTE2) may be arranged to extend along the side surface of the light-emitting element (LE) and cover the first-second reflective layer (RF1-2).

[0235] Additionally, one end of the first contact electrode (CTE1) and the second contact electrode (CTE2) may be spaced apart from each other. The first contact electrode (CTE1) and the second contact electrode (CTE2) are not electrically connected.

[0236] The second contact electrode (CTE2) can connect the second semiconductor layer (SEM2) of the light-emitting element (LE) to the common electrode (CE) of each sub-pixel (SPX) via the second connection electrode (BE2).

[0237] The first contact electrode (CTE1) and the second contact electrode (CTE2) may include a metal, metal oxide, or other conductive material having a higher conductivity than the first reflective layer (RF1). For example, the first contact electrode (CTE1) and the second contact electrode (CTE2) may include any one of gold (Au), copper (Cu), and chromium (Cr).

[0238] The second protective layer (INS2) may be disposed on at least a portion of a side surface of the element load (LD). For example, the second protective layer (INS2) may be disposed on the side surface of the second element load (LD2) and the third element load (LD3), and may extend from the side surface of the third element load (LD3) to be disposed at least partially on one surface of the third element load (LD3). For example, the second protective layer (INS2) may be disposed partially along the unevenness of the third element load (LD3). Accordingly, the contact area (CTA) between the common electrode (CE) and the third element load (LD3) in a plan view may be smaller than the area (LD3A) of the third element load (LD3). In addition, since the area (LEA) of the third element load (LD3) may be the same as the area (LEA) of the light-emitting element (LE) in a plan view, the contact area (CTA) may be smaller than the area (LEA) of the light-emitting element (LE).

[0239] The second protective layer (INS2) can cover and protect one end of the first contact electrode (CTE1) and one end of the second contact electrode (CTE2).

[0240] The connecting electrode (BE) may include a first connecting electrode (BE1) and a second connecting electrode (BE2).

[0241] The first connection electrode (BE1) connects the first contact electrode (CTE1) and one of the pixel electrodes (PXE1, PXE2, PXE3). In addition, the first connection electrode (BE1) may be disposed on the upper surface and the side surface of the organic pattern layer (210). In addition, the first connection electrode (BE1) may be disposed on a part of the side surface of the light emitting element (LE) on the first contact electrode (CTE1). For example, the first connection electrode (BE1) may be disposed on a part of the first contact electrode (CTE1).

[0242] The second connection electrode (BE2) connects the second contact electrode (CTE2) and one of the common electrodes (CE1, CE2, CE3). In addition, the second connection electrode (BE2) may be disposed on the upper surface and the side surface of the organic pattern layer (210). In addition, the second connection electrode (BE2) may be disposed on a portion of the side surface of the light emitting element (LE) on the second contact electrode (CTE2). For example, the second connection electrode (BE2) may be disposed on a portion of the second contact electrode (CTE2).

[0243] Each of the first connecting electrode (BE1) and the second connecting electrode (BE2) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, each of the first connecting electrode (BE1) and the second connecting electrode (BE2) may be made of a transparent metallic material (TCO, Transparent Conductive Material) such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide) that can transmit light.

[0244] Fig. 13 is a flowchart illustrating a method for manufacturing a display device according to one embodiment. Figs. 14 to 29 are cross-sectional views illustrating a method for manufacturing a display device according to one embodiment.

[0245] Figures 14 to 29 illustrate cross-sectional views of the structure of each layer of the display device according to the formation order. Figures 14 to 29 focus on the formation of a light-emitting element and a light-emitting element layer (LEL of Figure 6), which can generally correspond to the cross-sectional views of Figure 7. Below, a method for manufacturing the display device illustrated in Figures 14 to 29 will be described in connection with Figure 13.

[0246] Referring to Fig. 14, a plurality of semiconductor material layers (USEL, SEM2L, MQWL, SEM1L) and a current spreading layer (CSL) are laminated and patterned on a growth substrate (BSUB) to form a plurality of semiconductor layer stacks. (S110 of Fig. 13)

[0247] First, a growth substrate (BSUB) is prepared. The growth substrate (BSUB) may be a sapphire substrate (Al2O3) or a transparent silicon wafer containing silicon. However, this is not limited to the above, and in one embodiment, a case where the growth substrate (BSUB) is a sapphire substrate is described as an example.

[0248] A plurality of semiconductor material layers (SEM3L, SEM2L, SLTL, MQML, EBLL, SEM1L) are formed on a growth substrate (BSUB). The plurality of semiconductor material layers grown by an epitaxial method can be formed by growing a seed crystal. Here, a method for forming the semiconductor material layers may be electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, metal-organic chemical vapor deposition (MOCVD), etc., and preferably, it can be formed by metal-organic chemical vapor deposition (MOCVD). However, it is not limited thereto.

[0249] The precursor material for forming multiple semiconductor material layers is not particularly limited within a range that can be typically selected to form the target material. For example, the precursor material may be a metal precursor containing an alkyl group, such as a methyl group or an ethyl group. Examples thereof include, but are not limited to, compounds such as trimethyl gallium (Ga(CH3)3), trimethyl aluminum (Al(CH3)3), and triethyl phosphate ((C2H5)3PO4).

[0250] Specifically, a third semiconductor material layer (USEL) is formed on a growth substrate (BSUB). Although the drawing illustrates that the third semiconductor layer (USE) is laminated in one layer, the present invention is not limited thereto, and a plurality of layers may be formed. The third semiconductor material layer (USEL) may be disposed on the uneven structure of the growth substrate (BSUB). Accordingly, unevenness is also formed on one surface of the third semiconductor layer (USE) that is in contact with the uneven structure of the growth substrate (BSUB). The uneven structure of the third semiconductor layer (USE) corresponds to the uneven structure of the growth substrate (BSUB). For example, an upwardly convex unevenness is formed on one surface of the third semiconductor layer (USE) that is in contact with the upwardly convex uneven surface of the growth substrate (BSUB). The unevenness may be any one of a hemispherical shape, a cone shape, a truncated cone shape, a pyramid shape, a truncated pyramid shape, and a cylinder shape, but is not limited thereto.

[0251] The third semiconductor layer (USE) may be arranged to reduce the lattice constant difference between the second semiconductor material layer (SEM2L) and the growth substrate (BSUB). For example, the third semiconductor material layer (USEL) may include an undoped semiconductor and may be an n-type or p-type undoped material. In an exemplary embodiment, the third semiconductor material layer (USEL) may be at least one of, but is not limited to, undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and InN.

[0252] Using the above-described method, a second semiconductor material layer (SEM2L), an active material layer (MQWL), and a first semiconductor material layer (SEM1L) are sequentially formed on a third semiconductor material layer (USEL). In another variation, a superlattice material layer may be formed between the second semiconductor material layer (SEM2L) and the active material layer (MQWL). In addition, an electron blocking material layer may be formed between the active material layer (MQWL) and the first semiconductor material layer (SEM1L). A current spreading material layer (CSLL) may further be formed on the first semiconductor material layer (SEM1L). The current spreading material layer (CSLL) may be made of a transparent metal material (TCO, Transparent Conductive Material), such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide), which can transmit light.

[0253] Referring to FIG. 15, the first element load (LD1) having a first inclination angle (θ1) can be formed by etching the active material layer (MQWL) and the first semiconductor material layer (SEM1L) using the first mask. (S120 of FIG. 13)

[0254] For example, at least the current spreading layer (CSLL), the first semiconductor material layer (SEM1L), and the active material layer (MQWL) are dry etched using the first mask. At this time, a portion of the second semiconductor layer (SEM2) may be further etched.

[0255] As the etching depth increases during dry etching, the process time increases, and the plasma exposure time of the semiconductor material layer increases, which may increase damage to the active layer. Therefore, in one embodiment, the first semiconductor material layer (SEM1L), the active material layer (MQWL), the second semiconductor material layer (SEM2L), and the third semiconductor material layer (USEL) are not etched at once, but only a portion of the first semiconductor material layer (SEM1L), the electronically active material layer (MQWL), and the second semiconductor material layer (SEM2L), which correspond to about 1 / 10 of the entire semiconductor material layer, are etched. Therefore, damage to the active layer can be reduced or minimized. Subsequently, wet etching can be additionally performed.

[0256] Referring to FIGS. 16 and 17, a second semiconductor material layer (SEM2L) and a third semiconductor material layer (USEL) may be etched using a second mask to form a second element load (LD2') having a second inclination angle (θ2). (S130 of FIG. 13)

[0257] For example, referring to FIG. 16, a dielectric material such as ZAZ (ZrO2 / Al2O3 / ZrO2) is applied on the first element load (LD1) to wrap it.

[0258] Afterwards, a second element load (LD2) is formed by a photo process. The photo process is a process for forming a desired structure by applying PR (Photoresist) on a substrate and then passing light through a mask shaped in a desired pattern. For example, the photoresist (PR2) can be formed to surround the first element load (LD1). The photoresist (PR2) may have a rectangular pillar shape that narrows toward the top. The inclination angle (θ) of the photoresist (PR2) M ) can be set to 60 degrees or more and 80 degrees or less.

[0259] The second semiconductor material layer (SEM2L) and the third semiconductor material layer (USEL) are patterned using the second mask. For example, the second semiconductor material layer (SEM2L) and the third semiconductor material layer (USEL) can be formed through a dry etching process. Depending on the shape of the photoresist (PR), the width can increase from the second semiconductor layer (SEM2) toward the third semiconductor layer (USE). The inclination angle (θ) of the photoresist (PR) M ) can be formed so that the inclination angle of the second element load (LD2) is 60 degrees or more and 80 degrees or less. By this process, each light-emitting element can be separated from each other.

[0260] Referring to FIGS. 18 to 20, a first protective layer (INS1) covering a third semiconductor layer (USE), a second semiconductor layer (SEM2), an active layer (MQW), a first semiconductor layer (SEM1), and a current spreading layer (CSL) and a first reflective layer (RF1) covering a third semiconductor layer (USE), a second semiconductor layer (SEM2), and an active layer (MQW) can be formed. (S140 of FIG. 13)

[0261] For example, referring to FIG. 18, a first protective material layer (INS1L) is formed on a growth substrate (BSUB) to cover a first element load (LD1), a second semiconductor layer (SEM2), and a third semiconductor layer (USE). The first protective material layer (INS1L) may be formed of an inorganic film, for example, a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, but is not limited thereto.

[0262] Referring to FIG. 19, a first reflective material layer is formed on a first protective material layer (INS1L) to cover a first element load (LD1), a second semiconductor layer (SEM2), and a third semiconductor layer (USE). The first reflective material layer may be deposited by a process such as sputtering, but is not limited thereto.

[0263] Next, a first reflective layer (RF1) can be formed by etching a portion of the first reflective material layer through a photo process using a third mask. For example, the first reflective material layer disposed on the third semiconductor layer (USE) can be removed. The first reflective material layer can be etched using a wet etching process, but is not limited thereto.

[0264] Referring to FIG. 20, a portion of the first reflective layer (RF1) may be etched on the upper surface of the first element load (LD1) using a fourth mask, and one or more openings (OP1, OP2) overlapping the first protective material layer (INS1L) may be formed using the reflective layer (RF1) as a mask. The first opening (OP1) and the second opening (OP2) may be formed to be spaced apart from each other. The openings (OP1, OP2) may be formed by a dry etching process, but are not limited thereto.

[0265] In this process, a portion of the upper surface of the current spreading layer (CSL) may be exposed.

[0266] Referring to FIGS. 21 to 23, a contact electrode (CTE) and a third element load (LD3) are formed. (S150 of FIG. 13)

[0267] For example, referring to FIG. 21, a conductive material layer (CTEL) is formed on the entire surface of a plurality of semiconductor layer stacks and a growth substrate (BSUB). The conductive material layer (CTEL) may be deposited through a process such as sputtering, but is not limited thereto.

[0268] Referring to FIG. 22, a portion of a conductive material layer (CTEL) is etched using a fifth mask to form a contact electrode (CTE). For example, a photoresist is formed to cover the entire conductive material layer (CTEL) that will become the contact electrode (CTE), and the conductive material layer (CTEL) not covered by the photoresist is etched using the fifth mask to form the contact electrode (CTE). One end of the contact electrode (CTE) can be formed to have a minimum length that can completely cover the first reflective layer (RF1). One end of the contact electrode (CTE) is formed to be spaced apart from the growth substrate (BSUB). The photoresist can be removed by an ashing process, but is not limited thereto.

[0269] The third element load (LD3) is formed using the following contact electrode (CTE) as a mask. The portion where the contact electrode (CTE) is not positioned becomes the third element load (LD3), and the portion of the second element load (LD2' in Fig. 21) surrounded by the contact electrode (CTE) becomes the second element load (LD2). The sides of the contact electrode (CTE) and the third element load (LD3) can be aligned and matched with each other.

[0270] In another embodiment, a separate mask may be used instead of the contact electrode (CTE) as a mask. When a separate mask is used, one end of the contact electrode and the side of the third element load (LD3) may have a step, as described in FIG. 9.

[0271] Figure 23 is an enlarged view of area C of Figure 22. As illustrated in Figure 23, during the wet etching process for forming the third element load (LD3), a gap may be formed between the growth substrate (BSUB) and the third semiconductor layer (USE) at the edge of the third semiconductor layer (USE). The degree of gap opening can be adjusted by the wet etching time and etching material.

[0272] In one embodiment, the contact area between the third semiconductor layer (USE) and the growth substrate (BSUB) is reduced by the gap formed between the growth substrate (BSUB) and the third semiconductor layer (USE), so that less energy may be required in the laser lift off (LLO) process for subsequent separation of the growth substrate (BSUB).

[0273] Referring to FIGS. 24 and 25, a second protective layer (INS2) is formed. (S160 of FIG. 13)

[0274] Referring to Fig. 24, a second protective material layer (INS2L) is applied to the entire surface of the growth substrate (BSUB). A sputtering method may be used for the application, but is not limited thereto. When forming the second protective material layer (INS2L), the gap between the growth substrate (BSUB) and the third semiconductor layer (USE) may also be filled with the second protective material layer (INS2L).

[0275] Referring to FIG. 25, a part of the second protective material layer (INS2L) is selectively etched to form a second protective layer (INS2).

[0276] For example, by using the sixth mask, the second protective material layer (INS2L) disposed on the upper surface and side surfaces of the first element load (LD1) can be etched to form a second protective layer (INS2) disposed on the side surface of the second element load (LD2), the side surface of the third element load (LD3), and at least a portion between the third element load (LD3) and the growth substrate (BSUB).

[0277] Referring to FIGS. 26 and 27, a light emitting element (LE) is transferred onto a pixel electrode (PXE) of a circuit board. (S170 of FIG. 13)

[0278] The light-emitting element (LE) of the growth substrate (BSUB) manufactured in FIG. 26 is transferred to a target substrate. In one embodiment, the target substrate is described as a circuit board for convenience of explanation, but is not limited thereto. For example, the target substrate may be a relay substrate.

[0279] The light emitting element (LE) of the growth substrate (BSUB) is aligned to a desired position on the target substrate. For example, an organic pattern layer (210) is formed on the pixel electrode (PXE), and the light emitting element (LE) is positioned on the organic pattern layer (210).

[0280] The organic pattern layer (210) may be a photosensitive organic layer such as a photoresist. Alternatively, the organic pattern layer (210) may be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like. The thickness of the organic pattern layer (210) may be thicker than the thickness of the pixel electrode layer.

[0281] A portion of the light emitting element (LE) disposed on the organic pattern layer (210) may be temporarily fixed by being embedded in the organic pattern layer (210). For example, a portion of the contact electrode (CTE) of a plurality of light emitting elements (LE) may be fixed by being embedded in the organic pattern layer (210).

[0282] In this way, when the organic pattern layer (210) is a photosensitive organic layer such as a photoresist, after the organic pattern layer (210) is cured (soft baked) at a first temperature, at least a portion of each of the plurality of light-emitting elements (LE) is inserted into the organic pattern layer (210). Then, the organic pattern layer (210) can be completely cured at a second temperature higher than the first temperature. The first temperature may be approximately 100 degrees, and the second temperature may be approximately 230 degrees, but the embodiments of the present specification are not limited thereto. In the first curing, the first temperature is low enough to completely cure the organic pattern layer (210), so the organic pattern layer (210) can have fluidity. On the other hand, the second curing is performed at the second temperature for approximately 30 minutes and can completely cure the organic pattern layer (210). The completely cured organic pattern layer (210) does not have fluidity. When the light emitting element (LE) is embedded and has fluidity after the first curing, it can be completely fixed to the organic pattern layer (210) after the second curing.

[0283] Afterwards, the light emitting elements (LE) can be separated from the growth substrate (BSUB). The growth substrate (BSUB) is separated from each of the third semiconductor layers (USE) of the plurality of light emitting elements (LE).

[0284] The process of separating the growth substrate (BSUB) can be separated by a laser lift-off (LLO) process. The laser lift-off process uses a laser, and a KrF excimer laser (248 nm wavelength) can be used as a source. The energy density of the excimer laser is irradiated in a range of about 550 mJ / cm2 to 950 mJ / cm2, and the incident area can be in a range of 50 x 50 ㎛2 to 1 x 1 ㎠, but is not limited thereto. By irradiating the laser to the growth substrate (BSUB), the growth substrate (BSUB) can be separated from the light emitting element (LE).

[0285] In this way, after the lift-off process, a cleaning process can be performed to remove contaminants from the light-emitting element. For example, Cl2 can be used for the cleaning process, and at this time, HCl or the like can be formed. In this way, even if HCl is formed, since the reflective layer (RF1) is not exposed in the light-emitting element (LE) according to one embodiment, damage to the reflective layer (RF1) can be minimized. For example, if one end of the reflective layer (RF1) formed of aluminum (Al), silver (Ag), or the like is exposed, the HCl can penetrate through the exposed reflective layer and damage not only the exposed reflective layer, but also a large portion of the reflective layer.

[0286] Thereafter, referring to FIGS. 28 and 29, a connection electrode (BE) and a common electrode (CE) are formed. (S180 of FIG. 13)

[0287] For example, referring to FIG. 28, after forming a conductive material layer on a circuit board, a portion of the conductive material layer may be removed by a photo process to form a connection electrode (BE) connecting a contact electrode (CTE) of a light-emitting element (LE) and pixel electrodes (PXE1, PXE2, PXE3). The connection electrode (BE) is formed on the contact electrode (CTE), and the second protective layer (INS2) and the connection electrode (BE) may not overlap each other on the side of the light-emitting element (LE).

[0288] The connecting electrode (BE) can serve as a bonding metal for bonding pixel electrodes (PXE) and light emitting elements (LE).

[0289] Referring to FIG. 29, a third organic layer (190) is formed on a transistor layer (TFTL) of a growth substrate (SUB) on which no light-emitting elements (LE) are disposed. The third organic layer (190) can fill spaces between the light-emitting elements (LE) and can be formed to cover side surfaces of the light-emitting elements (LE). The third organic layer (190) can be formed lower than the height of the light-emitting elements (LE). Therefore, the upper surface of the light-emitting elements (LE) can be exposed.

[0290] The common electrode (CE) covers the light emitting element (LE) and the third organic layer (190), and can be formed in direct contact with them. The common electrode (CE) can be formed continuously over the entire display area. The common electrode (CE) can be formed along the unevenness of the upper surface of the third semiconductor (SEM3) of the light emitting element (LE).

[0291] FIG. 30 is an exemplary drawing showing a smart watch including a display device according to one embodiment. Referring to FIG. 30, the display device (10_1) according to one embodiment can be applied to a smart watch (1000_1), which is one of smart devices.

[0292] FIGS. 31 and 32 are exemplary drawings showing a virtual reality device including a display device according to one embodiment.

[0293] Referring to FIGS. 31 and 32, a head-mounted display device (1000_2) according to one embodiment includes a first display device (10_2), a second display device (10_3), a display device storage unit (1100), a storage unit cover (1200), a first eyepiece lens (1210), a second eyepiece lens (1220), a head-mounted band (1300), a middle frame (1400), a first optical member (1510), a second optical member (1520), and a control circuit board (1600).

[0294] The first display device (10_2) provides an image to the user's left eye, and the second display device (10_3) provides an image to the user's right eye. Since each of the first display device (10_2) and the second display device (10_3) is substantially the same as the display device (10) described in conjunction with FIGS. 1 and 2, descriptions of the first display device (10_2) and the second display device (10_3) are omitted.

[0295] The first optical member (1510) may be positioned between the first display device (10_2) and the first eyepiece lens (1210). The second optical member (1520) may be positioned between the second display device (10_3) and the second eyepiece lens (1220). Each of the first optical member (1510) and the second optical member (1520) may include at least one convex lens.

[0296] The middle frame (1400) is disposed between the first display device (10_2) and the control circuit board (1600), and may be disposed between the second display device (10_3) and the control circuit board (1600). The middle frame (1400) serves to support and fix the first display device (10_2), the second display device (10_3), and the control circuit board (1600).

[0297] The control circuit board (1600) may be placed between the middle frame (1400) and the display device housing (1100). The control circuit board (1600) may be connected to the first display device (10_2) and the second display device (10_3) via connectors. The control circuit board (1600) may convert an image source input from the outside into digital video data (DATA) and transmit the digital video data (DATA) to the first display device (10_2) and the second display device (10_3) via the connectors.

[0298] The control circuit board (1600) can transmit digital video data (DATA) corresponding to a left-eye image optimized for the user's left eye to the first display device (10_2) and digital video data (DATA) corresponding to a right-eye image optimized for the user's right eye to the second display device (10_3). Alternatively, the control circuit board (1600) can transmit the same digital video data (DATA) to the first display device (10_2) and the second display device (10_3).

[0299] The display device storage unit (1100) serves to store the first display device (10_2), the second display device (10_3), the middle frame (1400), the first optical member (1510), the second optical member (1520), and the control circuit board (1600). The storage unit cover (1200) is arranged to cover an open surface of the display device storage unit (1100). The storage unit cover (1200) may include a first eyepiece (1210) for the user's left eye and a second eyepiece (1220) for the user's right eye. In FIGS. 15 and 16 , the first eyepiece (1210) and the second eyepiece (1220) are separately arranged, but the embodiment of the present specification is not limited thereto. The first eyepiece (1210) and the second eyepiece (1220) may be combined into one.

[0300] The first eyepiece (1210) can be aligned with the first display device (10_2) and the first optical member (1510), and the second eyepiece (1220) can be aligned with the second display device (10_3) and the second optical member (1520). Accordingly, the user can view the image of the first display device (10_2) enlarged into a virtual image by the first optical member (1510) through the first eyepiece (1210), and can view the image of the second display device (10_3) enlarged into a virtual image by the second optical member (1520) through the second eyepiece (1220).

[0301] The head-mounted band (1300) serves to secure the display device storage unit (1100) to the user's head so that the first eyepiece (1210) and the second eyepiece (1220) of the storage unit cover (1200) can be positioned respectively for the user's left and right eyes. If the display device storage unit (1200) is implemented in a lightweight and compact form, the head-mounted display device (1000) may be equipped with a glasses frame as shown in FIG. 17 instead of the head-mounted band (800).

[0302] In addition, the head-mounted display device (1000) may further include a battery for supplying power, an external memory slot for storing external memory, and an external connection port and wireless communication module for receiving a video source. The external connection port may be a USB (universe serial bus) terminal, a display port, or an HDMI (high-definition multimedia interface) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0303] Fig. 33 is an exemplary drawing showing a virtual reality device including a display device according to another embodiment. Fig. 33 shows a virtual reality device (1000_3) to which a display device (10_4) according to one embodiment is applied.

[0304] Referring to FIG. 33, a virtual reality device (1000_3) according to one embodiment may be a device in the form of glasses. The virtual reality device (1000_3) according to one embodiment may include a display device (10_4), a left-eye lens (10a), a right-eye lens (10b), a support frame (20), eyeglass frame legs (30a, 30b), a reflective member (40), and a display device storage unit (50).

[0305] In Fig. 33, it is exemplified that the virtual reality device (1000_3) is a glasses-type display device including glasses frame legs (30a, 30b). That is, the virtual reality device (1000_3) according to one embodiment is not limited to that illustrated in Fig. 33, and can be applied in various forms in various other electronic devices.

[0306] The display device housing (50) may include a display device (10_4) and a reflective member (40). An image displayed on the display device (10_4) may be reflected by the reflective member (40) and provided to the user's right eye through the right eye lens (10b). As a result, the user may view a virtual reality image displayed on the display device (10_4) through the right eye.

[0307] In FIG. 33, the display device housing (50) is exemplified as being arranged at the right end of the support frame (20), but the embodiment of the present specification is not limited thereto. For example, the display device housing (50) may be arranged at the left end of the support frame (20), in which case the image displayed on the display device (10_4) may be reflected by the reflective member (40) and provided to the user's left eye through the left eye lens (10a). As a result, the user may view the virtual reality image displayed on the display device (10_4) through the left eye. Alternatively, the display device housing (50) may be arranged at both the left end and the right end of the support frame (20), in which case the user may view the virtual reality image displayed on the display device (10_4) through both the left eye and the right eye.

[0308] Fig. 34 is an exemplary drawing showing an automobile instrument panel and center fascia including display devices according to one embodiment. Fig. 34 shows an automobile to which display devices (10_a, 10_b, 10_c, 10_d, 10_e) according to one embodiment are applied.

[0309] Referring to FIG. 34, display devices (10_a, 10_b, 10_c) according to one embodiment may be applied to a dashboard of a vehicle, a center fascia of a vehicle, or a CID (Center Information Display) placed on a dashboard of a vehicle. In addition, display devices (10_d, 10_e) according to one embodiment may be applied to a room mirror display that replaces a side mirror of a vehicle.

[0310] FIG. 35 is an exemplary drawing showing a transparent display device including a display device according to one embodiment.

[0311] Referring to FIG. 35, a display device (10_5) according to one embodiment can be applied to a transparent display device. The transparent display device can display an image (IM) and transmit light at the same time. Therefore, a user positioned at the front of the transparent display device can view not only the image (IM) displayed on the display device (10_5), but also an object (RS) or background positioned at the back of the transparent display device. When the display device (10_5) is applied to a transparent display device, the substrate of the display device (10_5) can include a light-transmitting portion that can transmit light or can be formed of a material that can transmit light.

Claims

1. A substrate on which pixel electrodes are arranged; A light emitting element disposed on the pixel electrode, the light emitting element including a device load and a contact electrode disposed on one surface and a side surface of the device load; a connecting electrode electrically connecting the contact electrode and the pixel electrode; and including a common electrode disposed on the light emitting element, The above element load is, A first element load comprising a first semiconductor layer and an active layer, the side surface of which has a first inclined angle; A second element load disposed on the first element load and having a side surface having a second inclined angle; and A third element load is disposed on the second element load and has a side surface having a third inclined angle, The above light emitting element, A first protective layer disposed on one side and side of the first element load and on the side of the second element load; A reflective layer disposed on the first protective layer and disposed on one surface and a side surface of the first element load and a side surface of the second element load; and A display device further comprising a second protective layer disposed on a side surface of the second element load, a side surface of the third element load, and an edge of an upper surface of the third element load.

2. A display device according to claim 1, wherein the contact electrode is disposed on one side of the first element load on the reflective layer and extends to the side of the first element load and the side of the second element load.

3. In paragraph 1, The contact electrode is disposed between the reflective layer and the second protective layer on the second element load side, A display device, wherein one end of the reflective layer is completely surrounded by the first protective layer and the contact electrode on the second element load side.

4. In paragraph 1, A display device wherein the first protective layer, the reflective layer and the contact electrode are not disposed on the side of the third element load.

5. In paragraph 1, A display device, wherein the third semiconductor layer has a rough structure.

6. In paragraph 5, A display device, wherein the second protective layer extends from the side of the third element load and is positioned at the edge of the uneven structure of the third semiconductor layer.

7. In paragraph 1, A display device in which the second protective layer becomes thinner from the upper surface of the third semiconductor layer of the element load toward the inside.

8. In paragraph 1, Further comprising an organic pattern layer disposed on the pixel electrode and disposed on the lower surface of the light emitting element, A display device, wherein the connecting electrode is arranged on one side of the pixel electrode, a side of the organic pattern layer, and a side of the contact electrode of the light-emitting element.

9. In paragraph 1, The first protective layer has one or more openings defined on one surface of the first element load, A display device, wherein the above contact electrode is electrically connected to the element load exposed by the above opening.

10. In paragraph 1, A display device wherein the contact electrode has higher conductivity and lower reflectivity than the reflective layer.

11. In paragraph 1, The display device, wherein the second inclination angle is smaller than the first inclination angle and the third inclination angle.

12. A display device according to claim 11, wherein the second inclination angle is 60 degrees or more and 80 degrees.

13. In paragraph 1, A display device in which the second element load becomes wider as it goes toward the third element load, and the width of the third element load is wider than the width of the first element load.

14. A device load in which a first semiconductor layer, an active layer, a second semiconductor layer, and a third semiconductor layer are sequentially stacked, and which is divided into a first device load, a second device load, and a third device load according to an inclination angle; A first protective layer disposed on one side and side of the first element load and on the side of the second element load; A reflective layer disposed on the second protective layer and disposed on one surface and a side surface of the first element load and a side surface of the second element load; A contact electrode disposed on one side of the first element load on the reflective layer and extending to the side of the first element load and the side of the second element load; and A second protective layer disposed on the side of the second element load, the side of the third element load, and the edge of the upper surface of the third element load A light emitting element comprising:

15. In paragraph 14, The third semiconductor layer has a rough structure, A light emitting element in which the second protective layer is disposed at the edge of the uneven structure of the third semiconductor layer.

16. In paragraph 14, A light emitting element in which the second protective layer becomes thinner from the upper surface of the third semiconductor layer toward the inside.

17. In paragraph 14, The second inclination angle of the second element load is smaller than the first inclination angle of the first element load and the third inclination angle of the third element load. A light emitting element wherein the second inclination angle is 60 degrees or more and 80 degrees.

18. A step of forming a third semiconductor material layer, a second semiconductor material layer, an active material layer, and a first semiconductor material layer on a growth substrate; A step of forming a first element load having a first inclination angle by etching an active material layer and a first semiconductor material layer using a first mask; A step of forming a second element load having a second inclination angle by etching the second semiconductor material layer and the third semiconductor material layer using a second mask; A step of forming a third semiconductor material layer, a second semiconductor material layer, an active material layer, a first protective layer covering the first semiconductor material layer, a reflective layer, and a contact electrode; A step of forming a third element load having a third inclination angle by etching a portion of the second element load using a third mask; and A step of forming a second protective layer disposed on the side of the second element load and the side of the third element load, A method for manufacturing a display device, wherein the second protective layer extends from a side of the third element load and is disposed between the edge gap between the third element load and the second protective layer.

19. In paragraph 18, A step of transferring a light-emitting element including the first element load, the second element load, and the third element load to a circuit board having a pixel electrode; and A method for manufacturing a display device further comprising the step of forming a connecting electrode connecting the contact electrode and the pixel electrode.

20. In paragraph 19, The step of transferring the light-emitting element to a circuit board having the pixel electrode is as follows: A step of forming an organic pattern layer as an adhesive layer on the pixel electrode; and A method for manufacturing a display device, comprising the steps of arranging a plurality of light-emitting elements on the organic pattern layer and fixing the light-emitting elements by curing the organic pattern layer.

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