Circuit functional signal monitoring based on signature generation

Abstract

A circuit configured to monitor functional signals comprises a signal selection unit configured to select signals for monitoring from one or more signal sources and a signature generation unit configured to generate signatures for the selected signals. The signature generation unit comprises one or more multiple-input signature registers. Each of the one or more multiple-input signature registers being constructed based on an n-bit hybrid ring generator.

Description

[0001] Circuit Functional Signal Monitoring Based On Signature Generation

[0002] FIELD OF THE DISCLOSED TECHNIQUES

[0003]

[0001] The presently disclosed techniques relate to the field of on-chip monitoring of circuit activities. Various implementations of the disclosed techniques may be particularly useful for generating digital signatures for circuit activities in a normal mode of operation.

[0004] BACKGROUND OF THE DISCLOSED TECHNIQUES

[0005]

[0002] Embedded systems comprising multiple core devices incorporated on to a printed circuit board (PCB) have been in use for many years. The core devices, such as a central processing unit (CPU), memory, secondary storage and other computing or electronic system components, communicate via a series of buses connected between each component and the printed circuit board. Increasing demand for smaller electronic products and the growth in mobile computing and telecommunications has led to the development of so-called System-on-Chip (SoC) devices. Rather than multiple core devices on a PCB, an SoC is an integrated chip, or circuit, where most or all of the components of a system are integrated onto a single substrate. Communication between the components takes place by means of an internal bus system, with all traffic in the embedded system conveyed over these buses. Given that such SoC devices are increasingly implemented within mobile devices (smartphones, tablets) and in other applications, such as vehicles, the integrity of the data being communicated within the SoC is a primary concern. Data corruption or data error may occur due to variety or reasons, including malicious entities (viruses and malware), hardware or system malfunction or system corruption, and can result in the alteration of data from its expected or correct form. This is manifested as a change in one or more bits in a signal.

[0003] Silent data corruption occurs when data errors go undetected, risking that the undetected errors propagate through the SoC and are utilized by the various components. Whilst initially this may be a benign error in more extreme cases the error propagation may lead to cascading failures within the SoC or in any device or system that the SoC is deployed in. Error detection within an SoC is therefore of great importance in maintaining the operation of the system. One manner in which errors may be detected during a normal mode of operation of the SoC is by analyzing transaction communications over the existing interconnect circuitry. This may include parity and cyclic redundancy checks to determine whether the data contains an error. However, whilst effective, such a methodology involves both analyzing transactions and scanning memory blocks to determine if an error has been stored. A simpler alternative for use when the SoC is in a normal mode of operation would therefore be desirable.

[0006]

[0004] Another option to determine whether or not there are faults inherent in the SoC itself is to utilize a PRBS (pseudo-random binary sequence) monitor. A PRBS is a binary sequence that, although generated using a deterministic algorithm, is difficult to predict. When generated by a linear feedback shift register acting as a pattern generator the PRBS may be used for exhaustive testing of an integrated circuit. For example, a signature representing a “good” circuit can be compared with the signature of a Device Under Test (DUT) to determine whether or not the physical circuit is functioning correctly. However, this requires additional logic to be added to the DUT and can only be carried out as part of the design process in a test mode and does not allow any form of monitoring during the normal mode of operation of an SoC. Therefore, whilst the process is relatively simple in determining whether data corruption could occur from faults within the SoC itself, this is only of limited benefit.

[0007]

[0005] It is therefore of interest to be able to provide a method of monitoring activity on an integrated chip, such as an SoC, during its normal mode of operation to determine whether or not data corruption or incorrect operation has occurred. BRIEF SUMMARY OF THE DISCLOSED TECHNIQUES

[0008]

[0006] Various aspects of the disclosed technology relate to circuit functional signal monitoring based on signature generation. In one aspect, there is a circuit, comprising: a signal selection unit configured to select h signals from one or more signal sources (h > 1); and a signature generation unit configured to generate in signatures for the h signals (m > 1), the signature generation unit comprising one or more multiple-input signature registers, each of the one or more multiple-input signature registers being constructed based on an w-bit hybrid ring generator, an w-bit hybrid ring generator-based multiple-input signature register comprising n state elements coupled to each other to form an w-bit ringlike structure in a schematic diagram, k feedback-enable devices, and injection devices configured to inject bits into the w-bit ringlike structure, the w-bit ringlike structure having a top row and a bottom row, each of the top row and the bottom row having at least one of the n state elements and at least one of the k feedback-enable devices, each of the k feedback-enable devices being coupled to a state element on a different row through one of k feedback lines.

[0009]

[0007] The circuit may further comprise: an analysis unit configured to analyze the in signatures.

[0010]

[0008] The numbers of state elements in the n state elements placed on the top row and the bottom row may be equal or differ by one, the numbers of feedback-enable devices in the k feedback-enable devices placed on the top row and the bottom row may be equal or differ by one, k may be greater than 2, none of the k feedback lines may cross each other, and feedback lines coupled to feedback-enable devices on the top row and feedback lines coupled to feedback-enable devices on the bottom row may be placed alternatively with respective to each other. The k feedback lines may be distributed such that the numbers of two groups of state elements on the top row or on the bottom row between any three neighboring feedback lines or between two neighboring feedback lines and their neighboring end of the ringlike structure are equal or differ by no more than two.

[0009] The signal selection unit may comprise a circuit configured to generate start and stop signals for the one or more multiple-input signature registers.

[0011]

[0010] The signal selection unit may receive a mask signal for masking certain bits of one of the h signals.

[0012]

[0011] In another aspect, there are one or more non-transitory computer-readable media storing computer-executable instructions for causing one or more processors to perform a method, the method comprising: creating the above circuit in a circuit design.

[0013]

[0012] Certain inventive aspects are set out in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features of the independent claims and with features of other dependent claims as appropriate and not merely as explicitly set out in the claims.

[0014]

[0013] Certain objects and advantages of various inventive aspects have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the disclosed techniques. Thus, for example, those skilled in the art will recognize that the disclosed techniques may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein.

[0015] BRIEF DESCRIPTION OF THE DRAWINGS

[0016]

[0014] Figure 1 illustrates an example of a circuit for functional signal monitoring that may be implemented according to various embodiments of the disclosed technology.

[0017]

[0015] Figure 2 illustrates an example of a circuit for generating start and stop signals that may be implemented according to various embodiments of the disclosed technology.

[0016] Figure 3 illustrates an example of an w-bit hybrid ring generator that may be implemented according to various embodiments of the disclosed technology.

[0018]

[0017] Figure 4 illustrates a flowchart showing a process for generating a maximum-length hybrid ring generator-based system that may be implemented according to various examples of the disclosed technology.

[0019]

[0018] Figure 5 illustrates a 4-bit ring generator and a lookup table which are used to show how the primitiveness test operates.

[0020]

[0019] Figure 6A illustrates an example conventional 32-bit ring generator that implements a primitive polynomial.

[0021]

[0020] Figure 6B illustrates an example 32-bit hybrid ring generator and its feedback function corresponding to the primitive polynomial of Fig. 6A.

[0022]

[0021] Figure 7 illustrates an example of an analysis unit that may be implemented according to various embodiments of the disclosed technology.

[0023]

[0022] Figure 8 illustrates an example of a programmable computer system with which various embodiments of the disclosed technology may be employed.

[0024] DETAILED DESCRIPTION OF THE DISCLOSED TECHNIQUES

[0025]

[0023] Various aspects of the disclosed technology relate to circuit functional signal monitoring based on signature generation. In the following description, numerous details are set forth for the purpose of explanation. However, one of ordinary skill in the art will realize that the disclosed technology may be practiced without the use of these specific details. In other instances, well-known features have not been described in detail to avoid obscuring the disclosed technology.

[0026]

[0024] Some of the techniques described herein can be implemented in software instructions stored on a computer-readable medium, software instructions executed on a computer, or some combination of both. Some of the disclosed techniques, for example, can be implemented as part of an electronic design automation (EDA) tool. Such methods can be executed on a single computer or on networked computers.

[0027]

[0025] Although the operations of the disclosed methods are described in a particular sequential order for convenient presentation, it should be understood that this manner of description encompasses rearrangements, unless a particular ordering is required by specific language set forth below. For example, operations described sequentially may in some cases be rearranged or performed concurrently. Moreover, for the sake of simplicity, the disclosed flow charts and block diagrams typically do not show the various ways in which particular methods can be used in conjunction with other methods.

[0028]

[0026] The detailed description of a method or a device sometimes uses terms like “configure” and “select” to describe the disclosed method or the device function / structure. Such terms are high-level descriptions. The actual operations or functions / structures that correspond to these terms will vary depending on the particular implementation and are readily discernible by one of ordinary skill in the art.

[0027] As used in this disclosure, the singular forms “a,” “an,” and “the” include the plural forms unless the context clearly dictates otherwise. Additionally, the term “includes” means “comprises.” Moreover, unless the context dictates otherwise, the term “coupled” means electrically or electromagnetically connected or linked and includes both direct connections or direct links and indirect connections or indirect links through one or more intermediate elements not affecting the intended operation of the circuit.

[0029]

[0028] Additionally, as used herein, the term “design” is intended to encompass data describing an entire integrated circuit device. This term also is intended to encompass a smaller group of data describing one or more components of an entire device such as a portion of an integrated circuit device nevertheless.

[0030]

[0029] Fig. 1 illustrates an example of a circuit 100 for functional signal monitoring that may be implemented according to various embodiments of the disclosed technology. The circuit 100 comprises a signal selection unit 110 and a signature generation unit 120. The signal selection unit 110 can be configured to select h signals for signature generation from one or more signal sources 130. Here h is an integer, equal to or greater than one. The h signals can be those capable of transmission over exemplary communication interfaces such as traditional debug interfaces such as JTAG, parallel trace input / output, and Aurora based high-speed serial interface, and reuse of system interfaces such as USB, Ethernet, RS232, PCIe and CAN. Alternatively, the h signals may comprise address signals, control signals (signifying status, enable or other control action), security information (such as interconnect side-band signals) or the like, or a combination of any of these.

[0031]

[0030] The signal selection unit 110 may be in the form of a digital filter array. The signal selection unit 110 may be further configured to generate start and stop signals 160 for signature generation. For each of the h signals, the signal selection unit 110 may also be configured to select certain bits based on mask signals 170 for signature generation.

[0031] The signature generation unit 120 is shown to comprise a plurality of multiple-input signature registers 121, 122, ..., 123 and is configured to generate m signatures for the h signals. Here m is an integer, equal to or greater than one, and m can be equal to or not equal to h. When m = h = 1, there is a one-to-one correspondence of a single signal to a single corresponding signature. When m > 1, h > 1 and m = h, there is a many-to-many correspondence of signals and corresponding signatures. When h > 1 and m = 1, many signals are combined into a single signature. This may be a group of signals where once abnormal behavior of the group is observed, an alarm is raised. For example, the signature represents the behavior of the group of signals within the time window between the start and stop signals. When h =1 and m > 1, a single signal is represented by m signatures. While more than one multiple-input signature register is shown in Fig. 1, it should be noted that the signature generation unit 120 can comprise only one multipleinput signature register, i.e., m = 1, but h can still be equal to or greater than one.

[0032]

[0032] Each of the multiple- input signature registers 121, 122, ... , 123 can be constructed based on an w-bit hybrid ring generator. The w-bit hybrid ring generator is configured to implement a primitive polynomial of degree n and thus can yield a bit sequence comprising 2” - 1 states. Here, n is an integer. In a typical application, n is greater than 4. An w-bit hybrid ring generator-based multiple-input signature register comprises n state elements coupled to each other to form an w-bit ringlike structure in a schematic diagram, k feedback-enable devices, and injection devices configured to inject bits into the w-bit ringlike structure. The w-bit ringlike structure has a top row and a bottom row. Each of the top row and the bottom row has at least one of the n state elements and at least one of the k feedback-enable devices. Each of the k feedback-enable devices is coupled to a state element on a different row through one of k feedback lines. The injection devices are configured to inject bits into the w-bit ringlike structure in a parallel fashion. These bits can circulate in the w-bit ringlike structure until a bit sequence, a signature, is outputted.

[0033] By placing the k feedback-enable devices on both the top row and the bottom row, hybrid ring generators allow the feedback lines to connect in both directions: from top to bottom or vice versa. This arrangement can accelerate circulation of data injected into hybrid ring generator-based multiple-input signature register and thus can provide rapid error propagation. This is desirable in monitoring mission-mode (functional) logic activities. Hybrid ring generators can also have a minimal probability of aliasing due to the implementation of a primitive polynomial. Moreover, hybrid ring generators can employ, in many cases, fewer feedback taps than the number of terms of the deployed characteristic polynomial. Compared to conventional ring generators with popular and commonly deployed Fibonacci or Galois linear feedback shift registers (LFSRs) implementing the same characteristic (feedback) polynomials, fewer feedback taps can help reduce silicon area overhead and simplify the resultant circuit layout and routing. Detailed descriptions of hybrid ring generators will be presented below.

[0033]

[0034] The multiple- input signature registers 121, 122, ... , 123 can be configured and controlled by configuration and control signals 150. One of the configuration and control signals 150 may be the start and stop signals 160 generated by the signal selection unit 110. Other configuration and control signals 150 may comprise seeds to initialize the multipleinput signature registers 121, 122, ... , 123 and clock signals for the multiple-input signature registers 121, 122, ..., 123.

[0034]

[0035] With some implementations of the disclosed technology, the circuit 100 may further comprise an analysis unit 140 configured to analyze the m signatures generated by the signature generation unit 120. Upon detecting a mismatch between any of the m signatures and its expected signature value, the analysis unit 140 can be configured to send an alarm signal. With some other implementations of the disclosed technology, the m signatures can be sent out of the chip for analysis.

[0036] Fig. 2 illustrates an example of a circuit 200 for generating start and stop signals that may be implemented according to various embodiments of the disclosed technology. The circuit 200 comprises event generator 210 and three masking units 220, 230 and 240. The masking unit 220 can be configured to select certain bits of an input signal 250 based on a mask 260. The input signal can be an address signal from an address bus. The masking units 230 and 240 can be configured to select, based on the same mask 260, certain bits of a start value 270 and a stop value 280, respectively. The event generator 210 can be configured to compare the selected bits of the input signal 250 with the selected bits of the start value 270 and the stop value 280. If the selected bits of the input signal 250 match those of the start value 270, the event generator 210 will generate a start signal 290; and if the selected bits of the input signal 250 match those of the stop value 280, the event generator 210 will generate a stop signal 295. The start signal 290 and the stop signal 295 can be used to control a signature generation process performed by a multipleinput signature register.

[0035]

[0037] The circuit for generating start / stop signals 200 can be included in the signal selection unit 110 in Fig. 1 and the generated start signal 290 and the stop signal 295 can be used by the multiple-input signature registers 121, 122, ... , 123 in Fig. 1. To monitor the boot process of a central processing unit (CPU), for example, the start value 270 and the stop value 280 can define the boundary of addresses of interest and thus only addresses within the boundary of addresses of interest can trigger the event generator 210, generating a start signal 290, which in turn can start a process of converting data on the data bus into signatures by the multiple-input signature registers 121, 122, ... , 123. Similarly, the stop signal 295 generated by the event generator 210 can complete the process. This may allow the circuit 110 to monitor execution of certain function and any transitions on the address bus during active monitoring session doesn’t cause end of this session (e.g. access to external device, or other parts of memory where variables are stored). It should be noted that the circuit 200 is just an example and different circuits can be used to generate start and stop signals. It should also be noted that start and stop signals may be derived based on software.

[0036]

[0038] Fig. 3 illustrates an example of an 77-bit hybrid ring generator 300 that may be implemented according to various embodiments of the disclosed technology. The w-bit hybrid ring generator 300 comprises n state elements 310 and & feedback-enable devices 320. Here, k is greater than 2. The state elements 310 can be implemented using flipflops. The feedback-enable devices 320 can be implemented using XOR gates.

[0037]

[0039] The n state elements 310 are connected directly or indirectly to each other to form a ringlike structure in a schematic diagram as illustrated in Fig. 3. An example indirect connection is connecting through one of the k feedback-enable devices 320. Another example of indirect connection is connecting through an injection device (another XOR gate, for example) when the w-bit hybrid ring generator 300 serves as a multiple-input test response compactor, a decompressor, a true random number generator, or a multipleinput signature register like the multiple- input signature registers in Fig. 1. The numbers of state elements placed on the top and bottom rows of the ringlike structure can be equal or differ by one.

[0038]

[0040] Each of the k feedback-enable devices 320 is placed between two neighboring state elements in the n state elements 310, receiving signals directly or indirectly from one of the two neighboring state elements and a state element on a different row via one of feedback lines 330, 340, respectively. Again, an example indirect connection with one of the two neighboring state elements may be through an injection device.

[0039]

[0041] The numbers of feedback-enable devices placed on the top and bottom rows of the w-bit hybrid ring generator 300 are equal or differ by one. The feedback lines 330 are associated with the feedback-enable devices on the top row and thus are referred to as upward feedback lines. The feedback lines 340 are associated with the feedback-enable devices on the bottom row and thus are referred to as downward feedback lines. The total number of feedback lines are equal to the number of the feedback-enable devices, k. None of the feedback lines 330, 340 cross each other. The upward feedback lines 330 and the downward feedback lines 340 are placed alternatively.

[0040]

[0042] The mutual spatial separations between the feedback lines 330, 340 may be made roughly the same so that the feedback lines 330, 340 are (approximately) uniformly distributed. For example, the numbers of two groups state elements on the top row or on the bottom row between any three neighboring feedback lines or between two neighboring feedback lines and their neighboring end of the ringlike structure are equal or differ by no more than two. They are, therefore, amenable to implementing highly modular hybrid ring generators.

[0041]

[0043] If the w-bit hybrid ring generator 300 implements a primitive polynomial of degree n over Galois field of order 2, i.e., GF (2), it will yield a sequence comprising 2” - 1 states, preserving the maximum length property of the corresponding linear feedback shift register (LFSR). This can be verified using a fast LFSR simulation technique. The computing time for this primitiveness test is proportional to n i.e., O(«2). Due to the high computational efficacy, the test can be employed to obtain the w-bit hybrid ring generator 300.

[0042]

[0044] Fig. 4 illustrates a flowchart 400 showing a process for generating a maximum-length hybrid ring generator-based system that may be implemented according to various examples of the disclosed technology. A maximum-length hybrid ring generator is a hybrid ring generator implementing a primitive polynomial, and vice versa. In operation 410, a candidate hybrid ring generator is selected. Its size (the number of state elements, ri), the desired number of feedback taps (the number of feedback-enable devices, k), and other constraints such as feedback lines being approximately uniformly distributed can be set based on the application. The numbers of state elements in the state elements placed on the top row and the bottom row are equal or differ by one. The feedback lines of the candidate hybrid ring generator do not cross each other and the upward feedback lines and the downward feedback lines are placed alternatively.

[0043]

[0045] In operation 420, a primitiveness test is performed on the candidate hybrid ring generator. The primitiveness test is based on a lemma: Suppose that 2” - 1 =papib... pms, where p\ , pi, ... , pmare distinct primes. Then an irreducible polynomial h(x) over GF (2) is primitive if and only if _v ^ l mod h(x), where c = (2” - I ) / / ?, for i = 1, 2, ... , m, wherein the ring structure implements a primitive polynomial of degree n over GF(2). The primitiveness test can analyze the corresponding / / -bit LFSR implementing h(x). When initialized to a non-zero seed s, this LFSR generates a periodic sequence of span 2” - 1, i.e., a ^-sequence, provided that: after 2” - 1 steps the seed .s occurs again, and after (2” - l) / pt steps the seed 5 does not occur again, for i = 1, 2, ... , m.

[0044]

[0046] Specifically, let an / / -bit LFSR be initialized with a seed having a single one on the jth position (stage) and then run for c clock cycles reaching state S|j, c]. This requires a single simulation step to determine states S|j, l],j = 0, ... , n - 1. Subsequently, values of S|j, 2'] can be derived using exclusively the principle of superposition since S|j, 2'] is equal to a bit-wise XOR of S [ / / / , 2'"1], where S[m, 2'"1] is only taken into account if the / / / th bit of S[ / ? / , 2'-1] is set to 1. Consequently, in / / 2steps one can obtain states S|j, 2'], i = 0, ... , n - 1, j = 0, ... , n - 1. By virtue of these values, any other state the LFSR reaches after a given number of cycles (like those specified above) can be computed in a similar fashion, i.e., by applying the principle of superposition in at most n steps.

[0045]

[0047] Fig. 5 illustrates a 4-bit ring generator 510 and a lookup table 520 which are used to show how the primitiveness test operates. The 4-bit ring generator 510 implements a primitive polynomial h(x) = x4+ x + 1. The entry located in the / th row and jth column of the lookup table 520 represents a state that the 4-bit ring generator 510 enters after 21steps, assuming that the initial state features a single 1 on the jth position in its binary representation. Single simulation steps suffice to determine the contents of the first row of the lookup table 520. The first row entry in column j stores the state that immediately follows a state comprised of all zeros but a single 1 on position j. For instance, the 4-bit ring generator 510 initialized with state 0010 moves to state 0011 in one step, which is represented by the entry in row one, column three of the lookup table 520. The entries in the remaining rows can be determined using the principle of superposition. There is no need to use any form of logic simulation.

[0046]

[0048] Assuming that its initial state was 0010, determining the state that the 4-bit ring generator 510 reaches after two clock cycles can be reduced to finding a state that the same circuit reaches after one clock cycle, provided that its current state is 0011. Superposition allows further decomposition of the problem into two simpler tasks - finding immediate successors of states 0010 and 0001 - as the superposition of these states yields state 0011. As the first row of the lookup table 520 shows, the 4-bit ring generator 510 moves in one step from states 0010 and 0001 to states 0011 and 1000, respectively. Their bit- wise sum results in state 1011. This is exactly the state that should be placed in row two, column three, of the lookup table 520.

[0047]

[0049] Using the lookup table 520, a state reachable after an arbitrary number of cycles can be found in at most n basic steps, each comprising as many as n lookups. The computational complexity of this process is thus O(«2). Let the 4-bit ring generator 510 start in state 1010. The task is to determine a state that this circuit reaches after the next 11 clock cycles. Because 11 = 2° + 21+ 23, three steps are needed. An immediate (after 2° = 1 step) successor of state 1010 can be found by determining immediate successors of states 1000 and 0010, which are, according to the lookup table 520, states 0100 and 0011, respectively. Their sum yields state 0111. Next, this state can be decomposed into three components, look up states that can be reached from them in 21= 2 steps, and find their sum, that is, 1100. Eventually, the same approach can be applied to state 1100, this time by retrieving states reachable in 23= 8 clock cycles from states 1000 and 0100. These states are 0101 and 1010, respectively. Hence, the final state is 1111.

[0048]

[0050] Referring back to Fig. 4, in operation 430, the result of the primitiveness test is checked to determine whether the candidate hybrid ring generator can generate a maximum length sequence. Specifically, whether the seed S occurs again the after 2” - 1 steps and whether the seed S does not occur again, for i = 1, 2, ... , k, after (2” - I ) / / ?, steps are checked. If the answers for both questions are yes, in operation 440, a primitive polynomial is retrieved for the candidate hybrid ring generator. The Berlekamp-Massey algorithm may be employed for this operation. If the answer for either of the questions is no, in operation 450, some of the constraints may be relaxed, primarily locations of one or more feedback taps (feedback-enable devices). In some cases, another candidate hybrid ring generator with a different degree n, a different number of feedback taps, or both needs to be selected. Then the operations 420 and 430 are repeated.

[0049]

[0051] Following the structural approach illustrated by the flow chart 400, maximum-length hybrid ring generators can be obtained. The hybrid ring generators generated in such a way are optimal in the sense of having feedback connections (feedback lines) distributed as much uniformly as possible. They are, therefore, amenable to implementing highly modular hybrid ring generators. More importantly, these hybrid ring generators feature feedback lines alternately going up and down, which can significantly accelerate circulation of data injected into the register. The circulation speed can be measured as the number of clock cycles needed for an injected signal bit to reach every flip-flop of the ring generator at least once. Furthermore, these hybrid ring generators are lightweight compared with conventional ring generators because they are capable of using the smaller number of feedback taps than the number of terms of the deployed characteristic polynomial. Experimental data show that the XOR (feedback-enable devices) count reduction for hybrid ring generators over conventional ring generators can be as high as 7.57x, for 77 < 256.

[0052] Fig. 6A illustrates an example conventional 32-bit ring generator 610 that implements a primitive polynomial 620. For a ring generator, a given feedback loop, corresponding to tap x is created by encompassing k adjacent flip-flops, beginning with the leftmost ones. For example, in Fig. 6A, the first feedback loop, corresponding to the feedback tap x4, is created by encompassing four adjacent flip-flops 14-17; the second feedback loop, corresponding to the feedback tap x5, is created by encompassing five adjacent flip-flops 14-18; and the third feedback loop, corresponding to the feedback tap x6, is created by encompassing six adjacent flip-flops 13-18. In the figure, each of the symbols 615 for the 32-bit ring generator 610 represents a pair of two-input XOR gates (feedback-enable devices) while each of the other same symbols represents a single two-input XOR gates (feedback-enable devices). In total, the 32-bit ring generator 610 has nineteen XOR gates (feedback-enable devices), corresponding to the number of the corresponding feedback function terms in primitive polynomial 620 except terms 32 and 0.

[0050]

[0053] Fig. 6B illustrates an example 32-bit hybrid ring generator 630 and its feedback function 640 corresponding to the primitive polynomial 620 of Fig. 6A. Here, the symbols and “+” are used to indicate respective tap connection directions. The 32-bit hybrid ring generator 630 has only five XOR gates 633, 635 as feedback-enable devices. Compared with the conventional 32-bit ring generator 610, the reduction of feedback-enable device count is 19 / 5 = 3.8. The three XOR gates 633 and the two XOR gates 635 are placed alternatively on the top row and the bottom row of the 32-bit hybrid ring generator 630, respectively. As such, the upward feedback lines and the downward feedback lines not only do not cross each other but also are placed alternatively with respective to each other. Moreover, all of these upward / downward feedback lines are distributed in the ringlike structure approximately uniformly. The numbers of flip-flops between neighboring feedback lines or between a neighboring feedback line and a neighboring end of the 32-bit hybrid ring generator 630 are: 2, 2, 3, 3, 3, 3 for the top row (from left to right) and 2, 2, 3, 3, 4, 2 for the bottom row (from left to right). Thus, the numbers of two groups of flip flops on the top row or on the bottom row between any three neighboring feedback lines or between two neighboring feedback lines and their neighboring end of the 32-bit hybrid ring generator 630 are equal or differ by no more than two. Such a structure allows designers to minimize area and routing complexity, optimize wire sizing, and make the overall layout compact.

[0051]

[0054] In some instances, instead of the original pseudorandom sequence produced by a ring generator or a linear feedback shift register, one may need to employ a sequence which is exactly the reverse of the original vector. Typically, this can be achieved by using a linear feedback shift register or a ring generator implementing a reciprocal polynomial h*(x) of a given polynomial h(x), where h*(x) = h(l / x). As could be expected, given an w-bit hybrid ring generator, one can easily obtain its reciprocal version by converting the feedback function of the hybrid ring generator the same way it is done for the conventional ring generators. Note that all feedback connections will maintain their original directions.

[0052]

[0055] Fig. 7 illustrates an example of an analysis unit 700 that may be implemented according to various embodiments of the disclosed technology. The analysis unit 700 can be used to implement the analysis unit 140 in Fig. 1 which is configured to analyze signatures generated by the signature generation unit 120. The analysis unit 700 is configured to compare digital signatures received from a signature generation unit like the signature generation unit 120 with stored expected digital signatures and to generate an alarm if a mismatch is detected. The analysis unit 700 comprises a multiplexer 710, a storage device 720, a comparator 730, and an alarm generator 740. The multiplexer 710 is configured to feed the digital signatures received to the comparator 730. In Fig. 7, the comparator 730 is shown to be implemented using an operational amplifier. However, it may be implemented by using an alternative such as a clocked comparator (for example, a dynamic latched comparator). The storage device 720 is configured to store the corresponding expected digital signatures, which represent the signatures if there are no errors or data corruption present in the original signals. The storage device 720 can be implemented using a register or a memory device. The alarm generator 740 is configured to generate an alarm signal to alert to a possible signal compromise. The analysis unit 700 may be separate to and in communication with the signature generation unit. This enables the analysis unit 700 to be housed remotely.

[0053]

[0056] Various examples of the disclosed technology may be implemented through the execution of software instructions by a computing device, such as a programmable computer. Accordingly, Fig. 8 shows an illustrative example of a computing device 801. As seen in this figure, the computing device 801 includes a computing unit 803 with a processing unit 805 and a system memory 807. The processing unit 805 may be any type of programmable electronic device for executing software instructions, but it will conventionally be a microprocessor. The system memory 807 may include both a readonly memory (ROM) 809 and a random access memory (RAM) 811. As will be appreciated by those of ordinary skill in the art, both the read-only memory (ROM) 809 and the random access memory (RAM) 811 may store software instructions for execution by the processing unit 805.

[0054]

[0057] The processing unit 805 and the system memory 807 are connected, either directly or indirectly, through a bus 813 or alternate communication structure, to one or more peripheral devices. For example, the processing unit 805 or the system memory 807 may be directly or indirectly connected to one or more additional memory storage devices, such as a “hard” magnetic disk drive 815, a removable magnetic disk drive 817, an optical disk drive 819, or a flash memory card 821. The processing unit 805 and the system memory 807 also may be directly or indirectly connected to one or more input devices 823 and one or more output devices 825. The input devices 823 may include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices 825 may include, for example, a monitor display, a printer and speakers. With various examples of the computing device 801, one or more of the peripheral devices 815-825 may be internally housed with the computing unit 803. Alternately, one or more of the peripheral devices 815-825 may be external to the housing for the computing unit 803 and connected to the bus 813 through, for example, a Universal Serial Bus (USB) connection.

[0055]

[0058] With some implementations, the computing unit 803 may be directly or indirectly connected to one or more network interfaces 827 for communicating with other devices making up a network. The network interface 827 translates data and control signals from the computing unit 803 into network messages according to one or more communication protocols, such as the transmission control protocol (TCP) and the Internet protocol (IP). Also, the network interface 827 may employ any suitable connection agent (or combination of agents) for connecting to a network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art, and thus will not be discussed here in more detail.

[0056]

[0059] It should be appreciated that the computing device 801 is illustrated as an example only, and it is not intended to be limiting. Various embodiments of the disclosed technology may be implemented using one or more computing devices that include the components of the computing device 801 illustrated in Fig. 8, which include only a subset of the components illustrated in Fig. 8, or which include an alternate combination of components, including components that are not shown in Fig. 8. For example, various embodiments of the disclosed technology may be implemented using a multi-processor computer, a plurality of single and / or multiprocessor computers arranged into a network, or some combination of both.

[0057] Conclusion

[0058]

[0060] Having illustrated and described the principles of the disclosed technology, it will be apparent to those skilled in the art that the disclosed embodiments can be modified in arrangement and detail without departing from such principles. In view of the many possible embodiments to which the principles of the disclosed technologies can be applied, it should be recognized that the illustrated embodiments are only preferred examples of the technologies and should not be taken as limiting the scope of the disclosed technology. Rather, the scope of the disclosed technology is defined by the following claims and their equivalents. We therefore claim as our disclosed technology all that comes within the scope and spirit of these claims.

Claims

What is claimed is:

1. A circuit, comprising: a signal selection unit configured to select h signals from one or more signal sources (h > 1); and a signature generation unit configured to generate in signatures for the h signals (m > 1), the signature generation unit comprising one or more multiple-input signature registers, each of the one or more multiple-input signature registers being constructed based on an w-bit hybrid ring generator, an w-bit hybrid ring generator-based multiple-input signature register comprising n state elements coupled to each other to form an w-bit ringlike structure in a schematic diagram, k feedback-enable devices, and injection devices configured to inject bits into the w-bit ringlike structure, the w-bit ringlike structure having a top row and a bottom row, each of the top row and the bottom row having at least one of the n state elements and at least one of the k feedbackenable devices, each of the k feedback-enable devices being coupled to a state element on a different row through one of k feedback lines.

2. The circuit recited in claim 1, further comprising: an analysis unit configured to analyze the in signatures.

3. The circuit recited in claim 1, wherein the signal selection unit comprises a circuit configured to generate start and stop signals for the one or more multiple-input signature registers.

4. The circuit recited in claim 1, wherein the signal selection unit receives a mask signal for masking certain bits of one of the h signals.

5. The circuit recited in claim 1, wherein numbers of state elements in the n state elements placed on the top row and the bottom row are equal or differ by one, numbers of feedback-enable devices in the k feedback-enable devices placed on the top row and the bottom row are equal or differ by one, k is greater than 2, none of the k feedback lines cross each other, and feedback lines coupled to feedback-enable devices on the top row and feedback lines coupled to feedback-enable devices on the bottom row are placed alternatively with respective to each other.

6. The circuit recited in claim 5, wherein the k feedback lines are distributed such that numbers of two groups of state elements on the top row or on the bottom row between any three neighboring feedback lines or between two neighboring feedback lines and their neighboring end of the ringlike structure are equal or differ by no more than two.

7. One or more computer-readable media storing computer-executable instructions for causing a computer to perform a method, the method comprising: creating a circuit in a circuit design, the circuit comprising:a signal selection unit configured to select h signals from one or more signal sources (h >1); and a signature generation unit configured to generate m signatures for the h signals (m > 1), the signature generation unit comprising one or more multiple-input signature registers, each of the one or more multiple-input signature registers being constructed based on an 77-bit hybrid ring generator, an 77-bit hybrid ring generator-based multiple-input signature register comprising n state elements coupled to each other to form an w-bit ringlike structure in a schematic diagram, k feedback-enable devices, and injection devices configured to inject bits into the w-bit ringlike structure, the w-bit ringlike structure having a top row and a bottom row, each of the top row and the bottom row having at least one of the n state elements and at least one of the k feedbackenable devices, each of the k feedback-enable devices being coupled to a state element on a different row through one of k feedback lines.

8. The one or more computer-readable media recited in claim 7, wherein the circuit further comprises: an analysis unit configured to analyze the in signatures.

9. The one or more computer-readable media recited in claim 7, wherein the signal selection unit comprises a circuit configured to generate start and stop signals for the one or more multiple-input signature registers.

10. The one or more computer-readable media recited in claim 7, wherein the signal selection unit receives a mask signal for masking certain bits of one of the h signals.

11. The one or more computer-readable media recited in claim 7, wherein numbers of state elements in the n state elements placed on the top row and the bottom row are equal or differ by one, numbers of feedback-enable devices in the k feedback-enable devices placed on the top row and the bottom row are equal or differ by one, k is greater than 2, none of the k feedback lines cross each other, and feedback lines coupled to feedback-enable devices on the top row and feedback lines coupled to feedback-enable devices on the bottom row are placed alternatively with respective to each other.

12. The one or more computer-readable media recited in claim 11, wherein the k feedback lines are distributed such that numbers of two groups of state elements on the top row or on the bottom row between any three neighboring feedback lines or between two neighboring feedback lines and their neighboring end of the ringlike structure are equal or differ by no more than two.

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