Inspection pattern, element substrate, and display device

Abstract

This inspection pattern (30) is provided with: a substrate layer (5); a gate insulating film (14) that is provided on the substrate layer (5); an inspection object layer (38) that is formed of an oxide semiconductor and is provided on the gate insulating film (14); a conduction electrode (40) that is connected to the inspection object layer (38); and a passivation film (22) that is provided so as to cover the inspection object layer (38) and the conduction electrode (40). A first contact hole (Ha) which penetrates the conduction electrode (40) is formed in the passivation film (22).

Description

Inspection pattern, element substrate and display device

[0001] The present disclosure relates to a test pattern, an element substrate, and a display device.

[0002] Some display devices, such as organic electroluminescence (EL) display devices and liquid crystal display devices, use thin film transistors (hereinafter referred to as TFTs) that have an oxide semiconductor layer, typically an In—Ga—Zn—O-based semiconductor containing indium (In), gallium (Ga), and zinc (Zn). To control the performance of such TFTs, the state of the oxide semiconductor layer is inspected during the manufacturing process of the display device.

[0003] A technique for inspecting the state of an oxide semiconductor layer is disclosed, for example, in Patent Document 1. The circuit board disclosed in Patent Document 1 is provided with a trap level measurement pattern. The trap level measurement pattern is a pattern in which an oxide semiconductor layer is provided between a first electrode and a second electrode, and enables inspection of not only the state of oxygen vacancies in the oxide semiconductor but also the state of oxygen vacancies at the interfaces between the oxide semiconductor layer and the first electrode and the second electrode.

[0004] JP 2013-93470 A

[0005] The performance of semiconductor devices, such as TFTs, that include an oxide semiconductor layer is significantly affected by the composition ratio and redox state of the oxide semiconductor layer. Therefore, controlling the composition ratio and redox state of the oxide semiconductor layer is extremely important for ensuring the performance of the semiconductor device. However, there is currently no established method for accurately analyzing the composition ratio and redox state of the oxide semiconductor layer.

[0006] An object of the present disclosure is to accurately analyze the composition and redox state of an oxide semiconductor in a semiconductor device.

[0007] The present disclosure relates to a test pattern. The test pattern according to the present disclosure includes a substrate, a first insulating film formed on the substrate and made of an inorganic insulating material, an inspection target layer formed on the first insulating film and made of an oxide semiconductor, a second insulating film formed of an inorganic insulating material and covering the inspection target layer, a conductive electrode formed above the inspection target layer and connected to the inspection target layer, and a third insulating film formed of an inorganic insulating material and covering the conductive electrode. A first contact hole penetrating the conductive electrode is formed in the third insulating film.

[0008] The test pattern according to the present disclosure allows for accurate analysis of the composition and redox state of an oxide semiconductor in a semiconductor device.

[0009] FIG. 1 is a plan view of an organic EL display device. FIG. 2 is a plan view illustrating an enlarged portion of the display region surrounded by II in FIG. 1. FIG. 3 is a cross-sectional view of the organic EL display device taken along line III-III in FIG. 2. FIG. 4 is a schematic plan view of a TFT according to embodiment 1. FIG. 5 is a cross-sectional view of a TFT taken along line V-V in FIG. 4. FIG. 6 is a plan view illustrating an inspection pattern according to embodiment 1. FIG. 7 is a plan view of the inspection pattern taken along line VII-VII in FIG. 6. FIG. 8 is a plan view illustrating a panel base material used in the manufacture of multiple organic EL display devices. FIG. 9A is a conceptual diagram illustrating a portion of an inspection process in the manufacture of an organic EL display device. FIG. 9B is a conceptual diagram illustrating a portion of an inspection process in the manufacture of an organic EL display device. FIG. 9C is a conceptual diagram illustrating a portion of an inspection process in the manufacture of an organic EL display device. FIG. 9D is a conceptual diagram illustrating a portion of an inspection process in the manufacture of an organic EL display device. FIG. 9E is a conceptual diagram illustrating a portion of an inspection process in the manufacture of an organic EL display device. FIG. 9F is a conceptual diagram illustrating a portion of an inspection process in the manufacture of an organic EL display device. FIG. 10 is a cross-sectional view illustrating a state in which a test piece is set on a sample stage during an inspection process in the manufacture of an organic EL display device. FIG. 11 is a graph illustrating an image of the results of AES analysis in the inspection process in the manufacture of an organic EL display device. FIG. 12 is a schematic plan view of a TFT according to embodiment 2. FIG. 13 is a cross-sectional view of a TFT taken along line XIII-XIII in FIG. 12. FIG. 14 is a plan view illustrating an inspection pattern according to embodiment 2. FIG. 15 is a cross-sectional view of the inspection pattern taken along line XV-XV in FIG. 14. FIG. 16 is a cross-sectional view illustrating a state in which a test piece is set on a sample stage during an inspection process in the manufacture of an organic EL display device. FIG. 17 is a cross-sectional view of a portion of an inspection pattern according to a modified embodiment of embodiment 2, corresponding to FIG. 13. FIG. 18 is a plan view illustrating an inspection pattern according to embodiment 3. FIG. 19 is a cross-sectional view of the inspection pattern taken along line XIX-XIX in FIG. 18. FIG. 20 is a plan view illustrating an inspection pattern formation location according to another embodiment. Fig. 21 is a cross-sectional view of a portion of an inspection pattern of another embodiment, which corresponds to Fig. 7. Fig. 22 is a cross-sectional view of a portion of an inspection pattern of another embodiment, which corresponds to Fig. 15.

[0010] Exemplary embodiments will be described in detail below with reference to the drawings. In the following embodiments, an organic EL display device will be described as an example of a display device according to the present disclosure. Note that the drawings are intended to conceptually explain the technology of the present disclosure. Therefore, in the drawings, dimensions, ratios, or numbers may be exaggerated or simplified to facilitate understanding of the technology of the present disclosure.

[0011] In the following embodiments, when a component such as a film, layer, or element is provided or formed on another component such as another film, layer, or element, it does not only mean that the other component exists directly on top of the other component, but also includes cases where a component such as a film, layer, or element other than the one component is interposed between the two components.

[0012] In the following embodiments, a description that a certain component is connected to another component means that the components are electrically connected unless otherwise specified. This description not only means a direct connection, but also an indirect connection via other components, within the scope of the spirit of the technology of the present disclosure. This description also includes a case where another component is integrated with a certain component, that is, a part of a certain component constitutes the other component.

[0013] In the following embodiments, a description that a certain component is in the same layer as another component means that the certain component is formed in the same process as the other component. A description that a certain component is in an upper layer of the other component means that the certain component is deposited in a later process than the other component, or is formed from a film deposited in a later process.

[0014] In the following embodiments, a description that a certain component is identical to or equivalent to another component does not mean only a state in which the certain component and the other component are completely identical or completely equivalent, but also a state in which the certain component and the other component are substantially identical or substantially equivalent, such as fluctuating within the range of manufacturing variations or tolerances.

[0015] First Embodiment In this first embodiment, an organic EL display device 1 in which a bottom-gate TFT 10 is provided in a display area DA will be described.

[0016] The organic EL display device 1 is a display device that uses organic EL elements 52, also known as OLEDs (Organic Light Emitting Diodes). The organic EL display device 1 is used as a display for various devices, such as mobile devices such as multi-function mobile phones called smartphones and tablet terminals, personal computers (PCs), and television sets.

[0017] -Configuration of Organic EL Display Device- The organic EL display device 1 employs an active matrix driving system and is configured to provide a full-color display. As shown in Figure 1, the organic EL display device 1 has a display area DA and a frame area FA. The display area DA is an area where an image is displayed and constitutes a screen. The display area DA is provided in, for example, a rectangular shape.

[0018] As shown in Fig. 2, the display area DA is composed of a plurality of pixels PX. The plurality of pixels PX are arranged, for example, in a matrix. Each pixel PX is composed of three sub-pixels SP. The three sub-pixels SP are a sub-pixel SPr that emits red light, a sub-pixel SPg that emits green light, and a sub-pixel SPb that emits blue light. These three sub-pixels SP are arranged, for example, in a stripe pattern.

[0019] Each subpixel SP is composed of an organic EL element 52. Pixel circuits Pc are also provided in the display area DA to correspond to a plurality of subpixels SP. The pixel circuits Pc are circuits for each subpixel, and control the light emission of the organic EL elements 52 that constitute the corresponding subpixel SP. Although not shown, the display area DA is also provided with various wirings such as source lines, gate lines, and light emission control lines.

[0020] The frame area FA is a non-display area in which no image is displayed. The frame area FA is provided around the display area DA in the shape of, for example, a rectangular frame. A driving circuit (not shown) is provided in the frame area FA. The driving circuit is monolithically formed as part of the TFT layer 7 (described later). The driving circuit includes a gate driver and an emission driver.

[0021] Although not shown, a terminal portion is provided in the frame area FA. This terminal portion is for connecting to an external circuit such as a display control circuit (source driver), and is provided near the outer edge of one side of the frame area FA, extending along that side. A wiring board such as an FPC (Flexible Printed Circuit) is connected to the terminal portion.

[0022] Various wirings such as lead lines and power supply trunk lines are further provided in the frame area FA. The lead lines are wirings that are led out from the display area DA to terminal portions and are connected to wirings such as source lines that extend through the display area DA. The power supply trunk lines are wirings that pass drive current to the organic EL elements 52 and are connected to power supply branch lines that extend through the display area DA and electrodes (common electrodes 58) that constitute the organic EL elements 52.

[0023] 3, the organic EL display device 1 includes a circuit board 3, a light-emitting element layer 50, and a sealing film 70. The circuit board 3 includes a substrate layer 5 and a TFT layer 7. The circuit board 3 is an example of an element substrate.

[0024] The substrate layer 5 is a layer that forms the base of the organic EL display device 1. The substrate layer 5 is an example of a substrate. The substrate layer 5 is flexible. The substrate layer 5 is made of an organic resin material such as polyimide resin, polyamide resin, or epoxy resin. Although not shown, a protective film is attached to the back surface of the substrate layer 5.

[0025] The TFT layer 7 is provided on the substrate layer 5. The TFT layer 7 includes a drive circuit, various wirings, a pixel circuit Pc, and a planarization film 26. Various wirings such as gate lines, source lines, and light emission control lines are connected to the pixel circuit Pc. The pixel circuit Pc operates based on signals and voltages supplied by these various wirings, and supplies a drive current to the organic EL element 52.

[0026] The pixel circuit Pc includes a plurality of TFTs 10 and a capacitor 28. The TFTs 10 are an example of a semiconductor element. The TFTs 10 and the capacitors 28 are provided on a substrate layer 5. A base coat film may be provided between the TFTs 10 and the capacitors 28 and the substrate layer 5. The base coat film is made of an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0027] The planarization film 26 is provided so as to cover the drive circuit, various wirings, the plurality of TFTs 10, and the plurality of capacitors 28. The planarization film 26 is provided over the entire display area DA and extends into the frame area FA. The surface of the TFT layer 7 is planarized by the planarization film 26. The planarization film 26 may be formed of a single layer film or a laminated film.

[0028] A third contact hole Hc is formed for each sub-pixel SP in the planarization film 26. The third contact hole Hc penetrates to the terminal electrode 20 constituting the TFT 10 of the corresponding pixel circuit Pc or to the connection wiring 24 connected to the terminal electrode 20. The planarization film 26 is made of, for example, an organic insulating material such as polyimide resin or acrylic resin, or a polysiloxane-based SOG (Spin On Glass) material.

[0029] The light-emitting element layer 50 is provided on the TFT layer 7. The light-emitting element layer 50 includes a plurality of organic EL elements 52 and an edge cover 60. The organic EL elements 52 are an example of a light-emitting element. The organic EL elements 52 are provided to correspond to a plurality of sub-pixels SP. Each organic EL element 52 constitutes a sub-pixel SP.

[0030] Each organic EL element 52 is connected to a separate pixel circuit Pc. The light emission of each organic EL element 52 is controlled by the operation of the corresponding pixel circuit Pc. The organic EL elements 52 are configured as top-emission types. Light emitted by the organic EL elements 52 is extracted to the sealing film 70 side. Each organic EL element 52 has a pixel electrode 54, an organic EL layer 56, and a common electrode 58.

[0031] The pixel electrodes 54 are provided on the planarization film 26. The pixel electrodes 54 are provided in a predetermined arrangement so as to correspond to the plurality of sub-pixels SP. Each pixel electrode 54 is connected to the TFT 10 via a third contact hole Hc. The pixel electrodes 54 have the property of reflecting light and function as anodes. It is preferable that the pixel electrodes 54 be made of a conductive material with a large work function.

[0032] Examples of materials for the pixel electrodes 54 include metals such as silver (Ag), aluminum (Al), nickel (Ni), titanium (Ti), indium (In), and tin (Sn). The material for the pixel electrodes 54 may also be a metal compound or alloy. The material for the pixel electrodes 54 may also be a conductive oxide such as indium tin oxide (ITO) or indium tin zinc oxide. The pixel electrodes 54 may be formed of a single layer film or a laminated film.

[0033] The edge cover 60 is provided on the planarization film 26 so as to separate the plurality of pixel electrodes 54. The edge cover 60 is formed in a lattice shape overall, extends between adjacent pixel electrodes 54 and around the periphery of the display area DA, and covers the outer edges (peripheral end portions) of each pixel electrode 54. The edge cover 60 is made of, for example, an organic resin material such as polyimide resin or acrylic resin, or a polysiloxane-based SOG material.

[0034] The organic EL layer 56 is provided on each pixel electrode 54 within the opening 62 in the edge cover 60. The organic EL layer 56 has a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer, which are provided in this order on the pixel electrode 54. These functional layers are made of well-known compounds suitable for their respective functions. Some of the multiple functional layers may be provided in common as a continuous layer for multiple subpixels SP.

[0035] The common electrode 58 is provided as a continuous electrode commonly to the plurality of sub-pixels SP. The common electrode 58 is disposed on each organic EL layer 56, covering the edge cover 60, and overlaps each pixel electrode 54 via the organic EL layer 56. The common electrode 58 is made of a material that transmits light and functions as a cathode. It is preferable to use a conductive material with a small work function for the common electrode 58.

[0036] Examples of materials for the common electrode 58 include conductive oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO). The material for the common electrode 58 may be a metal such as silver (Ag), aluminum (Al), lithium (Li), magnesium (Mg), calcium (Ca), or ytterbium (Yb). The material for the common electrode 58 may be a metal compound or an alloy. The common electrode 58 may be formed of a single layer film or a laminated film.

[0037] The sealing film 70 is provided on the light-emitting element layer 50. The sealing film 70 covers and seals the plurality of organic EL elements 52, protecting each organic EL element 52 (particularly the organic EL layer 56) from moisture, oxygen, and the like. The sealing film 70 is provided over the entire display area DA and extends to the frame area FA. The sealing film 70 has a first inorganic sealing layer 72, an organic sealing layer 74, and a second inorganic sealing layer 76.

[0038] The first inorganic sealing layer 72 is provided to cover the common electrode 58. The organic sealing layer 74 is provided on the first inorganic sealing layer 72. The second inorganic sealing layer 76 is provided to cover the organic sealing layer 74. The first inorganic sealing layer 72 and the second inorganic sealing layer 76 overlap each other on the outer periphery of the frame area FA. The organic sealing layer 74 is enclosed by the first inorganic sealing layer 72 and the second inorganic sealing layer 76.

[0039] The first inorganic sealing layer 72 and the second inorganic sealing layer 76 are each made of an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc. The organic sealing layer 74 is made of an organic resin material such as acrylic resin, epoxy resin, silicone resin, polyurea resin, parylene resin, polyimide resin, polyamide resin, etc.

[0040] 4 and 5, the TFT 10 of this example is configured as a bottom-gate type having a top-contact structure. The TFT 10 includes a gate electrode 12, a gate insulating film 14, a semiconductor layer 18, and a pair of terminal electrodes 20.

[0041] The gate electrode 12 is provided on the substrate layer 5. The gate insulating film 14 is provided on the substrate layer 5 so as to cover the gate electrode 12. The semiconductor layer 18 is provided in an island shape on the surface of the gate insulating film 14 at a position overlapping the gate electrode 12 with the gate insulating film 14 interposed therebetween. The semiconductor layer 18 may be provided in a continuous manner for the plurality of TFTs 10, or may be separated for each TFT 10.

[0042] The pair of terminal electrodes 20 are provided so as to overlap with each other in mutually separated portions of the semiconductor layer 18. The portion of the semiconductor layer 18 between the pair of terminal electrodes 20 constitutes a first channel region 18a. The first channel region 18a is a region of the semiconductor layer 18 that does not overlap with the terminal electrodes 20 in a plan view. The area of ​​the first channel region 18a is, for example, 4 μm ２ More than 30 μm ２ The following is the result.

[0043] The pair of terminal electrodes 20 are covered with a passivation film 22. A pair of first contact holes Ha are formed in the passivation film 22. The pair of first contact holes Ha penetrate to different terminal electrodes 20. Although an example in which a pair of first contact holes Ha are formed for the TFT 10 is shown in FIGS. 4 and 5 , only one first contact hole Ha may be formed for the TFT 10.

[0044] Connection wiring 24 is provided on the passivation film 22. The connection wiring 24 is wiring for connecting the TFTs 10 to each other. The connection wiring 24 may also be wiring for connecting the TFTs 10 to the pixel electrodes 54. The connection wiring 24 is connected to the terminal electrodes 20 via first contact holes Ha. The passivation film 22 and the connection wiring 24, together with the TFTs 10, are covered by a planarization film 26.

[0045] The gate insulating film 14 and the passivation film 22 are each made of an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc. The gate insulating film 14 and the passivation film 22 may each be made of a single layer film or a multilayer film.

[0046] The gate electrode 12, each terminal electrode 20, connection wiring 24, and various other wirings are each made of a metal material such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), copper (Cu), etc. These electrodes and wirings may be made of a single layer film or a laminated film.

[0047] The semiconductor layer 18 is made of an oxide semiconductor. The oxide semiconductor that constitutes the semiconductor layer 18 in this example is an In—Ga—Zn—O-based semiconductor. The In—Ga—Zn—O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the proportions (composition ratios) of In, Ga, and Zn are not limited. The In—Ga—Zn—O-based semiconductor may be amorphous or crystalline.

[0048] 1, the organic EL display device 1 further includes a test pattern 30. The test pattern 30 is used to analyze the composition ratio and redox state of the semiconductor layer 18 of the TFT 10. The test pattern 30 is provided in the frame area FA as a pattern larger than the TFT 10. The test pattern 30 is formed on the substrate layer 5 together with the TFT 10. The test pattern 30 has a structure similar to that of the bottom-gate TFT 10 described above.

[0049] 6 and 7 , the test pattern 30 includes a dummy electrode 32, a gate insulating film 14, a test target layer 38, a pair of conductive electrodes 40, and a passivation film 22. The gate insulating film 14 is an example of a first insulating film. The passivation film 22 is an example of a second insulating film and a third insulating film. That is, in this example, the second insulating film and the third insulating film are the same insulating film.

[0050] The dummy electrode 32 is provided on the substrate layer 5 and is covered with the gate insulating film 14. The dummy electrode 32 is a component corresponding to the gate electrode 12. The dummy electrode 32 is formed in the same layer as the gate electrode 12 and from the same material. The dummy electrode 32 is provided in an island shape and is not connected to other electrodes, wiring, etc.

[0051] The inspection target layer 38 is provided on the gate insulating film 14. The inspection target layer 38 overlaps the dummy electrode 32 with the gate insulating film 14 interposed therebetween. The inspection target layer 38 is a component corresponding to the semiconductor layer 18, and is formed in the same layer and from the same material as the semiconductor layer 18. In other words, the inspection target layer 38 is made of an oxide semiconductor. The oxide semiconductor in this example is an In—Ga—Zn—O-based semiconductor.

[0052] The pair of conductive electrodes 40 are each provided in a layer above the inspection target layer 38 and connected to the inspection target layer 38. The pair of conductive electrodes 40 are connected with one end thereof overlapping with a portion of the inspection target layer 38 that is spaced apart from each other. The conductive electrode 40 is a component corresponding to the terminal electrode 20, and is formed in the same layer and from the same material as the terminal electrode 20. The portion of the inspection target layer 38 between the pair of conductive electrodes 40 constitutes an inspection region 38i in which analysis by Auger electron spectroscopy can be performed.

[0053] The inspection region 38i is a region that does not overlap with the conductive electrode 40 of the inspection target layer 38 in a plan view. The area of ​​the inspection region 38i in a plan view is larger than the area of ​​the first channel region 18a of the semiconductor layer 18 in a plan view, and is, for example, 100 μm ２ More than 10,000 μm ２ For example, the inspection region 38i is provided in a rectangular shape with one side of 10 μm to 100 μm.

[0054] If the area of ​​the inspection region 38i is small, corresponding to the first channel region 18a of the semiconductor layer 18, the surface of the inspection target layer 38 will be damaged by heat due to the concentrated electron beam irradiation during analysis by Auger electron spectroscopy, which will impair the analytical accuracy of the elemental composition and element distribution of the inspection target layer 38.

[0055] In contrast, the area of ​​the inspection region 38i is 100 μm２ In this way, analysis by Auger electron spectroscopy can be performed while suppressing damage to the surface of the inspection target layer 38 caused by heat due to electron beam irradiation, thereby improving the analytical accuracy of the elemental composition and element distribution of the inspection target layer 38.

[0056] On the other hand, if the area of ​​the inspection region 38i is too large, the size of the inspection target layer 38 will also be excessively large. As a result, the composition ratio and redox state of the inspection target layer 38 may differ relatively significantly from the composition ratio and redox state of the semiconductor layer 18. ２ If it is equal to or less than this, even if the composition ratio and redox state of the inspection target layer 38 differ from the composition ratio and redox state of the semiconductor layer 18 of the TFT 10, the degree of difference can be suppressed.

[0057] The passivation film 22 is provided to cover the pair of conductive electrodes 40 and the inspection target layer 38. The composition of the semiconductor layer 18 of the TFT 10 may change due to the influence of the film quality of the passivation film 22. For example, if the passivation film 22 contains hydrogen, the oxide semiconductor constituting the semiconductor layer 18 is reduced and altered. Such a change in the composition of the semiconductor layer 18 occurs particularly at the interface between the semiconductor layer 18 and the passivation film 22.

[0058] For this reason, the test pattern 30 is configured to include a passivation film 22. A pair of first contact holes Ha are formed in the passivation film 22. The pair of first contact holes Ha penetrate to different conductive electrodes 40. Each first contact hole Ha is formed at a position corresponding to the other end of the corresponding conductive electrode 40, which is located on the opposite side from the connection portion with the test target layer 38. The first contact holes Ha in this example are open to the outside.

[0059] -Method for Manufacturing Organic EL Display Device- To manufacture the organic EL display device 1, first, an organic resin material is applied to the surface of a glass substrate and baked, thereby forming a substrate layer 5 on the glass substrate.

[0060] Next, the TFT layer 7, the light-emitting element layer 50, and the sealing film 70 are formed in this order on the substrate layer 5 using a known film formation method such as plasma CVD (Chemical Vapor Deposition), sputtering, or vacuum deposition, a known coating method such as spin coating or slit coating, or a known patterning technique such as photolithography.

[0061] Thereafter, the glass substrate is peeled off from the substrate layer 5 by, for example, irradiating the rear surface of the substrate layer 5 with laser light from the glass substrate side. Next, a protective film is attached to the rear surface of the substrate layer 5. In addition, a polarizing plate and a cover panel are attached to the surface of the sealing film 70. Furthermore, a wiring board is connected to the terminal portion provided in the frame area FA, and a display control circuit (source driver) is mounted.

[0062] In this manner, the organic EL display device 1 can be manufactured.

[0063] <Inspection Process> In the manufacture of the organic EL display device 1, an inspection process is performed to check the quality of the TFT 10. The inspection process is performed by random inspection. In the inspection process, Auger electron spectroscopy, also known as AES, is used to check whether the composition ratio and redox state of the semiconductor layer 18 are sufficient to ensure the desired performance of the TFT 10.

[0064] 8, when manufacturing multiple organic EL display devices 1, a single large mother panel 80 including a plurality of individual panel regions 1A constituting the organic EL display device 1 is fabricated, and the mother panel 80 is then divided into individual panel regions 1A to manufacture a plurality of organic EL display devices 1. In this case, each individual panel region 1A has a display area DA and a frame area FA. The test pattern 30 is provided in the frame area FA of each individual panel region 1A.

[0065] The inspection process uses an Auger electron spectrometer 100 shown in Fig. 9A. The Auger electron spectrometer 100 is an apparatus that measures Auger electrons emitted from a sample by irradiating the sample with an electron beam, and analyzes the elemental composition and element distribution on the sample surface. The Auger electron spectrometer 100 includes a pre-evacuation chamber 101, a gate valve 102, an analysis chamber 103, a stage 104, a position adjustment mechanism 105, an electron gun 106, an ion gun 107, a secondary electron detector 108, and an Auger electron detector 109.

[0066] The pre-evacuation chamber 101 is provided as a front chamber for introducing a sample into the analysis chamber 103. A vacuum pump (not shown) is connected to the pre-evacuation chamber 101. The pre-evacuation chamber 101 is configured to be sealable so that it can be depressurized by operation of the vacuum pump to create a so-called vacuum state. A gate valve 102 is provided between the pre-evacuation chamber 101 and the analysis chamber 103. The sample stage 110 with the test piece 90 placed on it is transported from the pre-evacuation chamber 101 to the analysis chamber 103 by a transfer mechanism (not shown) and transferred to the stage 104.

[0067] A vacuum pump (not shown) is also connected to the analysis chamber 103. The analysis chamber 103 is configured to be sealable so that it can be depressurized to a vacuum state by operating the vacuum pump. The stage 104 is disposed inside the analysis chamber 103. The position adjustment mechanism 105 is configured to be able to adjust the position of the stage 104 by sliding it in three axial directions. The position adjustment mechanism 104 may also have the function of rotating or tilting the stage 104.

[0068] The electron gun 106 and the ion gun 107 are each provided with their gun tips facing into the analysis chamber 103. The electron gun 106 is a device that generates an electron beam. The electron gun 106 is, for example, a field emission electron gun, and is configured to be able to scan the electron beam within a predetermined range. The ion gun 107 is a device that generates an ion beam. The ion gun 107 has the function of etching the surface of the sample, and uses a rare gas element such as argon gas.

[0069] The secondary electron detector 108 and the Auger electron detector 109 are each provided with their detection surfaces facing into the analysis chamber 103. The secondary electron detector 108 is configured to detect secondary electrons emitted from the surface of the sample. The Auger electron detector 108 is configured to detect Auger electrons emitted from the surface of the sample and analyze the energy of the detected Auger electrons.

[0070] The inspection process is performed on the organic EL display device 1 or its in-process product picked up in the sampling inspection. In the inspection process, first, an area including an inspection pattern of the picked up organic EL display device 1 or its in-process product is cut out using a cutting tool or the like. In this way, an inspection piece 90 consisting of the cut-out area is obtained as a sample.

[0071] Next, the test piece 90 is placed on the sample stage 110 of the Auger electron spectrometer 100. The conductive electrode 40 of the test pattern 30 is then electrically connected to the sample stage 110. Specifically, as shown in FIG. 10 , a conductive paste 200 such as carbon paste or silver paste is applied continuously from the surface of the test piece 90 through the side surface to the sample stage 110, filling the first contact hole Ha and covering the opening, thereby establishing electrical continuity between the conductive electrode 40 and the sample stage 110. At this time, the conductive paste 200 is prevented from reaching the surface of the test piece 90 corresponding to the test region 38i of the test target layer 38.

[0072] Next, as shown in Fig. 9A, with the gate valve 102 closed, the sample stage 110 on which the test piece 90 is set is carried into the preliminary exhaust chamber 101, and the preliminary exhaust chamber 101 is sealed. Furthermore, the vacuum pump is operated to evacuate the preliminary exhaust chamber 101. At this time, the analysis chamber 103 is also evacuated by operating the vacuum pump. Thereafter, as shown in Fig. 9B, the gate valve 102 is opened, and the transfer mechanism transports the sample stage 110 into the analysis chamber 103 and transfers it onto the stage 104.

[0073] In this way, by introducing the test piece 90 into the analysis chamber 103 via the preliminary evacuation chamber 101 rather than directly into the analysis chamber 103, the analysis chamber 103 can be maintained in a high vacuum state. A high degree of vacuum in the analysis chamber 103 is preferable from the viewpoint of improving the accuracy of Auger electron energy analysis. Next, as shown in FIG. 9C , the sample stage 110 on which the test piece 90 is set is moved by operating the position adjustment mechanism 105 to a predetermined position within the analysis chamber 103, that is, a position where the test piece 90 is aligned with the irradiation position of the electron gun 106 and the irradiation position of the ion gun 107.

[0074] Next, as shown in FIG. 9D , an electron beam is irradiated onto the test piece 90 from the electron gun 106. When the electron beam is irradiated onto the test piece 90, secondary electrons and Auger electrons are emitted from the surface of the test piece 90 irradiated with the electron beam. The secondary electrons emitted from the surface of the test piece 90 are detected by the secondary electron detector 108. Then, a secondary electron image (SEM image) is obtained by synchronizing information on the secondary electrons detected by the secondary electron detector 108 with information on the scanning position of the electron beam. Furthermore, based on the obtained secondary electron image, a surface portion of the test piece 90 corresponding to the inspection region 38i of the inspection target layer 38 is determined as the measurement region. At this time, the position of the measurement region of the test piece 90 may be adjusted by adjusting the position of the stage 104 using the position adjustment mechanism 105.

[0075] Next, as shown in FIG. 9E , an electron beam is irradiated onto the measurement region of the test piece 90 from the electron gun 106. Auger electrons emitted from the surface of the test piece 90 are detected by the Auger electron detector 109. The Auger electron detector 109 then measures the energy spectrum of the Auger electrons by dispersing the detected Auger electrons by energy. Because the energy of Auger electrons is element-specific, it is possible to identify the elements that make up the measurement region of the test piece 90. Using this fact, the Auger electron spectrometer 100 analyzes the types and amounts of elements that make up the measurement region of the test piece 90.

[0076] 9F , an ion beam is irradiated onto the measurement region of the test piece 90 from the ion gun 107, thereby slightly etching the surface of the test piece 90 that forms the measurement region. Thereafter, the steps of determining the measurement region of the test piece 90, measuring the Auger electron energy spectrum on the surface of the test piece 90, and etching the surface of the test piece 90 are repeated. In this way, the measurement region of the test piece 90, including the test region 38i of the test target layer 38, is analyzed in the depth direction.

[0077] FIG. 11 shows an example of a graph of an Auger spectrum resulting from analysis of the inspection region 38i of the inspection target layer 38 using the Auger electron spectrometer 100. FIG. 11 shows only the analysis results for the inspection target layer 38, omitting the analysis results for portions other than the inspection target layer 38, such as the passivation film 22 of the inspection piece 90. In FIG. 11, the vertical axis represents the abundance of each atom, and the horizontal axis represents the etching time. The etching time corresponds to the depth from the surface of the inspection target layer 38. In FIG. 11, In having an In—Ga—Zn—O bonding state is represented as "In(IGZO)," In having a metallic bonding state is represented as "In(pure)," and In including all bonding states is represented as "In(Total)."

[0078] During the inspection process, if the conductive electrodes 40 of the inspection pattern 30 are not electrically connected to the sample stage 110, electron beam irradiation causes a charging phenomenon (charge-up) in which negative charges accumulate on the surface of the inspection target layer 38. The energy of Auger electrons emitted from the surface of the inspection target layer 38 by electron beam irradiation changes depending on the charging phenomenon on the surface of the inspection target layer 38. This significantly reduces the accuracy of state analysis of the elemental composition, etc. of the inspection target layer 38 using Auger electron spectroscopy. In contrast, in this embodiment, electrical continuity is established between the conductive electrodes 40 of the inspection pattern 30 and the sample stage 110, so that negative charges that accumulate on the surface of the inspection target layer 38 can escape to the sample stage 110, thereby suppressing the charging phenomenon on the surface of the inspection target layer 38. As a result, highly accurate analysis results can be obtained for the elemental composition and element distribution of the inspection target layer 38, as shown in FIG. 11 .

[0079] - Features of First Embodiment - In the test pattern 30 of this first embodiment, a test target layer 38 made of an oxide semiconductor is provided on the gate insulating film 14. A conductive electrode 40 is connected to the test target layer 38. The test target layer 38 and the conductive electrode 40 are both covered with a passivation film 22. Such a test pattern 30 can have a structure similar to that of a bottom-gate TFT 10 that uses an oxide semiconductor.

[0080] Furthermore, in the test pattern 30 of this embodiment 1, a first contact hole Ha is formed in the passivation film 22, penetrating to the conductive electrode 40. This allows electrical continuity between the conductive electrode 40 and the sample stage 110 via the first contact hole Ha. This makes it possible to prevent the test target layer 38 from being charged by irradiation with an electron beam. Therefore, the composition and redox state of the oxide semiconductor constituting the test target layer 38 can be accurately analyzed by analysis using Auger electron spectroscopy.

[0081] Furthermore, the inspection pattern 30 of this embodiment 1 can also analyze the composition and oxidation-reduction state at the interface between the gate insulating film 14 and the inspection target layer 38, and at the interface between the inspection target layer 38 and the passivation film 22. As a result, if a defect is found in the inspection process, feedback can be applied to an appropriate process depending on the defect.

[0082] For example, if the composition or redox state at the interface between the gate insulating film 14 and the inspection target layer 38 is not good, there may be a problem in the film formation process of the gate insulating film 14, and feedback may be provided to request that the film formation conditions, etc. be revised. Also, if the composition or redox state inside the oxide semiconductor layer 18 is not good, there may be a problem in the film formation process of the oxide semiconductor layer 18, and feedback may be provided to request that the film formation conditions, etc. be revised. Also, if the composition or redox state at the interface between the inspection target layer 38 and the passivation film 22 is not good, there may be a problem in the film formation process of the passivation film 22, and feedback may be provided to request that the film formation conditions, etc. be revised.

[0083] Second Embodiment In the second embodiment, an organic EL display device 1 in which a top-gate TFT 10 is provided in a display area DA will be described.

[0084] In the organic EL display device 1 of this embodiment 2, the configurations of the TFTs 10 and the check patterns 30 that constitute the pixel circuits Pc are different from those of the embodiment 1, and the organic EL display device 1 is otherwise configured in the same manner as in the embodiment 1. Therefore, only the TFTs 10 and the check patterns 30 that have different configurations will be described, and detailed descriptions of matters relating to the same components will be omitted.

[0085] 13, a base coat film 11 is provided on a substrate layer 5. A TFT 10 is provided on the base coat film 11. The TFT 10 in this example is configured as a top-gate type. As also shown in FIG. 12, the TFT 10 includes a semiconductor layer 18, a gate insulating film 14, a gate electrode 12, an interlayer insulating film 15, and a pair of terminal electrodes 20.

[0086] The semiconductor layer 18 is provided on the base coat film 11. The semiconductor layer 18 is formed in an island shape on the surface of the substrate layer 5. The semiconductor layer 18 may be provided continuously for the plurality of TFTs 10, or may be separated for each TFT 10. The semiconductor layer 18 includes a first channel region 18a and a pair of first conductor regions 18b. The first channel region 18a is provided between the pair of first conductor regions 18b.

[0087] The gate insulating film 14 is provided so as to cover the semiconductor layer 18. The gate electrode 12 is provided on the surface of the gate insulating film 14 at a position overlapping with a first channel region 18a of the semiconductor layer 18 with the gate insulating film 14 interposed therebetween. The interlayer insulating film 15 is provided so as to cover the gate electrode 12. A pair of second contact holes Hb are formed in a stacked insulating film 16 made of the gate insulating film 14 and the interlayer insulating film 15.

[0088] The pair of second contact holes Hb penetrate to different first conductor regions 18b of the semiconductor layer 18. The pair of terminal electrodes 20 are provided on the interlayer insulating film 15. Each terminal electrode 20 is connected to the first conductor region 18b of the semiconductor layer 18 via a separate second contact hole Hb. Although an example in which a pair of second contact holes Hb are formed for the TFT 10 is shown in FIGS. 12 and 13 , only one second contact hole Hb may be formed for the TFT 10.

[0089] The pair of terminal electrodes 20 are covered with a passivation film 22. A pair of first contact holes Ha are formed in the passivation film 22. The pair of first contact holes Ha penetrate to different terminal electrodes 20. Although an example in which a pair of first contact holes Ha are formed for the TFT 10 is shown in Figures 12 and 13, only one first contact hole Ha may be formed for the TFT 10.

[0090] The gate insulating film 14, the interlayer insulating film 15, and the passivation film 22 are each made of an inorganic insulating material such as silicon oxide, silicon nitride, silicon oxynitride, etc. The gate insulating film 14, the interlayer insulating film 15, and the passivation film 22 may each be made of a single layer film or a multilayer film.

[0091] The gate electrode 12 and each terminal electrode 20 are each made of a metal material such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), copper (Cu), etc. The gate electrode and each terminal electrode may be made of a single layer film or a laminated film.

[0092] The semiconductor layer 18 is made of an oxide semiconductor. The oxide semiconductor that constitutes the semiconductor layer 18 in this example is an In—Ga—Zn—O-based semiconductor. The In—Ga—Zn—O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the proportions (composition ratios) of In, Ga, and Zn are not limited. The In—Ga—Zn—O-based semiconductor may be amorphous or crystalline.

[0093] <Test Pattern> The test pattern 30 has a structure similar to that of the top-gate TFT 10 described above. As shown in Figures 14 and 15, the test pattern 30 includes a base coat film 11, a test target layer 38, a gate insulating film 14, a dummy electrode 32, an interlayer insulating film 15, a pair of conductive electrodes 40, and a passivation film 22. The base coat film 11 is an example of a first insulating film. The stacked insulating film 16 consisting of the gate insulating film 14 and the interlayer insulating film 15 is an example of a second insulating film. The passivation film 22 is an example of a third insulating film.

[0094] The base coat film 11 is provided on the substrate layer 5. The inspection target layer 38 is provided on the base coat film 11. The inspection target layer 38 is formed in an island shape on the surface of the base coat film 11. The inspection target layer 38 is a component corresponding to the semiconductor layer 18, and is formed in the same layer and from the same material as the semiconductor layer 18. In other words, the inspection target layer 38 is made of an oxide semiconductor. The oxide semiconductor in this example is an In—Ga—Zn—O based semiconductor.

[0095] The inspection target layer 38 includes a second channel region 38a and a pair of second conductor regions 38b. The second channel region 38a is provided between the pair of second conductor regions 38b. The gate insulating film 14 is provided to cover the inspection target layer 38. The dummy electrode 32 is provided at a position overlapping the second channel region 38a of the semiconductor layer 18 with the gate insulating film 14 interposed therebetween.

[0096] The gate insulating film 14 is provided so as to cover the inspection target layer 38. The dummy electrode 32 is provided on the gate insulating film 14. It is a component corresponding to the gate electrode 12, and is formed in the same layer and from the same material as the gate electrode 12. The dummy electrode 32 is provided in an island shape, and is not connected to other electrodes or wiring.

[0097] The interlayer insulating film 15 is provided so as to cover the dummy electrode 32. A pair of second contact holes Hb are formed in the stacked insulating film 16 made up of the gate insulating film 14 and the interlayer insulating film 15. The pair of second contact holes Hb penetrate to different second conductor regions 38b of the inspection target layer 38. The pair of conductive electrodes 40 are each connected to the inspection target layer 38, which is provided in a layer above the inspection target layer 38.

[0098] Each of the conductive electrodes 40 is provided on the stacked insulating film 16 (interlayer insulating film 15). One end of each of the conductive electrodes 40 is connected to the inspection target layer 38. Each of the conductive electrodes 40 is connected to the second conductor region 38b of the inspection target layer 38 via a separate second contact hole Hb. The conductive electrodes 40 are components corresponding to the terminal electrodes 20, and are formed in the same layer and from the same material as the terminal electrodes 20.

[0099] The region of the inspection target layer 38 that does not overlap with the conductive electrode 40 in plan view is an inspection region 38i where analysis by Auger electron spectroscopy is possible. The inspection region 38i includes the second channel region 38a. The area of ​​the inspection region 38i in plan view is larger than the area of ​​the region of the semiconductor layer 18 that does not overlap with the terminal electrode 20 in plan view, and is, for example, 100 μm ２ More than 10,000 μm ２ For example, the inspection region 38i is provided in a rectangular shape with one side of 10 μm to 100 μm.

[0100] The passivation film 22 is provided so as to cover the pair of conductive electrodes 40. A pair of first contact holes Ha are formed in the passivation film 22. The pair of first contact holes Ha penetrate to different conductive electrodes 40. Each first contact hole Ha is formed at a position corresponding to the other end of the corresponding conductive electrode 40, which is located on the opposite side from the connection portion with the inspection target layer 38. The first contact holes Ha in this example are open to the outside.

[0101] In manufacturing the organic EL display device 1 having such a test pattern 30, the test process is carried out in the same manner as in the first embodiment.

[0102] In the inspection process of this example, a region including the inspection pattern 30 of the organic EL display device 1 or a product in the manufacturing process picked up in the sampling inspection is cut out to obtain a test piece 90, and the test piece 90 is placed on the sample stage 110 of the Auger electron spectrometer 100. Then, the conductive electrode 40 of the inspection pattern 30 and the sample stage 110 are electrically connected.

[0103] 16, a conductive paste 200 such as carbon paste or silver paste is applied continuously from the surface of the test piece 90 over the side surface to the sample stage 110 so as to fill the first contact hole Ha and cover the opening, thereby establishing electrical continuity between the conductive electrode 40 and the sample stage 110. At this time, care is taken to ensure that the conductive paste 200 does not come into contact with the surface of the test piece 90 corresponding to the test region 38i of the test target layer 38.

[0104] In this way, also in the inspection process of this example, the elemental composition and element distribution of the test piece 90 are analyzed by the Auger electron spectrometer 100 with electrical continuity between the conductive electrode 40 and the sample stage 110. By doing so, negative charges that accumulate on the surface of the inspection target layer 38 due to irradiation with the electron beam can be released toward the sample stage 110, thereby suppressing charging of the surface of the inspection target layer 38. As a result, highly accurate analysis results of the elemental composition and element distribution of the inspection target layer 38 can be obtained, as shown in FIG.

[0105] Features of the Second Embodiment In the test pattern 30 of the second embodiment, a test target layer 38 made of an oxide semiconductor is provided on a base coat film 11, and the test target layer 38 is covered with an interlayer insulating film 15. A conductive electrode 40 is connected to the test target layer 38. The conductive electrode 40 is covered with a passivation film 22. Such a test pattern 30 can have a structure similar to that of a top-gate TFT 10 that uses an oxide semiconductor.

[0106] Furthermore, in the test pattern 30 of this second embodiment, a first contact hole Ha is formed in the passivation film 22, penetrating to the conductive electrode 40. This allows electrical continuity between the conductive electrode 40 and the sample stage 110 via the first contact hole Ha when analyzing the test target layer 38 by Auger electron spectroscopy. This makes it possible to prevent the test target layer 38 from becoming charged up due to irradiation with an electron beam. Therefore, analysis using Auger electron spectroscopy allows accurate analysis of the composition and redox state of the oxide semiconductor that constitutes the test target layer 38.

[0107] Furthermore, the inspection pattern 30 of this second embodiment can also analyze the composition and oxidation-reduction state at the interface between the base coat film 11 and the inspection target layer 38, and at the interface between the inspection target layer 38 and the gate insulating film 14. This allows for feedback to be applied to an appropriate process depending on the defect, if any.

[0108] For example, if the composition or redox state at the interface between the base coat film 11 and the inspection target layer 38 is not good, there may be a problem in the film formation process of the base coat film 11, and feedback may be provided to request that the film formation conditions, etc. be revised. Also, if the composition or redox state inside the oxide semiconductor layer 18 is not good, there may be a problem in the film formation process of the oxide semiconductor layer 18, and feedback may be provided to request that the film formation conditions, etc. be revised. Also, if the composition or redox state at the interface between the inspection target layer 38 and the gate insulating film 14 is not good, there may be a problem in the film formation process of the lower gate insulating film 14, and feedback may be provided to request that the film formation conditions, etc. be revised.

[0109] Modification of Embodiment 2 In the organic EL display device 1 of this modification, the configuration of the test pattern 30 is different from that of the above-described embodiment 2. As shown in Fig. 17 , in the test pattern 30 of this example, a portion of the interlayer insulating film 15 and the passivation film 22 corresponding to the test region 38i, for example, a portion corresponding to the second channel region 38a, is removed, and a recess 23 is formed in that portion.

[0110] The test pattern 30 of this example does not include a dummy electrode 32. The gate insulating film 14 is exposed at the bottom of the recess 23. The gate insulating film 14 may have the same thickness in the portion corresponding to the recess 23 as the other portions, or may be thinner than the other portions. In this way, no metal layer is provided above the portion of the test target layer 38 corresponding to the test region 38i of the test target layer 38.

[0111] With this configuration, in the inspection process, it is possible to reduce the number of times that the surface of the test piece 90 is etched before the electron beam is irradiated onto the inspection region 38i of the inspection target layer 38 and the energy spectrum of the Auger electrons is measured. This reduces the time from the start to the completion of inspection of the test piece 90 using the Auger electron spectrometer 100, thereby making the inspection process more efficient.

[0112] Third Embodiment In this third embodiment, an organic EL display device 1 will be described in which the inspection pattern 30 functions as an alignment mark. The alignment mark is used to align a substrate on which a film to be patterned is formed with a photomask when performing patterning by photolithography.

[0113] In the organic EL display device 1 of this embodiment 3, the configuration of the test pattern 30 is different from that of the embodiment 1, but the organic EL display device 1 is configured in the same manner as the embodiment 1. Therefore, only the test pattern 30 having a different configuration will be described, and detailed descriptions of matters relating to the same configuration parts will be omitted.

[0114] As shown in Fig. 18, the test pattern 30 of this example is provided in a cross shape in a plan view. As shown in Fig. 19, the test pattern 30 has a structure similar to that of a bottom-gate TFT 10, and includes a dummy electrode 32, a gate insulating film 14, a test target layer 38, a pair of conduction electrodes 40, and a passivation film 22. The layers and materials forming these components are the same as those in the first embodiment.

[0115] The dummy electrode 32 is formed in a rectangular shape with its long sides extending in a predetermined first direction Dx (the up-and-down direction in FIG. 18 ). The inspection target layer 38 is also formed in a rectangular shape with its long sides extending in the first direction Dx. The dummy electrode 32 overlaps the inspection target layer 38 via the gate insulating film 14. The pair of conduction electrodes 40 are provided with one end overlapping with a portion of the inspection target layer 38 that is spaced apart from each other.

[0116] The conductive electrode 40 has a connection portion 40a connected to the conductive electrode 40, and an alignment mark portion 40b. The connection portion 40a extends in the first direction Dx along substantially the entire length of the end of the inspection target layer 38. The alignment mark portion 40b is a portion that protrudes in a rectangular shape or the like from a central portion of the connection portion 40a in the first direction Dx in a second direction Dy that is perpendicular to the first direction Dx, and constitutes part of the outline of the alignment mark.

[0117] Both the pair of conductive electrodes 40 and the dummy electrode 32 have light-blocking properties. Therefore, the pair of conductive electrodes 40 and the dummy electrode 32 form a cross shape similar to the shape generally used as an alignment mark, and function as an alignment mark. The pair of conductive electrodes 40 and the inspection target layer 38 are covered with a passivation film 22.

[0118] A pair of first contact holes Ha are formed in the passivation film 22. The pair of first contact holes Ha penetrate to different conductive electrodes 40. Each first contact hole Ha is formed at an end of the corresponding conductive electrode 40 opposite to the connection portion with the inspection target layer 38, that is, at a position corresponding to the tip portion of the alignment mark portion 40b. The first contact holes Ha in this example are open to the outside.

[0119] - Features of Embodiment 3 - In the test pattern 30 of this embodiment 3, the test pattern 30 functions as an alignment mark, so there is no need to provide an alignment mark separate from the test pattern 30. This is advantageous for the organic EL display device 1, which requires a narrow frame. Furthermore, with the test pattern 30 of this embodiment 3, as in the above-described embodiment 1, the composition and redox state of the oxide semiconductor constituting the test target layer 38 can be accurately analyzed by analysis using Auger electron spectroscopy.

[0120] Other Embodiments In the above-described first to third embodiments, when the organic EL display device 1 is manufactured using multiple panels, the test pattern 30 is provided in the frame area FA of each individual panel area 1A on the mother panel 80. However, this is not limiting. In this case, as shown in Fig. 20 , for example, the test pattern 30 may be provided in an area OA that becomes waste material when each individual panel area 1A is cut on the mother panel 80.

[0121] In the above-described first to third embodiments, the first contact hole Ha formed in the passivation film 22 is open to the outside, but this is not limiting. For example, in the organic EL display device 1 of the first embodiment, the planarization film 26 may be provided in the frame area FA so as to cover the test pattern 30, as shown in FIG. 21 . This also applies to the organic EL display device 1 of the third embodiment. In the above-described case, a sampling inspection step may be performed before the step of forming the planarization film 26.

[0122] 22 , the configuration in which the planarization film 26 is provided so as to cover the check pattern 30 can also be employed in the organic EL display device 1 of the above-described embodiment 2. Furthermore, in the frame area FA, the component provided on the passivation film 22 so as to cover the check pattern 30 is not limited to the planarization film 26, but may be any other organic insulating film such as a transparent conductive film, a metal film, or a polyimide film, or an inorganic insulating film such as an inorganic sealing layer, and various other films or layers are possible.

[0123] In the above-described first to third embodiments, the test pattern 30 includes a pair of conductive electrodes 40, and a pair of first contact holes Ha are formed in the passivation film 22, but this is not limiting. The test pattern 30 may include only one conductive electrode 40. Furthermore, even when a pair of conductive electrodes 40 is included, there may be only one first contact hole Ha.

[0124] In the above-described first to third embodiments, in the inspection step, a region including the inspection pattern 30 of the organic EL display device 1 or a product in the manufacturing process is cut out to obtain the test piece 90, and the test piece 90 is placed on the sample stage 110 of the Auger electron spectrometer 100. However, this is not limitative. In the inspection step, the organic EL display device 1 or a product in the manufacturing process may be placed directly on the sample stage 110, electrical continuity may be established between the conductive electrodes 40 of the inspection pattern 30 and the sample stage 110, and the elemental composition and element distribution of the test piece 90 may be analyzed by the Auger electron spectrometer 100.

[0125] In the first to third embodiments, the oxide semiconductors constituting the semiconductor layer 18 and the inspection target layer 38 are In—Ga—Zn—O-based semiconductors, but this is not limiting. For example, the oxide semiconductors constituting the semiconductor layer 18 and the inspection target layer 38 may be other oxide semiconductors, such as In—Ga—Zn—O-based semiconductors, In—Sn—Zn—O-based semiconductors, In—Al—Zn—O-based semiconductors, In—Al—Sn—O-based semiconductors, Zn—O-based semiconductors, In—Zn—O-based semiconductors, Zn—Ti—O-based semiconductors, Cd—Ge—O-based semiconductors, Cd—Pb—O-based semiconductors, Mg—Zn—O-based semiconductors, In—Ga—Sn—O-based semiconductors, and In—Ga—Zn—Sn—O-based semiconductors.

[0126] In the above-described third embodiment, the alignment mark is configured by a test pattern having a structure similar to that of a bottom-gate TFT. However, this is not limiting. A test pattern having a structure similar to that of a top-gate TFT, as shown in the second embodiment, can also function as an alignment mark. In this case, the dummy electrode overlaps the test target layer via the gate insulating film serving as the second insulating film, and the pair of conductive electrodes and the dummy electrode form a cross shape similar to the shape generally used as an alignment mark, thereby functioning as an alignment mark.

[0127] In the above-described first to third embodiments, each pixel PX is configured with sub-pixels SP of three colors, but this is not limited thereto. The sub-pixels SP that configure each pixel PX may be of four or more colors. Furthermore, the three sub-pixels SP that configure each pixel PX are arranged in a stripe pattern, but this is not limited thereto. The arrangement of the multiple sub-pixels SP may be a Pentile arrangement or other arrangement.

[0128] In the above-described first to third embodiments, the organic EL layer 56 is provided individually for each subpixel SP, but this is not limiting. The organic EL layer 56 may be provided as a single layer common to a plurality of subpixels SP. In this case, the organic EL display device 1 may be provided with a color filter or the like to express color tones in each subpixel SP.

[0129] In the above-described first to third embodiments, the pixel electrode 54 functions as an anode and the common electrode 58 functions as a cathode, but this is not limiting. The organic EL display device 1 may be configured so that the pixel electrode 54 functions as a cathode and the common electrode 58 functions as an anode. In this case, the organic EL layer 56 has an inverted stacked structure.

[0130] In the above-described first to third embodiments, the organic EL layer 56 has a five-layer structure including a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer, but is not limited to this. The organic EL layer 56 may have a three-layer structure including a hole injection / transport layer, a light-emitting layer, and an electron injection / transport layer, or any other laminated structure may be adopted.

[0131] In the above-described first to third embodiments, the substrate of the organic EL display device 1 is the substrate layer 5, but this is not limiting. The substrate can be made of any material, such as a plastic substrate made of polyethylene terephthalate (PET) or a glass substrate, as long as it is optically transparent.

[0132] In the above-described first to third embodiments, the organic EL display device 1 is exemplified as a display device according to the present disclosure, but the present disclosure is not limited thereto. The technology of the present disclosure can be applied to a display device including a semiconductor element using an oxide semiconductor. For example, an example of such a display device is a quantum dot display device including a QLED (Quantum-dot Light Emitting Diode), which is a light-emitting element using a quantum dot-containing layer. In addition, the technology of the present disclosure can also be applied to a liquid crystal display device or a plasma display device.

[0133] As described above, preferred embodiments have been described as examples of the technology of the present disclosure. However, the technology of the present disclosure is not limited to these, and can be applied to embodiments in which appropriate modifications, substitutions, additions, omissions, etc. are made. It will be understood by those skilled in the art that various modifications are possible to the above-described embodiments without departing from the spirit of the technology of the present disclosure, and that such modifications also fall within the scope of the technology of the present disclosure.

[0134] It should be noted that the terms "first," "second," etc. mentioned above are merely used to distinguish the terms to which these terms are attached, and do not limit the number or order of the terms.

[0135] As described above, the present disclosure is useful for a test pattern, an element substrate, and a display device.

[0136] REFERENCE SIGNS LIST 1 Organic EL display device (display device) 5 Circuit board (element substrate) 10 TFT (semiconductor element) 14 Gate insulating film (first insulating film, second insulating film) 18 Semiconductor layer 20 Terminal electrode 22 Passivation film (second insulating film, third insulating film) 30 Inspection pattern 32 Dummy electrode 38 Inspection target layer 38i Inspection area 40 Conductive electrode DA Display area FA Frame area Ha First contact hole Hb Second contact hole

Claims

1. A test pattern comprising: a substrate; a first insulating film formed on the substrate and made of an inorganic insulating material; an inspection target layer formed on the first insulating film and made of an oxide semiconductor; a second insulating film formed so as to cover the inspection target layer and made of an inorganic insulating material; a conductive electrode formed above the inspection target layer and connected to the inspection target layer; and a third insulating film formed so as to cover the conductive electrode, wherein a first contact hole penetrating to the conductive electrode is formed in the third insulating film.

2. The inspection pattern according to claim 1, wherein the second insulating film and the third insulating film are the same insulating film.

3. The test pattern according to claim 2, further comprising a dummy electrode provided on the substrate and covered by the first insulating film, the dummy electrode overlapping the test target layer via the first insulating film.

4. A test pattern according to claim 1, wherein a second contact hole penetrating to the test target layer is formed in the second insulating film, and the conductive electrode is provided on the second insulating film and connected to the test target layer via the second contact hole.

5. An inspection pattern according to claim 4, wherein an area of ​​the inspection target layer that does not overlap with the conductive electrode in a plan view constitutes an inspection area in which analysis by Auger electron spectroscopy can be performed, and no metal layer is provided above the inspection target layer in the portion corresponding to the inspection area.

6. A test pattern according to any one of claims 1 to 5, wherein one end of the conductive electrode is connected to the layer to be inspected, and the first contact hole is formed at a position corresponding to the other end of the conductive electrode located on the opposite side to the connection part with the layer to be inspected.

7. In the inspection pattern according to any one of claims 1 to 6, the area of ​​the inspection target layer that does not overlap with the conductive electrodes in plan view constitutes an inspection area that can be analyzed by Auger electron spectroscopy, and the area of ​​the inspection area in plan view is 100 μm ２ More than 10,000 μm ２ Below is the test pattern.

8. The inspection pattern according to claim 1, further comprising a dummy electrode that overlaps the inspection target layer via the first insulating film or the second insulating film, and the conductive electrode and the dummy electrode function as alignment marks.

9. The inspection pattern according to any one of claims 1 to 8, wherein the oxide semiconductor is an In-Ga-Zn-O based semiconductor.

10. An element substrate comprising: an inspection pattern according to any one of claims 1 to 9; and a semiconductor element provided on said substrate, wherein said semiconductor element comprises: a semiconductor layer formed of the same material in the same layer as said inspection target layer; and terminal electrodes formed of the same material in the same layer as said conductive electrodes and connected to said semiconductor layer.

11. An element substrate according to claim 10, wherein a region of the inspection target layer that does not overlap with the conductive electrodes in a planar view constitutes an inspection region in which analysis by Auger electron spectroscopy can be performed, and the area of ​​the inspection region in a planar view is larger than the area of ​​the region of the semiconductor layer that does not overlap with the terminal electrodes in a planar view.

12. The element substrate according to claim 10 or 11, wherein the semiconductor element is a thin film transistor.

13. A display device comprising an element substrate according to any one of claims 10 to 12.

14. A display device according to claim 13, comprising: a display area for displaying an image; and a frame area provided outside the display area as a non-display area in which no image is displayed; and the inspection pattern is provided in the frame area.

Images