Image processing optimization apparatus based on RISC-v soc

Abstract

Disclosed in the present invention is an image processing optimization apparatus based on an RISC-V SOC. The image processing optimization apparatus comprises an image sampling module, an ISP chip image processing unit and a processor, wherein the image sampling module comprises an image sensor, a signal conditioning module, an analog-to-digital conversion module and an image sensor control module. An input end of the signal conditioning module is used for receiving an analog electrical signal collected by the image sensor, and an output end of the signal conditioning module is connected to the ISP chip image processing unit by means of the analog-to-digital conversion module; the image sensor control module is used for receiving control signals of the ISP chip image processing unit and the processor to adjust the image sensor; and the signal conditioning module comprises a signal amplifier, a differential converter and a noise-reducing output device which are connected in sequence, wherein an input end of the signal amplifier is connected to an output end of the image sensor, and an output end of the noise-reducing output device is connected to an input end of the analog-to-digital conversion module. The present invention can realize the efficient processing of an image signal and improve the system stability.

Description

An image processing optimization device based on RISC-V SOC Technical Field

[0001] This invention belongs to the field of image processing technology, specifically relating to an image processing optimization device based on RISC-V SOC. Background Technology

[0002] Modern applications place ever-increasing demands on computing and image processing performance. Smartphones, smart cameras, and IoT devices all require efficient image processing and artificial intelligence computing capabilities. By integrating advanced image signal processors and specially designed AI accelerators, SoCs can provide high-performance image processing and fast, efficient machine learning inference support, offering powerful intelligent functions for applications. Image sensors, as a crucial component, generate analog signals through photoelectric conversion to form photogenerated carriers. These signals are then processed using signal processing methods, including analog-to-digital conversion. The processed image signal is finally analyzed and output by ISPs, CPUs, and other components. Traditional signal processing circuits either directly sample and quantize the image signal, resulting in high readout noise and requiring high compatibility with the analog-to-digital converter; otherwise, the image resolution will be severely affected. Another approach is to use amplifier circuits that are limited by capacitor values, making it difficult to achieve high gain and low noise. Using large capacitor values, however, leads to poor amplifier stability. Summary of the Invention

[0003] To address the above problems, this invention proposes an image processing optimization device based on a RISC-V SOC. The technical solution adopted by this invention to solve the above technical problems is as follows:

[0004] An image processing optimization device based on a RISC-V SOC includes an image sampling module, an ISP chip image processing unit, and a processor connected in sequence. The image sampling module includes an image sensor, a signal conditioning module, an analog-to-digital converter (ADC), and an image sensor control module. The input of the signal conditioning module receives analog electrical signals acquired by the image sensor, and the output of the signal conditioning module is connected to the ISP chip image processing unit via the ADC. The image sensor control module receives control signals from the ISP chip image processing unit and the processor to adjust the image sensor. The signal conditioning module includes a signal amplifier, a differential converter, and a noise reduction output unit. The input of the signal amplifier is connected to the output of the image sensor, and the output of the signal amplifier is connected to the input of the differential converter. The differential converter converts the received signal into a differential signal and sends the converted differential signal to the noise reduction output unit. The noise reduction output unit performs noise reduction on the received differential signal and then transmits the noise-reduced signal to the ADC module.

[0005] The ISP chip image processing unit includes an optical front-end processing subunit, a digital front-end processing subunit, an optical back-end processing subunit, a digital back-end processing subunit, and a 3A statistical subunit. The input terminal of the optical front-end processing subunit is connected to the output terminal of the analog-to-digital conversion module. The output terminal of the optical front-end processing subunit is connected to the input terminal of the digital front-end processing subunit. The output terminal of the digital front-end processing subunit is connected to the input terminal of the optical back-end processing subunit. The output terminal of the optical back-end processing subunit is connected to the input terminal of the digital back-end processing subunit. The output terminal of the digital back-end processing subunit is connected to the input terminal of the 3A statistical subunit. The output terminal of the 3A statistical subunit is connected to the image sensor control module and the processor.

[0006] The signal amplifier includes a capacitor C1. One end of capacitor C1 receives the analog electrical signal output from the image sensor. The other end of capacitor C1 is connected to one end of resistor R1. The other end of resistor R1 is connected to one end of resistor R2, one end of capacitor C2, and the inverting input of operational amplifier AR1. The non-inverting input of operational amplifier AR1 is connected to one end of resistor R3. The output of operational amplifier AR1 is connected to the other end of resistor R2, one end of capacitor C3, and one end of capacitor C5. The other end of capacitor C3 is connected to one end of capacitor C4 and the other end of capacitor C2. The other end of capacitor C5 is connected to one end of resistor R4. The gate of the field-effect transistor T1 is connected to one end of resistor R5. The source of the field-effect transistor T1 is connected to the collector of transistor Q1 and the input terminal of the differential converter. The emitter of transistor Q1 is connected to one end of resistor R6. The base of transistor Q1 is connected to one end of resistor R7 and the lower end of the sliding rheostat X1. The upper end of the sliding rheostat X1, the adjustment terminal of the sliding rheostat X1, the other end of power supply R4, and the drain of field-effect transistor T1 are all connected to power supply VCC. The other ends of resistor R7, resistor R3, capacitor C4, resistor R5, and resistor R6 are all grounded.

[0007] The differential converter includes a resistor R10. One end of resistor R10 is connected to the output terminal of the signal amplifier, and the other end of resistor R10 is connected to one end of capacitor C6 and the gate of field-effect transistor T3. The source of field-effect transistor T3 is connected to the other end of capacitor C6 and one end of resistor R12. The drain of field-effect transistor T3 is connected to one end of capacitor C7 and the source of field-effect transistor T2. The gate of field-effect transistor T2 is connected to one end of variable resistor X2. The drain of field-effect transistor T2 is connected to one end of resistor R11. The other end of capacitor C7 is connected to one end of capacitor C8 and the gate of field-effect transistor T5. The source of transistor T5 is connected to the other end of capacitor C8 and one end of resistor R14. The other ends of resistor R14 and resistor R12 are both grounded. The drain of transistor T5 is connected to the source of transistor T4. The drain of transistor T4 is connected to one end of resistor R13. The gate of transistor T4 is connected to one end of variable resistor X3. The other ends of variable resistor X3, resistor R13, variable resistor X2, and resistor R11 are all connected to power supply VCC. The drains of transistor T2 and transistor T4 are also connected to a noise reduction output.

[0008] The noise cancellation output includes a field-effect transistor (FET) T6. The gate of FET T6 is connected to one end of capacitor C20, one end of capacitor C21, and the drain of FET T2 in the differential converter. The drain of FET T6 is connected to the other end of capacitor C20, the drain of FET T7, the gate of FET T7, and one end of capacitor C10. The source of FET T6 is connected to the drain of FET T8, the gate of FET T8, and the gate of FET T9. The drain of FET T9 is connected to the source of FET T10. The gate of FET T10 is connected to capacitor C21. One end of capacitor C23, one end of capacitor C22, and the drain of field-effect transistor T4 of the differential converter are connected. The other ends of capacitor C23 and C21, the source of field-effect transistor T8, and the source of field-effect transistor T9 are all grounded. The drain of field-effect transistor T10 is connected to the other end of capacitor C22, one end of capacitor C11, the drain of field-effect transistor T11, and the gate of field-effect transistor T11. The sources of field-effect transistor T11 and T7 are both connected to the power supply VCC. The other ends of capacitor C11 and C10 are both connected to the input terminal of the analog-to-digital converter.

[0009] The beneficial effects of this invention are:

[0010] 1. The RISC-V architecture processor can meet the special requirements of ISP integrated SoC for processors, achieving a balance between high performance and low power consumption. This allows the chip to maintain efficient processing capabilities while reducing power consumption and extending the lifespan of the device.

[0011] 2. ISP technology can be deeply integrated with SoC chips to achieve high-performance image processing capabilities and computing, communication, and other functions on a single chip, significantly improving overall system performance, simplifying system complexity, reducing costs, and enhancing system stability and reliability. The ISP chip image processing unit outputs RGB or YUV format image data through processes such as black level compensation, lens shading correction, bad pixel elimination, color interpolation, white balance correction, and color space conversion, achieving optimized image signal processing.

[0012] 3. The signal amplifier, differential converter, and noise cancellation output work together to amplify the signal while suppressing noise signals generated by the power supply, further shielding the influence of interference signals, improving the signal-to-noise ratio, effectively improving the purity and stability of the signal, ensuring that the analog signal can be accurately and stably transmitted to the analog-to-digital converter, and thus optimizing the image signal. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0014] Figure 1 is a schematic diagram of the module structure of the present invention;

[0015] Figure 2 is a schematic diagram of the module structure of the image processing unit of the ISP chip;

[0016] Figure 3 is a schematic diagram of the module structure of the optical front-end processing subunit;

[0017] Figure 4 is a schematic diagram of the module structure of the digital front-end processing subunit;

[0018] Figure 5 is a schematic diagram of the module structure of the optical back-end processing subunit;

[0019] Figure 6 is a schematic diagram of the module structure of the digital back-end processing subunit;

[0020] Figure 7 is a schematic diagram of the circuit structure of the signal amplifier;

[0021] Figure 8 is a schematic diagram of the circuit structure of the differential converter and the noise-canceling output circuit. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] RISC-V is an open-source instruction set architecture designed and released by the University of California, Berkeley, with applications including IoT devices and high-performance computing. RISC-V instructions have three operands, employ a load-store RISC architecture, and consist of 32-bit, 64-bit, and 128-bit basic instruction sets and six extended instruction sets: M, A, F, D, Q, and C. One of the advantages of RISC-V is its support for instruction extensions, allowing for application-specific instruction extensions, making processor design more flexible, and avoiding patent licensing issues due to its open-source nature. Using the RISC-V architecture not only reduces development costs but also promotes the development of the open-source hardware ecosystem, fostering innovation and collaboration. One of the characteristics of the RISC-V architecture is its streamlined design and small instruction set, enabling its processor cores to achieve efficient computation with low power consumption. Furthermore, SoC processors based on this architecture can address future quantum computing threats, improve computing and image processing performance, achieve low power consumption and high energy efficiency, promote the open-source ecosystem, enhance device security, and meet diverse application needs.

[0024] An image processing optimization device based on a RISC-V SoC, as shown in Figure 1, includes an image sampling module, an ISP (Image Signal Processor) chip image processing unit, and a processor (CPU) connected in sequence. The image sampling module is used to acquire image signals, process the sampled image signals, and convert them into digital signals. The ISP chip image processing unit is mainly used to process image signals, enabling image restoration or optimization. It plays a core and dominant role in video or photographic systems and is an important component of a camera. The signal processed by the ISP is transmitted to the processor, which can control the image sampling module and further process the image. In this embodiment, the processor is based on the RISC-V architecture. RISC-V SoCs have significant advantages in image quality and encryption performance. Its 4K image quality and 64MB encryption performance far exceed MediaTek's 2K image quality and 48MB encryption performance, making it more suitable for applications requiring high resolution and strong data protection capabilities. For example, in video surveillance and high-end consumer electronics devices, high-resolution images and strong encryption performance can provide a better user experience and data security. In addition, using low-power RISC-V series processors can maintain low power consumption when handling high-performance tasks, extend the device's battery life, and improve overall energy efficiency, which is especially important for devices that need to run for a long time and have limited battery capacity.

[0025] The image sampling module includes an image sensor, a signal conditioning module, an analog-to-digital converter (ADC), and an image sensor control module. Due to physical limitations of the lens and image sensor, and the diversity of lighting conditions in shooting scenes, cameras and other devices cannot achieve the desired image quality without an ISP chip. Light from the scene is projected onto the surface of the image sensor through the lens, where it undergoes photoelectric conversion to generate an analog electrical signal. The signal conditioning module amplifies and reduces noise in the analog electrical signal. The processed analog electrical signal is then converted into a RAW format digital image signal by the ADC module and sent to the ISP image signal processor for optimization. The image sensor control module is connected to the processor, which controls the activation and deactivation of the image sensor through this module. The ISP chip processes the Bell-shaped raw image from the sensor using algorithms such as black level compensation, lens shading correction, bad pixel removal, color interpolation, white balance correction, and color space conversion. It also performs automatic exposure and autofocus controls, finally outputting image data in RGB or YUV format, which is transmitted to the processor via a bus interface for further processing.

[0026] As shown in Figure 2, the ISP chip image processing unit mainly includes an optical front-end processing subunit (OFE), a digital front-end processing subunit (DFE), an optical back-end processing subunit (OBE), a digital back-end processing subunit (DBE), a 3A statistical subunit, and other functional units. The raw image from the CIS (CMOS Image Sensor) is converted into a RAW format image signal by the analog-to-digital conversion module, and then sequentially processed by the optical front-end processing subunit, digital front-end processing subunit, optical back-end processing subunit, and digital back-end processing subunit to complete image algorithm processing before output. Simultaneously, during image processing, the 3A statistical subunit performs statistical analysis on the image information and feeds the results back to the image sensor control module to correct camera parameters such as exposure, focal length, and white balance.

[0027] The optical front-end processing subunit is the first raw image processing subunit of the ISP chip, and its main function is to correct image distortion caused by the camera's optical system. As shown in Figure 3, the optical front-end processing subunit mainly includes several functional modules connected in sequence, such as the image generation module (patgen), image cropping module (crop), downsampling module (binning), fixed noise cancellation module (FPNR), image formatting module (input formatter), artifact repair module (bac), bad pixel correction module (dpc), and green balance module (ge). The image formatting specifically includes the pre-multiplexing preprocessing module (pre mux), decoding module (decompander), and post-multiplexing postprocessing module (post mux), which are connected in sequence. The post-multiplexing postprocessing module then sends the processed signal to the digital front-end processing subunit.

[0028] After image data is processed by the optical front-end processing unit (OFE), it will undergo further processing by the digital front-end processing unit (DFE). As shown in Figure 4, the DFE subunit comprises three core functional modules: a DFE preprocessing module (dfe_pre), a shared buffer module, and an image denoising module (nr), as well as a DFE post-processing module (dfe_post). Data input from the OFE subunit first undergoes basic functions such as black level correction, digital signal compensation, and data conversion in the DFE preprocessing module. The data is then written to the shared buffer module. Subsequently, the image denoising module performs image noise reduction on the buffered data. Finally, the DFE post-processing module performs chromaticity correction on the denoised image and outputs it to the subsequent optical back-end processing unit for further processing.

[0029] The Optical Back-End Processing (OBE) subunit, acting as a downstream module of the DFE subunit, further optimizes the output data of the DFE subunit. As shown in Figure 5, the OBE subunit mainly comprises a Lens Shading Correction module and a Tone Mapping module connected in sequence, used to eliminate the shading effect of the camera lens and simultaneously correct the tone of the original image.

[0030] The digital back-end processing subunit is the last image algorithm processing subunit in the ISP hardware unit, as shown in Figure 6. It mainly includes a color interpolation function module (Demosaic) and a data post-processing module (dbe_post) connected in sequence. The optimized RAW image is color interpolated by the color interpolation function module, thereby converting it into RGB format image data. Then, data post-processing is performed according to different data output modes. After the color gamut space conversion of the image is completed by the data post-processing module, the RGB format or YUV format can be selected for data output according to application requirements.

[0031] The 3A statistical subunit can be functionally divided into three parts: an autofocus module (AF), an auto exposure module (AE), and an auto white balance module (AWB). Its main function is to statistically analyze image features and output statistical values ​​via the RO (Real Image Layout) module. This provides feedback to the image sensor control module, enabling automatic optimization of parameters such as camera focus, exposure, and white balance. The basic data processing flow involves statistically analyzing and accumulating feature values ​​from RAW or RGB format images. Three statistical methods are used: region statistics, global statistics, and region of interest (ROI) statistics. The final calculation results are packaged and output in read-only register mode. The emergence of the 3A system has lowered the technical barrier to photography, making photography accessible in daily life and introducing photographic systems into new fields such as security monitoring, facial recognition, and robotics.

[0032] The signal conditioning module includes a signal amplifier, a differential converter, and a noise cancellation output unit. The input of the signal amplifier is connected to the output of the image sensor, and the output of the signal amplifier is connected to the input of the differential converter. The differential converter converts the received signal into a differential signal and sends the converted differential signal to the noise cancellation output unit. The noise cancellation output unit performs noise cancellation on the received differential signal before transmitting the denoised signal to the analog-to-digital converter module. These components work together to ensure that the analog signal can be accurately and stably transmitted to the analog-to-digital converter. The signal amplifier is an important part of the signal conditioning module, and its main function is to increase the amplitude of the analog signal. The differential converter converts the image signal into a differential signal while amplifying it, which can suppress noise signals generated by power supply, etc., and further shield the influence of interference signals. The main purpose of the noise cancellation output unit is to eliminate noise and interference components in the analog signal, improve the signal-to-noise ratio, and effectively improve the purity and stability of the signal.

[0033] As shown in Figure 7, the signal amplifier includes a capacitor C1. One end of capacitor C1 receives the analog electrical signal output from the image sensor. The other end of capacitor C1 is connected to one end of resistor R1. The other end of resistor R1 is connected to one end of resistor R2, one end of capacitor C2, and the inverting input of operational amplifier AR1. The non-inverting input of operational amplifier AR1 is connected to one end of resistor R3. The output of operational amplifier AR1 is connected to the other end of resistor R2, one end of capacitor C3, and one end of capacitor C5. The other end of capacitor C3 is connected to one end of capacitor C4 and the other end of capacitor C2. The other end of capacitor C5 is connected to the other end of resistor R4. One end of resistor R5 is connected to the gate of field-effect transistor T1. The source of field-effect transistor T1 is connected to the collector of transistor Q1 and the input terminal of the differential converter. The emitter of transistor Q1 is connected to one end of resistor R6. The base of transistor Q1 is connected to one end of resistor R7 and the lower end of sliding rheostat X1. The upper end of sliding rheostat X1, the adjustment terminal of sliding rheostat X1, the other end of power supply R4, and the drain of field-effect transistor T1 are all connected to power supply VCC. The other ends of resistor R7, resistor R3, capacitor C4, resistor R5, and resistor R6 are all grounded.

[0034] Capacitor C1 is a DC blocking capacitor. The analog image signal output from the image sensor is transmitted to the inverting input of operational amplifier AR1 through capacitor C1 and resistor R1. Capacitors C2-C4 form a T-type feedback network connected between the inverting input and output of operational amplifier AR1, which can feed the output signal back to the input stage for distortion compensation and reduce signal distortion. The signal amplified by operational amplifier AR1 is transmitted to the gate of field-effect transistor T1 through capacitor C5. Resistors R4 and R5 are gate bias resistors. Sliding rheostat X1 and resistor R7 are voltage divider resistors, providing bias voltage for transistor Q1. Transistor Q1 and resistor R6 are connected to the source of field-effect transistor T1 and form a constant current circuit, which better ensures that the amplified image signal is accurately transmitted to the output.

[0035] As shown in Figure 8, the differential converter includes a resistor R10. One end of resistor R10 is connected to the output terminal of the signal amplifier, and the other end of resistor R10 is connected to one end of capacitor C6 and the gate of field-effect transistor T3. The source of field-effect transistor T3 is connected to the other end of capacitor C6 and one end of resistor R12. The drain of field-effect transistor T3 is connected to one end of capacitor C7 and the source of field-effect transistor T2. The gate of field-effect transistor T2 is connected to one end of variable resistor X2. The drain of field-effect transistor T2 is connected to one end of resistor R11. The other end of capacitor C7 is connected to one end of capacitor C8 and the gate of field-effect transistor T5. The source of MOSFET T5 is connected to the other end of capacitor C8 and one end of resistor R14. The other ends of resistor R14 and resistor R12 are both grounded. The drain of MOSFET T5 is connected to the source of MOSFET T4. The drain of MOSFET T4 is connected to one end of resistor R13. The gate of MOSFET T4 is connected to one end of variable resistor X3. The other ends of variable resistor X3, resistor R13, variable resistor X2, and resistor R11 are all connected to power supply VCC. The drains of MOSFET T2 and MOSFET T4 are also connected to a noise reduction output.

[0036] The amplified image signal output from the signal amplifier is transmitted to the gate of MOSFET T3 through resistor R10. MOSFETs T3 and T5 form a differential circuit. Capacitor C7 is connected between the drain of MOSFET T3 and the gate of MOSFET T5 as a compensation capacitor. By appropriately selecting the capacitance value of the compensation capacitor, the output characteristics of the differential circuit can be effectively improved. Variable resistors X2 and X3 are the bias resistors for MOSFETs T2 and T4, respectively. MOSFETs T2 and T4 are connected to the drains of MOSFETs T3 and T5, respectively. The Cascode structure can effectively improve the circuit voltage gain. Converting a single-ended signal to a dual-ended signal based on differential switching can effectively suppress common-mode noise and common-mode interference, increasing the output swing.

[0037] The noise cancellation output includes a field-effect transistor (FET) T6. The gate of FET T6 is connected to one end of capacitor C20, one end of capacitor C21, and the drain of FET T2 in the differential converter. The drain of FET T6 is connected to the other end of capacitor C20, the drain of FET T7, the gate of FET T7, and one end of capacitor C10. The source of FET T6 is connected to the drain of FET T8, the gate of FET T8, and the gate of FET T9. The drain of FET T9 is connected to the source of FET T10. The gate of FET T10 is connected to capacitor C21. One end of capacitor C23, one end of capacitor C22, and the drain of field-effect transistor T4 of the differential converter are connected. The other ends of capacitor C23 and C21, the source of field-effect transistor T8, and the source of field-effect transistor T9 are all grounded. The drain of field-effect transistor T10 is connected to the other end of capacitor C22, one end of capacitor C11, the drain of field-effect transistor T11, and the gate of field-effect transistor T11. The sources of field-effect transistor T11 and T7 are both connected to the power supply VCC. The other ends of capacitor C11 and C10 are both connected to the input terminal of the analog-to-digital converter.

[0038] Field-effect transistors (FETs) T8 and T9 form a current source and serve as the source load for FETs T6 and T10, reducing the impact of external interference factors such as temperature changes and high-frequency signals on the circuit and improving its overall stability. FET T7's gate and drain are connected, serving as the drain load for FET T6. Simultaneously, FET T11's gate and drain are connected, serving as the drain load for FET T10, further enhancing circuit stability and reducing signal distortion. The differential signal output from the differential converter is transmitted to the gates of FETs T6 and T10. Capacitors C21 and C23 filter high-frequency signals, while capacitors C20 and C22 improve the gain of the FETs, enhancing the signal-to-noise ratio of the image signal and thus optimizing the image signal. The improved analog image signal is then transmitted to the A / D converter for A / D conversion.

[0039] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An image processing optimization device based on a RISC-V SOC, comprising an image sampling module, an ISP chip image processing unit, and a processor connected in sequence, characterized in that, The image sampling module includes an image sensor, a signal conditioning module, an analog-to-digital converter (ADC), and an image sensor control module. The input of the signal conditioning module receives the analog electrical signals acquired by the image sensor, and its output is connected to the ISP chip image processing unit via the ADC. The image sensor control module receives control signals from the ISP chip image processing unit and the processor to adjust the image sensor. The signal conditioning module includes a signal amplifier, a differential converter, and a noise reduction output unit. The input of the signal amplifier is connected to the output of the image sensor, and its output is connected to the input of the differential converter. The differential converter converts the received signal into a differential signal and sends the converted differential signal to the noise reduction output unit. The noise reduction output unit performs noise reduction on the received differential signal before transmitting the denoised signal to the ADC module.

2. The image processing optimization device based on RISC-V SOC according to claim 1, characterized in that, The ISP chip image processing unit includes an optical front-end processing subunit, a digital front-end processing subunit, an optical back-end processing subunit, a digital back-end processing subunit, and a 3A statistical subunit. The input terminal of the optical front-end processing subunit is connected to the output terminal of the analog-to-digital conversion module. The output terminal of the optical front-end processing subunit is connected to the input terminal of the digital front-end processing subunit. The output terminal of the digital front-end processing subunit is connected to the input terminal of the optical back-end processing subunit. The output terminal of the optical back-end processing subunit is connected to the input terminal of the digital back-end processing subunit. The output terminal of the digital back-end processing subunit is connected to the input terminal of the 3A statistical subunit. The output terminal of the 3A statistical subunit is connected to the image sensor control module and the processor.

3. The image processing optimization device based on RISC-V SOC according to claim 1, characterized in that, The signal amplifier includes a capacitor C1. One end of capacitor C1 receives the analog electrical signal output from the image sensor. The other end of capacitor C1 is connected to one end of resistor R1. The other end of resistor R1 is connected to one end of resistor R2, one end of capacitor C2, and the inverting input of operational amplifier AR1. The non-inverting input of operational amplifier AR1 is connected to one end of resistor R3. The output of operational amplifier AR1 is connected to the other end of resistor R2, one end of capacitor C3, and one end of capacitor C5. The other end of capacitor C3 is connected to one end of capacitor C4 and the other end of capacitor C2. The other end of capacitor C5 is connected to one end of resistor R4. The gate of the field-effect transistor T1 is connected to one end of resistor R5. The source of the field-effect transistor T1 is connected to the collector of transistor Q1 and the input terminal of the differential converter. The emitter of transistor Q1 is connected to one end of resistor R6. The base of transistor Q1 is connected to one end of resistor R7 and the lower end of the sliding rheostat X1. The upper end of the sliding rheostat X1, the adjustment terminal of the sliding rheostat X1, the other end of power supply R4, and the drain of field-effect transistor T1 are all connected to power supply VCC. The other ends of resistor R7, resistor R3, capacitor C4, resistor R5, and resistor R6 are all grounded.

4. The image processing optimization device based on RISC-V SOC according to claim 1, characterized in that, The differential converter includes a resistor R10. One end of resistor R10 is connected to the output terminal of the signal amplifier, and the other end of resistor R10 is connected to one end of capacitor C6 and the gate of field-effect transistor T3. The source of field-effect transistor T3 is connected to the other end of capacitor C6 and one end of resistor R12. The drain of field-effect transistor T3 is connected to one end of capacitor C7 and the source of field-effect transistor T2. The gate of field-effect transistor T2 is connected to one end of variable resistor X2. The drain of field-effect transistor T2 is connected to one end of resistor R11. The other end of capacitor C7 is connected to one end of capacitor C8 and the gate of field-effect transistor T5. The source of transistor T5 is connected to the other end of capacitor C8 and one end of resistor R14. The other ends of resistor R14 and resistor R12 are both grounded. The drain of transistor T5 is connected to the source of transistor T4. The drain of transistor T4 is connected to one end of resistor R13. The gate of transistor T4 is connected to one end of variable resistor X3. The other ends of variable resistor X3, resistor R13, variable resistor X2, and resistor R11 are all connected to power supply VCC. The drains of transistor T2 and transistor T4 are also connected to a noise reduction output.

5. The image processing optimization device based on RISC-V SOC according to claim 1, characterized in that, The noise cancellation output includes a field-effect transistor (FET) T6. The gate of FET T6 is connected to one end of capacitor C20, one end of capacitor C21, and the drain of FET T2 in the differential converter. The drain of FET T6 is connected to the other end of capacitor C20, the drain of FET T7, the gate of FET T7, and one end of capacitor C10. The source of FET T6 is connected to the drain of FET T8, the gate of FET T8, and the gate of FET T9. The drain of FET T9 is connected to the source of FET T10. The gate of FET T10 is connected to capacitor C21. One end of capacitor C23, one end of capacitor C22, and the drain of field-effect transistor T4 of the differential converter are connected. The other ends of capacitor C23 and C21, the source of field-effect transistor T8, and the source of field-effect transistor T9 are all grounded. The drain of field-effect transistor T10 is connected to the other end of capacitor C22, one end of capacitor C11, the drain of field-effect transistor T11, and the gate of field-effect transistor T11. The sources of field-effect transistor T11 and T7 are both connected to the power supply VCC. The other ends of capacitor C11 and C10 are both connected to the input terminal of the analog-to-digital converter.

Images