Communication method and apparatus

Abstract

Provided in the present application are a communication method and apparatus, which are used for reducing the blind detection complexity of PDCCHs. In the method, when PDCCHs support self-decoding (i.e., the length of an information bit sequence is less than a threshold value), the encoding structures (i.e., information bits / frozen bits) of PDCCHs having higher aggregation levels (e.g., AL=4 / 8 / 16, etc.) include the encoding structures (i.e., information bits / frozen bits) of PDCCHs having lower aggregation levels (e.g., AL=2 / 4 / 8, etc.), such that even if the aggregation level of a PDCCH is relatively high, a receiving end can decode a small number of CCEs to acquire data, without needing to continue decoding the other CCEs, thereby realizing early termination of blind detection and reducing the complexity of a receiver.

Description

Communication method and device

[0001] Cross-references to related applications

[0002] This application claims priority to Chinese Patent Application No. 202410487359.X, filed on April 22, 2024, entitled "A Communication Method and Apparatus", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of communication technology, and in particular to a communication method and apparatus. Background Technology

[0004] The physical downlink control channel (PDCCH) carries downlink control information (DCI). The scheduling unit of the PDCCH is the control channel element (CCE). Currently, the PDCCH supports aggregation levels of 1 / 2 / 4 / 8 / 16, meaning that the PDCCH can include 1 / 2 / 4 / 8 / 16 CCEs.

[0005] Currently, terminal devices must fully decode the received PDCCH before stopping decoding. This means that while decoding only a portion of the PDCCH, the terminal device cannot obtain the data sent by the network device via that PDCCH; it must wait until all PDCCH blocks are decoded before ceasing blind detection. For example, if a network device sends a PDCCH with aggregation level 8 to a terminal device, the terminal device cannot obtain the data sent by the network device via that PDCCH after decoding the first four CCEs; it must decode all eight blocks before ceasing blind detection. Summary of the Invention

[0006] This application provides a communication method and apparatus to reduce the complexity of blind detection in PDCCH.

[0007] Firstly, a communication method is provided, which can be executed by a transmitting end. The transmitting end can be a network device or a chip / chip system applied to a network device. Taking a network device as an example, in this method, the network device determines the information bits corresponding to a first coded bit sequence based on the length of the information bit sequence. If the length of the information bit sequence is less than or equal to a threshold value, the information bits corresponding to the first coded bit sequence include the information bits corresponding to a second coded bit sequence. The first and second coded bit sequences are carried in a PDCCH, and the aggregation level of the first coded bit sequence is higher than that of the second coded bit sequence. The network device maps the information bit sequence to the information bits corresponding to the first coded bit sequence, generates the first coded bit sequence based on the mapped bit sequence, and then sends the first coded bit sequence.

[0008] This application enables PDCCH to support self-decoding, making the encoding structure (i.e., information bits / freeze bits) of some bits in PDCCH with a high aggregation level (e.g., AL=4 / 8 / 16) the same as the encoding structure (i.e., information bits / freeze bits) of PDCCH with a low aggregation level (e.g., AL=2 / 4 / 8). Thus, even if the PDCCH has a high aggregation level, the receiver can decode a small number of CCEs to obtain data without having to decode other CCEs, thereby achieving blind detection and early stopping, and reducing receiver complexity.

[0009] In one possible design, the information bits corresponding to the first encoded bit sequence include:

[0010] The first set of information bits, the second set of information bits, and the third set of information bits.

[0011] The first information bit set consists of the same information bits in the fourth and fifth information bit sets.

[0012] The second information bit set consists of different information bits from the fourth information bit set and the fifth information bit set.

[0013] The third information bit set consists of different information bits from the fourth and fifth information bit sets within the fifth information bit set.

[0014] The fourth set of information bits consists of the bits corresponding to the H most reliable sub-channels out of the E sub-channels, and the fifth set of information bits consists of the bits corresponding to the H most reliable sub-channels out of the E / 2 sub-channels.

[0015] The second and third information bit sets are used to carry the same first information bit, and the first information bit set is used to carry information bits other than the first information bit in the information bit sequence.

[0016] E is the length of the first encoded bit sequence, and H is an integer greater than 0.

[0017] The above design includes information bits corresponding to H highly reliable sub-channels from E / 2 sub-channels in the information bits of the high-aggregation-level coded bit sequence, thereby enabling the information bits of the high-aggregation-level coded bit sequence to include information bits of the low-aggregation-level coded bit sequence.

[0018] In one possible design, the information bits corresponding to the second coded bit sequence consist of a first set of information bits and a third set of information bits. This approach allows the information bits of a high-aggregation-level coded bit sequence to include the information bits of a low-aggregation-level coded bit sequence.

[0019] In one possible design, if the length of the information bit sequence is greater than a threshold value, the information bits corresponding to the first encoded bit sequence include the bits corresponding to the H high-reliability sub-channels out of the E sub-channels, where E is the length of the first encoded bit sequence and H is an integer greater than 0.

[0020] In one possible design, H is equal to the length of the information bit sequence, or H is equal to the sum of the length of the information bit sequence and the length of the CRC bit sequence.

[0021] In one possible design, if the aggregation level of the first coded bit sequence is 4, the threshold value is 70; or, if the aggregation level of the first coded bit sequence is greater than or equal to 8, the threshold value is 140.

[0022] In one possible design, if the aggregation level of the first encoded bit sequence is 4, the threshold value is 94; or, if the aggregation level of the first encoded bit sequence is greater than or equal to 8, the threshold value is 164.

[0023] In one possible design, the threshold value is related to at least one of the following: the aggregation level of the first coded bit sequence, the size of the CCE in the PDCCH, the switching threshold of the rate matching mode, and the length of the CRC bit sequence of the first coded bit sequence.

[0024] In one possible design, the threshold value is related to at least one of the following: the aggregation level of the first coded bit sequence, the size of the CCE in the PDCCH, and the switching threshold of the rate matching mode.

[0025] In one possible design, the threshold value satisfies the following formula: Th = floor(AL / 2 × CCE) size ×R-CRC size );

[0026] Where Th is the threshold value, AL is the aggregation level of the first encoded bit sequence, and CCE is the threshold value. sizeThe size of CCE in PDCCH, CRC size R is the length of the CRC bit sequence of the first encoded bit sequence, R is the rate matching mode switching threshold, and floor() is the floor function.

[0027] In one possible design, the threshold value satisfies the following formula: Th = floor(AL / 2 × CCE) size ×R);

[0028] Where Th is the threshold value, AL is the aggregation level of the first encoded bit sequence, and CCE is the threshold value. size R is the size of CCE in PDCCH, R is the rate matching mode switching threshold, and floor() is the floor function.

[0029] The above three threshold designs enable most PDCCHs to support self-decoding, thus allowing for blind detection and early stopping.

[0030] In one possible design, some bits in the first coded bit sequence map to the same CCE as those in the second coded bit sequence, and some bits correspond to the same information bits as those in the second coded bit sequence. This design allows the receiver to decode a small number of CCEs to obtain data without needing to decode other CCEs, thus achieving blind detection and early stopping, and reducing receiver complexity.

[0031] In one possible design, the starting point for bit selection corresponding to the first coded bit sequence is related to at least one of the following parameters: the aggregation level of the first coded bit sequence, the code rate of the first coded bit sequence, and the rate matching method of the first coded bit sequence.

[0032] In one possible design, the first encoded bit sequence satisfies the following formula:

[0033] Among them, e k Let k be the bit numbered k in the first encoded bit sequence, E be the length of the first encoded bit sequence, N be the length of the corresponding mother code, and d be the bit numbered k. n This refers to bit n in the third encoded bit sequence, which is the bit sequence obtained by encoding the information bit sequence.

[0034] The above design ensures that some bits carried by the PDCCH with higher AL are the same as those carried by the PDCCH with lower AL, and the mapped CCEs are also the same. Therefore, if the communication environment of the terminal device is good, data can be obtained by decoding this part of the CCEs without decoding all the CCEs of the PDCCH with higher AL.

[0035] In one possible design, the first coded bit sequence is obtained by interleaving the fourth coded bit sequence, which is a bit sequence obtained by encoding and selecting bits from the information bit sequence. This design allows the receiver to decode a small number of CCEs using the decoding method corresponding to the second coded bit sequence, thus enabling blind detection and early stop after data acquisition.

[0036] In one possible design, the first M bits of the first coded bit sequence are the same as the last M bits of the fourth coded bit sequence, where M is the length of the second coded bit sequence. This design ensures that some bits carried by the PDCCH with higher AL are the same as those carried by the PDCCH with lower AL, and the mapped CCEs are also the same. Therefore, if the terminal device has a good communication environment, data can be obtained by decoding this portion of the CCEs without needing to decode all the CCEs of the PDCCH with higher AL.

[0037] In one possible design, the rate matching method for the first encoded bit sequence is either repetition or puncturing.

[0038] In one possible design, generating a first encoded bit sequence based on a bit sequence mapped to an information bit sequence includes: encoding the bit sequence mapped to the information bit sequence to obtain an encoded bit sequence; performing bit selection on the encoded bit sequence; and generating the first encoded bit sequence based on the bit sequence obtained after bit selection.

[0039] In one possible design, the aggregation level of the second encoded bit sequence is 4 or 2.

[0040] Secondly, a communication method is provided, which can be executed by a receiving end. The receiving end can be a terminal device or a chip / chip system applied to a terminal device. Taking a terminal device as an example, in this method, the terminal device receives a first symbol sequence, which is carried in a PDCCH; determines the information bits corresponding to the first symbol sequence based on the length of the information bit sequence; if the length of the information bit sequence is less than or equal to a threshold value, the information bits corresponding to the first symbol sequence include the information bits corresponding to the second symbol sequence, and the aggregation level of the first symbol sequence is higher than the aggregation level of the second symbol sequence; and decodes the first symbol sequence based on the information bits.

[0041] This application enables PDCCH to support self-decoding, making the encoding structure (i.e., information bits / freeze bits) of some bits in PDCCH with a high aggregation level (e.g., AL=4 / 8 / 16) the same as the encoding structure (i.e., information bits / freeze bits) of PDCCH with a low aggregation level (e.g., AL=2 / 4 / 8). Thus, even if the PDCCH has a high aggregation level, the receiver can decode a small number of CCEs to obtain data without having to decode other CCEs, thereby achieving blind detection and early stopping, and reducing receiver complexity.

[0042] In one possible design, the information bits corresponding to the first symbol sequence include:

[0043] The first set of information bits, the second set of information bits, and the third set of information bits.

[0044] The first information bit set consists of the same information bits in the fourth and fifth information bit sets.

[0045] The second information bit set consists of different information bits from the fourth information bit set and the fifth information bit set.

[0046] The third information bit set consists of different information bits from the fourth and fifth information bit sets within the fifth information bit set.

[0047] The fourth information bit set consists of the bits corresponding to the H sub-channels with high reliability out of the E sub-channels, and the fifth information bit set consists of the bits corresponding to the H sub-channels of the E / 2 sub-channels sorted by reliability.

[0048] The second and third information bit sets are used to carry the same first information bit, and the first information bit set is used to carry information bits other than the first information bit in the information bit sequence.

[0049] E is the length of the first encoded bit sequence, and H is an integer greater than 0.

[0050] The above design includes information bits corresponding to H highly reliable sub-channels from E / 2 sub-channels in the information bits of the high-aggregation-level coded bit sequence, thereby enabling the information bits of the high-aggregation-level coded bit sequence to include information bits of the low-aggregation-level coded bit sequence.

[0051] In one possible design, the information bits corresponding to the second symbol sequence consist of a first set of information bits and a third set of information bits. This approach allows the information bits of a high-aggregation-level coded bit sequence to include the information bits of a low-aggregation-level coded bit sequence.

[0052] In one possible design, if the length of the information bit sequence is greater than a threshold value, the information bits corresponding to the first symbol sequence include the bits corresponding to the H most reliable sub-channels out of the E sub-channels, where E is the length of the first coded bit sequence and H is an integer greater than 0.

[0053] In one possible design, H is equal to the length of the information bit sequence, or H is equal to the sum of the length of the information bit sequence and the length of the CRC bit sequence.

[0054] In one possible design, if the aggregation level of the first symbol sequence is 4, the threshold value is 70; or, if the aggregation level of the first symbol sequence is greater than or equal to 8, the threshold value is 140.

[0055] In one possible design, if the aggregation level of the first encoded bit sequence is 4, the threshold value is 94; or, if the aggregation level of the first encoded bit sequence is greater than or equal to 8, the threshold value is 164.

[0056] In one possible design, the threshold value is related to at least one of the following: the aggregation level of the first symbol sequence, the size of the CCE in the PDCCH, the switching threshold of the rate matching mode, and the length of the CRC bit sequence of the first symbol sequence.

[0057] In one possible design, the threshold value is related to at least one of the following: the aggregation level of the first coded bit sequence, the size of the CCE in the PDCCH, and the switching threshold of the rate matching mode.

[0058] In one possible design, the threshold value satisfies the following formula: Th = floor(AL / 2 × CCE) size ×R-CRC size );

[0059] Where Th is the threshold value, AL is the aggregation level of the first symbol sequence, and CCE is the threshold value. size The size of CCE in PDCCH, CRC size R is the length of the CRC bit sequence of the first symbol sequence, R is the rate matching mode switching threshold, and floor() is the floor function.

[0060] The above three threshold designs enable most PDCCHs to support self-decoding, thus allowing for blind detection and early stopping.

[0061] In one possible design, the threshold value satisfies the following formula: Th = floor(AL / 2 × CCE) size ×R);

[0062] Where Th is the threshold value, AL is the aggregation level of the first encoded bit sequence, and CCE is the threshold value. sizeR is the size of CCE in PDCCH, R is the rate matching mode switching threshold, and floor() is the floor function.

[0063] In one possible design, some bits in the first symbol sequence map to the same control channel elements (CCEs) as the CCEs mapped to the second symbol sequence, and some bits correspond to the same information bits as the corresponding information bits in the second symbol sequence. This design allows the receiver to decode a small number of CCEs to obtain data without needing to decode other CCEs, thus achieving blind detection and early stopping, and reducing receiver complexity.

[0064] In one possible design, the starting point for selecting the bits corresponding to the first symbol sequence is related to at least one of the following parameters: the aggregation level of the first symbol sequence, the code rate of the first symbol sequence, and the rate matching method of the first symbol sequence.

[0065] In one possible design, the starting point for selecting the bits corresponding to the first symbol sequence is the same as the starting point for selecting the bits corresponding to the second symbol sequence. This design allows the receiver to decode a small number of CCEs using the decoding method corresponding to the second encoded bit sequence, thus enabling blind detection and early stop after data acquisition.

[0066] In one possible design, the first encoded bit sequence satisfies the following formula:

[0067] Among them, e k Let k be the bit numbered k in the first encoded bit sequence, E be the length of the first encoded bit sequence, N be the length of the corresponding mother code, and d be the bit numbered k. n This refers to bit n in the third encoded bit sequence, which is the bit sequence obtained by encoding the information bit sequence.

[0068] The above design ensures that some bits carried by the PDCCH with higher AL are the same as those carried by the PDCCH with lower AL, and the mapped CCEs are also the same. Therefore, if the communication environment of the terminal device is good, data can be obtained by decoding this part of the CCEs without decoding all the CCEs of the PDCCH with higher AL.

[0069] In one possible design, the coded bit sequence corresponding to the first symbol sequence is obtained by interleaving the fourth coded bit sequence. The fourth coded bit sequence is the bit sequence obtained by encoding and selecting the information bit sequence. This design allows the receiver to decode a small number of CCEs using the decoding method corresponding to the second coded bit sequence, thus enabling blind detection and early stop after data acquisition.

[0070] In one possible design, the first M bits of the encoded bit sequence corresponding to the first symbol sequence are the same as the last M bits of the fourth encoded bit sequence, where M is the length of the second symbol sequence. This design ensures that some bits carried by the PDCCH with higher AL are the same as those carried by the PDCCH with lower AL, and the mapped CCEs are also the same. Therefore, if the terminal device has a good communication environment, data can be obtained by decoding this portion of the CCEs without needing to decode all the CCEs of the PDCCH with higher AL.

[0071] In one possible design, the rate matching method for the first symbol sequence is either repetition or punching.

[0072] In one possible design, decoding the first symbol sequence based on the information bits includes: recovering the first symbol sequence according to the bit selection method corresponding to the first symbol sequence to obtain the third symbol sequence; decoding the third symbol sequence based on the information bits; and obtaining the information bit sequence from the decoded bit sequence.

[0073] In one possible design, the aggregation level of the second encoded bit sequence is 4 or 2.

[0074] Thirdly, this application also provides a communication device, which is a network device or a chip within a network device. This communication device has the function of implementing any of the methods provided in the first aspect. The communication device can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more units or modules corresponding to the aforementioned functions.

[0075] In one possible design, the communication device includes a processor configured to support the communication device in performing the corresponding functions of the network device described above. The communication device may also include a memory coupled to the processor, which stores necessary program instructions and data for the communication device. Optionally, the communication device further includes interface circuitry for supporting communication between the communication device and devices such as terminal devices, for example, the transmission and reception of data or signals. Exemplarily, the communication interface may be a transceiver, circuit, bus, module, or other type of communication interface.

[0076] In one possible design, the communication device includes corresponding functional modules, each used to implement the steps in the above method. The functions can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the functions described above.

[0077] In one possible design, the communication device includes a processing unit (or processing module) and a communication unit (or communication module). These units can perform the corresponding functions in the above method examples, as described in the method provided in the first aspect, and will not be repeated here.

[0078] Fourthly, this application also provides a communication device, which is a terminal device or a chip within a terminal device. This communication device has the function of implementing any of the methods provided in the second aspect above. The communication device can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more units or modules corresponding to the above-described functions.

[0079] In one possible design, the communication device includes a processor configured to support the communication device in performing corresponding functions of the terminal device described above. The communication device may also include a memory coupled to the processor, which stores necessary program instructions and data for the communication device. Optionally, the communication device further includes interface circuitry for supporting communication between the communication device and devices such as network devices, for example, the transmission and reception of data or signals. Exemplarily, the communication interface may be a transceiver, circuit, bus, module, or other type of communication interface.

[0080] In one possible design, the communication device includes corresponding functional modules, each used to implement the steps in the above method. The functions can be implemented in hardware or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the functions described above.

[0081] In one possible design, the communication device includes a processing unit (or processing module) and a communication unit (or communication module). These units can perform the corresponding functions in the above method examples, as described in the method provided in the second aspect, and will not be repeated here.

[0082] Fifthly, a communication device is provided, including a processor and an interface circuit. The interface circuit is used to receive signals from other communication devices outside the communication device and transmit them to the processor, or to send signals from the processor to other communication devices outside the communication device. The processor is used to implement the methods of the first aspect and any possible design through logic circuits or execution code instructions.

[0083] In a sixth aspect, a communication device is provided, including a processor and an interface circuit. The interface circuit is configured to receive signals from other communication devices outside the communication device and transmit them to the processor, or to send signals from the processor to other communication devices outside the communication device. The processor is configured to implement the methods of the second aspect and any possible design described above through logic circuits or execution code instructions.

[0084] In a seventh aspect, a computer-readable storage medium is provided that stores a computer program or instructions which, when executed by a processor, implement the methods of the first or second aspect and any possible design described above.

[0085] Eighthly, a computer program product storing instructions is provided, which, when executed by a processor, implement the methods of the first or second aspect and any possible design described above.

[0086] A ninth aspect provides a chip system including a processor and potentially a memory for implementing the methods described in the first or second aspect and any possible design. The chip system may be composed of chips or may include chips and other discrete devices.

[0087] In a tenth aspect, a communication system is provided, the system comprising the apparatus of the first aspect (such as a network device) and the apparatus of the second aspect (such as a terminal device).

[0088] The technical effects that can be achieved by any of the technical solutions in the third to tenth aspects mentioned above can be described with reference to the technical effects that can be achieved by the technical solution in the first aspect mentioned above, and the repeated parts will not be repeated. Attached Figure Description

[0089] Figure 1 is a schematic diagram of the architecture of a communication system according to an embodiment of this application;

[0090] Figure 2 is a schematic diagram of a polar encoding according to an embodiment of this application;

[0091] Figure 3 is a flowchart illustrating a communication method according to an embodiment of this application;

[0092] Figure 4 is a schematic diagram of information bits according to an embodiment of this application;

[0093] Figure 5 is a schematic diagram of an encoding process according to an embodiment of this application;

[0094] Figure 6 is a schematic diagram of a sub-block interleaving according to an embodiment of this application;

[0095] Figure 7 is a schematic diagram of a sub-block interleaving according to an embodiment of this application;

[0096] Figure 8 is a schematic diagram of the structure of a communication device according to an embodiment of this application;

[0097] Figure 9 is a schematic diagram of the structure of a communication device according to an embodiment of this application. Detailed Implementation

[0098] The embodiments of this application can be applied to various fields that employ polar coding, such as data storage, optical network communication, and wireless communication. The aforementioned wireless communication fields may include, but are not limited to, 5G communication systems, future communication systems (such as 6G communication systems), satellite communication systems, device-to-device (D2D) communication systems, machine-to-machine (M2M) communication systems, the Internet of Things (IoT), drone communication systems, narrowband Internet of Things (NB-IoT) systems, long-term evolution (LTE) systems, and the three major application scenarios of 5G mobile communication systems: eMBB, ultra-reliable low-latency communication (URLLC), and massive machine-type communications (mMTC).

[0099] The following description, with reference to Figure 1, introduces the communication system to which the data transmission method provided in this application is applicable. Referring to Figure 1, the communication system 100 includes a transmitting end 101 and a receiving end 102. The transmitting end 101 can be a network device or a terminal device, and the receiving end 102 can be either a network device or a terminal device. Optionally, when the transmitting end 101 is a network device, the receiving end 102 can be a terminal device; when the receiving end 102 is a network device, the transmitting end 101 can be a terminal device.

[0100] The transmitting end 101 may include an encoder, which can polar encode the bits to be encoded and output the encoded codeword. The encoded codeword can be transmitted to the receiving end 102 over the channel after rate matching, interleaving, and modulation. The receiving end 102 may include a decoder, which can receive and demodulate the signal from the transmitting end 101. The receiving end 102 can decode the received signal using the decoder.

[0101] The terminal equipment involved in this application includes devices that provide voice and / or data connectivity to users. Specifically, it includes devices that provide voice connectivity to users, or devices that provide data connectivity to users, or devices that provide both voice and data connectivity to users. For example, it may include a handheld device with wireless connectivity or a processing device connected to a wireless modem. The terminal equipment may include user equipment (UE), wireless terminal equipment, mobile terminal equipment, device-to-device (D2D) terminal equipment, vehicle-to-everything (V2X) terminal equipment, machine-to-machine / machine-type communications (M2M / MTC) terminal equipment, Internet of Things (IoT) terminal equipment, subscriber unit, subscriber station, mobile station, remote station, access point (AP), remote terminal, access terminal, user terminal, user agent, or user device, satellite, drone, balloon, aircraft, etc. For example, it may include mobile phones (or "cellular" phones), computers with mobile terminal equipment, portable, pocket-sized, handheld, or computer-embedded mobile devices, etc. Examples include personal communication service (PCS) phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, personal digital assistants (PDAs), and other similar devices. It also includes limited devices, such as those with low power consumption, limited storage capacity, or limited computing power. Examples include information sensing devices such as barcode scanners, radio frequency identification (RFID), sensors, global positioning systems (GPS), and laser scanners. By way of example and not limitation, in this embodiment, the terminal device can also be a wearable device.Wearable devices, also known as wearable smart devices or smart wearable devices, are a general term for devices that utilize wearable technology to intelligently design and develop everyday wearables. The various terminal devices described above, if located in a vehicle (e.g., placed inside or installed in a vehicle), can be considered in-vehicle terminal devices, also known as on-board units (OBUs).

[0102] The network devices involved in this application, such as access network (AN) devices, such as base stations (e.g., access points), can refer to devices in the access network that communicate with wireless terminal devices through one or more cells over the air interface, or, for example, network devices in a vehicle-to-everything (V2X) technology, such as roadside units (RSUs). Network equipment may include evolved base stations (NodeBs, eNBs, or e-NodeBs) in long-term evolution (LTE) systems or long-term evolution-advanced (LTE-A) systems, or may include next-generation node Bs (gNBs) in evolved packet core (EPC), the 5th generation (5G), new radio (NR) systems (also referred to as NR systems), or may include centralized units (CUs) and distributed units (DUs) in cloud radio access networks (Cloud RAN) systems, satellites, drones, balloons, and aircraft, etc., which are not limited to the embodiments of this application.

[0103] Currently, polar coding is a channel coding scheme that can be rigorously proven to achieve the required channel capacity, possessing characteristics such as high performance, low complexity, and flexible matching methods. It has already been adopted by the Third Generation Cooperation Project (3GCP). rd The Generation Partnership Project (3GPP) has determined it to be the control channel coding scheme for the 5G control channel in the enhanced mobile broadband (eMBB) scenario.

[0104] Referring to Figure 2, a schematic diagram of polar encoding is shown. The corresponding code length in Figure 2 is 8. Each circle in each row represents a summation between the bits in the circle's row and the bits in the row it reaches. The bits to the right of the circle are the summation result. For example, the first circle in the row containing the first frozen bit means summing the frozen bit 0 in the circle's row (the first row) with the bit 0 in the row it reaches (the second row), resulting in a sum of 0.

[0105] In this diagram, u0 to u7 are the bits to be encoded. These bits are categorized into two types based on the reliability of their respective sub-channels: frozen bits and data bits. Sub-channels with lower reliability are designated as frozen sub-channels, and their values ​​are typically 0. Sub-channels with higher reliability are designated as data sub-channels, used to carry information bits. As shown in Figure 2, u7, u6, u5, and u3 are the four most reliable sub-channels, designated as data bits, while u4, u2, u1, and u0 are the four least reliable bits, designated as frozen bits.

[0106] It should be noted that during data transmission, the receiver and transmitter of the fixed-bit sub-channel are known. It is understood that, in this paper, the bit sub-channel can also be referred to as a sub-channel. Similarly, the set of bit sub-channels can also be referred to as the sub-channel set.

[0107] Currently, polar coding can be applied to the physical downlink control channel (PDCCH). The PDCCH is described below.

[0108] PDCCH is used to carry downlink control information (DCI). The scheduling unit of PDCCH is the control channel element (CCE). A CCE can carry a 108-bit coded bit sequence. Currently, PDCCH supports aggregation levels (AL) of 1 / 2 / 4 / 8 / 16, meaning a PDCCH can include 1 / 2 / 4 / 8 / 16 CCEs. Therefore, the length E of the PDCCH coded bit sequence is 108 bits, 216 bits, 432 bits, 864 bits, and 1728 bits. Currently, NR specifies that the maximum mother code length N for PDCCH encoding and decoding is 512 bits. Therefore, for a PDCCH with an AL of 8 / 16, a 512-bit sequence can be obtained through polar encoding, and then bits can be repeatedly selected from this 512-bit sequence to obtain 864-bit and 1728-bit coded bit sequences.

[0109] For example, when AL = 8 / 16 in PDCCH, a 512-bit encoded bit sequence d0, d1, d2, ..., d3 can be obtained through Polar code encoding. N-1 Then, sub-block interleaving is performed. The resulting coded bit sequence can be denoted as y0, y1, y2, ..., y N-1 Then you can use the following pseudocode to define y0, y1, y2, ..., y N-1 Performing bit selection yields a encoded bit sequence of length 864 / 1728:

[0110] for k=0 to E-1

[0111] e k =y mod(k,N) ;

[0112] end for

[0113] As can be seen from the above pseudocode, when AL = 8 / 16, the starting point e0 of bit selection starts from the first bit y0.

[0114] When AL=4 in PDCCH, a 512-bit encoded bit sequence can be obtained through Polar coding, followed by sub-block interleaving. The interleaved encoded bit sequence can be denoted as y0, y1, y2, ..., y N-1 Then you can use the following pseudocode to define y0, y1, y2, ..., y N-1 Performing bit selection yields a coded bit sequence of length 432:

[0115] for k=0 to E-1

[0116] e k =y k+N-E ;

[0117] end for

[0118] As shown in the pseudocode above, when AL=4, the first 80 bits are skipped during bit selection, and the starting point e0 of bit selection is from the 81st bit y. 80 The beginning.

[0119] Currently, terminal devices must fully decode a received PDCCH before stopping decoding. Even if the terminal device has already obtained data sent by the network device through the PDCCH while decoding a portion of the PDCCH, it still needs to wait for the entire PDCCH to be decoded before stopping decoding. For example, if a network device sends a PDCCH with AL=8 to a terminal device, and the terminal device's communication environment is good, it can obtain the data through 4 CCEs. However, the terminal device still needs to decode all 8 CCEs of the PDCCH according to the decoding method corresponding to AL=8, resulting in high complexity for blind PDCCH detection.

[0120] Based on this, embodiments of this application provide a communication method and apparatus. By enabling self-decoding of the PDCCH (i.e., the length of the information bit sequence is less than a threshold), the encoding structure (i.e., information bits / freeze bits) of the PDCCH with a higher aggregation level (e.g., AL = 4 / 8 / 16) includes the encoding structure (i.e., information bits / freeze bits) of the PDCCH with a lower aggregation level (e.g., AL = 2 / 4 / 8). Therefore, even with a high aggregation level of the PDCCH, the receiving end can decode a small number of CCEs to obtain data without needing to decode other CCEs, thus achieving blind detection and early stopping, reducing receiver complexity. The method and apparatus are based on the same concept. Since the principles by which the method and apparatus solve problems are similar, the implementations of the apparatus and method can be mutually referred to, and repeated details will not be elaborated further.

[0121] In the embodiments of this application, "when," "if," and "if" all refer to the device taking corresponding actions under certain objective circumstances, and are not time-limited, nor do they require the device to perform a judgment action, nor do they imply any other limitations. Unless otherwise specified, "if" and "if" can be substituted, and "when" and "in the case of" can be substituted. "When" and "if" / "if" can be substituted.

[0122] In the embodiments of this application, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, and c can be single or multiple.

[0123] Furthermore, unless otherwise stated, the ordinal numbers such as "first" and "second" mentioned in the embodiments of this application are used to distinguish multiple objects and are not used to limit the size, content, order, timing, priority, or importance of multiple objects. For example, the first coded bit sequence and the second coded bit sequence are only used to distinguish different coded bit sequences, and do not indicate that the length, priority, or importance of the two coded bit sequences are different.

[0124] The network architecture and business scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. As those skilled in the art will know, with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0125] In this application, the encoding structure can be understood as the position of the information bits / freeze bits. Identical encoding structures mean identical information bits. Identical information bits also mean identical freeze bits. Information bits and freeze bits can be derived from each other.

[0126] Referring to Figure 3, this is a flowchart illustrating a communication method provided in this application. The method includes:

[0127] S301, the network device determines the information bits corresponding to the first encoded bit sequence based on the length of the information bit sequence.

[0128] Wherein, if the length of the information bit sequence is less than the threshold value Th, the information bits corresponding to the first encoded bit sequence include the information bits corresponding to the second encoded bit sequence, the aggregation level of the first encoded bit sequence is higher than the aggregation level of the second encoded bit sequence, and the first encoded bit sequence is carried in the PDCCH.

[0129] For example, the length of the information bit sequence can be the length K of the payload, or the length of the information bit sequence can be the sum of the lengths of the payload and the CRC bits, i.e., K+L.

[0130] For example, the information bits corresponding to the first coded bit sequence may include: a first set of information bits, a second set of information bits, and a third set of information bits. This encoding construction of the first coded bit sequence can be called the first encoding construction, as shown in Figure 4.

[0131] The first information bit set consists of the bits corresponding to the same sub-channels among the H sub-channels with high reliability from the E sub-channels and the H sub-channels with high reliability from the E / 2 sub-channels. For example, the aforementioned E / 2 sub-channels may be the last E / 2 sub-channels among the E sub-channels.

[0132] For ease of description, the set of bits corresponding to the H most reliable sub-channels out of E sub-channels is referred to as the fourth information bit set, and the set of bits corresponding to the H most reliable sub-channels out of E / 2 sub-channels is referred to as the fifth information bit set. E is the length of the first coded bit sequence, and H is an integer greater than 0. For example, H is equal to the length of the payload K, or H is equal to the sum of the length of the payload and the length of the cyclic redundancy check (CRC) bits, i.e., K+L, etc.

[0133] In one exemplary illustration, the H sub-channels with high reliability can be understood as the top H sub-channels sorted from highest to lowest reliability.

[0134] The second information bit set consists of different information bits from the fourth information bit set and the fifth information bit set.

[0135] The third information bit set consists of different information bits from the fourth and fifth information bit sets within the fifth information bit set.

[0136] In the aforementioned information bits, the second and third information bit sets are used to carry the same first information bit. The information bits in the second and third information bit sets can be in one-to-one correspondence (or associated), with corresponding or associated information bits carrying the same information bit. The first information bit set is used to carry all information bits in the information bit sequence except for the first information bit. That is, the first and second information bit sets together carry all bits of the information bit sequence, and the first and third information bit sets together carry all bits of the information bit sequence. It should be understood that the first information bit may include one or more information bits.

[0137] In the above method, the fourth information bit set can be the union of the first information bit set and the second information bit set, and the fifth information bit set can be the union of the first information bit set and the third information bit set.

[0138] Since the information bits corresponding to the second coded bit sequence can include the bits corresponding to the H most reliable sub-channels out of E / 2 sub-channels (i.e., the aforementioned fifth information bit set, which is the union of the first and third information bit sets), it is evident that the information bits corresponding to the first coded bit sequence include the information bits corresponding to the second coded bit sequence.

[0139] If the length of the information bit sequence is greater than the threshold value Th, the information bits corresponding to the first coded bit sequence include the bits corresponding to the H most reliable sub-channels out of the E sub-channels, which is the fourth information bit set mentioned above, where E is the length of the first coded bit sequence and H is an integer greater than 0. This coding construction of the first coded bit sequence can be called the second coding construction.

[0140] When the length of the information bit sequence is equal to the threshold value Th, the encoding construction of the first encoded bit sequence can be a first encoding construction, which includes a first set of information bits, a second set of information bits, and a third set of information bits. Alternatively, the encoding construction of the first encoded bit sequence can also be a second encoding construction, which includes a fourth set of information bits.

[0141] The threshold value will be introduced below in light of two cases involving the length of the information bit sequence.

[0142] In case one, the length of the information bit sequence can be the length K of the payload, and the threshold value can be any one of the examples from Example 1 to Example 3 below.

[0143] Example 1: If the aggregation level of the first coded bit sequence is 1 or 2, Th is the value 1, for example, the value 1 is 0. If the aggregation level of the first coded bit sequence is 4, Th is the value 2, for example, the value 2 is 70. If the aggregation level of the first coded bit sequence is greater than or equal to 8, Th is the value 3, for example, the value 3 is 140.

[0144] Understandably, if the aggregation level of the first coded bit sequence is 1 or 2, the encoding structure of the first coded bit sequence is the second encoding structure. If the aggregation level of the first coded bit sequence is 4 or 8, or a higher aggregation level, and the aggregation level of the first coded bit sequence is greater than 8, then when the length K of the information bit sequence is less than Th, the encoding structure of the first coded bit sequence is the first encoding structure; when the length K of the information bit sequence is less than Th, the encoding structure of the first coded bit sequence is the second encoding structure.

[0145] Example 2: Th is related to at least one of the following: the aggregation level of the first coded bit sequence, the size (or length) of the CCE in the PDCCH, the switching threshold of the rate matching mode (or described as the switching code rate R), and the length of the CRC bit sequence of the first coded bit sequence. The switching threshold of the rate matching mode can be understood as a threshold value that determines the rate matching mode. For example, suppose the rate matching mode is determined as follows: if E > N, then the rate matching mode uses repetition; if E ≤ N, when R = K / E ≤ 7 / 16, then puncturation is used; and when R = K / E > 7 / 16, then truncation is used. The switching threshold of the rate matching mode can be 7 / 16.

[0146] Example 3, Th can satisfy the following formula:

[0147] Th = floor(AL / 2×CCE) size ×R-CRC size );

[0148] Alternatively, Th = ceil(AL / 2×CCE) size ×R-CRC size );

[0149] Alternatively, Th = round(AL / 2×CCE) size ×R-CRC size );

[0150] Where Th is the threshold value, AL is the aggregation level of the first encoded bit sequence, and CCE is the threshold value. size The size (or length) of the CCE in the PDCCH, CRC size R is the length of the CRC bit sequence of the first encoded bit sequence, R is the rate matching mode switching threshold, and floor() is the floor function.

[0151] Case 2: The length of the information bit sequence is the sum of the lengths of the payload and the CRC bits, i.e., K+L. The threshold value can be any one of the examples from Example 4 to Example 6 below.

[0152] Example 4: If the aggregation level of the first coded bit sequence is 1 or 2, Th is a value of 2, for example, value 1 is 24. If the aggregation level of the first coded bit sequence is 4, Th is a value of 2, for example, value 2 is 94. If the aggregation level of the first coded bit sequence is greater than or equal to 8, Th is a value of 3, for example, value 3 is 164.

[0153] Understandably, if the aggregation level of the first coded bit sequence is 1 or 2, the encoding structure of the first coded bit sequence is the second encoding structure. If the aggregation level of the first coded bit sequence is 4 or 8, or a higher aggregation level, and the aggregation level of the first coded bit sequence is greater than 8, then when the length of the information bit sequence is less than Th, the encoding structure of the first coded bit sequence is the first encoding structure, and when the length of the information bit sequence is less than Th, the encoding structure of the first coded bit sequence is the second encoding structure.

[0154] Example 5: Th is related to at least one of the following: the aggregation level of the first coded bit sequence, the size (or length) of the CCE in the PDCCH, and the switching threshold of the rate matching mode (or described as the switching code rate R). The switching threshold of the rate matching mode can be understood as a threshold value that determines the rate matching mode. For example, suppose the rate matching mode is determined as follows: if E > N, then repetition is used; if E ≤ N, then puncturing is used when R = K / E ≤ 7 / 16; and truncating is used when R = K / E > 7 / 16. The switching threshold of the rate matching mode can be 7 / 16.

[0155] Example 6, Th can satisfy the following formula:

[0156] Th = floor(AL / 2×CCE) size ×R);

[0157] Alternatively, Th = ceil(AL / 2×CCE) size ×R);

[0158] Alternatively, Th = round(AL / 2×CCE) size ×R);

[0159] Where Th is the threshold value, AL is the aggregation level of the first encoded bit sequence, and CCE is the threshold value. size R is the size (or length) of the CCE in the PDCCH, R is the rate matching mode switching threshold, floor() is round down, ceil() is round up, and round() is the nearest integer.

[0160] S302, the network device maps the information bit sequence to the information bits corresponding to the first encoded bit sequence.

[0161] S303, the network device generates a first encoded bit sequence based on the bit sequence that maps the information bit sequence.

[0162] S304, the network device sends the first encoded bit sequence. Correspondingly, the terminal device receives the first symbol sequence.

[0163] It should be understood that the first symbol sequence can be the signal received through a space channel after the first coded bit sequence has undergone modulation, frequency conversion, or other operations.

[0164] S305, the terminal device determines the information bits corresponding to the first symbol sequence based on the length of the information bit sequence.

[0165] Wherein, if the length of the information bit sequence is less than the threshold value, the information bits corresponding to the first symbol sequence include the information bits corresponding to the second symbol sequence, and the aggregation level of the first symbol sequence is higher than the aggregation level of the second symbol sequence;

[0166] S306, the terminal device decodes the first symbol sequence based on the information bits.

[0167] The specific decoding process will be described below in conjunction with the encoding process of the first encoded bit sequence.

[0168] This application enables PDCCH to support self-decoding, making the encoding structure (i.e., information bits / freeze bits) of some bits in PDCCH with a high aggregation level (e.g., AL=4 / 8 / 16) the same as the encoding structure (i.e., information bits / freeze bits) of PDCCH with a low aggregation level (e.g., AL=2 / 4 / 8). Thus, even if the PDCCH has a high aggregation level, the receiver can decode a small number of CCEs to obtain data without having to decode other CCEs, thereby achieving blind detection and early stopping, and reducing receiver complexity.

[0169] In one possible embodiment, the CCE mapped to some bits in the first coded bit sequence is the same as the CCE mapped to the second coded bit sequence. For example, taking the aggregation level of the first coded bit sequence as 8 and the aggregation level of the second coded bit sequence as 4, assuming the first coded bit sequence is mapped to CCEs #0 to #7 and the second coded bit sequence is mapped to CCEs #0 to #3, in this application, some bits in the first coded bit sequence that have the same encoding structure as the second coded bit sequence (i.e., the same information bits) can be mapped to CCEs #0 to #3. The following will describe two implementation methods of this embodiment in conjunction with the generation process of the first coded bit sequence.

[0170] The generation / encoding process of the first encoded bit sequence will be introduced below.

[0171] As shown in Figure 5, the process of generating the first encoded bit sequence may include:

[0172] S501, determine the mother code length N of PDCCH.

[0173] In one implementation, the parameter n can be determined first using the following pseudocode, and then based on N=2 n The length N of the mother code of PDCCH is obtained as follows:

[0174] Based on the pseudocode above, in one example, the mother code length of PDCCH is... n max It is a positive integer, for example, n max = 9th grade.

[0175] In another implementation, the parameter n1 can be determined first based on the length E of the first encoded bit sequence, and then the following pseudocode can be used to determine the parameter n1 based on N=2. n The length N of the mother code of PDCCH is obtained as follows: R min =1 / 8; n = max{min{n1, n2, n...} max}, n min};

[0176] Compared to the previous implementation, this method improves the performance and stability of Polar code construction.

[0177] S502, determine the rate matching method for the first encoded bit sequence.

[0178] In one possible implementation, if E>N, the rate matching method is repetition; if E≤N, when K / E≤7 / 16, punching is used, and when K / E>7 / 16, shortening is used.

[0179] For example, the rate matching method for the first encoded bit sequence can be repetition or punching.

[0180] S503, confirm information bits / freeze bits.

[0181] For specific details, please refer to the relevant description in S301.

[0182] S504, map the information bit sequence to information bits, and perform Polar code encoding to obtain an N-length encoded bit vector d0, d1, d2, ..., d N-1 .

[0183] S505, for d0, d1, d2, ..., d N-1 Sub-block interleaving is performed to obtain an N-length coded bit vector y0, y1, y2, ..., y N-1 .

[0184] It should be noted that S505 is an optional step.

[0185] S506, for an N-length encoded bit vector (which can be d0, d1, d2, ..., d... N-1 It can also be y0, y1, y2, ..., y N-1 Bit selection is performed, and the first encoded bit sequence is obtained based on the bit sequence after bit selection.

[0186] Optionally, the starting point for selecting the bits corresponding to the first encoded bit sequence in S506 above is related to the aggregation level, code rate, rate matching method, etc.

[0187] The starting point of bit selection corresponding to the first encoded bit sequence can refer to the position of the first bit selected in the N-length encoded bit vector, or it can be understood as the position of the first bit of the first encoded bit sequence in the N-length encoded bit vector.

[0188] In one possible implementation, to ensure that the CCE of the portion of bits in the first coded bit sequence that has the same encoding construction as the second coded bit sequence is the same as the CCE of the portion of bits mapped in the second coded bit sequence, the starting point of the bit selection corresponding to the first coded bit sequence can be modified. For example, the starting point of the bit selection corresponding to the first coded bit sequence can be related to the aggregation level, code rate, rate matching method, etc.

[0189] For example, the first coded bit sequence can satisfy the following formula, or the first coded bit sequence can be determined by the following formula:

[0190] Among them, e k Let k be the bit numbered k in the first coded bit sequence, where e0 is the first bit of the first coded bit sequence, which is the starting point for bit selection corresponding to the first coded bit sequence. For example, the length of the first bit sequence is determined based on the length of the first coded bit sequence; or, the length of the first bit sequence is 432 / 216 / 108; or, the length of the first bit sequence is the length of the second coded bit sequence.

[0191] Optionally, if the length of the information bit sequence is greater than the threshold value, the first encoded bit sequence can satisfy the following formula: e k =d k+N-E .

[0192] 7. The above method can be implemented using the following pseudocode:

[0193] Bit selection section:

[0194] In another possible implementation, to ensure that the CCE of the bits mapped to the portion of the first coded bit sequence that has the same coding construction as the second coded bit sequence is the same as the CCE mapped to the second coded bit sequence, interleaving can be performed after bit selection in S506. For example, suppose that after bit selection in S506, coded bit sequence 1 is obtained, and the first coded bit sequence is obtained by interleaving coded bit sequence 1.

[0195] In this method, bit selection can be implemented using the following pseudocode:

[0196] For example, the first M bits in the first encoded bit sequence are the same as the last M bits in encoded bit sequence 1, where M is the length of the second encoded bit sequence.

[0197] In one specific implementation, the encoded bit sequence 1 can be cyclically shifted forward according to the starting point of PDCCH (or encoded bit sequence) when AL=2, so that the first M bits in the first encoded bit sequence are the same as the bit sequence of PDCCH when AL=2.

[0198] For example, the encoded bit sequence 1 can be divided into several sub-blocks according to the length of the PDCCH (or encoded bit sequence) when AL=4. For instance, if the AL of encoded bit sequence 1 is 8, then encoded bit sequence 1 can be divided into 2 sub-blocks. If the AL of encoded bit sequence 1 is 16, then encoded bit sequence 1 can be divided into 4 sub-blocks. When interleaving the encoded bit sequence 1 into sub-blocks, the last sub-block can be interleaved to the first position in the sequence. For example, assuming the AL of encoded bit sequence 1 is 8, then encoded bit sequence 1 can be divided into 2 sub-blocks, namely sub-block 0 and sub-block 1. After interleaving, sub-block 1 is located before sub-block 0, as shown in Figure 6. Assuming the AL of encoded bit sequence 1 is 16, then encoded bit sequence 1 can be divided into 4 sub-blocks, namely sub-blocks 0 to 3. After interleaving, sub-block 3 is located before sub-blocks 0, 1, and 2, as shown in Figure 7.

[0199] Another example is that the encoded bit sequence 1 can be interleaved in reverse order. For example, the encoded bit sequence 1 can be divided into R sub-blocks, which are sub-blocks 0 to R-1 in sequence. After interleaving, the order of the sub-blocks is sub-block R-1, sub-block R-2, ..., sub-block 0.

[0200] The above describes the generation process of the first encoded bit sequence. The following describes the decoding process of the first symbol sequence in conjunction with the generation process of the first encoded bit sequence.

[0201] The decoding process of the first symbol sequence may include:

[0202] A1, confirm information bits / freeze bits.

[0203] The terminal device determines the information bit and the freeze bit in the same way as the network device. For details, please refer to the relevant description in S301 above. It will not be repeated here.

[0204] A2 performs the inverse process of S506 on the symbol sequence of length E to obtain the third symbol sequence of length N.

[0205] For example, the E-length symbol sequence is actually the bit sequence after bit selection. Therefore, the bit sequence before bit selection can be derived from the E-length symbol sequence by using the bit selection method in S506. As another example, the E-length symbol sequence is actually the bit sequence after interleaving. Therefore, the bit sequence before sub-block interleaving can be derived from the E-length symbol sequence by using the sub-block interleaving method in S506.

[0206] A3 decodes the third symbol sequence based on the information bits and the freeze bits to recover the original bit sequence.

[0207] For example, calculate the log likelihood ratio (LLR) of each bit in the third symbol sequence. For information bits, if LLR > 0, the bit is determined to be 0; if LLR < 0, the bit is determined to be 1. For frozen bits, the bit can be set to 0 regardless of the LLR value.

[0208] A4, retrieve the information bit sequence from the information bits.

[0209] This application enables the encoding structure (i.e., information bits / freeze bits) of PDCCH with a higher aggregation level (e.g., AL=4 / 8 / 16) to include the encoding structure (i.e., information bits / freeze bits) of PDCCH with a lower aggregation level (e.g., AL=2 / 4 / 8). Thus, even if the aggregation level of PDCCH is high, the receiver can decode a small number of CCEs to obtain data without having to decode other CCEs, thereby achieving blind detection and early stopping, and reducing receiver complexity.

[0210] Furthermore, by modifying the starting point of bit selection corresponding to the first coded bit sequence or by interleaving after bit selection, the CCE mapped by the part of the first coded bit sequence that has the same coding construction as the second coded bit sequence can be the same as the CCE mapped by the second coded bit sequence. Thus, the receiver can decode a small number of CCEs to obtain data, which further facilitates the implementation of blind detection and early stopping, and reduces the complexity of the receiver.

[0211] Based on the same inventive concept as the method embodiment, this application provides a communication device, the structure of which can be as shown in FIG8, including a communication unit 801 and a processing unit 802.

[0212] In one embodiment, the communication device can specifically be used to implement the method executed by the network device in the embodiment of FIG3. The device can be the network device itself, or a chip or chipset within the network device, or a part of the chip used to execute the relevant method function. Specifically, the processing unit 802 is configured to determine the information bit corresponding to the first coded bit sequence based on the length of the information bit sequence; if the length of the information bit sequence is less than or equal to a threshold value, the information bit corresponding to the first coded bit sequence includes the information bit corresponding to the second coded bit sequence; the aggregation level of the first coded bit sequence is higher than the aggregation level of the second coded bit sequence; and the first coded bit sequence is carried on a PDCCH; and to map the information bit sequence to the information bit corresponding to the first coded bit sequence; and to generate the first coded bit sequence based on the bit sequence mapped from the information bit sequence; the communication unit 801 is configured to transmit the first coded bit sequence.

[0213] Optionally, when generating the first encoded bit sequence based on the bit sequence mapped to the information bits, the processing unit 802 is specifically configured to: perform bit selection on the bit sequence mapped to the information bits; and generate the first encoded bit sequence based on the bit sequence obtained after bit selection.

[0214] In one embodiment, the communication device can specifically be used to implement the method executed by the terminal device in the embodiment of FIG3. The device can be the terminal device itself, or a chip or chipset within the terminal device, or a part of the chip used to execute the relevant method function. Specifically, the communication unit 801 is used to receive a first symbol sequence, the first symbol sequence being carried on a PDCCH; the processing unit 802 is used to determine the information bits corresponding to the first symbol sequence based on the length of the information bit sequence; if the length of the information bit sequence is less than or equal to a threshold value, the information bits corresponding to the first symbol sequence include the information bits corresponding to a second symbol sequence, and the aggregation level of the first symbol sequence is higher than the aggregation level of the second symbol sequence; and to decode the first symbol sequence based on the information bits.

[0215] Optionally, the processing unit 802, when decoding the first symbol sequence according to the information bits, is specifically configured to: recover the first symbol sequence according to the bit selection method corresponding to the first symbol sequence to obtain a third symbol sequence; decode the third symbol sequence according to the information bits; and obtain the information bit sequence from the decoded bit sequence.

[0216] The module division in this application embodiment is illustrative and represents only one logical functional division. In actual implementation, other division methods may be used. Furthermore, the functional modules in the various embodiments of this application can be integrated into a single processor, exist as separate physical entities, or be integrated into a single module. The integrated modules described above can be implemented in hardware or as software functional modules. It is understood that the functions or implementations of the modules in the embodiments of this application can be further described in the relevant descriptions of the method embodiments.

[0217] In one possible embodiment, the communication device can be as shown in FIG9. This device can be a communication equipment or a chip within a communication equipment, wherein the communication equipment can be the terminal device or the network device described in the above embodiments. The device includes a processor 901 and a communication interface 902, and may also include a memory 903. The processing unit 802 can be the processor 901. The communication unit 801 can be the communication interface 902. Optionally, the processor 901 and the memory 903 can also be integrated together.

[0218] The processor 901 can be a CPU, a digital processing unit, or something similar. The communication interface 902 can be a transceiver, an interface circuit such as a transceiver circuit, or a transceiver chip, etc. The device also includes a memory 903 for storing the program executed by the processor 901. The memory 903 can be non-volatile memory, such as a hard disk drive (HDD) or a solid-state drive (SSD), or it can be volatile memory, such as random-access memory (RAM). The memory 903 can be any other medium capable of carrying or storing desired program code in the form of instructions or data structures that can be accessed by a computer, but is not limited to this.

[0219] The processor 901 is used to execute the program code stored in the memory 903, specifically to perform the actions of the processing unit 802 described above, which will not be described in detail here. The communication interface 902 is specifically used to perform the actions of the communication unit 801 described above, which will not be described in detail here.

[0220] This application embodiment does not limit the specific connection medium between the communication interface 902, processor 901, and memory 903. In this application embodiment, the memory 903, processor 901, and communication interface 902 are connected via a bus 904 in Figure 9. The bus is represented by a thick line in Figure 9. The connection methods between other components are only for illustrative purposes and are not intended to be limiting. Buses can be divided into address buses, data buses, control buses, etc. For ease of illustration, only one thick line is used in Figure 9, but this does not mean that there is only one bus or one type of bus.

[0221] This application also provides a computer-readable storage medium for storing computer software instructions required to execute the processor, including a program required to execute the processor.

[0222] This application also provides a communication system, including a communication device for implementing the terminal device function in the embodiment of FIG3 and a communication device for implementing the network device function in the embodiment of FIG3.

[0223] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0224] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in one or more blocks of the flowchart illustrations and / or one or more blocks of the block diagrams.

[0225] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means that implement the functions specified in one or more flowcharts and / or one or more block diagrams.

[0226] These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process, such that the instructions, which execute on the computer or other programmable apparatus, provide steps for implementing the functions specified in one or more flowcharts and / or one or more block diagrams.

Claims

1. A communication method, characterized in that, The method includes: The information bits corresponding to the first encoded bit sequence are determined based on the length of the information bit sequence. If the length of the information bit sequence is less than or equal to a threshold value, the information bits corresponding to the first encoded bit sequence include the information bits corresponding to the second encoded bit sequence. The aggregation level of the first encoded bit sequence is higher than that of the second encoded bit sequence. The first encoded bit sequence is carried on the physical downlink control channel PDCCH. Map the information bit sequence to the information bits corresponding to the first encoded bit sequence; The first encoded bit sequence is generated based on the bit sequence that maps the information bit sequence; Send the first encoded bit sequence.

2. The method as described in claim 1, characterized in that, The information bits corresponding to the first encoded bit sequence include: The first set of information bits, the second set of information bits, and the third set of information bits; The first information bit set is composed of the same information bits in the fourth information bit set and the fifth information bit set; The second information bit set is composed of information bits that are different from those in the fourth information bit set and the fifth information bit set; The third information bit set is composed of information bits that are different from those in the fourth information bit set and the fifth information bit set in the fifth information bit set; The fourth information bit set consists of the bits corresponding to the H most reliable sub-channels out of the E sub-channels, and the fifth information bit set consists of the bits corresponding to the H most reliable sub-channels out of the E / 2 sub-channels. The second information bit set and the third information bit set are used to carry the same first information bit, and the first information bit set is used to carry information bits in the information bit sequence other than the first information bit; E is the length of the first encoded bit sequence, and H is an integer greater than 0.

3. The method as described in claim 2, characterized in that, The information bits corresponding to the second encoded bit sequence are composed of the first set of information bits and the third set of information bits.

4. The method according to any one of claims 1-3, characterized in that, If the length of the information bit sequence is greater than the threshold value, the information bits corresponding to the first encoded bit sequence include the bits corresponding to the H sub-channels with the highest reliability among the E sub-channels, where E is the length of the first encoded bit sequence and H is an integer greater than 0.

5. The method according to any one of claims 1-4, characterized in that, The aggregation level of the first coded bit sequence is 4, and the threshold value is 70; or, The aggregation level of the first coded bit sequence is greater than or equal to 8, and the threshold value is 140; or, The aggregation level of the first coded bit sequence is 4, and the threshold value is 94; or, The aggregation level of the first encoded bit sequence is greater than or equal to 8, and the threshold value is 164.

6. The method according to any one of claims 1-4, characterized in that, The threshold value is related to at least one of the following: the aggregation level of the first encoded bit sequence, the size of the CCE in the PDCCH, the switching threshold of the rate matching mode, and the length of the CRC bit sequence of the first encoded bit sequence.

7. The method according to any one of claims 1-4, characterized in that, The threshold value satisfies the following formula: Th = floor(AL / 2 × CCE) size ×R-CRC size ); Wherein, Th is the threshold value, AL is the aggregation level of the first encoded bit sequence, and CCE is... size The size of CCE in the PDCCH, the CRC size R is the CRC size of the first encoded bit sequence, R is the rate matching mode switching threshold, and floor() is the floor function; or, the threshold value satisfies the following formula: Th=floor(AL / 2×CCE size ×R); Where Th is the threshold value, AL is the aggregation level of the first encoded bit sequence, and CCE is the threshold value. size R is the size of CCE in the PDCCH, R is the rate matching mode switching threshold, and floor() is the floor function.

8. The method according to any one of claims 1-7, characterized in that, The control channel element (CCE) mapped by a portion of the bits in the first coded bit sequence is the same as the CCE mapped by the second coded bit sequence, and the information bits corresponding to the portion of the bits are the same as the information bits corresponding to the second coded bit sequence.

9. The method as described in claim 8, characterized in that, The starting point for bit selection corresponding to the first encoded bit sequence is related to at least one of the following parameters: the aggregation level of the first encoded bit sequence, the bit rate of the first encoded bit sequence, and the rate matching method of the first encoded bit sequence.

10. The method according to any one of claims 1-9, characterized in that, The first encoded bit sequence satisfies the following formula: Among them, e k Let k be the bit numbered k in the first encoded bit sequence, E be the length of the first encoded bit sequence, N be the mother code length of the PDCCH, and d be the bit numbered k in the first encoded bit sequence. n The bit numbered n in the third encoded bit sequence is the bit sequence obtained by encoding the information bit sequence.

11. The method as described in claim 8, characterized in that, The first coded bit sequence is obtained by interleaving the fourth coded bit sequence, which is a bit sequence obtained by encoding and bit selection of the information bit sequence.

12. The method as described in claim 11, characterized in that, The first M bits of the first encoded bit sequence are the same as the last M bits of the fourth encoded bit sequence, where M is the length of the second encoded bit sequence.

13. The method according to any one of claims 1-12, characterized in that, The rate matching method for the first encoded bit sequence is either repetition or punching.

14. The method according to any one of claims 1-13, characterized in that, The step of generating the first encoded bit sequence based on the bit sequence mapped to the information bit sequence includes: The bit sequence that maps the information bit sequence is encoded to obtain the encoded bit sequence; Bit selection is performed on the encoded bit sequence; The first encoded bit sequence is generated based on the bit sequence obtained after bit selection.

15. The method according to any one of claims 1-14, characterized in that, The aggregation level of the second encoded bit sequence is 4 or 2.

16. A communication method, characterized in that, The method includes: Receive a first symbol sequence, the first symbol sequence being carried in the physical downlink control channel (PDCCH); The information bits corresponding to the first symbol sequence are determined based on the length of the information bit sequence. If the length of the information bit sequence is less than or equal to a threshold value, the information bits corresponding to the first symbol sequence include the information bits corresponding to the second symbol sequence. The aggregation level of the first symbol sequence is higher than the aggregation level of the second symbol sequence. The first symbol sequence is decoded based on the information bits.

17. The method as described in claim 16, characterized in that, The information bits corresponding to the first symbol sequence include: The first set of information bits, the second set of information bits, and the third set of information bits; The first information bit set is composed of the same information bits in the fourth information bit set and the fifth information bit set; The second information bit set is composed of information bits that are different from those in the fourth information bit set and the fifth information bit set; The third information bit set is composed of information bits that are different from those in the fourth information bit set and the fifth information bit set in the fifth information bit set; The fourth information bit set consists of the bits corresponding to the H sub-channels with the highest reliability among the E sub-channels, and the fifth information bit set consists of the bits corresponding to the H sub-channels with the highest reliability among the E / 2 sub-channels. The second information bit set and the third information bit set are used to carry the same first information bit, and the first information bit set is used to carry information bits in the information bit sequence other than the first information bit; E is the length of the first encoded bit sequence, and H is an integer greater than 0.

18. The method as described in claim 17, characterized in that, The information bits corresponding to the second symbol sequence are composed of the first set of information bits and the third set of information bits.

19. The method according to any one of claims 16-18, characterized in that, If the length of the information bit sequence is greater than the threshold value, the information bits corresponding to the first symbol sequence include the bits corresponding to the first H sub-channels in the E sub-channels sorted by reliability, where E is the length of the first encoded bit sequence and H is an integer greater than 0.

20. The method according to any one of claims 16-19, characterized in that, The aggregation level of the first symbol sequence is 4, and the threshold value is 70; or, The aggregation level of the first symbol sequence is greater than or equal to 8, and the threshold value is 140; or, The aggregation level of the first coded bit sequence is 4, and the threshold value is 94; or, The aggregation level of the first encoded bit sequence is greater than or equal to 8, and the threshold value is 164.

21. The method according to any one of claims 16-20, characterized in that, The threshold value is related to at least one of the following: the aggregation level of the first symbol sequence, the size of the CCE in the PDCCH, the switching threshold of the rate matching mode, and the length of the cyclic redundancy check (CRC) bit sequence of the first symbol sequence.

22. The method according to any one of claims 16-20, characterized in that, The threshold value satisfies the following formula: Th = floor(AL / 2 × CCE) size ×R-CRC size ); Where Th is the threshold value, AL is the aggregation level of the first symbol sequence, and CCE is... size The size of CCE in the PDCCH, the CRC size Where R is the length of the CRC bit sequence of the first symbol sequence, R is the rate matching mode switching threshold, and floor() is the floor function; or, the threshold value satisfies the following formula: Th=floor(AL / 2×CCE size ×R); Where Th is the threshold value, AL is the aggregation level of the first encoded bit sequence, and CCE is the threshold value. size R is the size of CCE in the PDCCH, R is the rate matching mode switching threshold, and floor() is the floor function.

23. The method according to any one of claims 16-22, characterized in that, The control channel element (CCE) mapped by a portion of the bits in the first symbol sequence is the same as the CCE mapped by the second symbol sequence, and the information bits corresponding to the portion of the bits are the same as the information bits corresponding to the second symbol sequence.

24. The method as described in claim 23, characterized in that, The starting point for bit selection corresponding to the first symbol sequence is related to at least one of the following parameters: the aggregation level of the first symbol sequence, the code rate of the first symbol sequence, and the rate matching method of the first symbol sequence.

25. The method according to any one of claims 16-24, characterized in that, The encoded bit sequence corresponding to the first symbol sequence satisfies the following formula: Among them, e k The bit numbered k in the encoded bit sequence corresponding to the first symbol sequence, E is the length of the first symbol sequence, N is the mother code length of the PDCCH, and d n The bit numbered n in the third encoded bit sequence is the bit sequence obtained by encoding the information bit sequence.

26. The method as described in claim 25, characterized in that, The encoded bit sequence corresponding to the first symbol sequence is obtained by interleaving the fourth encoded bit sequence, which is a bit sequence obtained by encoding and bit selection of the information bit sequence.

27. The method as described in claim 26, characterized in that, The first M bits of the encoded bit sequence corresponding to the first symbol sequence are the same as the last M bits of the fourth encoded bit sequence, where M is the length of the second symbol sequence.

28. The method according to any one of claims 16-27, characterized in that, The rate matching method for the first symbol sequence is either repetition or punching.

29. The method according to any one of claims 16-28, characterized in that, Decoding the first symbol sequence based on the information bits includes: The first symbol sequence is recovered according to the bit selection method corresponding to the first symbol sequence to obtain the third symbol sequence; The third symbol sequence is decoded based on the information bits; Extract the information bit sequence from the decoded bit sequence.

30. The method according to any one of claims 16-29, characterized in that, The aggregation level of the second encoded bit sequence is 4 or 2.

31. A communication device, characterized in that, It includes a processor and a memory, the memory being used to store program instructions, the processor executing the program instructions causing the method as claimed in any one of claims 1-15 to be executed, or the method as claimed in any one of claims 16-30 to be executed.

32. A computer-readable storage medium, characterized in that, The computer storage medium stores computer-readable instructions that, when executed on a communication device, cause the method described in any one of claims 1-15 to be performed, or the method described in any one of claims 16-30 to be performed.

33. A computer program product, characterized in that, When the computer program product is run on the device, the device causes the device to perform the method according to any one of claims 1-15 or the method according to any one of claims 16-30.

34. A communication device, characterized in that, It includes a module for performing the method as described in any one of claims 1-15, or includes a module for performing the method as described in any one of claims 16-30.

35. A communication device, characterized in that, The device includes a processor and an interface circuit. The interface circuit is used to receive signals from other communication devices outside the communication device and transmit them to the processor, or to send signals from the processor to other communication devices outside the communication device. The processor is used to implement the method as described in any one of claims 1-15 through logic circuits or execution code instructions; or to implement the method as described in any one of claims 16-30.

36. A communication system, characterized in that, It includes a communication device for implementing the method as claimed in any one of claims 1-15, and a communication device for implementing the method as claimed in any one of claims 16-30.

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