Display substrate and display apparatus

Abstract

A display substrate (910), comprising a base (10) and a gate drive circuit arranged on the base (10). The gate drive circuit comprises a plurality of cascaded shift register circuits (GOA). Each shift register circuit (GOA) comprises a plurality of oxide transistors. The plurality of oxide transistors comprise a first group of oxide transistors and a second group of oxide transistors, each group of oxide transistors comprising at least one oxide transistor. A bottom gate and a top gate of each oxide transistor in the first group of oxide transistors are connected to each other, and a bottom gate and a top gate of at least one oxide transistor in the first group of oxide transistors are configured to receive a clock signal; and a bottom gate and a top gate of each oxide transistor in the second group of oxide transistors are independent of each other.

Description

Display substrate and display device

[0001] This application claims priority to Chinese Patent Application No. 202410544894.4, filed on April 30, 2024, entitled "Shift Register Unit and Driving Method Thereof, Gate Driving Circuit, Display Device", the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a display device. Background Technology

[0003] With the advancement of display technology, gate driving circuits are typically mounted on the display substrate using array substrate row driving technology to facilitate narrow bezel designs. The gate driving circuit is connected to multiple rows of pixels on the display substrate and is used to transmit gate driving signals to the pixels row by row to light up the pixels one by one, thus realizing row-by-row scanning and refreshing, enabling the display substrate to display images.

[0004] Summary of the Invention

[0005] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0006] This embodiment provides a display substrate and a display device.

[0007] On one hand, this embodiment provides a display substrate, including: a substrate and a gate driving circuit disposed on the substrate. The gate driving circuit includes a plurality of cascaded shift register circuits. The shift register circuit includes: a first group of oxide transistors and a second group of oxide transistors, each group of oxide transistors including at least one oxide transistor. The bottom gate and top gate of each oxide transistor in the first group of oxide transistors are connected, and the bottom gate and top gate of at least one oxide transistor in the first group of oxide transistors are configured to receive a clock signal. The bottom gate and top gate of each oxide transistor in the second group of oxide transistors are independent of each other.

[0008] In some exemplary embodiments, the second group of oxide transistors includes a plurality of oxide transistors, wherein the bottom gate of the plurality of oxide transistors in the second group of oxide transistors is connected to the same voltage line.

[0009] In some exemplary embodiments, the second set of oxide transistors includes an oxide output transistor and a plurality of oxide switching transistors; the oxide output transistor is directly connected to the output terminal of the shift register circuit. The bottom gate of the oxide output transistor is independently configured from the bottom gate of the plurality of oxide switching transistors. The bottom gate of at least a portion of the plurality of oxide switching transistors is connected to the same voltage line.

[0010] In some exemplary embodiments, the plurality of oxide switching transistors within the second group of oxide transistors are divided into a first group of oxide switching transistors and a second group of oxide switching transistors, each group of oxide switching transistors including at least one oxide switching transistor; within one frame duration, the duty cycle of the first potential of the top-gate voltage signal of the oxide switching transistor in the first group of oxide switching transistors is greater than the duty cycle of the first potential of the top-gate voltage signal of the oxide switching transistor in the second group of oxide switching transistors. The bottom gate of at least one oxide switching transistor in the first group of oxide switching transistors is connected to a first voltage line; the bottom gate of at least one oxide switching transistor in the second group of oxide switching transistors is connected to a second voltage line; the first voltage line and the second voltage line are configured to provide different voltage signals.

[0011] In some exemplary embodiments, each group of oxide switching transistors includes a plurality of oxide switching transistors; at least some of the oxide switching transistors in the first group of oxide switching transistors have an integral bottom gate structure, and the plurality of oxide switching transistors in the second group of oxide switching transistors have an integral bottom gate structure.

[0012] In some exemplary embodiments, in a direction perpendicular to the display substrate, the display substrate includes: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer disposed on the substrate. The top gates of the plurality of oxide transistors are located on the third conductive layer, the active layers of the plurality of oxide transistors are located on the second semiconductor layer, and the bottom gates of the plurality of oxide transistors are located on the second conductive layer.

[0013] In some exemplary embodiments, the shift register circuit includes: an input shift circuit, a transmission control circuit, and a drive enhancement circuit. The input shift circuit is connected to a first clock terminal, a second clock terminal, a third clock terminal, a fourth clock terminal, the input terminal of the shift register circuit, a reset control terminal, a first intermediate node, and a second intermediate node, respectively, and is configured to control the potentials of the first intermediate node and the second intermediate node under the control of the first clock terminal, the second clock terminal, the third clock terminal, the fourth clock terminal, the input terminal, and the reset control terminal. The transmission control circuit is connected to the first intermediate node, the second intermediate node, an enable control terminal, and the drive enhancement circuit, respectively, and is configured to provide an output signal to the drive enhancement circuit under the control of the first intermediate node, the second intermediate node, and the enable control terminal. The drive enhancement circuit is connected between the transmission control circuit and the output terminal of the shift register circuit, and is configured to invert the output signal provided by the transmission control circuit at least once before outputting it to the output terminal of the shift register circuit. The input shifting circuit, the transmission control circuit, and the drive enhancement circuit are arranged sequentially along the first direction in the orthogonal projection of the substrate.

[0014] In some exemplary embodiments, the input shift circuit includes: a first NOR gate, a first NOT gate, a first transmission gate, and a second transmission gate. The first transmission gate is connected to the first clock terminal, the second clock terminal, the input terminal of the shift register circuit, and the input node, and is configured to control the on / off state of the input terminal and the input node under the control of the first clock terminal and the second clock terminal. The second transmission gate is connected to the third clock terminal, the fourth clock terminal, the input node, and the second intermediate node, and is configured to control the on / off state of the input node and the second intermediate node under the control of the third clock terminal and the fourth clock terminal. The first NOR gate is connected to the input node, the reset control terminal, and the first intermediate node, and is configured to control the potential of the first intermediate node under the control of the input node and the reset control terminal. The first NOT gate is connected between the first intermediate node and the second intermediate node. The first transmission gate circuit, the second transmission gate circuit, and the first NOT gate circuit are arranged sequentially along the second direction in the orthogonal projection of the substrate, and are located between the first NOR gate circuit and the transmission control circuit in the orthogonal projection of the substrate in the first direction; the second direction intersects the first direction.

[0015] In some exemplary embodiments, the first transmission gate circuit includes: a first P-type transistor and a first N-type transistor; the gate of the first P-type transistor is connected to the second clock terminal; the top gate and bottom gate of the first N-type transistor are connected to the first clock terminal; the first terminals of the first P-type transistor and the first N-type transistor are both connected to the input terminal of the shift register circuit, and the second terminals of the first P-type transistor and the first N-type transistor are both connected to the input node. The second transmission gate circuit includes: a fifth P-type transistor and a fifth N-type transistor; the gate of the fifth P-type transistor is connected to the fourth clock terminal; the top gate and bottom gate of the fifth N-type transistor are connected to the third clock terminal; the first terminals of the fifth P-type transistor and the fifth N-type transistor are both connected to the input node, and the second terminals of the fifth P-type transistor and the fifth N-type transistor are both connected to the second intermediate node. The orthographic projections of the first P-type transistor and the first N-type transistor on the substrate are aligned along the first direction; the orthographic projections of the fifth P-type transistor and the fifth N-type transistor on the substrate are aligned along the first direction. The first P-type transistor and the fifth P-type transistor are aligned along the second direction when projected onto the substrate; the first N-type transistor and the fifth N-type transistor are aligned along the second direction when projected onto the substrate.

[0016] In some exemplary embodiments, the transmission control circuit includes a second NOR gate, a third transmission gate, and a capacitor. The third transmission gate is connected to the first intermediate node, the second intermediate node, the enable control terminal, the first input terminal of the second NOR gate, and the capacitor, and is configured to control the switching of the enable control terminal and the first input terminal of the second NOR gate under the control of the first and second intermediate nodes. The second input terminal of the second NOR gate is connected to the second intermediate node, and the output terminal of the second NOR gate is connected to the drive enhancement circuit. The second NOR gate and the third transmission gate are arranged sequentially along the second direction in their orthographic projections onto the substrate, and the orthographic projection of the third transmission gate onto the substrate is located between the orthographic projections of the capacitor and the first NOR gate onto the substrate in the first direction.

[0017] In some exemplary embodiments, the drive enhancement circuit includes: a second NOT gate, a third NOT gate, and a fourth NOT gate connected in series; the orthographic projections of the second NOT gate, the third NOT gate, and the fourth NOT gate on the substrate are arranged sequentially along the first direction. The orthographic projection of the second NOT gate on the substrate is adjacent to the orthographic projection of the capacitor on the substrate in the second direction, and the orthographic projection of the capacitor on the substrate is located between the orthographic projections of the third transmission gate and the third NOT gate on the substrate in the first direction.

[0018] In some exemplary embodiments, the first NOR gate circuit includes: a second P-type transistor, a third P-type transistor, a second N-type transistor, and a third N-type transistor; the gate of the third P-type transistor and the top gate of the third N-type transistor are connected to the reset control terminal; the gate of the second P-type transistor and the top gate of the second N-type transistor are connected to the input node; the first terminal of the third P-type transistor is connected to a first power supply terminal; the second terminal of the third P-type transistor is connected to the first terminal of the second P-type transistor; the second terminals of the second P-type transistor, the second terminals of the second N-type transistor, and the second terminals of the third N-type transistor are connected to the first intermediate node; and the first terminals of the second N-type transistor and the third N-type transistor are connected to a second power supply terminal. The second NOR gate circuit includes: a seventh P-type transistor, an eighth P-type transistor, a seventh N-type transistor, and an eighth N-type transistor; the gate of the eighth P-type transistor and the top gate of the eighth N-type transistor are connected to the third transmission gate circuit; the gate of the seventh P-type transistor and the top gate of the seventh N-type transistor are connected to the second intermediate node; the first terminal of the eighth P-type transistor is connected to the first power supply terminal; the second terminal of the eighth P-type transistor is connected to the first terminal of the seventh P-type transistor; the second terminals of the seventh P-type transistor, the seventh N-type transistor, and the eighth N-type transistor are connected as the output terminal of the second NOR gate circuit; and the first terminals of the seventh N-type transistor and the eighth N-type transistor are both connected to the second power supply terminal. The third transmission gate circuit includes a sixth P-type transistor and a sixth N-type transistor. The gate of the sixth P-type transistor is connected to the second intermediate node, the top gate of the sixth N-type transistor is connected to the first intermediate node, the first terminals of the sixth P-type transistor and the sixth N-type transistor are connected to the enable control terminal, and the second terminals of the sixth P-type transistor and the sixth N-type transistor are connected to the gate of the eighth P-type transistor of the second NOR gate circuit. The first NOT gate circuit includes a fourth P-type transistor and a fourth N-type transistor. The gate of the fourth P-type transistor and the top gate of the fourth N-type transistor are connected to the first intermediate node, the first terminal of the fourth P-type transistor is connected to the first power supply terminal, the second terminals of the fourth P-type transistor and the fourth N-type transistor are connected to the second intermediate node, and the first terminal of the fourth N-type transistor is connected to the second power supply terminal.The second NOT gate circuit includes a ninth P-type transistor and a ninth N-type transistor. The gate of the ninth P-type transistor and the top gate of the ninth N-type transistor are connected to the output terminal of the second NOT gate circuit. The first terminal of the ninth P-type transistor is connected to a first power supply terminal, the first terminal of the ninth N-type transistor is connected to a second power supply terminal, and the second terminals of the ninth P-type transistor and the ninth N-type transistor are connected together as the output terminal of the second NOT gate circuit. The third NOT gate circuit includes a tenth P-type transistor and a tenth N-type transistor. The gate of the tenth P-type transistor and the top gate of the tenth N-type transistor are connected to the output terminal of the second NOT gate circuit. The first terminal of the tenth P-type transistor is connected to a first power supply terminal, the first terminal of the tenth N-type transistor is connected to a second power supply terminal, and the second terminals of the tenth P-type transistor and the tenth N-type transistor are connected together as the output terminal of the third NOT gate circuit. The bottom gates of the second N-type transistor, the seventh N-type transistor, the eighth N-type transistor, and the tenth N-type transistor are connected to a first voltage line. The bottom gates of the third N-type transistor, the fourth N-type transistor, the sixth N-type transistor, and the ninth N-type transistor are connected to the second voltage line; the first voltage line and the second voltage line are configured to provide different voltage signals.

[0019] In some exemplary embodiments, the bottom gates of the second N-type transistor, the seventh N-type transistor, and the eighth N-type transistor of any first-level shift register circuit are integral structures.

[0020] In some exemplary embodiments, the bottom gate of the tenth N-type transistor of the nth-stage shift register circuit is connected to the bottom gates of the second N-type transistor, the seventh N-type transistor, and the eighth N-type transistor of the (n+1)th-stage shift register circuit via a first bottom gate connection line; the first bottom gate connection line is a polygonal line extending along the first direction in the orthographic projection of the nth-stage shift register circuit and the (n+1)th-stage shift register circuit on the orthographic projection of the substrate, where n is a positive integer.

[0021] In some exemplary embodiments, the bottom gates of the third and fourth N-type transistors of any stage of the shift register circuit are integral structures, and these integral structures are connected to the bottom gates of the sixth and ninth N-type transistors of the shift register circuit via a third bottom gate connection line. The third bottom gate connection line, when projected onto the substrate, is a broken line extending along the first direction, and is located between the projected views of the third transmission gate and the second NOR gate of the shift register circuit onto the substrate, and between the projected views of the second transmission gate and the first NOT gate of the shift register circuit onto the substrate.

[0022] In some exemplary embodiments, the third P-type transistor, the second P-type transistor, and the second N-type transistor are arranged in a stepped configuration on the substrate along the second direction, and the second N-type transistor and the third N-type transistor are aligned along the second direction. The third N-type transistor and the fourth N-type transistor are aligned along the first direction; the orthogonal projection of the fourth P-type transistor on the substrate is located on the side of the fourth N-type transistor away from the orthogonal projection of the third N-type transistor on the substrate in the first direction.

[0023] In some exemplary embodiments, the sixth N-type transistor and the sixth P-type transistor are aligned along the first direction when their orthogonal projections onto the substrate are aligned along the first direction. The seventh N-type transistor and the eighth N-type transistor are aligned along the first direction when their orthogonal projections onto the substrate are aligned along the second direction, and the sixth P-type transistor and the eighth N-type transistor are aligned along the second direction when their orthogonal projections onto the substrate are aligned along the second direction. The seventh P-type transistor and the eighth P-type transistor are sequentially arranged along the first direction when their orthogonal projections onto the substrate are aligned along the first direction.

[0024] In some exemplary embodiments, the ninth P-type transistor and the tenth N-type transistor are arranged sequentially along the first direction when projected onto the substrate. The ninth N-type transistor and the ninth P-type transistor are staggered along the second direction when projected onto the substrate. The tenth N-type transistor and the tenth P-type transistor are aligned along the second direction when projected onto the substrate.

[0025] In some exemplary embodiments, the fourth NOT gate circuit includes an eleventh-N type transistor and an eleventh-P type transistor; the gate of the eleventh-P type transistor and the top gate of the eleventh-N type transistor are connected to the output terminal of the third NOT gate circuit; the first terminal of the eleventh-P type transistor is connected to a first power supply terminal; the first terminal of the eleventh-N type transistor is connected to a second power supply terminal; the second terminals of the eleventh-P type transistor and the eleventh-N type transistor are connected to the output terminal of the shift register circuit; the bottom gate of the eleventh-N type transistor is connected to a third voltage line. The orthographic projections of the eleventh-N type transistor and the eleventh-P type transistor on the substrate are aligned along the second direction; the orthographic projections of the eleventh-N type transistor and the eleventh-P type transistor on the substrate are adjacent in the first direction; the orthographic projections of the eleventh-P type transistor and the eleventh-N type transistor on the substrate are adjacent in the first direction.

[0026] In some exemplary embodiments, the first voltage line, the second voltage line, and the third voltage line are located on the same conductive layer; the orthographic projection of the third voltage line onto the substrate is located on the side of the eleventh N-type transistor away from the tenth P-type transistor in the first direction; the orthographic projections of the first voltage line and the second voltage line onto the substrate are located on the side of the input shift circuit away from the transmission control circuit in the first direction.

[0027] On the other hand, this embodiment provides a display device including the display substrate as described above.

[0028] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood.

[0029] Overview of the attached figures

[0030] The accompanying drawings are provided to further understand the technical solutions of this disclosure and constitute a part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0031] Figure 1 is a schematic diagram of a shift register circuit according to at least one embodiment of the present disclosure;

[0032] Figure 2 is a schematic diagram of the gate-level circuit of a shift register circuit according to at least one embodiment of the present disclosure;

[0033] Figure 3 is an equivalent circuit diagram of a shift register circuit according to at least one embodiment of the present disclosure;

[0034] Figure 4 is a timing diagram of the local brush drive of a shift register circuit according to at least one embodiment of the present disclosure;

[0035] Figure 5 is another equivalent circuit diagram of the shift register circuit of at least one embodiment of the present disclosure;

[0036] Figure 6 is another equivalent circuit diagram of a shift register circuit according to at least one embodiment of the present disclosure;

[0037] Figure 7 is a schematic diagram of a gate driving circuit according to at least one embodiment of the present disclosure;

[0038] Figure 8 is a partial cross-sectional schematic diagram of the display area of ​​a display substrate according to at least one embodiment of the present disclosure;

[0039] Figure 9 is a partial top view of a display substrate according to at least one embodiment of the present disclosure;

[0040] Figure 10 is a schematic diagram of the display substrate after the first semiconductor layer is formed in Figure 9;

[0041] Figure 11A is a schematic diagram of the display substrate after the first conductive layer is formed in Figure 9;

[0042] Figure 11B is a schematic diagram of the first conductive layer in Figure 11A;

[0043] Figure 12A is a schematic diagram of the display substrate after the second conductive layer is formed in Figure 9;

[0044] Figure 12B is a schematic diagram of the second conductive layer in Figure 12A;

[0045] Figure 13A is a schematic diagram of the display substrate after the second semiconductor layer is formed in Figure 9;

[0046] Figure 13B is a schematic diagram of the second semiconductor layer in Figure 13A;

[0047] Figure 14A is a schematic diagram of the display substrate after the third conductive layer is formed in Figure 9;

[0048] Figure 14B is a schematic diagram of the third conductive layer in Figure 14A;

[0049] Figures 15A and 15B are schematic diagrams of the display substrate after the fifth insulating layer is formed in Figure 9;

[0050] Figure 16A is a schematic diagram of the display substrate after the fourth conductive layer is formed in Figure 9;

[0051] Figure 16B is a schematic diagram of the fourth conductive layer in Figure 16A;

[0052] Figure 17 is a schematic diagram of a display substrate after the formation of a seventh insulating layer in at least one embodiment of the present disclosure;

[0053] Figure 18A is a schematic diagram of a display substrate after the fifth conductive layer has been formed according to at least one embodiment of the present disclosure;

[0054] Figure 18B is a schematic diagram of the fifth conductive layer in Figure 18A;

[0055] Figure 19 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0056] Detailed Explanation

[0057] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into other forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0058] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shape and size of one or more parts in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0059] The ordinal numbers such as "first," "second," and "third" used in this specification are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0060] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of the constituent elements being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0061] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or joint; a direct connection, an indirect connection via an intermediate component, or a connection within two components. "Joining" includes "electrical connection." "Electrical connection" includes situations where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the term "component having a certain electrical function," as long as it allows for the transmission of electrical signals between the connected constituent elements. Examples of "components having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other multifunctional components. Those skilled in the art will understand the meaning of the above terms in this disclosure as appropriate.

[0062] In this specification, a transistor is a device that includes at least three terminals: a gate (gate electrode), a drain, and a source. A transistor has a channel region between its drain (drain electrode terminal, drain region, or drain electrode) and its source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. The channel region refers to the area through which current primarily flows.

[0063] In this specification, the first terminal can be the drain and the second terminal can be the source, or vice versa. Additionally, the gate can also be called the control terminal. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this specification, the "source" and "drain" can be interchanged.

[0064] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0065] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined. They can be approximate circles, ellipses, triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, such as chamfers, curved edges, and other variations.

[0066] In this specification, "approximately" and "roughly" mean without strictly defined limits, allowing for errors in the process and measurement. In this disclosure, "same" and "roughly the same" mean values ​​that differ by no more than 10%.

[0067] In this specification, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped solid. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In this specification, "A extends along direction B" refers to "the main part of A extends along direction B".

[0068] With the rapid development of OLED display technology, various requirements have been placed on display products, including high resolution, narrow bezels, and low power consumption. Partial refresh technology (for example, displaying a high refresh rate in one area of ​​the screen and a low refresh rate in another) offers significant benefits in reducing power consumption and has therefore attracted considerable attention. In display products employing partial refresh technology, the gate drive circuit structure is relatively complex, and achieving better drive stability is a problem that needs to be solved.

[0069] This embodiment provides a display substrate, including: a substrate and a gate driving circuit disposed on the substrate. The gate driving circuit includes multiple cascaded shift register circuits (also referred to as shift register circuits or shift register units). The shift register circuit includes: a first group of oxide transistors and a second group of oxide transistors, each group of oxide transistors including at least one oxide transistor. The bottom gate and top gate of each oxide transistor in the first group of oxide transistors are connected, and the bottom gate and top gate of at least one oxide transistor in the first group of oxide transistors are configured to receive a clock signal; the bottom gate and top gate of each oxide transistor in the second group of oxide transistors are independent of each other.

[0070] The display substrate provided in this embodiment distinguishes and connects the bottom gates of multiple oxide transistors in the shift register circuit, which can reduce the impact of long-term bias on the threshold voltage of the oxide transistors, thereby improving the driving capability and stability of the shift register circuit.

[0071] In some exemplary embodiments, the second set of oxide transistors may include a plurality of oxide transistors, the bottom gates of which are connected to the same voltage line. The bottom gates of the plurality of oxide transistors in the second set may be configured to receive the same voltage signal. This example interconnects the bottom gates of all oxide transistors in the second set, which not only ensures the driving capability and stability of the shift register circuit but also reduces additional wiring.

[0072] In some exemplary embodiments, the second set of oxide transistors may include an oxide output transistor and a plurality of oxide switching transistors; the oxide output transistor is directly connected to the output terminal of the shift register circuit. The bottom gate of the oxide output transistor is independently configured from the bottom gate of the plurality of oxide switching transistors; the bottom gate of at least some of the plurality of oxide switching transistors is connected to the same voltage line. The bottom gates of at least some of the oxide switching transistors in the second set of oxide transistors may be configured to receive the same voltage signal. This example, by separately controlling the bottom gate of the oxide output transistor and the bottom gate of the plurality of oxide switching transistors in the second set of oxide transistors, allows for independent adjustment of the threshold voltage, which is beneficial for improving the output stability of the shift register circuit.

[0073] In some exemplary embodiments, the plurality of oxide switching transistors within the second group of oxide switching transistors can be divided into a first group of oxide switching transistors and a second group of oxide switching transistors, each group of oxide switching transistors including at least one oxide switching transistor. Within one frame duration, the duty cycle of the first potential of the top-gate voltage signal of the oxide switching transistors in the first group of oxide switching transistors is greater than the duty cycle of the first potential of the top-gate voltage signal of the oxide switching transistors in the second group of oxide switching transistors. Within one frame duration, the duty cycle of the first potential of the top-gate voltage signal of the oxide switching transistors can refer to the ratio of the duration of the first potential of the top-gate voltage signal within one frame duration to the frame duration itself; that is, the proportion of the duration of the first potential of the top-gate voltage signal within one frame duration. For example, the first potential can be a high potential or a low potential; a high potential can be represented by binary "1", and a low potential can be represented by binary "0". The bottom gate of at least one oxide switching transistor in the first group of oxide switching transistors is connected to a first voltage line; the bottom gate of at least one oxide switching transistor in the second group of oxide switching transistors is connected to a second voltage line; the first voltage line and the second voltage line are configured to provide different voltage signals. This example demonstrates how to further precisely adjust the threshold voltage of the oxide switching transistors by further grouping and controlling the bottom gate of the multiple oxide switching transistors within the second group of oxide transistors.

[0074] The following examples illustrate the solution of this embodiment.

[0075] In some examples, the display substrate may include a display area and a non-display area. For example, the non-display area may be a peripheral area located outside the display area. However, this embodiment is not limited to this. For example, the non-display area may be located between adjacent display areas.

[0076] In some examples, the display area may include multiple light-emitting units. A pixel within the display area may include three light-emitting units (also referred to as sub-pixels), which may be red, green, and blue sub-pixels, respectively. However, this embodiment is not limited to this. In some examples, a pixel may include four sub-pixels, which may be red, green, blue, and white sub-pixels, respectively.

[0077] In some examples, a subpixel may include a pixel circuit and a light-emitting element connected to the pixel circuit. The shape of the light-emitting element may be rectangular, rhomboid, pentagonal, or hexagonal. When a pixel includes three subpixels, the light-emitting elements of the three subpixels may be arranged horizontally side-by-side, vertically side-by-side, or in a triangular arrangement; when a pixel includes four subpixels, the light-emitting elements of the four subpixels may be arranged horizontally side-by-side, vertically side-by-side, or in a square arrangement. However, this embodiment is not limited in this respect.

[0078] In some examples, the display area may include at least: a plurality of pixel circuits arranged in an array, a plurality of gate lines extending along a first direction (e.g., scan lines, reset signal lines, and light emission control lines), and a plurality of data lines and power lines extending along a second direction. Multiple rows of pixel circuits may be arranged along the second direction, and each row of pixel circuits may include a plurality of pixel circuits arranged along the first direction. The first and second directions may be located in the same plane, and the first and second directions may intersect; for example, the first direction may be perpendicular to the second direction. For example, the first direction may include a horizontal direction, and the second direction may include a vertical direction.

[0079] In some examples, the pixel circuit can be configured to drive the connected light-emitting element. For example, the pixel circuit can be configured to provide drive current to drive the light-emitting element to emit light. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. In these circuit structures, T refers to a thin-film transistor, C refers to a capacitor, the number before T represents the number of thin-film transistors in the circuit, and the number before C represents the number of capacitors in the circuit.

[0080] In some examples, the pixel circuit may include P-type transistors and N-type transistors. The P-type transistor conducts when the gate is at a low potential and is cut off when the gate is at a high potential; the N-type transistor conducts when the gate is at a high potential and is cut off when the gate is at a low potential. The N-type transistor can be an oxide thin-film transistor, and the P-type transistor can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor. The active layer of the LTPS thin-film transistor is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the oxide thin-film transistor is made of oxide semiconductor. LTPS thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO+Oxide) display substrate allows for the utilization of the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0081] In some examples, the non-display area may include a timing controller, a data driving circuit, and a gate driving circuit. The gate driving circuit may be located on opposite sides of the display area, for example, the left and right sides of the display area (e.g., the left and right border areas included in the peripheral area); the timing controller and data driving circuit may be located on one side of the display area, for example, the lower side of the display area (e.g., the lower border area included in the peripheral area). However, this embodiment is not limited to this. In some examples, the gate driving circuit may be located within the display area.

[0082] In some examples, the data driving circuitry can provide data signals to the sub-pixels of the display area via data lines. The timing controller can provide drive signals to both the data driving circuitry and the gate driving circuitry. The operation of the gate driving circuitry and the data driving circuitry can be controlled by the timing controller. The timing controller can provide the data driving circuitry with grayscale data specifying the grayscale level to be displayed in the sub-pixel. The data driving circuitry can provide a data signal corresponding to the potential of the grayscale data of the sub-pixel to the sub-pixel of the row selected by the gate driving circuitry via data lines.

[0083] In some examples, the display substrate may include multiple gate drive circuits, such as gate drive circuits for providing gate drive signals to P-type transistors in pixel circuits, gate drive circuits for providing gate drive signals to N-type transistors in pixel circuits, etc. Each gate drive circuit may include multiple cascaded shift register circuits. The output of each stage of the shift register circuit may be connected to multiple pixel circuits in a corresponding row of pixel circuits, configured to provide gate drive signals to that row of pixel circuits.

[0084] Figure 1 is a schematic diagram of a shift register circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 1, the shift register circuit provided in this embodiment may include: an input shift circuit 11, a transmission control circuit 12, and a drive enhancement circuit 13.

[0085] In some examples, the input shift circuit 11 can be connected to the first clock terminal CKn, the second clock terminal CB, the third clock terminal CBn, the fourth clock terminal CK, the input terminal IN_n of the shift register circuit, the reset control terminal Trst, the first intermediate node Q1_n, and the second intermediate node Q2_n, and configured to control the potential of the first intermediate node Q1_n (or labeled GNc_n) and the second intermediate node Q2_n (or labeled GPc_n) under the control of the first clock terminal CKn, the second clock terminal CB, the third clock terminal CBn, the fourth clock terminal CK, the input terminal IN_n, and the reset control terminal Trst.

[0086] In some examples, the input shift circuit 11 may include an input control circuit 111, a first control circuit 112, and a latch circuit 113. The input control circuit 111 may be connected to a first clock terminal CKn, a second clock terminal CB, an input terminal IN_n, and an input node Q_n, and is configured to control the on / off state of the input terminal IN_n and the input node Q_n in response to a first clock signal provided by the first clock terminal CKn and a second clock signal provided by the second clock terminal CB. The first control circuit 112 may be connected to a reset control terminal Trst, the input node Q_n, and a first intermediate node Q1_n, and is configured to control the potential of the first intermediate node Q1_n based on the potential of the input node Q_n and a reset signal provided by the reset control terminal Trst. The latch circuit 113 can be connected to the third clock terminal CBn, the fourth clock terminal CK, the input node Q_n, the first intermediate node Q1_n, and the second intermediate node Q2_n. It is configured to control the on / off state of the second intermediate node Q2_n and the input node Q_n in response to the third clock signal provided by the third clock terminal CBn and the fourth clock signal provided by the fourth clock terminal CK, and to transmit the potential of the first intermediate node Q1_n to the input node Q_n after inverting the potential.

[0087] In some examples, the transmission control circuit 12 can be connected to the first intermediate node Q1_n, the second intermediate node Q2_n, the enable control terminal GEN, and the drive enhancement circuit 13, and configured to provide an output signal to the drive enhancement circuit 13 under the control of the first intermediate node Q1_n, the second intermediate node Q2_n, and the enable control terminal GEN.

[0088] In some examples, the transmission control circuit 12 may include a second control circuit 121 and a switching circuit 122. The second control circuit 121 may be connected to the second intermediate node Q2_n, the switching circuit 122, and the drive enhancement circuit 13, and is configured to control the potential of the output signal provided to the drive enhancement circuit 13 based on the potential of the second intermediate node Q2_n and the signal output by the switching circuit 122. The switching circuit 122 is connected between the enable control terminal GEN and the second control circuit 121, and is also connected to the first intermediate node Q1_n and the second intermediate node Q2_n, and is configured to control the on / off state of the enable control terminal GEN and the second control circuit 121 based on the potentials of the first intermediate node Q1_n and the second intermediate node Q2_n.

[0089] In some examples, the drive enhancement circuit 13 is connected between the transmission control circuit 12 and the output terminal OUT_n (or labeled GP_n) of the shift register circuit, and is configured to invert the potential of the output signal provided by the transmission control circuit 12 at least once before outputting it to the output terminal OUT_n of the shift register circuit. The drive enhancement circuit 13 may also be configured to invert the potential of the output signal of the second control circuit 121 at least once (e.g., an odd number of times) before outputting it to the output terminal OUT_n of the shift register circuit.

[0090] Figure 2 is a schematic diagram of the gate-level circuit of a shift register circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 2, the input control circuit 111 may include a first transmission gate circuit (also referred to as a first transmission gate) Tg1. The first transmission gate circuit Tg1 may be connected between the input terminal IN_n and the input node Q_n of the shift register circuit, and may also be connected to the first clock terminal CKn and the second clock terminal CB, respectively.

[0091] In some examples, the first control circuit 112 may include a first NOR gate (also referred to as a first NOR gate) NOR1. The first input terminal of the first NOR gate NOR1 is connected to the reset control terminal Trst, the second input terminal of the first NOR gate NOR1 is connected to the input node Q_n, and the output terminal of the first NOR gate NOR1 is connected to the first intermediate node Q1_n.

[0092] In some examples, the latch circuit 113 may include a second transmission gate (also referred to as a second transmission gate) Tg2 and a first NOT gate (also referred to as a first NOT gate) INV1. The second transmission gate Tg2 and the first NOT gate INV1 are connected in series between the input node Q_n and the first intermediate node Q1_n. The second transmission gate Tg2 can be connected between the input node Q_n and the second intermediate node Q2_n, and can also be connected to the third clock terminal CBn and the fourth clock terminal CK. The input terminal of the first NOT gate INV1 can be connected to the first intermediate node Q1_n, and the output terminal of the first NOT gate INV1 can be connected to the second intermediate node Q2_n.

[0093] In some examples, the second control circuit 121 may include a second NOR gate (also referred to as a second NOR gate) NOR2. The first input of the second NOR gate NOR2 may be connected to the second intermediate node Q2_n, the second input of the second NOR gate NOR2 may be connected to the output of the switching circuit 122, and the output of the second NOR gate NOR2 may be connected to the drive enhancement circuit 13.

[0094] In some examples, the switching circuit 122 may include a third transmission gate circuit (also referred to as a third transmission gate) Tg3. The third transmission gate circuit Tg3 may be connected between the enable control terminal GEN and the second input terminal of the second NOR gate circuit NOR2, and may also be connected to the first intermediate node Q1_n and the second intermediate node Q2_n.

[0095] In some examples, the drive enhancement circuit 13 may include a plurality (e.g., an odd number) of NOT gates connected in series, such as a second NOT gate INV2, a third NOT gate INV3, and a fourth NOT gate INV4. The input of the second NOT gate INV2 is connected to the output of the second NOR gate NOR2, the output of the second NOT gate INV2 is connected to the input of the third NOT gate INV3, the output of the third NOT gate INV3 is connected to the input of the fourth NOT gate INV4, and the output of the fourth NOT gate INV4 is connected to the output OUT_n of the shift register circuit.

[0096] In this example, the logic principle of the NOR gate is: all 0s output 1, and any 1 outputs 0; that is, when the potential of all received signals is low (0), the potential of the output signal can be controlled to be high (1); otherwise, as long as the potential of any received signal is high (1), the potential of the output signal can be controlled to be low (0).

[0097] In this example, the NOT gate can be a complementary metal-oxide-semiconductor (CMOS) transistor formed by a pair of complementary P-type and N-type transistors.

[0098] In this example, the input node Q_n, the first intermediate node Q1_n, and the second intermediate node Q2_n do not represent actual components, but rather the junctions of related electrical connections in the circuit diagram. In other words, these nodes are equivalent to the junctions of related electrical connections in the circuit diagram.

[0099] Figure 3 is an equivalent circuit diagram of a shift register circuit according to at least one embodiment of the present disclosure. Figure 3 can be an equivalent circuit diagram of the nth stage shift register circuit. Here, n can be an integer greater than 0.

[0100] In some examples, as shown in Figure 3, the first transmission gate circuit Tg1 may include a first N-type transistor Tn_1 and a first P-type transistor Tp_1. The gate of the first P-type transistor Tp_1 is connected to the second clock terminal CB, the first terminal of the first P-type transistor Tp_1 is connected to the input terminal IN_n of the shift register circuit, and the second terminal of the first P-type transistor Tp_1 is connected to the input node Q_n. The top and bottom gates of the first N-type transistor Tn_1 are connected, and both are connected to the first clock terminal CKn. The first terminal of the first N-type transistor Tn_1 is connected to the input terminal IN_n of the shift register circuit, and the second terminal of the first N-type transistor Tn_1 is connected to the input node Q_n.

[0101] In some examples, the first NOR gate NOR1 may include: a second N-type transistor Tn_2, a third N-type transistor Tn_3, a second P-type transistor Tp_2, and a third P-type transistor Tp_3. The gate of the third P-type transistor Tp_3 is connected to the reset control terminal Trst, the first terminal of the third P-type transistor Tp_3 is connected to the first power supply terminal VGH1, and the second terminal of the third P-type transistor Tp_3 is connected to the first terminal of the second P-type transistor Tp_2. The gate of the second P-type transistor Tp_2 is connected to the input node Q_n, and the second terminal of the second P-type transistor Tp_2 is connected to the first intermediate node Q1_n. The top gate of the second N-type transistor Tn_2 is connected to the input node Q_n, the first terminal of the second N-type transistor Tn_2 is connected to the second power supply terminal VGL1, and the second terminal of the second N-type transistor Tn_2 is connected to the first intermediate node Q1_n. The top gate of the third N-type transistor Tn_3 is connected to the reset control terminal Trst, the first terminal of the third N-type transistor Tn_3 is connected to the second power supply terminal VGL1, and the second terminal of the third N-type transistor Tn_3 is connected to the first intermediate node Q1_n. The bottom gates of both the second N-type transistor Tn_2 and the third N-type transistor Tn_3 are connected to the fifth voltage line BG5.

[0102] In some examples, the first NOT gate INV1 may include: a fourth N-type transistor Tn_4 and a fourth P-type transistor Tp_4. The gate of the fourth P-type transistor Tp_4 is connected to the first intermediate node Q1_n, the first terminal of the fourth P-type transistor Tp_4 is connected to the first power supply terminal VGH1, and the second terminal of the fourth P-type transistor Tp_4 is connected to the second intermediate node Q2_n. The top gate of the fourth N-type transistor Tn_4 is connected to the first intermediate node Q1_n, the first terminal of the fourth N-type transistor Tn_4 is connected to the second power supply terminal VGL1, and the second terminal of the fourth N-type transistor Tn_4 is connected to the second intermediate node Q2_n. The bottom gate of the fourth N-type transistor Tn_4 is connected to the fifth voltage line BG5.

[0103] In some examples, the second transmission gate circuit Tg2 may include a fifth N-type transistor Tn_5 and a fifth P-type transistor Tp_5. The gate of the fifth P-type transistor Tp_5 is connected to the fourth clock terminal CK, the first terminal of the fifth P-type transistor Tp_5 is connected to the input node Q_n, and the second terminal of the fifth P-type transistor Tp_5 is connected to the second intermediate node Q2_n. The top and bottom gates of the fifth N-type transistor Tn_5 are connected and both are connected to the third clock terminal CBn. The first terminal of the fifth N-type transistor Tn_5 is connected to the input node Q_n, and the second terminal of the fifth N-type transistor Tn_5 is connected to the second intermediate node Q2_n.

[0104] In some examples, the third transmission gate Tg3 may include a sixth N-type transistor Tn_6 and a sixth P-type transistor Tp_6. The gate of the sixth P-type transistor Tp_6 is connected to the second intermediate node Q2_n, the first terminal of the sixth P-type transistor Tp_6 is connected to the enable control terminal GEN, and the second terminal of the sixth P-type transistor Tp_6 is connected to the second terminal of the sixth N-type transistor Tn_6. The top gate of the sixth N-type transistor Tn_6 is connected to the first intermediate node Q1_n, the bottom gate of the sixth N-type transistor Tn_6 is connected to the fifth voltage line BG5, and the first terminal of the sixth N-type transistor Tn_6 is connected to the enable control terminal GEN.

[0105] In some examples, the second NOR gate circuit NOR2 may include: a seventh N-type transistor Tn_7, an eighth N-type transistor Tn_8, a seventh P-type transistor Tp_7, and an eighth P-type transistor Tp_8. The gate of the eighth P-type transistor Tp_8 is connected to the second terminals of the sixth P-type transistor Tp_6 and the sixth N-type transistor Tn_6. The first terminal of the eighth P-type transistor Tp_8 is connected to the first power supply terminal VGH1, and the second terminal of the eighth P-type transistor Tp_8 is connected to the first terminal of the seventh P-type transistor Tp_7. The gate of the seventh P-type transistor Tp_7 is connected to the second intermediate node Q2_n, and the second terminal of the seventh P-type transistor Tp_7 is connected to the second terminal of the seventh N-type transistor Tn_7. The top gate of the seventh N-type transistor Tn_7 is connected to the second intermediate node Q2_n, the bottom gate of the seventh N-type transistor Tn_7 is connected to the fifth voltage line BG5, and the first terminal of the seventh N-type transistor Tn_7 is connected to the second power supply terminal VGL1. The top gate of the eighth N-type transistor Tn_8 is connected to the gate of the eighth P-type transistor Tp_8, the bottom gate of the eighth N-type transistor Tn_8 is connected to the fifth voltage line BG5, the first terminal of the eighth N-type transistor Tn_8 is connected to the second power supply terminal VGL1, and the second terminal of the eighth N-type transistor Tn_8 is connected to the second terminal of the seventh N-type transistor Tn_7 and the second terminal of the seventh P-type transistor Tp_7.

[0106] In some examples, the second NOT gate INV2 may include a ninth N-type transistor Tn_9 and a ninth P-type transistor Tp_9. The gate of the ninth P-type transistor Tp_9 is connected to the second terminals of the seventh P-type transistor Tp_7, the seventh N-type transistor Tn_7, and the eighth N-type transistor Tn_8. The first terminal of the ninth P-type transistor Tp_9 is connected to the first power supply terminal VGH1, and the second terminal of the ninth P-type transistor Tp_9 is connected to the second terminal of the ninth N-type transistor Tn_9. The top gate of the ninth N-type transistor Tn_9 is connected to the gate of the ninth P-type transistor Tp_9, the bottom gate of the ninth N-type transistor Tn_9 is connected to the fifth voltage line BG5, and the first terminal of the ninth N-type transistor Tn_9 is connected to the second power supply terminal VGL1.

[0107] In some examples, the third NOT gate INV3 may include: a tenth N-type transistor Tn_10 and a tenth P-type transistor Tp_10. The gate of the tenth P-type transistor Tp_10 is connected to the second terminals of the ninth P-type transistor Tp_9 and the ninth N-type transistor Tn_9. The first terminal of the tenth P-type transistor Tp_10 is connected to the first power supply terminal VGH1, and the second terminal of the tenth P-type transistor Tp_10 is connected to the second terminal of the tenth N-type transistor Tn_10. The top gate of the tenth N-type transistor Tn_10 is connected to the gate of the tenth P-type transistor Tp_10, the bottom gate of the tenth N-type transistor Tn_10 is connected to the fifth voltage line BG5, and the first terminal of the tenth N-type transistor Tn_10 is connected to the second power supply terminal VGL1.

[0108] In some examples, the fourth NOT gate circuit INV4 may include an eleventh N-type transistor Tn_11 and an eleventh P-type transistor Tp_11. The gate of the eleventh P-type transistor Tp_11 is connected to the second terminal of the tenth P-type transistor Tp_10 and the second terminal of the tenth N-type transistor Tn_10. The first terminal of the eleventh P-type transistor Tp_11 is connected to the first power supply terminal VGH2, and the second terminal of the eleventh P-type transistor Tp_11 is connected to the second terminal of the eleventh N-type transistor Tn_11. The top gate of the eleventh N-type transistor Tn_11 is connected to the gate of the eleventh P-type transistor Tp_11, the bottom gate of the eleventh N-type transistor Tn_11 is connected to the fifth voltage line BG5, and the first terminal of the eleventh N-type transistor Tn_11 is connected to the second power supply terminal VGL2.

[0109] In some examples, the second control circuit 121 may further include a capacitor C. The first electrode of the capacitor C may be connected to the gate of the eighth P-type transistor Tp_8, and the second electrode of the capacitor C may be connected to the second power supply terminal VGL1.

[0110] In some examples, the potential of the first power signal provided by the first power supply terminal (including first power supply terminals VGH1 and VGH2) may be greater than the potential of the second power signal provided by the second power supply terminal (including second power supply terminals VGL1 and VGL2). The first power signal provided by the first power supply terminal VGH1 and the first power signal provided by the first power supply terminal VGH2 may be the same or different; for example, the potential of the first power signal provided by the first power supply terminal VGH2 may be greater than or equal to the potential of the first power signal provided by the first power supply terminal VGH1. The second power signal provided by the second power supply terminal VGL1 and the second power signal provided by the second power supply terminal VGL2 may be the same or different; for example, the potential of the second power signal provided by the second power supply terminal VGL2 may be less than or equal to the potential of the second power signal provided by the second power supply terminal VGL1.

[0111] In some examples, the potential of the second power supply signal received by the fourth NOT gate INV4 is lower than the potential of the second power supply signals received by the third NOT gate INV3 and the second NOT gate INV2. This ensures that the N-type transistor in the fourth NOT gate INV4 can be completely turned off, allowing the shift register circuit to reliably control the output terminal OUT_n to a high potential. Conversely, the potential of the first power supply signal received by the fourth NOT gate INV4 is higher than the potential of the first power supply signals received by the third NOT gate INV3 and the second NOT gate INV2. This ensures that the P-type transistor in the fourth NOT gate INV4 can be completely turned off, allowing the shift register circuit to reliably control the output terminal OUT_n to a low potential. This example can accelerate the charging and discharging speed of the fourth NOT gate INV4, which is directly connected to the output terminal OUT_n of the shift register circuit, thereby further improving the driving capability of the shift register circuit and reducing leakage current, thus saving power consumption.

[0112] In this example, the first N-type transistor Tn_1 through the eleventh N-type transistor Tn_11 are all oxide transistors. The first group of oxide transistors may include: the first N-type transistor Tn_1 and the fifth N-type transistor Tn_5; the second group of oxide transistors may include: the second N-type transistor Tn_2, the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6, the seventh N-type transistor Tn_7, the eighth N-type transistor Tn_8, the ninth N-type transistor Tn_9, the tenth N-type transistor Tn_10, and the eleventh N-type transistor Tn_11.

[0113] In this example, the top gate of the first N-type transistor Tn_1 and the top gate of the fifth N-type transistor Tn_5 are configured to receive the clock signal. No bias voltage is applied to the transistor for a long time, and there is no need to adjust the threshold voltage separately. By connecting the top and bottom gates of the first N-type transistor Tn_1 and the top and bottom gates of the fifth N-type transistor Tn_5, additional wiring can be reduced.

[0114] In this example, the top and bottom gates of the second N-type transistor Tn_2, the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6, the seventh N-type transistor Tn_7, the eighth N-type transistor Tn_8, the ninth N-type transistor Tn_9, the tenth N-type transistor Tn_10, and the eleventh N-type transistor Tn_11 are controlled separately, and the bottom gates of these N-type transistors are all connected to the fifth voltage line BG5 and configured to receive the same voltage signal. This allows adjustment of the threshold voltage of the N-type transistors in the shift register circuit, thereby optimizing the output signal of the shift register circuit.

[0115] Figure 4 is a partial brush drive timing diagram of a shift register circuit according to at least one embodiment of the present disclosure. The partial brush drive timing diagram shown in Figure 4 may include the timing of the high brush region and the low brush region.

[0116] In some examples, the enable control terminal GEN can be connected to either the first enable control line EN1 or the second enable control line EN2. For instance, the enable control terminal GEN connected to the shift register circuit for odd-numbered rows of sub-pixels can be connected to the first enable control line EN1, while the enable control terminal GEN connected to the shift register circuit for even-numbered rows of sub-pixels can be connected to the second enable control line EN2.

[0117] In some examples, four clock terminals (first clock terminal CKn, second clock terminal CB, third clock terminal CBn, and fourth clock terminal CK) can provide four sets of clock signals. The period of the four sets of clock signals can be 2H (1H can be one cycle), and the clock signal provided by clock terminal CK and the clock signal provided by clock terminal CB can differ by 1H. The clock signal provided by clock terminal CKn and the clock signal provided by clock terminal CB can be inverted signals, and the clock signal provided by clock terminal CBn and the clock signal provided by clock terminal CK can be inverted signals. In addition, the pulse width of the low potential 0 of the clock signals provided by clock terminals CK and CB is generally 0 to 2 microseconds (μs) shorter than 1H, and can be selected according to the load resistance RC. The configuration in this example can eliminate the effect of clock delay and avoid the risk of competition between the first NOR gate NOR1 and the first NOT gate INV1 when the input state is switched, which would be caused by the first transmission gate Tg1 and the second transmission gate Tg2 being turned on simultaneously.

[0118] In some examples, in the high refresh rate region, the enable control signal provided by the first enable control line EN1 connecting the shift register circuit of the odd-numbered row sub-pixels can be configured to have the same phase as the clock signal provided by the clock terminal CK; the enable control signal provided by the second enable control line EN2 connecting the shift register circuit of the even-numbered row sub-pixels can have the same phase as the clock signal provided by the clock terminal CB. In other examples, the enable control signals provided by the first enable control line EN1 and the second enable control line EN2 can be interchanged. That is, the enable control signal provided by the first enable control line EN1 connecting the shift register circuit of the odd-numbered row sub-pixels has the same phase as the clock signal provided by the clock terminal CB; the enable control signal provided by the second enable control line EN2 connecting the shift register circuit of the even-numbered row sub-pixels has the same phase as the clock signal provided by the clock terminal CK.

[0119] In some examples, in the low-brush region, the output can be reset by setting the enable control signals provided by the first enable control line EN1 and the second enable control line EN2 to a high potential.

[0120] The timing diagram of the nth stage shift register circuit in this example is described below with reference to Figures 3 and 4.

[0121] In the first stage t01, a high-level first clock signal can be provided to the first clock terminal CKn, and a low-level second clock signal can be provided to the second clock terminal CB, causing the first transmission gate circuit Tg1 to turn on. This enables the input terminal IN_n to conduct with the input node Q_n, allowing the input terminal IN_n (i.e., the second intermediate node Q2_n-1 of the nth stage shift register circuit) to output an input signal to the input node Q_n. At this time, the output input signal can have a high potential. A high-level reset control signal can be provided to the reset control terminal Trst, which, after passing through the first NOR gate circuit NOR1, controls the potential of the first intermediate node Q1_n to be low, and after passing through the first NOT gate circuit INV1, controls the potential of the second intermediate node Q2_n to be high. Because the potential of the first intermediate node Q1_n is low and the potential of the second intermediate node Q2_n is high, the third transmission gate Tg3 can be turned off, and a low-potential signal can be output through the second NOR gate circuit NOR2. This low-potential signal, after passing through the second NOT gate circuit INV2, the third NOT gate circuit INV3, and the fourth NOT gate circuit INV4, can make the potential of the output terminal OUT_n high. Furthermore, in the first stage t01, a low-potential third clock signal can be provided to the third clock terminal CBn, and a high-potential fourth clock signal can be provided to the fourth clock terminal CK, causing the second transmission gate circuit Tg2 to be turned off, thereby disconnecting the second intermediate node Q2_n from the input node Q_n.

[0122] In the second stage t02, a low-level first clock signal can be provided to the first clock terminal CKn, and a high-level second clock signal can be provided to the second clock terminal CB, causing the first transmission gate circuit Tg1 to turn off, thereby disconnecting the input terminal IN_n from the input node Q_n. A high-level third clock signal can be provided to the third clock terminal CBn, and a low-level fourth clock signal can be provided to the fourth clock terminal CK, causing the second transmission gate circuit Tg2 to turn on, thereby turning the second intermediate node Q2_n on with the input node Q_n, thus latching the potential of the input node Q_n to the high potential of the second intermediate node Q2_n. In addition, a low-level reset control signal can be provided to the reset control terminal Trst, so after passing through the first NOR gate circuit NOR1, the potential of the first intermediate node Q1_n can be controlled to be low, and after passing through the first NOT gate circuit INV1, the potential of the second intermediate node Q2_n can be controlled to be high. Since the potential of the first intermediate node Q1_n is low and the potential of the second intermediate node Q2_n is high, the third transmission gate Tg3 can be turned off, and a low-potential signal can be output through the second NOR gate NOR2. This low-potential signal, after passing through the second NOT gate circuit INV2, the third NOT gate circuit INV3, and the fourth NOT gate circuit INV4, can make the potential of the output terminal OUT_n high.

[0123] In the third stage t03, a high-level first clock signal can be provided to the first clock terminal CKn, and a low-level second clock signal can be provided to the second clock terminal CB. This enables the first transmission gate circuit Tg1, thereby connecting the input terminal IN_n and the input node Q_n. The input terminal IN_n can then provide an input signal to the input node Q_n, and the potential of the input signal can be low. Furthermore, a low-level reset control signal can be provided to the reset control terminal Trst. This signal, after passing through the first NOR gate circuit NOR1, controls the potential of the first intermediate node Q1_n to be high, and after passing through the first NOT gate circuit INV1, controls the potential of the second intermediate node Q2_n to be low. Because the potential of the first intermediate node Q1_n is high and the potential of the second intermediate node Q2_n is low, the third transmission gate circuit Tg3 can be enabled, that is, the enable control signal provided by the enable control terminal GEN is transmitted to the second NOR gate circuit NOR2. For example, the potential of the enable control signal can be high. Therefore, a low-level signal can be output after passing through the second NOR gate NOR2. This low-level signal, after passing through the second NOT gate INV2, the third NOT gate INV3, and the fourth NOT gate INV4, can make the output terminal OUT_n high. Furthermore, in the third stage t03, a low-level third clock signal can be provided to the third clock terminal CBn, and a high-level fourth clock signal can be provided to the fourth clock terminal CK, causing the second transmission gate Tg2 to turn off, thereby disconnecting the second intermediate node Q2_n from the input node Q_n.

[0124] In the fourth stage t04, a low-level first clock signal can be provided to the first clock terminal CKn, and a high-level second clock signal can be provided to the second clock terminal CB, causing the first transmission gate circuit Tg1 to turn off, thereby disconnecting the input terminal IN_n from the input node Q_n. A high-level third clock signal can be provided to the third clock terminal CBn, and a low-level fourth clock signal can be provided to the fourth clock terminal CK, causing the second transmission gate circuit Tg2 to turn on, thereby turning the second intermediate node Q2_n on with the input node Q_n, thus latching the potential of the input node Q_n to the low potential of the second intermediate node Q2_n. In addition, a low-level reset control signal can be provided to the reset control terminal Trst, so after passing through the first NOR gate circuit NOR1, the potential of the first intermediate node Q1_n can be controlled to be high, and after passing through the first NOT gate circuit INV1, the potential of the second intermediate node Q2_n can be controlled to be low. Because the potential of the first intermediate node Q1_n is high and the potential of the second intermediate node Q2_n is low, the third transmission gate circuit Tg3 can be turned on, that is, the enable control signal provided by the enable control terminal GEN is transmitted to the second NOR gate circuit NOR2. For example, the potential of the enable control signal can be low. Thus, a high-potential signal can be output after passing through the second NOR gate circuit NOR2. This high-potential signal, after passing through the second NOT gate circuit INV2, the third NOT gate circuit INV3, and the fourth NOT gate circuit INV4, can make the potential of the output terminal OUT_n low.

[0125] In this example, the low-level output signal provided by the output terminal OUT_n occupies a relatively small proportion of a frame duration; that is, the output signal provided by the output terminal OUT_n is a P-type output (i.e., the low-level duty cycle is small). To ensure that the output terminal OUT_n provides a low-level output signal with a small duty cycle, the tenth N-type transistor Tn_10, the eighth N-type transistor Tn_8, the seventh N-type transistor Tn_7, and the second N-type transistor Tn_2 must be in the on state for a relatively long time within a frame duration, while the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6, and the ninth N-type transistor Tn_9 must be in the off state for a relatively long time within a frame duration. In other words, the duty cycle of the high potential of the top gate voltage signal of the tenth N-type transistor Tn_10, the eighth N-type transistor Tn_8, the seventh N-type transistor Tn_7, and the second N-type transistor Tn_2 is relatively large (i.e., the ratio of the duration of the high potential of the top gate voltage signal within one frame to the duration of one frame); the duty cycle of the low potential of the top gate voltage signal of the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6, and the ninth N-type transistor Tn_9 is relatively large (i.e., the ratio of the duration of the low potential of the top gate voltage signal within one frame to the duration of one frame). Specifically, the top gate voltage signal of the second N-type transistor Tn_2 is controlled by the input node Q_n; the top gate voltage signal of the third N-type transistor Tn_3 is controlled by the reset control terminal Trst; the top gate voltage signals of the fourth N-type transistor Tn_4 and the sixth N-type transistor Tn_6 are controlled by the first intermediate node Q1_n; the top gate voltage signal of the seventh N-type transistor Tn_7 is controlled by the second intermediate node Q2_n; the top gate voltage signal of the eighth N-type transistor Tn_8 is controlled by the output terminal of the third transmission gate circuit; the top gate voltage signal of the ninth N-type transistor Tn_9 is controlled by the output terminal of the second NOR gate circuit; and the top gate voltage signal of the tenth N-type transistor Tn_10 is controlled by the output terminal of the second NAND gate circuit.

[0126] In some examples, the high-potential duty cycle of the top-gate voltage signal of the tenth N-type transistor Tn_10, the eighth N-type transistor Tn_8, the seventh N-type transistor Tn_7, and the second N-type transistor Tn_2 can be greater than the high-potential duty cycle of the top-gate voltage signal of the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6, and the ninth N-type transistor Tn_9; the low-potential duty cycle of the top-gate voltage signal of the tenth N-type transistor Tn_10, the eighth N-type transistor Tn_8, the seventh N-type transistor Tn_7, and the second N-type transistor Tn_2 can be less than the low-potential duty cycle of the top-gate voltage signal of the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6, and the ninth N-type transistor Tn_9.

[0127] The shift register circuit provided in this example can not only match the timing requirements of the P-type transistor in the pixel circuit well, but also realize local pixel refresh, reliably reset the output signal, and has good driving flexibility and driving effect.

[0128] Figure 5 is another equivalent circuit diagram of a shift register circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 5, the top and bottom gates of the first N-type transistor Tn_1 are connected and connected to the first clock terminal CKn, configured to receive a clock signal. The top and bottom gates of the fifth N-type transistor Tn_5 are connected and connected to the third clock terminal CBn, configured to receive a clock signal.

[0129] In some examples, the top and bottom gates of the eleventh N-type transistor Tn_11 are controlled separately, and the bottom gate of the eleventh N-type transistor Tn_11 is connected to the third voltage line BG3. The top and bottom gates of each of the following N-type transistors—the second N-type transistor Tn_2, the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6, the seventh N-type transistor Tn_7, the eighth N-type transistor Tn_8, the ninth N-type transistor Tn_9, and the tenth N-type transistor Tn_10—are controlled separately, and the bottom gates of all these N-type transistors are connected to the fourth voltage line BG4. The fourth voltage signal provided by the fourth voltage line BG4 may be different from the third voltage signal provided by the third voltage line BG3.

[0130] In this example, the first N-type transistor Tn_1 through the eleventh N-type transistor Tn_11 are all oxide transistors. The first group of oxide transistors may include: the first N-type transistor Tn_1 and the fifth N-type transistor Tn_5; the second group of oxide transistors may include: the second N-type transistor Tn_2, the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6, the seventh N-type transistor Tn_7, the eighth N-type transistor Tn_8, the ninth N-type transistor Tn_9, the tenth N-type transistor Tn_10, and the eleventh N-type transistor Tn_11. The eleventh N-type transistor Tn_11 in the second group of oxide transistors is an oxide output transistor, and the remaining N-type transistors are oxide switching transistors.

[0131] In this example, the eleventh N-type transistor Tn_11, acting as an output transistor, receives a second power supply signal that may differ from the second power supply signals received by the other N-type transistors. Therefore, the gate voltage requirements for adjusting the threshold voltages of the eleventh N-type transistor and the other N-type transistors (including the second N-type transistor Tn_2, the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6, the seventh N-type transistor Tn_7, the eighth N-type transistor Tn_8, the ninth N-type transistor Tn_9, and the tenth N-type transistor Tn_10) are different. By separately controlling the bottom gates of the eleventh N-type transistor and the other N-type transistors, the threshold voltages of the transistors can be adjusted independently. Further descriptions of the shift register circuit in this example can be found in the descriptions of the foregoing embodiments, and will not be repeated here.

[0132] Figure 6 is another equivalent circuit diagram of a shift register circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 6, the top and bottom gates of the first N-type transistor Tn_1 are connected and connected to the first clock terminal CKn. The top and bottom gates of the fifth N-type transistor Tn_5 are connected and connected to the third clock terminal CBn.

[0133] In some examples, the top and bottom gates of the eleventh N-type transistor Tn_11 are controlled separately, and the bottom gate of the eleventh N-type transistor Tn_11 is connected to the third voltage line BG3. The top and bottom gates of each of the following N-type transistors are controlled separately: the second N-type transistor Tn_2, the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6, the seventh N-type transistor Tn_7, the eighth N-type transistor Tn_8, the ninth N-type transistor Tn_9, and the tenth N-type transistor Tn_10. The bottom gates of the second N-type transistor Tn_2, the seventh N-type transistor Tn_7, the eighth N-type transistor Tn_8, and the tenth N-type transistor Tn_10 are all connected to the first voltage line BG1; the bottom gates of the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6, and the ninth N-type transistor Tn_9 are all connected to the second voltage line BG2. The first voltage signal provided by the first voltage line BG1, the second voltage signal provided by the second voltage line BG2, and the third voltage signal provided by the third voltage line BG3 can be different.

[0134] In this example, the first N-type transistor Tn_1 through the eleventh N-type transistor Tn_11 are all oxide transistors. The first group of oxide transistors may include: the first N-type transistor Tn_1 and the fifth N-type transistor Tn_5; the second group of oxide transistors may include: the second N-type transistor Tn_2, the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6, the seventh N-type transistor Tn_7, the eighth N-type transistor Tn_8, the ninth N-type transistor Tn_9, the tenth N-type transistor Tn_10, and the eleventh N-type transistor Tn_11. The eleventh N-type transistor Tn_11 in the second group of oxide transistors is an oxide output transistor, and the remaining N-type transistors are oxide switching transistors.

[0135] In this example, during a one-frame driving process, based on the difference in duty cycle between the high and low gate voltages of the N-type switching transistors, the second N-type transistor Tn_2, the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6, the seventh N-type transistor Tn_7, the eighth N-type transistor Tn_8, the ninth N-type transistor Tn_9, and the tenth N-type transistor Tn_10 can be divided into two groups. The first group of N-type switching transistors (corresponding to the aforementioned first group of oxide switching transistors) includes the second N-type transistor Tn_2, the seventh N-type transistor Tn_7, the eighth N-type transistor Tn_8, and the tenth N-type transistor Tn_10. The second group of N-type switching transistors (corresponding to the aforementioned second group of oxide switching transistors) includes the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, the sixth N-type transistor Tn_6, and the ninth N-type transistor Tn_9. In some examples, the first group of N-type switching transistors remains on for a longer period within a frame, resulting in a large high-potential duty cycle for the gate voltage; conversely, the second group of N-type switching transistors remains off for a longer period within a frame, resulting in a large low-potential duty cycle for the gate voltage. For instance, when the output signal of the shift register circuit's output terminal OUT_n is configured to drive the P-type transistor in the pixel circuit (i.e., the low-potential duty cycle of the output signal is small), the high-potential duty cycle of the gate voltage of the tenth N-type transistor Tn_10 is large, meaning that the tenth N-type transistor Tn_10 remains on for a longer period.

[0136] This example uses different voltage controls on the bottom gates of multiple N-type switching transistors based on the difference in duty cycles between their high and low gate voltage levels, allowing for more precise adjustment of the threshold voltage of the N-type transistors. Further details regarding the shift register circuit in this example can be found in the description of the foregoing embodiments, and will not be repeated here.

[0137] Figure 7 is a schematic diagram of a gate driving circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 7, the gate driving circuit may include multiple cascaded shift register circuits (e.g., a first-stage shift register circuit GOA(1), a second-stage shift register circuit GOA(2), an (n-1)th-stage shift register circuit GOA(n-1), and an nth-stage shift register circuit GOA(n)). The second intermediate node Q2_n-1 of the (n-1)th-stage shift register circuit GOA(n-1) is connected to the input terminal IN_n of the nth-stage shift register circuit GOA(n). Except for the last stage shift register circuit, the second intermediate node of each stage shift register circuit can provide an input signal to the input terminal of the next stage shift register circuit. Here, n can be an integer greater than 0. The input terminal IN_1 of the first-stage shift register circuit GOA(1) can be connected to the start signal line STV.

[0138] In some examples, the first clock input CKn of the (2i-1)th stage shift register circuit can be connected to the first clock signal line CL1, the second clock input CB can be connected to the second clock signal line CL2, the third clock input CBn can be connected to the third clock signal line CL3, and the fourth clock input CK can be connected to the fourth clock signal line CL4. In the second stage shift register circuit, the first clock input CKn can be connected to the third clock signal line CL3, the second clock input CB can be connected to the fourth clock signal line CL4, the third clock input CBn can be connected to the first clock signal line CL1, and the fourth clock input CK can be connected to the second clock signal line CL2. Here, i can be an integer greater than 0.

[0139] In some examples, the enable control terminal GEN of the 2i-1 stage shift register circuit can be connected to the first enable control line EN1, and the enable control terminal GEN of the 2i stage shift register circuit can be connected to the second enable control line EN2.

[0140] In some examples, the first power supply terminal VGH1 of each shift register circuit can be connected to the first power supply line VH1, the first power supply terminal VGH2 can be connected to the first power supply line VH2, the second power supply terminal VGL1 can be connected to the second power supply line VL1, and the second power supply terminal VGL2 can be connected to the second power supply line VL2. The reset control terminal Trst of each shift register circuit can be connected to the reset control line RST.

[0141] Figure 8 is a partial cross-sectional schematic diagram of the display area of ​​a display substrate according to at least one embodiment of the present disclosure. Figure 8 illustrates the film layer stacking order of the display substrate. In some examples, as shown in Figure 8, in the direction perpendicular to the display substrate, the display substrate may include: a substrate 10, and a circuit structure layer 20, a light-emitting structure layer 30, and an encapsulation structure layer 40 sequentially disposed on the substrate 10.

[0142] In some examples, the circuit structure layer 20 may include: a buffer layer BF, a first semiconductor layer PY1, a first insulating layer (also referred to as a first gate insulating layer) GI1, a first conductive layer (also referred to as a first gate metal layer) GT1, a second insulating layer (also referred to as a second gate insulating layer) GI2, a second conductive layer (also referred to as a second gate metal layer) GT2, a third insulating layer (also referred to as a third gate insulating layer) GI3, a second semiconductor layer PY2, a fourth insulating layer (also referred to as a fourth gate insulating layer) GI4, a third conductive layer (also referred to as a third gate metal layer) GT3, a fifth insulating layer (also referred to as an interlayer insulating layer) ILD, a fourth conductive layer (also referred to as a first source / drain metal layer) SD1, a sixth insulating layer (also referred to as a passivation layer) PVX, a seventh insulating layer (also referred to as a first planarization layer) PLN1, a fifth conductive layer (also referred to as a second source / drain metal layer) SD2, and an eighth insulating layer (also referred to as a second planarization layer) PLN2, sequentially disposed on the substrate 10. However, this embodiment is not limited to this. In other examples, the sixth insulating layer PVX may be omitted, or the sixth insulating layer PVX may be located between the seventh insulating layer and the fifth conductive layer.

[0143] In some examples, the light-emitting structure layer 30 may include: an anode layer ANO, a pixel definition layer PDL, a light-emitting functional layer EL, and a cathode layer CATH. The anode layer ANO may include the anode of the light-emitting element, the pixel definition layer PDL may form multiple pixel openings exposing the anode layer ANO, and the light-emitting functional layer EL may be disposed within the pixel openings and connected to the anode within the anode layer ANO. The cathode layer CATH may be connected to the light-emitting functional layer EL.

[0144] In some examples, the encapsulation structure layer 40 may include: a first encapsulation layer CVD1, a second encapsulation layer IJP, and a third encapsulation layer CVD2. The first and third encapsulation layers CVD1 and CVD2 may be made of inorganic materials, while the second encapsulation layer IJP may be made of organic materials. The second encapsulation layer IJP may be disposed between the first and third encapsulation layers CVD1 and CVD2, forming an inorganic / organic / inorganic material stacked structure, which ensures that external moisture cannot enter the light-emitting structure layer 30. In some possible implementations, the display substrate may also include other film layers, such as a touch structure layer and a color filter layer; this embodiment does not limit this.

[0145] Figure 9 is a partial top view of a display substrate according to at least one embodiment of the present disclosure. Figure 9 shows a top view of two shift register circuits (e.g., the nth-level shift register circuit GOA(n) and the (n+1)th-level shift register circuit GOA(n+1)) of the display substrate. The equivalent circuit of the shift register circuit in this example can be shown in Figure 6.

[0146] In some examples, as shown in Figure 9, the outer contour of a single shift register circuit can be approximately rectangular in a plane parallel to the display substrate. The input shift circuit may include: a first transmission gate circuit Tg1, a second transmission gate circuit Tg2, a first NOR gate circuit NOR1, and a first NOT gate circuit INV1; the transmission control circuit may include: a second NOR gate circuit NOR2, a third transmission gate circuit Tg3, and a capacitor C; the drive enhancement circuit may include: a second NOT gate circuit INV2, a third NOT gate circuit INV3, and a fourth NOT gate circuit INV4. In the first direction D1, the input shift circuit, transmission control circuit, and drive enhancement circuit can be arranged sequentially.

[0147] In some examples, the orthographic projections of the first transmission gate Tg1, the second transmission gate Tg2, and the first NOT gate INV1 onto the substrate can be arranged sequentially along the second direction D2; the orthographic projection of the first NOR gate NOR1 onto the substrate can be located on the same side of the orthographic projections of the first transmission gate Tg1, the second transmission gate Tg2, and the first NOT gate INV1 onto the substrate in the first direction D1, and the orthographic projection of the first NOR gate NOR1 onto the substrate can be located on the side of the orthographic projections of the first transmission gate Tg1, the second transmission gate Tg2, and the first NOT gate INV1 onto the substrate away from the orthographic projection of the transmission control circuit onto the substrate. The orthographic projections of the second NOR gate NOR2 and the third transmission gate Tg3 onto the substrate can be arranged sequentially along the second direction D2. The orthographic projection of the second NOR gate NOR2 onto the substrate, along the first direction D1, is adjacent to the orthographic projections of the first transmission gate Tg1 and the second transmission gate Tg2 onto the substrate. Similarly, the orthographic projection of the third transmission gate Tg3 onto the substrate, along the first direction D1, is adjacent to the orthographic projection of the first NOT gate INV1 onto the substrate. The orthographic projections of the second NOT gate INV2, the third NOT gate INV3, and the fourth NOT gate INV4 onto the substrate can be arranged sequentially along the first direction D1. The orthographic projection of the second NOT gate INV2 onto the substrate, along the first direction D1, is adjacent to the orthographic projection of the second NOR gate NOR2 onto the substrate. The orthographic projection of the capacitor C onto the substrate, along the first direction D1, can be located between the orthographic projections of the third transmission gate Tg3 and the third NOT gate INV3 onto the substrate. The orthographic projections of the second NOT gate INV2 and the capacitor C onto the substrate can be adjacent along the second direction D2. This arrangement of the shift register circuit in this example effectively reduces wiring length, thereby saving space and facilitating the implementation of a narrow bezel.

[0148] In some examples, the orthographic projections of the second N-type transistor Tn_2, the second P-type transistor Tp_2, and the third N-type transistor Tn_3 of the first NOR gate NOR1 onto the substrate can be arranged in a stepped manner along the second direction D2. The orthographic projection of the third P-type transistor Tp_3 onto the substrate, in the first direction D1, can be located on the side of the orthographic projection of the second P-type transistor Tp_2 onto the substrate that is away from the orthographic projection of the second transmission gate Tg2 onto the substrate. The orthographic projections of the second N-type transistor Tn_2 and the third N-type transistor Tn_3 onto the substrate can be aligned along the second direction D2. The orthographic projection of the third N-type transistor Tn_3 onto the substrate, along with the orthographic projections of the fourth N-type transistor Tn_4 and the fourth P-type transistor Tp_4 of the first NOT gate INV1 onto the substrate, can be arranged sequentially along the first direction D1.

[0149] In some examples, the orthographic projections of the first P-type transistor Tp_1 and the first N-type transistor Tn_1 of the first transmission gate circuit Tg1 onto the substrate can be aligned along the first direction D1. Similarly, the orthographic projections of the fifth P-type transistor Tp_5 and the fifth N-type transistor Tn_5 of the second transmission gate circuit Tg2 onto the substrate can be aligned along the first direction D1. The orthographic projections of the fifth P-type transistor Tp_5 and the first P-type transistor Tp_1 onto the substrate can be aligned along the second direction D2, and the orthographic projections of the fifth N-type transistor Tn_5 and the first N-type transistor Tn_1 onto the substrate can also be aligned along the second direction D2.

[0150] In some examples, the orthographic projections of the seventh N-type transistor Tn_7 and the eighth N-type transistor Tn_8 of the second NOR gate NOR2 onto the substrate can be aligned along the first direction D1, and the orthographic projections of the seventh P-type transistor Tp_7 and the eighth P-type transistor Tp_8 onto the substrate can be located on the side of the third transmission gate Tg3 away from the orthographic projections of the seventh N-type transistor Tn_7 and the eighth N-type transistor Tn_8 onto the substrate in the second direction D2. The orthographic projections of the seventh P-type transistor Tp_7 and the eighth P-type transistor Tp_8 onto the substrate can be arranged sequentially along the first direction D1. The orthographic projections of the seventh P-type transistor Tp_7 and the seventh N-type transistor Tn_7 onto the substrate can be staggered along the second direction D2, and the orthographic projections of the eighth P-type transistor Tp_8 and the eighth N-type transistor Tn_8 onto the substrate can also be staggered along the second direction D2.

[0151] In some examples, the orthographic projections of the sixth N-type transistor Tn_6 and the sixth P-type transistor Tp_6 of the third transmission gate circuit Tg3 onto the substrate can be aligned along the first direction D1. The orthographic projections of the sixth N-type transistor Tn_6 and the seventh N-type transistor Tn_7 onto the substrate can be aligned along the second direction D2, and the orthographic projections of the sixth P-type transistor Tp_6 and the eighth N-type transistor Tn_8 onto the substrate can be aligned along the second direction D2.

[0152] In some examples, the orthogonal projection of capacitor C onto the substrate can lie between the orthogonal projections of the sixth P-type transistor Tp_6 and the tenth N-type transistor Tn_10 onto the substrate in the first direction D1, and can be adjacent to the orthogonal projection of the ninth N-type transistor Tn_9 onto the substrate in the second direction D2.

[0153] In some examples, the orthogonal projection of the ninth N-type transistor Tn_9 of the second NOT gate circuit INV2 onto the substrate in the first direction D1 can be aligned with the eighth N-type transistor Tn_9, and the orthogonal projection of the ninth P-type transistor Tp_9 onto the substrate in the second direction D2 can be misaligned with the orthogonal projection of the ninth N-type transistor Tn_9 onto the substrate.

[0154] In some examples, the orth projections of the tenth N-type transistor Tn_10 and the tenth P-type transistor Tp_10 of the third NOT gate INV3 onto the substrate can be aligned along the second direction D2. The orth projection of the tenth P-type transistor Tp_10 onto the substrate can be adjacent to the orth projection of the ninth P-type transistor Tp_9 onto the substrate in the first direction D1.

[0155] In some examples, the orthographic projections of the eleventh N-type transistor Tn_11 and the eleventh P-type transistor Tp_11 onto the substrate of the fourth NOT gate INV4 can be aligned along the second direction D2. The orthographic projection of the eleventh P-type transistor Tp_11 onto the substrate can be adjacent to the orthographic projection of the tenth N-type transistor Tn_10 onto the substrate in the first direction D1, and the orthographic projection of the eleventh N-type transistor Tn_11 onto the substrate can be adjacent to the orthographic projection of the tenth P-type transistor Tp_10 onto the substrate in the first direction D1.

[0156] The fabrication process of the display substrate is described below by way of example. The "patterning process" mentioned in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. "Thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes.

[0157] The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the projection of A includes the projection of B" means that the boundary of the projection of B falls within the boundary range of the projection of A, or the boundary of the projection of A overlaps with the boundary of the projection of B.

[0158] The fabrication process of the display substrate in this exemplary embodiment may include the following steps. The fabrication process of the circuit structure layer will be described below as an example.

[0159] (1) Providing a substrate. In some examples, the substrate can be a rigid substrate or a flexible substrate. For example, a rigid substrate can be, but is not limited to, one or more of glass and quartz; a flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In some examples, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer film, etc. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx, x>0) or silicon oxide (SiOy, y>0), etc., to improve the substrate's resistance to water and oxygen.

[0160] (2) Forming the first semiconductor layer. In some examples, a buffer thin film and a first semiconductor thin film are sequentially deposited on a substrate, and the first semiconductor thin film is patterned by a patterning process to form a buffer layer and a first semiconductor layer disposed on the substrate. In some examples, the material of the first semiconductor layer can be amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, etc.

[0161] Figure 10 is a schematic diagram of the display substrate after the first semiconductor layer in Figure 9 has been formed. In some examples, as shown in Figure 10, the first semiconductor layer of the display substrate may include: an active layer of multiple P-type transistors of a shift register circuit, such as an active layer 201 of a first P-type transistor, an active layer 202 of a second P-type transistor, an active layer 203 of a third P-type transistor, an active layer 204 of a fourth P-type transistor, an active layer 205 of a fifth P-type transistor, an active layer 206 of a sixth P-type transistor, an active layer 207 of a seventh P-type transistor, an active layer 208 of an eighth P-type transistor, an active layer 209 of a ninth P-type transistor, an active layer 210 of a tenth P-type transistor, and active layers 211a and 211b of an eleventh P-type transistor.

[0162] In some examples, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. The material of the first semiconductor layer may, for example, include polysilicon. The channel region of the first type of transistor may be undoped and possess semiconductor properties. The first and second regions may be doped regions on either side of the channel region and are doped with impurities, thus possessing conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped regions of the active layer may be interpreted as the source or drain electrodes of the transistor. For example, the first region of the active layer may be interpreted as the first electrode of the transistor, and the second region of the active layer may be interpreted as the second electrode of the transistor. The portions of the active layer between transistors may be interpreted as doped wiring that can be used to electrically connect the transistors. This embodiment is not limited in this respect.

[0163] In some examples, the active layer 202 of the second P-type transistor can extend along the first direction D1, and the active layer 203 of the third P-type transistor can extend along the second direction D2. The active layer 202 of the second P-type transistor and the active layer 203 of the third P-type transistor can be an integral structure, and the orthographic projection of this integral structure onto the substrate can be approximately L-shaped. The first region 202-1 of the active layer 202 of the second P-type transistor can simultaneously serve as the second region of the active layer 203 of the third P-type transistor; the second region 202-2 of the active layer 202 of the second P-type transistor and the first region 203-1 of the active layer 203 of the third P-type transistor can be set independently.

[0164] In some examples, the active layer 201 of the first P-type transistor and the active layer 205 of the fifth P-type transistor can extend along the second direction D2. The active layer 205 of the fifth P-type transistor can be adjacent to the active layer 202 of the second P-type transistor in the first direction D1. The active layer 201 of the first P-type transistor and the active layer 205 of the fifth P-type transistor can be an integral structure, and the orthographic projection of this integral structure onto the substrate can be approximately type I. The second region 201-2 of the active layer 201 of the first P-type transistor can simultaneously serve as the first region of the active layer 205 of the fifth P-type transistor; the first region 201-1 of the active layer 201 of the first P-type transistor and the second region 205-2 of the active layer 205 of the fifth P-type transistor can be independently configured.

[0165] In some examples, the orthogonal projection of the active layer 204 of the fourth P-type transistor onto the substrate can be a dumbbell shape extending along the first direction D1. The first region 204-1 and the second region 204-2 of the active layer 204 of the fourth P-type transistor can be located on both sides of the channel region of the active layer 204 of the fourth P-type transistor along the first direction D1.

[0166] In some examples, the orthogonal projection of the active layer 206 of the sixth P-type transistor onto the substrate can be a dumbbell shape extending along the second direction D2. The first region 206-1 and the second region 206-2 of the active layer 206 of the sixth P-type transistor can be located on both sides of the channel region of the active layer 206 of the sixth P-type transistor along the second direction D2.

[0167] In some examples, the active layer 207 of the seventh P-type transistor can extend along the second direction D2, and the active layers 208 and 209 of the eighth and ninth P-type transistors can extend along the first direction D1. The active layers 207, 208, and 209 of the seventh, eighth, and ninth P-type transistors can be a single, integral structure, and the orthographic projection of this integral structure onto the substrate can be approximately L-shaped. The active layer 208 of the eighth P-type transistor can be connected between the active layers 207 and 209 of the seventh and ninth P-type transistors. The first region 208-1 of the active layer 208 of the eighth P-type transistor can also serve as the first region of the active layer 209 of the ninth P-type transistor, and the second region 208-2 of the active layer 208 of the eighth P-type transistor can also serve as the first region of the active layer 207 of the seventh P-type transistor; the second region 207-2 of the active layer 207 of the seventh P-type transistor and the second region 209-2 of the active layer 209 of the ninth P-type transistor can be set independently.

[0168] In some examples, the active layer 210 of the tenth P-type transistor can extend along the second direction D2, and the orthographic projection of the active layer 210 of the tenth P-type transistor onto the substrate can be approximately a rectangle extending along the second direction D2, such as a rounded rectangle. The first region 210-1 and the second region 210-2 of the active layer 210 of the tenth P-type transistor can be located on both sides of the channel region of the active layer 210 of the tenth P-type transistor along the second direction D2.

[0169] In some examples, the orthographic projections of the active layers 211a and 211b of the eleventh P-type transistor onto the substrate can be aligned along the first direction D1 and both extend along the first direction D1. The orthographic projections of the active layers 211a and 211b of the eleventh P-type transistor onto the substrate can be approximately rectangular, such as rounded rectangles. The first region 211a-1 and the second region 211a-2 of the active layer 211a of the eleventh P-type transistor can be located on both sides of the channel region of the active layer 211a of the eleventh P-type transistor along the second direction D2; the first region 211b-1 and the second region 211b-2 of the active layer 211b of the eleventh P-type transistor can be located on both sides of the channel region of the active layer 211b of the eleventh P-type transistor along the second direction D2.

[0170] This example demonstrates how the placement of multiple P-type transistor active layers can be effectively utilized to reduce wasted space on the display substrate.

[0171] (3) Forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on the substrate on which the aforementioned structure is formed, and the first conductive film is patterned by a patterning process to form a first insulating layer and a first conductive layer disposed on the first insulating layer.

[0172] Figure 11A is a schematic diagram of the display substrate after the formation of the first conductive layer in Figure 9; Figure 11B is a schematic diagram of the first conductive layer in Figure 11A. In some examples, as shown in Figures 11A and 11B, the first conductive layer of the display substrate may include: the first plate C01 of the capacitor of the shift register circuit, and the gates of multiple P-type transistors, such as: the gate 301 of the first P-type transistor Tp_1, the gate 302 of the second P-type transistor Tp_2, the gate 303 of the third P-type transistor Tp_3, the gate 304 of the fourth P-type transistor Tp_4, the gate 305 of the fifth P-type transistor Tp_5, the gate 306 of the sixth P-type transistor Tp_6, the gate 307 of the seventh P-type transistor Tp_7, the gate 308 of the eighth P-type transistor Tp_8, the gate 309 of the ninth P-type transistor Tp_9, the gate 310 of the tenth P-type transistor Tp_10, and the gate 311 of the eleventh P-type transistor Tp_11.

[0173] In some examples, the gate 302 of the second P-type transistor Tp_2 and the gate 303 of the third P-type transistor Tp_3 are adjacent in the second direction D2. The orthographic projection of the gate 302 of the second P-type transistor Tp_2 onto the substrate can be approximately a strip extending along the second direction D2. The orthographic projection of the gate 303 of the third P-type transistor Tp_3 onto the substrate can be approximately a strip extending along the first direction D1.

[0174] In some examples, the gate 301 of the first P-type transistor Tp_1 and the gate 305 of the fifth P-type transistor Tp_5 can be approximately aligned in the second direction D2. The orthographic projection of the gate 301 of the first P-type transistor Tp_1 onto the substrate can be approximately a strip extending along the first direction D1. The orthographic projection of the gate 305 of the fifth P-type transistor Tp_5 onto the substrate can also be approximately a strip extending along the first direction D1.

[0175] In some examples, the orthographic projection of the gate 304 of the fourth P-type transistor Tp_4 onto the substrate can be approximately T-shaped. The gate 306 of the sixth P-type transistor Tp_6 can be located in the first direction D1 between the gate 304 of the fourth P-type transistor Tp_4 and the first plate C01 of the capacitor. The orthographic projection of the gate 306 of the sixth P-type transistor Tp_6 onto the substrate can be approximately step-shaped extending along the second direction D2. The orthographic projection of the first plate C01 of the capacitor onto the substrate can be approximately knife-shaped.

[0176] In some examples, the orthographic projection of the gate 307 of the seventh P-type transistor Tp_7 onto the substrate can be approximately a strip extending along the first direction D1. The orthographic projections of the gate 308 of the eighth P-type transistor Tp_8 and the gate 309 of the ninth P-type transistor Tp_9 onto the substrate can be approximately strips extending along the second direction D2. The orthographic projection of the gate 310 of the tenth P-type transistor Tp_10 onto the substrate can be approximately U-shaped, with the opening of the U-shape facing away from the gate 309 of the ninth P-type transistor Tp_9. The orthographic projection of the gate 311 of the eleventh P-type transistor Tp_11 onto the substrate can be approximately a straight line extending along the first direction D1.

[0177] (4) Forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on the substrate on which the aforementioned structure is formed, and the second conductive film is patterned by a patterning process to form a second insulating layer and a second conductive layer disposed on the second insulating layer.

[0178] Figure 12A is a schematic diagram of the display substrate after the second conductive layer is formed in Figure 9; Figure 12B is a schematic diagram of the second conductive layer in Figure 12A. In some examples, as shown in Figures 12A and 12B, the second conductive layer of the display substrate may include: the second plate C02 of the capacitor of the shift register circuit, the bottom gates of multiple N-type transistors (e.g., including the bottom gate 341 of the first N-type transistor, the bottom gate 342 of the second N-type transistor, the bottom gate 343 of the third N-type transistor, the bottom gate 344 of the fourth N-type transistor, the bottom gate 345 of the fifth N-type transistor, the bottom gate 346 of the sixth N-type transistor, the bottom gate 347 of the seventh N-type transistor, the bottom gate 348 of the eighth N-type transistor, the bottom gate 349 of the ninth N-type transistor, the bottom gate 350 of the tenth N-type transistor, and the bottom gate 351 of the eleventh N-type transistor), and multiple bottom gate connection lines (e.g., including the first bottom gate connection line 51, the second bottom gate connection line 52, and the third bottom gate connection line 53).

[0179] In some examples, the orthographic projection of the second plate C02 of the capacitor onto the substrate can be approximately rectangular, for example, a rounded rectangle. The orthographic projection of the second plate C02 onto the substrate can partially overlap with the orthographic projection of the first plate C01 onto the substrate.

[0180] In some examples, the orthographic projections of the bottom gate 341 of the first N-type transistor and the bottom gate 345 of the fifth N-type transistor onto the substrate can both extend along the first direction D1 and be aligned along the second direction D2. The orthographic projections of the bottom gate 341 of the first N-type transistor and the bottom gate 345 of the fifth N-type transistor onto the substrate can be approximately L-shaped.

[0181] In some examples, the orthographic projection of the bottom gate 342 of the second N-type transistor onto the substrate can be approximately a rectangle extending along the first direction D1. The orthographic projection of the bottom gate 343 of the third N-type transistor onto the substrate can also be approximately a rectangle extending along the first direction D1. The orthographic projections of the bottom gates 342 and 343 of the second and third N-type transistors onto the substrate can be aligned along the second direction D2. The orthographic projection of the bottom gate 344 of the fourth N-type transistor onto the substrate can be approximately n-type. The bottom gates 343 and 344 of the third and fourth N-type transistors are adjacent and connected along the second direction D2.

[0182] In some examples, the orthographic projection of the bottom gate 346 of the sixth N-type transistor onto the substrate can be approximately a rectangle extending along the first direction D1. The orthographic projections of the bottom gate 347 of the seventh N-type transistor and the bottom gate 346 of the sixth N-type transistor onto the substrate can be aligned along the second direction D2. The orthographic projections of the bottom gate 347 of the seventh N-type transistor and the bottom gate 348 of the eighth N-type transistor onto the substrate can be approximately rectangles extending along the first direction D1. The bottom gates of the seventh N-type transistor 347 and the bottom gates of the eighth N-type transistor 348 are adjacent and connected in the second direction D2.

[0183] In some examples, the orthographic projection of the bottom gate 349 of the ninth N-type transistor onto the substrate can be approximately a rectangle extending along the second direction D2. The bottom gate 349 of the ninth N-type transistor is aligned with the second plate C02 of the capacitor along the second direction D2. The orthographic projection of the bottom gate 350 of the tenth N-type transistor onto the substrate can be approximately U-shaped, with the opening of the U-shape facing away from the second plate of the capacitor. The orthographic projection of the bottom gate 351 of the eleventh N-type transistor onto the substrate can be approximately "mountain"-shaped, with the opening of the "mountain"-shaped shape facing away from the bottom gate 350 of the tenth N-type transistor.

[0184] In some examples, the bottom gate 350 of the tenth N-type transistor of the current shift register circuit (e.g., the nth-stage shift register circuit GOA(n)) can be connected via the first bottom gate connection line 51 to the bottom gate 342 of the second N-type transistor, the bottom gate 347 of the seventh N-type transistor, and the bottom gate 348 of the eighth N-type transistor of the next-stage shift register circuit (e.g., the (n+1)th-stage shift register circuit GOA(n+1)). For example, the bottom gate 350 of the tenth N-type transistor of the current shift register circuit (e.g., the nth-stage shift register circuit GOA(n)), the bottom gate 342 of the second N-type transistor, the bottom gate 347 of the seventh N-type transistor, and the bottom gate 348 of the eighth N-type transistor of the next-stage shift register circuit (e.g., the (n+1)th-stage shift register circuit GOA(n+1)), and the first bottom gate connection line 51 can be a single integrated structure.

[0185] In some examples, the first bottom gate connection line 51 may include: a first trace segment 510 extending along a first direction D1, a first connection segment 511 extending along a second direction D2, and a second connection segment 512. The orthographic projection of the first trace segment 510 onto the substrate is a broken line segment extending along the first direction D1. One end of the first trace segment 510 may be connected to a first voltage line, and the other end may be connected to the bottom gate 350 of the tenth type N transistor of the current stage shift register circuit (e.g., the nth stage shift register circuit GOA(n)). The first trace segment 510 may be located within the interval between two adjacent shift register circuits. The first connection segment 511 and the second connection segment 512 are connected to the same side of the first trace segment 510 in the second direction D2. The orthographic projection of the first connection segment 511 and the second connection segment 512 onto the substrate is a strip extending along the second direction D2. The first connection segment 511 is connected to the bottom gate 342 of the second N-type transistor of the next-stage shift register circuit (e.g., the (n+1)th stage shift register circuit GOA(n+1)), and the second connection segment 512 is connected to the bottom gate 347 of the seventh N-type transistor and the bottom gate 348 of the eighth N-type transistor of the next-stage shift register circuit.

[0186] In some examples, the bottom gate 343 of the third N-type transistor, the bottom gate 344 of the fourth N-type transistor, the bottom gate 346 of the sixth N-type transistor, and the bottom gate 349 of the ninth N-type transistor in this shift register circuit, as well as the connected second bottom gate connection line 52 and third bottom gate connection line 53, can be an integral structure.

[0187] In some examples, the orthographic projection of the second gate connection 52 onto the substrate is approximately U-shaped. One end of the second gate connection 52 can be connected to the second voltage line, and the other end can be connected to the gate 343 of the third N-type transistor. The gate 344 of the fourth N-type transistor can be connected between the gate 343 of the third N-type transistor and the third gate connection 53.

[0188] In some examples, the third bottom gate connection line 53 may include: a second trace segment 530 extending along a first direction D1, and a third connection segment 531 extending along a second direction D2. The orthographic projection of the second trace segment 530 onto the substrate is a broken line segment extending along the first direction D1. One end of the second trace segment 530 is connected to the bottom gate 344 of the fourth N-type transistor, and the other end is connected to the bottom gate 349 of the ninth N-type transistor. The orthographic projection of the third connection segment 531 onto the substrate is a strip extending along the second direction D2. The third connection segment 531 is connected to the bottom gate 346 of the sixth N-type transistor. The orthographic projection of the second trace segment 530 onto the substrate may lie between the orthographic projections of the second NOR gate circuit and the third transmission gate circuit onto the substrate, and between the orthographic projections of the second transmission gate circuit and the first NOT gate circuit onto the substrate.

[0189] This example demonstrates how to connect multiple N-type transistors to their bottom gates by setting up multiple bottom gate connection lines, which helps reduce the layout difficulty of shift register circuits.

[0190] In some examples, the orthographic projection of the second conductive layer onto the substrate may not overlap with the orthographic projections of the first semiconductor layer and the first conductive layer onto the substrate, thereby reducing the impact on the P-type transistor.

[0191] (5) Forming a second semiconductor layer. In some examples, a third insulating film and a second semiconductor film are sequentially deposited on the substrate on which the aforementioned pattern is formed. The second semiconductor film is patterned using a patterning process to form a third insulating layer and a second semiconductor layer disposed on the third insulating layer. In some examples, the material of the second semiconductor layer may include indium gallium zinc oxide (IGZO).

[0192] Figure 13A is a schematic diagram of the display substrate after the second semiconductor layer is formed in Figure 9; Figure 13B is a schematic diagram of the second semiconductor layer in Figure 13A. In some examples, as shown in Figures 13A and 13B, the second semiconductor layer of the display substrate may include: an active layer of multiple N-type transistors of a shift register circuit, such as: an active layer 221 of a first N-type transistor Tn_1, an active layer 222 of a second N-type transistor Tn_2, an active layer 223 of a third N-type transistor Tn_3, an active layer 224 of a fourth N-type transistor Tn_4, an active layer 225 of a fifth N-type transistor Tn_5, an active layer 226 of a sixth N-type transistor Tn_6, an active layer 227 of a seventh N-type transistor Tn_7, an active layer 228 of an eighth N-type transistor Tn_8, an active layer 229 of a ninth N-type transistor Tn_9, an active layer 230 of a tenth N-type transistor Tn_10, and active layers 231a and 231b of an eleventh N-type transistor Tn_11.

[0193] In some examples, the orthogonal projection of the active layer 222 of the second N-type transistor Tn_2 onto the substrate can be a dumbbell shape extending along the second direction D2. The first region 222-1 and the second region 222-2 of the active layer 222 of the second N-type transistor Tn_2 are located on both sides of the channel region along the second direction D2.

[0194] In some examples, the active layer 223 of the third N-type transistor Tn_3 can extend along the second direction D2, and the active layer 224 of the fourth N-type transistor Tn_4 can extend along the first direction D1. The active layer 223 of the third N-type transistor Tn_3 and the active layer 224 of the fourth N-type transistor Tn_4 can be an integral structure, and the orthographic projection of this integral structure onto the substrate is approximately L-shaped. The first region 223-1 of the active layer 223 of the third N-type transistor Tn_3 can simultaneously serve as the first region of the active layer 224 of the fourth N-type transistor Tn_4; the second region 223-2 of the active layer 223 of the third N-type transistor Tn_3 and the second region 224-2 of the active layer 224 of the fourth N-type transistor Tn_4 can be set independently.

[0195] In some examples, the active layer 221 of the first N-type transistor Tn_1 and the active layer 225 of the fifth N-type transistor Tn_5 can both extend along the second direction D2. The active layer 221 of the first N-type transistor Tn_1 and the active layer 225 of the fifth N-type transistor Tn_5 can be an integral structure, and the orthogonal projection of this integral structure onto the substrate can be approximately type I. The second region 221-2 of the active layer 221 of the first N-type transistor Tn_1 can simultaneously serve as the first region of the active layer 225 of the fifth N-type transistor Tn_5; the first region 221-1 of the active layer 221 of the first N-type transistor Tn_1 and the second region 225-2 of the active layer 225 of the fifth N-type transistor Tn_5 can be set independently.

[0196] In some examples, the orthographic projection of the active layer 226 of the sixth N-type transistor Tn_6, the active layer 227 of the seventh N-type transistor Tn_7, and the active layer 228 of the eighth N-type transistor Tn_8 onto the substrate can be approximately dumbbell-shaped, extending along the second direction D2. The active layer 227 of the seventh N-type transistor Tn_7 and the active layer 228 of the eighth N-type transistor Tn_8 can be aligned along the first direction D1, and the active layer 227 of the seventh N-type transistor Tn_7 and the active layer 226 of the sixth N-type transistor Tn_6 can be aligned along the second direction D2. The first region 226-1 and the second region 226-2 of the active layer 226 of the sixth N-type transistor Tn_6 can be located on both sides of the channel region of the sixth N-type transistor Tn_6 along the second direction D2. The first region 227-1 and the second region 227-2 of the active layer 227 of the seventh N-type transistor Tn_7 can be located on both sides of the channel region of the seventh N-type transistor Tn_7 along the second direction D2. The first region 228-1 and the second region 228-2 of the active layer 228 of the eighth N-type transistor Tn_8 can be located on both sides of the channel region of the eighth N-type transistor Tn_8 along the second direction D2.

[0197] In some examples, the active layer 229 of the ninth N-type transistor Tn_9 and the active layer 228 of the eighth N-type transistor Tn_8 can be aligned along the first direction D1. The active layer 229 of the ninth N-type transistor Tn_9 can extend along the first direction D1, and its orthographic projection onto the substrate can be approximately rectangular. The first region 229-1 and the second region 229-2 of the active layer 229 of the ninth N-type transistor Tn_9 can be located on both sides of the channel region of the ninth N-type transistor Tn_9 along the first direction D1.

[0198] In some examples, the active layer 230 of the tenth N-type transistor Tn_10 can extend along the second direction D2, and its orthographic projection onto the substrate can be approximately rectangular. The active layers 231a and 231b of the eleventh N-type transistor Tn_11 can be aligned along the first direction D1, and their orthographic projection onto the substrate can also be approximately rectangular.

[0199] (6) Forming a third conductive layer. In some examples, a fourth insulating film and a third conductive film are sequentially deposited on the substrate on which the aforementioned pattern is formed. The third conductive film is patterned by a patterning process to form a fourth insulating layer and a third conductive layer disposed on the fourth insulating layer.

[0200] Figure 14A is a schematic diagram of the display substrate after the formation of the third conductive layer in Figure 9; Figure 14B is a schematic diagram of the third conductive layer in Figure 14A. In some examples, as shown in Figures 14A and 14B, the third conductive layer of the display substrate may include the top gates of multiple N-type transistors of the shift register circuit, for example, it may include: the top gate 321 of the first N-type transistor Tn_1, the top gate 322 of the second N-type transistor Tn_2, the top gate 323 of the third N-type transistor Tn_3, the top gate 324 of the fourth N-type transistor Tn_4, the top gate 325 of the fifth N-type transistor Tn_5, the top gate 326 of the sixth N-type transistor Tn_6, the top gate 327 of the seventh N-type transistor Tn_7, the top gate 328 of the eighth N-type transistor Tn_8, the top gate 329 of the ninth N-type transistor Tn_9, the top gate 330 of the tenth N-type transistor Tn_10, and the top gate 331 of the eleventh N-type transistor Tn_11.

[0201] In some examples, the top gate 321 of the first N-type transistor Tn_1, the top gate 322 of the second N-type transistor Tn_2, the top gate 323 of the third N-type transistor Tn_3, the top gate 325 of the fifth N-type transistor Tn_5, the top gate 326 of the sixth N-type transistor Tn_6, the top gate 327 of the seventh N-type transistor Tn_7, and the top gate 328 of the eighth N-type transistor Tn_8 can all extend along the first direction D1, for example, their orthogonal projection onto the substrate can be a strip extending along the first direction D1. The top gate 329 of the ninth N-type transistor Tn_9 can extend along the second direction D2, for example, its orthogonal projection onto the substrate can be a strip extending along the second direction D2. The top gate 324 of the fourth N-type transistor Tn_4 can have its orthogonal projection onto the substrate approximately n-type. The orthographic projection of the top gate 330 of the N-type transistor Tn_10 onto the substrate can be approximately U-shaped, with the opening of the U-shape facing the top gate 331b of the eleventh N-type transistor Tn_11. The orthographic projection of the top gate 331a of the eleventh N-type transistor Tn_11 onto the substrate is an elongated strip extending along the first direction D1, and the orthographic projection of the top gate 331b of the eleventh N-type transistor Tn_11 onto the substrate is approximately U-shaped, with the opening of the U-shape facing away from the top gate 330 of the tenth N-type transistor Tn_10.

[0202] In some examples, the top gate 322 of the second N-type transistor Tn_2 and the top gate 323 of the third N-type transistor Tn_3 can be aligned along the second direction D2. The top gate 321 of the first N-type transistor Tn_1 and the top gate 325 of the fifth N-type transistor Tn_5 can be aligned along the second direction D2. The top gate 326 of the sixth N-type transistor Tn_6 and the top gate 327 of the seventh N-type transistor Tn_7 can be aligned along the second direction D2. The top gate 327 of the seventh N-type transistor Tn_7 and the top gate 328 of the eighth N-type transistor Tn_8 can be aligned along the first direction D1.

[0203] In some examples, the orthographic projection of the overlap region between the top gate and the active layer of the N-type transistor onto the substrate can be located within the orthographic projection range of the overlap region between the bottom gate and the active layer of the N-type transistor onto the substrate. This example demonstrates how setting the bottom gate of the N-type transistor allows for adjustment of its characteristics, thereby achieving better transistor performance.

[0204] (7) Forming the fifth insulating layer. In some examples, a fifth insulating film is deposited on the substrate on which the aforementioned pattern is formed, and the fifth insulating film is patterned by a patterning process to form the fifth insulating layer. In some examples, the fifth insulating film can be patterned by two patterning processes. The first patterning process can form a first set of vias in the fifth insulating layer, and the second patterning process can form a second set of vias in the fifth insulating layer. For example, the first set of vias can expose a portion of the surface of the first semiconductor layer, the first conductive layer, and the second conductive layer, and the second set of vias can expose a portion of the surface of the second semiconductor layer and the third conductive layer.

[0205] Figures 15A and 15B are schematic diagrams of the display substrate after the fifth insulating layer is formed in Figure 9. Figure 15A shows the first group of vias in the fifth insulating layer, and Figure 15B shows the second group of vias in the fifth insulating layer.

[0206] In some examples, as shown in Figure 15A, the first set of vias in the fifth insulating layer of the display substrate may include: first vias V1 to twentieth vias V20, twenty-first vias V21 to thirty-third vias V33, and thirty-fourth vias V34 to fortieth vias V40. The fifth, fourth, third, second, and first insulating layers within the first vias V1 to twentieth vias V20 may be removed, exposing a portion of the surface of the first semiconductor layer; the fifth, fourth, third, and second insulating layers within the twenty-first vias V21 to thirty-third vias V33 may be removed, exposing a portion of the surface of the first conductive layer; and the fifth, fourth, and third insulating layers within the thirty-fourth vias V34 to fortieth vias V40 may be removed, exposing a portion of the surface of the second conductive layer.

[0207] In some examples, as shown in Figure 15B, the second set of vias in the fifth insulating layer of the display substrate may include: vias V41 to V67 (41st to 67th), and vias V68 to V79 (68th to 79th). The fifth and fourth insulating layers within vias V41 to V67 can be removed to expose a portion of the surface of the second semiconductor layer; the fifth insulating layer within vias V68 to V79 can be removed to expose a portion of the surface of the third conductive layer.

[0208] (8) Forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the fourth conductive film is patterned by a patterning process to form a fourth conductive layer on the fifth insulating layer.

[0209] Figure 16A is a schematic diagram of the display substrate after the fourth conductive layer is formed in Figure 9; Figure 16B is a schematic diagram of the fourth conductive layer in Figure 16A. In some examples, as shown in Figures 16A and 16B, the fourth conductive layer of the display substrate may include: a plurality of connection electrodes (e.g., including the first connection electrode 401 to the thirty-first connection electrode 431).

[0210] In some examples, the orthographic projection of the first connection electrode 401 onto the substrate can be rectangular. The first connection electrode 401 can be connected to the first region 222-1 of the active layer 222 of the second N-type transistor Tn_2 through the forty-first via V41.

[0211] In some examples, the orthographic projection of the second connection electrode 402 onto the substrate can be rectangular. The second connection electrode 402 can be connected to the first region 223-1 of the active layer 223 of the third N-type transistor Tn_3 via the forty-fourth via V44. The second connection electrode 402 and the first connection electrode 401 can be aligned along the second direction D2. The first connection electrode 401 and the second connection electrode 402 can subsequently be connected to the second power line VL1a located on the fifth conductive layer.

[0212] In some examples, the orthographic projection of the third connection electrode 403 onto the substrate can be approximately rectangular. The third connection electrode 403 can be connected to the first region 203-1 of the active layer 203 of the third P-type transistor Tp_3 via the second via V2. The third connection electrode 403 can subsequently be connected to the first power line VH1a located on the fifth conductive layer.

[0213] In some examples, the orthographic projection of the fourth connection electrode 404 onto the substrate is approximately a rectangle extending along the second direction D2. The fourth connection electrode 404 can be connected to the gate 303 of the third P-type transistor Tp_3 via the twenty-second via V22, and also to the top gate 323 of the third N-type transistor Tn_3 via the sixty-ninth via V69. The fourth connection electrode 404 can subsequently be connected to the reset control line RST located on the fifth conductive layer.

[0214] In some examples, the orthographic projection of the fifth connection electrode 405 onto the substrate can be approximately rectangular. The fifth connection electrode 405 can be connected to the gate 305 of the fifth P-type transistor Tp_5 via the twenty-third via V23. The fifth connection electrode 405 of the nth stage shift register circuit GOA(n) can subsequently be connected to the fourth clock signal line CL4 located on the fifth conductive layer.

[0215] In some examples, the orthographic projection of the sixth connection electrode 406 onto the substrate can be approximately rectangular. The sixth connection electrode 406 can be connected to the gate 301 of the first P-type transistor Tp_1 via the twenty-fourth via V24. The sixth connection electrode 406 of the nth stage shift register circuit GOA(n) can subsequently be connected to the second clock signal line CL2 located on the fifth conductive layer.

[0216] In some examples, the orthographic projection of the seventh connection electrode 407 onto the substrate can be approximately rectangular. The seventh connection electrode 407 can be connected to the bottom gate 341 of the first N-type transistor Tn_1 via the thirty-eighth via V38, and also to the top gate 321 of the first N-type transistor Tn_1 via the seventy-first via V71. The seventh connection electrode 407 of the nth-stage shift register circuit GOA(n) can subsequently be connected to the first clock signal line CL1 located on the fifth conductive layer.

[0217] In some examples, the orthographic projection of the eighth connection electrode 408 onto the substrate can be approximately L-shaped. The eighth connection electrode 408 can be connected to the bottom gate 345 of the fifth N-type transistor Tn_5 via the thirty-ninth via V39, and also to the top gate 325 of the fifth N-type transistor Tn_5 via the seventy-second via V72. The eighth connection electrode 408 of the nth-stage shift register circuit GOA(n) can subsequently be connected to the third clock signal line CL3 located on the fifth conductive layer.

[0218] In some examples, the orthographic projection of the ninth connection electrode 409 onto the substrate can be approximately rectangular. The ninth connection electrode 409 can be connected to the second region 208-2 of the active layer 208 of the eighth P-type transistor Tp_8 via the ninth via V9.

[0219] In some examples, the orthographic projection of the tenth connection electrode 410 onto the substrate can be approximately rectangular. The tenth connection electrode 410 can be connected to the first region 227-1 of the active layer 227 of the seventh N-type transistor Tn_7 via the fifty-first via V51, and also to the first region 228-1 of the active layer 228 of the eighth N-type transistor Tn_8 via the fifty-second via V52. The tenth connection electrode 410 can subsequently be connected to the second power line VL1b located on the fifth conductive layer.

[0220] In some examples, the orthographic projection of the eleventh connection electrode 411 onto the substrate can be approximately L-shaped. The eleventh connection electrode 411 can be connected to the first region 208-1 of the active layer 208 of the eighth P-type transistor Tp_8 via the tenth via V10. The eleventh connection electrode 411 can subsequently be connected to the first power line VH1c located on the fifth conductive layer.

[0221] In some examples, the orthographic projection of the twelfth connection electrode 412 onto the substrate can be approximately rectangular. The twelfth connection electrode 412 can be connected to the conductive region between the two channel regions of the active layer 210 of the tenth P-type transistor Tp_10 via a plurality (e.g., three) fifteenth vias V15 aligned along the first direction D1. The twelfth connection electrode 412 can subsequently be connected to the first power line VH1d located on the fifth conductive layer.

[0222] In some examples, the orthographic projection of the thirteenth connection electrode 413 onto the substrate can be approximately L-shaped. The thirteenth connection electrode 413 can be connected to the first region 204-1 of the active layer 204 of the fourth P-type transistor Tp_4 via the seventh via V7. The thirteenth connection electrode 413 can subsequently be connected to the first power line VH1b located on the fifth conductive layer.

[0223] In some examples, the orthographic projection of the fourteenth connection electrode 414 onto the substrate can be approximately L-shaped. The fourteenth connection electrode 414 can be connected to the first region 206-1 of the active layer 206 of the sixth P-type transistor Tp_6 via the thirteenth via V13, and also to the first region 226-1 of the active layer 226 of the sixth N-type transistor Tp_6 via the fifty-fourth via V54. The fourteenth connection electrode 414 of the nth stage shift register circuit GOA(n) can subsequently be connected to the first enable control line EN1 located on the fifth conductive layer.

[0224] In some examples, the orthographic projection of the fifteenth connection electrode 415 onto the substrate can be a strip extending along the first direction D1. The fifteenth connection electrode 415 can be connected to the active layer 231a of the eleventh N-type transistor Tn_11 via a plurality of (e.g., seven) sixtieth vias V60 aligned along the first direction D1, and can also be connected to the active layer 231b of the eleventh N-type transistor Tn_11 via a plurality of (e.g., seven) sixty-fourth vias V64 aligned along the first direction D1. The fifteenth connection electrode 415 can subsequently be connected to a second power line VL2 located on the fifth conductive layer.

[0225] In some examples, the orthographic projection of the sixteenth connection electrode 416 onto the substrate can be U-shaped, with the opening of the U-shape facing the tenth P-type transistor Tp_10. The sixteenth connecting electrode 416 can be connected to the active layer 231a of the eleventh N-type transistor Tn_11 through a plurality of (e.g., seven) sixty-first vias V61 and a plurality of (e.g., seven) sixty-third vias V63 arranged along the first direction D1. It can also be connected to the active layer 231b of the eleventh N-type transistor Tn_11 through a plurality of (e.g., seven) sixty-fifth vias V65 and a plurality of (e.g., seven) sixty-seventh vias V67 arranged along the first direction D1. It can also be connected to the second region 211a-2 of the active layer 211a of the eleventh P-type transistor Tp_11 through a plurality of (e.g., seven) seventeenth vias V17 arranged along the first direction D1. It can also be connected to the second region 211b-2 of the active layer 211b of the eleventh P-type transistor Tp_11 through a plurality of (e.g., seven) nineteenth vias V19 arranged along the first direction D1. The sixteenth connecting electrode 416 can be used as the output terminal of the shift register circuit.

[0226] In some examples, the orthographic projection of the seventeenth connection electrode 417 onto the substrate can be a strip extending along the first direction D1. The seventeenth connection electrode 417 can be located within the U-shaped opening of the sixteenth connection electrode 416. The seventeenth connection electrode 417 can be connected to the active layer 231a of the eleventh N-type transistor Tn_11 via a plurality (e.g., seven) of sixty-second vias V62 aligned along the first direction D1, and can also be connected to the active layer 231b of the eleventh N-type transistor Tn_11 via a plurality (e.g., seven) of sixty-sixth vias V66 aligned along the first direction D1. The seventeenth connection electrode 417 can subsequently be connected to the second power line VL2 located on the fifth conductive layer.

[0227] In some examples, the orthogonal projection of the eighteenth connection electrode 418 onto the substrate can be an extension along the second direction D2. The eighteenth connection electrode 418 can be connected to the second region 209-2 of the active layer 209 of the ninth P-type transistor Tp_9 via the eleventh via V11, to the gate 310 of the tenth P-type transistor Tp_10 via the thirty-first via V31, to the second region 229-2 of the active layer 229 of the ninth N-type transistor Tn_9 via the fifty-sixth via V56, and to the top gate 330 of the tenth N-type transistor Tn_10 via the seventy-sixth via V76.

[0228] In some examples, the orthographic projection of the nineteenth connection electrode 419 onto the substrate can be rectangular. The nineteenth connection electrode 419 can be connected to the bottom gate 351 of the eleventh N-type transistor Tn_11 through the thirty-fifth via V35. The nineteenth connection electrode 419 can subsequently be connected to the third voltage line BG3 located on the fifth conductive layer, realizing the electrical connection between the bottom gate 351 of the eleventh N-type transistor Tn_11 and the third voltage line BG3.

[0229] In some examples, the orthographic projection of the twentieth connection electrode 420 onto the substrate can be approximately L-shaped. The twentieth connection electrode 420 can be connected to the first region 201-1 of the active layer 201 of the first P-type transistor Tp_1 via the third via V3, and also to the first region 221-1 of the active layer 221 of the first N-type transistor Tn_1 via the forty-sixth via V46. The twentieth connection electrode 420 can serve as the input terminal of this stage's shift register circuit.

[0230] In some examples, the orthographic projection of the twenty-first connecting electrode 421 onto the substrate can be approximately a broken line extending along the first direction D1. The twenty-first connecting electrode 421 can be connected to the gate 302 of the second P-type transistor Tp_2 through the twenty-first via V21, and can also be connected to the top gate 322 of the second N-type transistor Tn_2 through the sixty-eighth via V68, and can also be connected to the second region 201-2 of the active layer 201 of the first P-type transistor Tp_1 through the fourth via V4, and can also be connected to the second region 221-2 of the active layer 221 of the first N-type transistor Tn_1 through the forty-seventh via V47. Since the second region of the active layer of the first P-type transistor Tp_1 also serves as the second region of the active layer of the fifth P-type transistor Tp_5, and the second region of the active layer of the first N-type transistor Tn_1 also serves as the second region of the active layer of the fifth N-type transistor Tn_5, the twenty-first connecting electrode 421 can serve as an input node to realize the connection of the first transmission gate circuit, the first NOR gate circuit, and the second transmission gate circuit.

[0231] In some examples, the orthographic projection of the twenty-second connection electrode 422 onto the substrate can be approximately a broken line extending along the first direction D1. The twenty-second connection electrode 422 can be connected to the second region of the active layer of the second P-type transistor Tp_2 via the first via V1, to the second region 222-2 of the active layer 222 of the second N-type transistor Tn_2 via the forty-second via V42, to the second region 223-2 of the active layer 223 of the third N-type transistor Tn_3 via the forty-third via V43, to the top gate 324 of the fourth N-type transistor Tn_4 via the seventieth via V70, and to the gate 304 of the fourth P-type transistor Tp_4 via the twenty-fifth via V25. The twenty-second connection electrode 422 can realize the connection of the first NOR gate circuit and the first NOT gate circuit.

[0232] In some examples, the orthographic projection of the twenty-third connection electrode 423 onto the substrate can be approximately L-shaped. The twenty-third connection electrode 423 can be connected to the gate 304 of the fourth P-type transistor Tp_4 via the twenty-sixth via V26, and also to the top gate 326 of the sixth N-type transistor Tn_6 via the seventy-fifth via V75. In this example, the twenty-second connection electrode 422, the gate 304 of the fourth P-type transistor Tp_4, and the twenty-third connection electrode 423 can be connected as a first intermediate node.

[0233] In some examples, the orthographic projection of the twenty-fourth connection electrode 424 onto the substrate can be approximately a stepped shape extending along the second direction D2. The twenty-fourth connection electrode 424 can be connected to the second region 205-2 of the active layer 205 of the fifth P-type transistor Tp_5 via the fifth via V5, to the second region 204-2 of the active layer 204 of the fourth P-type transistor Tp_4 via the sixth via V6, to the second region 225-2 of the active layer 225 of the fifth N-type transistor Tn_5 via the forty-eighth via V48, to the second region 224-2 of the active layer 224 of the fourth N-type transistor Tn_4 via the forty-fifth via V45, to the gate 306 of the sixth P-type transistor Tn_6 via the twenty-seventh via V27, to the gate 307 of the seventh P-type transistor Tn_7 via the twenty-eighth via V28, and to the top gate 327 of the seventh N-type transistor Tn_7 via the seventy-third via V73. The twenty-fourth connection electrode 424 can serve as a second intermediate node to connect the second transmission gate circuit, the first NOT gate circuit, the second NOR gate circuit, and the third transmission gate circuit. The twenty-fourth connection electrode 424 of this stage shift register circuit (e.g., the nth stage shift register circuit GOA(n)) and the twentieth connection electrode 420 of the next stage shift register circuit (e.g., the (n+1)th stage shift register circuit GOA(n+1)) can be a single integrated structure.

[0234] In some examples, the orthographic projection of the twenty-fifth connection electrode 425 onto the substrate can be approximately a broken line extending along the first direction D1. The twenty-fifth connection electrode 425 can be connected to the second region 207-2 of the active layer 207 of the seventh P-type transistor Tp_7 via the eighth via V8, to the gate 309 of the ninth P-type transistor Tp_9 via the thirtieth via V30, to the second region 227-2 of the active layer 227 of the seventh N-type transistor Tn_7 via the forty-ninth via V49, to the second region 228-2 of the active layer 228 of the eighth N-type transistor Tn_8 via the fiftieth via V50, and to the top gate 329 of the ninth N-type transistor Tn_9 via the seventy-ninth via V79.

[0235] In some examples, the orthographic projection of the twenty-sixth connection electrode 426 onto the substrate can be approximately L-shaped. The twenty-sixth connection electrode 426 can be connected to the gate 308 of the eighth P-type transistor Tp_8 through the twenty-ninth via V29, to the first plate C01 of the capacitor through the thirty-second via V32, to the second region 206-2 of the active layer 206 of the sixth P-type transistor Tp_6 through the twelfth via V12, to the top gate 328 of the eighth N-type transistor Tn_8 through the seventy-fourth via V74, and to the second region 226-2 of the active layer 226 of the sixth N-type transistor Tn_6 through the fifty-third via V53.

[0236] In some examples, the orthographic projection of the twenty-seventh connection electrode 427 onto the substrate can be approximately L-shaped. The twenty-seventh connection electrode 427 can be connected to the second plate C02 of the capacitor via two fortieth vias V40 aligned along the second direction D2, and also to the first region 229-1 of the active layer 229 of the ninth N-type transistor Tn_9 via a fifty-fifth via V55, and to the active layer 230 of the tenth N-type transistor Tn_10 via three fifty-eighth vias V58 aligned along the first direction D1. The twenty-seventh connection electrode 427 can subsequently be connected to the second power line VL1c located on the fifth conductive layer.

[0237] In some examples, the orthographic projection of the twenty-eighth connecting electrode 428 onto the substrate can be approximately E-shaped. The 28th connecting electrode 428 can be connected to the active layer 210 of the 10th P-type transistor Tp_10 through three 14th vias V14 and three 16th vias V16 aligned along the first direction D1, and can also be connected to the bottom gate 351 of the 11th N-type transistor Tn_11 through the 34th via V34, and can also be connected to the gate 311 of the 11th P-type transistor Tp_11 through the 33rd via V33, and can also be connected to the active layer 230 of the 10th N-type transistor Tn_10 through three 57th vias V57 and three 59th vias V59 aligned along the first direction D1, and can also be connected to the top gate 331a of the 11th N-type transistor Tn_11 through the 77th via V77, and can also be connected to the top gate 331b of the 11th N-type transistor Tn_11 through the 78th via V78.

[0238] In some examples, the orthographic projection of the twenty-ninth connection electrode 429 onto the substrate is approximately a strip extending along the second direction D2. The twenty-ninth connection electrode 429 can be connected to the second bottom gate connection line 52 via two thirty-sixth vias V36 aligned along the second direction D2. The twenty-ninth connection electrode 429 can subsequently be connected to the second voltage line BG2 located in the fifth conductive layer.

[0239] In some examples, the orthographic projection of the thirtieth connection electrode 430 onto the substrate can be approximately a strip extending along the second direction D2. The thirtieth connection electrode 430 can be connected to the first bottom gate connection line 51 via two thirty-seventh vias V37 aligned along the second direction D2. The thirtieth connection electrode 430 can subsequently be connected to the first voltage line BG1 located on the fifth conductive layer.

[0240] In some examples, the orthographic projection of the thirty-first connection electrode 431 onto the substrate can be a strip extending along the first direction D1. The thirty-first connection electrode 431 can be connected to the active layer 211a of the eleventh P-type transistor Tp_11 via a plurality of (e.g., seven) eighteenth vias V18 aligned along the first direction D1, and can also be connected to the active layer 211b of the eleventh P-type transistor Tp_11 via a plurality of (e.g., seven) twentieth vias V20 aligned along the first direction D1. The thirty-first connection electrode 431 can subsequently be connected to the first power line VH2 located on the fifth conductive layer.

[0241] (9) Forming the sixth insulating layer and the seventh insulating layer. In some examples, a sixth insulating film is deposited on the substrate on which the aforementioned pattern is formed, and the sixth insulating film is patterned by a patterning process to form the sixth insulating layer. Subsequently, a seventh insulating film is coated, and the seventh insulating film is patterned by a patterning process to form the seventh insulating layer.

[0242] Figure 17 is a schematic diagram of a display substrate after the formation of the seventh insulating layer in at least one embodiment of the present disclosure. In some examples, as shown in Figure 17, the seventh insulating layer of the display substrate has multiple vias, such as vias V81 to V100. The seventh and sixth insulating layers within vias V81 to V100 can be removed, exposing a portion of the surface of the fourth conductive layer.

[0243] (10) Forming the fifth conductive layer. In some examples, a fifth conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the fifth conductive film is patterned by a patterning process to form the fifth conductive layer on the seventh insulating layer.

[0244] Figure 18A is a schematic diagram of a display substrate after the formation of the fifth conductive layer according to at least one embodiment of the present disclosure. Figure 18B is a schematic diagram of the fifth conductive layer in Figure 18A. In some examples, as shown in Figures 18A and 18B, the fifth conductive layer of the display substrate may include: multiple signal lines, such as: a first voltage line BG1, a second voltage line BG2, a third voltage line BG3, a first clock signal line CL1, a second clock signal line CL2, a third clock signal line CL3, a fourth clock signal line CL4, a reset control line RST, a first enable control line EN1, a second enable control line EN2, multiple first power lines (such as first power lines VH1a, VH1b, VH1c, VH1d, VH2), multiple second power lines (such as second power lines VL1a, VL1b, and VL2), and a start signal line STV.

[0245] In some examples, multiple signal lines extend along the second direction D2. Along the first direction D1, the first voltage line BG1, the second voltage line BG2, the first power supply line VH1a, the reset control line RST, the second power supply line VL1a, the fourth clock signal line CL4, the second clock signal line CL2, the third clock signal line CL3, the first clock signal line CL1, the first power supply line VH1b, the second power supply line VL1b, the first enable control line EN1, the second enable control line EN2, the first power supply line VH1c, the second power supply line VL1c, the first power supply line VH1d, the first power supply line VH2, the second power supply line VL2, the start signal line STV, and the third voltage line BG3 can be arranged sequentially.

[0246] In some examples, the first voltage line BG1 can be connected to the thirtieth connection electrode 430 via two eighty-first vias V81 aligned along the second direction D2, thus connecting to the first bottom gate connection line. The second voltage line BG2 can be connected to the twenty-ninth connection electrode 429 via two eighty-second vias V82 aligned along the second direction D2, thus connecting to the second bottom gate connection line. The first power line VH1a can be connected to the third connection electrode 403 via the eighty-third via V83, thus connecting to the third P-type transistor Tp_3. The reset control line RST can be connected to the fourth connection electrode 404 via the eighty-fourth via V84, thus electrically connecting to the third P-type transistor Tp_3 and the third N-type transistor Tn_3. The second power line VL1a can be connected to the first connection electrode 401 via the eighty-sixth via V86, and can also be connected to the second connection electrode 402 via the eighty-fifth via V85, thus electrically connecting to the second N-type transistor Tn_2 and the third N-type transistor Tn_3.

[0247] In some examples, the fourth clock signal line CL4 can be connected to the fifth connection electrode 405 of the nth-stage shift register circuit GOA(n) via the eighty-eighth via V88, and can also be connected to the sixth connection electrode of the (n+1)th-stage shift register circuit GOA(n+1). The second clock signal line CL2 can be connected to the sixth connection electrode 406 of the nth-stage shift register circuit GOA(n) via the eighty-seventh via V87, and can also be connected to the fifth connection electrode of the (n+1)th-stage shift register circuit GOA(n+1). The third clock signal line CL3 can be connected to the eighth connection electrode 408 of the nth-stage shift register circuit GOA(n) via the ninetieth via V90, and can also be connected to the seventh connection electrode of the (n+1)th-stage shift register circuit GOA(n+1). The first clock signal line CL1 can be connected to the seventh connection electrode 407 of the nth-stage shift register circuit GOA(n) through the eighty-ninth via V89, and can also be connected to the eighth connection electrode of the (n+1)th-stage shift register circuit GOA(n+1).

[0248] In some examples, the first power line VH1b can be connected to the thirteenth connection electrode 413 via the ninety-sixth via V96, thereby achieving an electrical connection with the fourth P-type transistor Tp_4. The second power line VL1b can be connected to the tenth connection electrode 410 via the ninety-first via V91, thereby achieving an electrical connection with the seventh N-type transistor Tn_7 and the eighth N-type transistor Tn_8.

[0249] In some examples, the first enable control line EN1 can be connected to the fourteenth connection electrode 414 of the nth stage shift register circuit GOA(n) via a ninety-five-inch via V95. The second enable control line EN2 can be connected to the fourteenth connection electrode of the (n+1)th stage shift register circuit GOA(n+1).

[0250] In some examples, the first power line VH1c can be connected to the eleventh connecting electrode 411 via the ninety-second via V92, achieving electrical connection with the eighth P-type transistor Tp_8 and the ninth P-type transistor Tp_9. The second power line VL1c can be connected to the twenty-seventh connecting electrode 427 via the ninety-fourth via V94, achieving electrical connection with the ninth N-type transistor Tn_9, the tenth N-type transistor Tn_10, and the capacitor. The first power line VH1d can be connected to the twelfth connecting electrode 412 via the ninety-third via V93, achieving electrical connection with the tenth P-type transistor Tp_10. The first power line VH2 can be connected to the thirty-first connecting electrode 431 via the hundredth via V100, achieving electrical connection with the eleventh P-type transistor Tp_11. The second power line VL2 can be connected to the fifteenth connecting electrode 415 via the ninety-seventh via V97, and also to the seventeenth connecting electrode 417 via the ninety-ninth via V99, achieving electrical connection with the eleventh N-type transistor Tn_11.

[0251] In some examples, the third voltage line BG3 can be connected to the nineteenth connection electrode 419 via the ninety-eighth via V98, thereby achieving an electrical connection to the bottom gate 351 of the eleventh N-type transistor Tn_11.

[0252] In some examples, the potentials of the first power signals provided by the first power lines VH1a, VH1b, VH1c, and VH1d can be the same, while the potential of the first power signal provided by the first power line VH2 can be different from the potentials of the first power signals provided by the first power lines VH1a, VH1b, VH1c, and VH1d; for example, the potential of the first power signal provided by the first power line VH2 can be greater than the potentials of the first power signals provided by the first power lines VH1a, VH1b, VH1c, and VH1d.

[0253] In some examples, the potentials of the second power signals provided by the second power lines VL1a and VL1b can be the same, while the potential of the second power signal provided by the second power line VL2 can be different from the potentials of the second power signals provided by the second power lines VL1a and VL1b; for example, the potential of the second power signal provided by the second power line VL2 can be lower than the potentials of the second power signals provided by the second power lines VL1a and VL1b.

[0254] In this example, the eleventh N-type transistor Tn_11 is located in the rightmost region of the shift register circuit. The bottom gate 351 of the eleventh N-type transistor Tn_11 located in the second conductive layer can be connected to the third voltage line BG3 located in the rightmost region of the fifth conductive layer. The threshold voltage of the eleventh N-type transistor Tn_11 can be adjusted independently through the third voltage line BG3, thereby improving the output stability.

[0255] In this example, the bottom gate of the tenth N-type transistor Tn_10 of the nth-stage shift register circuit GOA(n) can be connected to the bottom gates of the second, seventh, and eighth N-type transistors of the (n+1)th-stage shift register circuit GOA(n+1) via a first bottom gate connection line extending along the first direction D1. The first bottom gate connection line can be connected to the leftmost first voltage line BG1 located within the fifth conductive layer. In some examples, the bottom gates of the second, seventh, and eighth N-type transistors of the first-stage shift register circuit can be connected via a single first bottom gate connection line. This example allows setting the threshold voltage of the oxide transistor, which independently affects the long-term on-state, via the first voltage line BG1, thereby improving transistor stability.

[0256] In this example, the bottom gates of the ninth N-type transistor Tn_9, the third N-type transistor Tn_3, the fourth N-type transistor Tn_4, and the sixth N-type transistor Tn_6 in any stage of the shift register circuit are connected via a third bottom gate connection line. They can also be connected to the second voltage line BG2 located in the left region within the fifth conductive layer via a second bottom gate connection line. The third bottom gate connection line can pass through the middle of the second NOR gate and the third transmission gate, and also through the middle of the second transmission gate and the first NOT gate. This example allows setting the threshold voltage of the oxide transistor, which independently affects the long-term off-state, via the second voltage line BG2, thereby improving transistor stability.

[0257] In this example, the bottom gate of the oxide transistor is located on the second conductive layer. Under the premise of ensuring that the bottom gate of the corresponding transistor is connected to the same signal, the transposition connection on the fourth conductive layer can be avoided by lateral routing, reducing the parasitic capacitance between it and other traces (such as traces on the fifth conductive layer), and also avoiding routing and reducing the trace length.

[0258] In some examples, pixel circuits can be formed in the display area simultaneously with the formation of the shift register circuit on the display substrate. For example, the first semiconductor layer of the display area may include: the active layer of the P-type transistor of the pixel circuit; the first conductive layer of the display area may include: the gate of the P-type transistor of the pixel circuit and the first electrode of the storage capacitor; the second conductive layer of the display area may include: the second electrode of the storage capacitor of the pixel circuit and the bottom gate of the N-type transistor; the second semiconductor layer of the display area may include: the active layer of the N-type transistor of the pixel circuit; the third conductive layer of the display area may include: the top gate of the N-type transistor of the pixel circuit; the fourth conductive layer of the display area may include at least: the connection electrodes of the plurality of transistors of the pixel circuit; and the fifth conductive layer of the display area may include at least: data lines and power lines connected to the pixel circuit. This embodiment is not limited in this respect.

[0259] In some examples, the first, second, third, fourth, and fifth conductive layers can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). These can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The first, second, third, fourth, and fifth insulating layers can be made of any one or more of silicon oxide (SiOx, x>0), silicon nitride (SiNy, y>0), and silicon oxynitride (SiON). These can be single-layer, multi-layer, or composite layers. The sixth and seventh insulating layers can be made of organic materials such as polyimide, acrylic, or polyethylene terephthalate. However, this embodiment is not limited in this regard.

[0260] The structure and its fabrication process shown in this exemplary embodiment are merely illustrative. In some exemplary embodiments, the corresponding structure and the patterning process can be modified and added or reduced according to actual needs. The fabrication process of this exemplary embodiment can be implemented using currently mature fabrication equipment, is well compatible with related fabrication processes, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0261] The display substrate provided in this exemplary embodiment, based on the implementation of partial refresh, can save the space occupied by the shift register circuit through the layout design of the shift register circuit, which is conducive to realizing a display substrate with a narrow bezel.

[0262] Figure 19 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. As shown in Figure 19, this embodiment provides a display device 91, including a display substrate 910. The display substrate 910 is the display substrate provided in the foregoing embodiments. The display substrate 910 can be an OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device 91 can be any product or component with display function, such as an OLED display device, a watch, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigator. However, this embodiment is not limited to this.

[0263] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0264] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A display substrate, comprising: A substrate and a gate driving circuit disposed on the substrate, the gate driving circuit including a plurality of cascaded shift register circuits, the shift register circuit including: a first group of oxide transistors and a second group of oxide transistors, each group of oxide transistors including at least one oxide transistor; The bottom gate and top gate of each oxide transistor in the first group of oxide transistors are connected, and the bottom gate and top gate of at least one oxide transistor in the first group of oxide transistors are configured to receive a clock signal. The bottom gate and top gate of each oxide transistor in the second group of oxide transistors are independent of each other.

2. The display substrate according to claim 1, wherein, The second group of oxide transistors includes a plurality of oxide transistors, wherein the bottom gate of the plurality of oxide transistors in the second group of oxide transistors is connected to the same voltage line.

3. The display substrate according to claim 1, wherein, The second group of oxide transistors includes: an oxide output transistor and a plurality of oxide switching transistors; the oxide output transistor is directly connected to the output terminal of the shift register circuit; The bottom gate of the oxide output transistor is independently configured from the bottom gate of the plurality of oxide switching transistors; At least some of the oxide switching transistors have their bottom gates connected to the same voltage line.

4. The display substrate according to claim 3, wherein, The plurality of oxide switching transistors in the second group of oxide transistors are divided into a first group of oxide switching transistors and a second group of oxide switching transistors, each group of oxide switching transistors including at least one oxide switching transistor; within one frame, the duty cycle of the first potential of the top gate voltage signal of the oxide switching transistor in the first group of oxide switching transistors is greater than the duty cycle of the first potential of the top gate voltage signal of the oxide switching transistor in the second group of oxide switching transistors. The bottom gate of at least one oxide switching transistor in the first group of oxide switching transistors is connected to the first voltage line; The bottom gate of at least one oxide switching transistor in the second group of oxide switching transistors is connected to the second voltage line; The first voltage line and the second voltage line are configured to provide different voltage signals.

5. The display substrate according to claim 4, wherein, Each group of oxide switching transistors includes multiple oxide switching transistors; at least some of the oxide switching transistors in the first group of oxide switching transistors have a single bottom gate structure, and the multiple oxide switching transistors in the second group of oxide switching transistors have a single bottom gate structure.

6. The display substrate according to claim 1, wherein, In a direction perpendicular to the display substrate, the display substrate includes: a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer disposed on the substrate; The top gates of the plurality of oxide transistors are located in the third conductive layer, the active layers of the plurality of oxide transistors are located in the second semiconductor layer, and the bottom gates of the plurality of oxide transistors are located in the second conductive layer.

7. The display substrate according to claim 1, wherein, The shift register circuit includes: an input shift circuit, a transmission control circuit, and a drive enhancement circuit; The input shift circuit is connected to the first clock terminal, the second clock terminal, the third clock terminal, the fourth clock terminal, the input terminal of the shift register circuit, the reset control terminal, the first intermediate node, and the second intermediate node, respectively, and is configured to connect the first clock terminal, the second clock terminal, the third clock terminal, the fourth clock terminal, and the shift register circuit. Under the control of the input terminal and the reset control terminal, the potentials of the first intermediate node and the second intermediate node are controlled; The transmission control circuit is connected to the first intermediate node, the second intermediate node, the enable control terminal and the drive enhancement circuit respectively, and is configured to provide an output signal to the drive enhancement circuit under the control of the first intermediate node, the second intermediate node and the enable control terminal. The drive enhancement circuit is connected between the output terminals of the transmission control circuit and the shift register circuit, and is configured to invert the output signal provided by the transmission control circuit at least once and then output it to the output terminal of the shift register circuit. The input shifting circuit, the transmission control circuit, and the drive enhancement circuit are arranged sequentially along the first direction in the orthogonal projection of the substrate.

8. The display substrate according to claim 7, wherein, The input shift circuit includes: a first NOR gate, a first NOT gate, a first transmission gate, and a second transmission gate. The first transmission gate circuit is connected to the first clock terminal, the second clock terminal, the input terminal and the input node of the shift register circuit, and is configured to control the on / off state of the input terminal and the input node of the shift register circuit under the control of the first clock terminal and the second clock terminal; The second transmission gate circuit is connected to the third clock terminal, the fourth clock terminal, the input node, and the second intermediate node, and is configured to control the on / off state of the input node and the second intermediate node under the control of the third clock terminal and the fourth clock terminal; The first NOR gate is connected to the input node, the reset control terminal, and the first intermediate node, and is configured to control the potential of the first intermediate node under the control of the input node and the reset control terminal; The first NOT gate is connected between the first intermediate node and the second intermediate node; The first transmission gate circuit, the second transmission gate circuit, and the first NOT gate circuit are arranged sequentially along the second direction in the orthogonal projection of the substrate, and are located between the first NOR gate circuit and the transmission control circuit in the orthogonal projection of the substrate in the first direction; the second direction intersects the first direction.

9. The display substrate according to claim 8, wherein, The first transmission gate circuit includes: a first P-type transistor and a first N-type transistor; the gate of the first P-type transistor is connected to the second clock terminal; the top gate and bottom gate of the first N-type transistor are connected and connected to the first clock terminal; the first terminals of the first P-type transistor and the first terminals of the first N-type transistor are both connected to the input terminal of the shift register circuit, and the second terminals of the first P-type transistor and the second terminals of the first N-type transistor are both connected to the input node. The second transmission gate circuit includes: a fifth P-type transistor and a fifth N-type transistor; the gate of the fifth P-type transistor is connected to the fourth clock terminal; the top gate and bottom gate of the fifth N-type transistor are connected, and are also connected to the third clock terminal; the first terminals of the fifth P-type transistor and the fifth N-type transistor are both connected to the input node, and the second terminals of the fifth P-type transistor and the fifth N-type transistor are both connected to the second intermediate node. The first P-type transistor and the first N-type transistor are aligned along the first direction when projected onto the substrate; the fifth P-type transistor and the fifth N-type transistor are aligned along the first direction when projected onto the substrate. The first P-type transistor and the fifth P-type transistor are aligned along the second direction when projected onto the substrate; the first N-type transistor and the fifth N-type transistor are aligned along the second direction when projected onto the substrate.

10. The display substrate according to claim 8, wherein, The transmission control circuit includes: a second NOR gate circuit, a third transmission gate circuit, and a capacitor; The third transmission gate circuit is connected to the first intermediate node, the second intermediate node, the enable control terminal, the first input terminal of the second NOR gate circuit, and the capacitor, and is configured to control the on / off state of the enable control terminal and the first input terminal of the second NOR gate circuit under the control of the first intermediate node and the second intermediate node. The second input terminal of the second NOR gate is connected to the second intermediate node, and the output terminal of the second NOR gate is connected to the drive enhancement circuit. The second NOR gate and the third transmission gate are arranged sequentially along the second direction in the orthographic projection of the substrate, and the orthographic projection of the third transmission gate on the substrate is located between the orthographic projections of the capacitor and the first NOT gate on the substrate in the first direction.

11. The display substrate according to claim 10, wherein, The driving enhancement circuit includes: a second NOT gate circuit, a third NOT gate circuit, and a fourth NOT gate circuit connected in series; the second NOT gate circuit, the third NOT gate circuit, and the fourth NOT gate circuit are arranged sequentially along the first direction in the orthographic projection of the substrate. The orthographic projection of the second NOT gate on the substrate is adjacent to the orthographic projection of the capacitor on the substrate in the second direction, and the orthographic projection of the capacitor on the substrate is located between the orthographic projections of the third transmission gate and the third NOT gate on the substrate in the first direction.

12. The display substrate according to claim 11, wherein, The first NOR gate circuit includes: a second P-type transistor, a third P-type transistor, a second N-type transistor, and a third N-type transistor; the gate of the third P-type transistor and the top gate of the third N-type transistor are connected to the reset control terminal; the gate of the second P-type transistor and the top gate of the second N-type transistor are connected to the input node; the first terminal of the third P-type transistor is connected to the first power supply terminal; the second terminal of the third P-type transistor is connected to the first terminal of the second P-type transistor; the second terminals of the second P-type transistor, the second terminals of the second N-type transistor, and the second terminals of the third N-type transistor are connected to the first intermediate node; and the first terminals of the second N-type transistor and the third N-type transistor are connected to the second power supply terminal. The second NOR gate circuit includes: a seventh P-type transistor, an eighth P-type transistor, a seventh N-type transistor, and an eighth N-type transistor; the gate of the eighth P-type transistor and the top gate of the eighth N-type transistor are connected to the third transmission gate circuit; the gate of the seventh P-type transistor and the top gate of the seventh N-type transistor are connected to the second intermediate node; the first terminal of the eighth P-type transistor is connected to the first power supply terminal; the second terminal of the eighth P-type transistor is connected to the first terminal of the seventh P-type transistor; the second terminals of the seventh P-type transistor, the seventh N-type transistor, and the eighth N-type transistor are connected as the output terminal of the second NOR gate circuit; the first terminals of the seventh N-type transistor and the eighth N-type transistor are both connected to the second power supply terminal. The third transmission gate circuit includes: a sixth P-type transistor and a sixth N-type transistor, the gate of the sixth P-type transistor is connected to the second intermediate node, the top gate of the sixth N-type transistor is connected to the first intermediate node, the first terminal of the sixth P-type transistor and the first terminal of the sixth N-type transistor are connected to the enable control terminal, and the second terminal of the sixth P-type transistor and the second terminal of the sixth N-type transistor are connected to the gate of the eighth P-type transistor of the second NOR gate circuit. The first NOT gate circuit includes: a fourth P-type transistor and a fourth N-type transistor, wherein the gate of the fourth P-type transistor and the top gate of the fourth N-type transistor are connected to the first intermediate node, the first terminal of the fourth P-type transistor is connected to the first power supply terminal, the second terminal of the fourth P-type transistor and the second terminal of the fourth N-type transistor are connected to the second intermediate node, and the first terminal of the fourth N-type transistor is connected to the second power supply terminal. The second NOT gate circuit includes a ninth P-type transistor and a ninth N-type transistor. The gate of the ninth P-type transistor and the top gate of the ninth N-type transistor are connected to the output terminal of the second NOR gate circuit. The first terminal of the ninth P-type transistor is connected to a first power supply terminal, and the first terminal of the ninth N-type transistor is connected to a second power supply terminal. The second terminal of the ninth P-type transistor and the second terminal of the ninth N-type transistor are connected to serve as the output terminal of the second NOT gate circuit. The third NOT gate circuit includes: a tenth P-type transistor and a tenth N-type transistor. The gate of the tenth P-type transistor and the top gate of the tenth N-type transistor are connected to the output terminal of the second NOT gate circuit. The first terminal of the tenth P-type transistor is connected to the first power supply terminal. The first terminal of the tenth N-type transistor is connected to the second power supply terminal. The second terminals of the tenth P-type transistor and the second terminals of the tenth N-type transistor are connected to serve as the output terminal of the third NOT gate circuit. The bottom gates of the second N-type transistor, the seventh N-type transistor, the eighth N-type transistor, and the tenth N-type transistor are connected to the first voltage line; The bottom gates of the third N-type transistor, the fourth N-type transistor, the sixth N-type transistor, and the ninth N-type transistor are connected to the second voltage line; the first voltage line and the second voltage line are configured to provide different voltage signals.

13. The display substrate according to claim 12, wherein, The bottom gates of the second N-type transistor, the seventh N-type transistor, and the eighth N-type transistor in any level shift register circuit are integrated into a single structure.

14. The display substrate according to claim 13, wherein, The bottom gate of the tenth N-type transistor of the nth-stage shift register circuit is connected to the bottom gates of the second N-type transistor, the seventh N-type transistor, and the eighth N-type transistor of the (n+1)th-stage shift register circuit via a first bottom gate connection line; the first bottom gate connection line is a broken line extending along the first direction in the orth projection of the nth-stage shift register circuit and the (n+1)th-stage shift register circuit on the orth projection of the substrate, where n is a positive integer.

15. The display substrate according to claim 12, wherein, The bottom gates of the third N-type transistor and the fourth N-type transistor in any level shift register circuit are integrated into a single structure, and the integrated structure is connected to the bottom gates of the sixth N-type transistor and the ninth N-type transistor in the shift register circuit through the third bottom gate connection line. The third bottom gate connection line is projected onto the substrate in the form of a broken line extending along the first direction, and is located between the third transmission gate circuit and the second NOR gate circuit of the shift register circuit in the projection onto the substrate, and between the second transmission gate circuit and the first NOT gate circuit in the projection onto the substrate.

16. The display substrate according to claim 12, wherein, The third P-type transistor, the second P-type transistor, and the second N-type transistor are arranged in a stepped manner on the substrate with their orthogonal projections along the second direction, and the second N-type transistor and the third N-type transistor are aligned and arranged with their orthogonal projections on the substrate along the second direction. The third N-type transistor and the fourth N-type transistor are aligned along the first direction when projected onto the substrate; the fourth P-type transistor is located on the side of the substrate away from the projection of the third N-type transistor onto the substrate in the first direction when projected onto the substrate.

17. The display substrate according to claim 12, wherein, The sixth N-type transistor and the sixth P-type transistor are aligned along the first direction when projected onto the substrate. The seventh N-type transistor and the eighth N-type transistor are aligned and arranged along the first direction when projected onto the substrate. The sixth N-type transistor and the seventh N-type transistor are aligned along the second direction when projected onto the substrate, and the sixth P-type transistor and the eighth N-type transistor are aligned along the second direction when projected onto the substrate. The seventh P-type transistor and the eighth P-type transistor are arranged sequentially along the first direction in the orthogonal projection of the substrate.

18. The display substrate according to claim 12, wherein, The ninth P-type transistor and the tenth N-type transistor are arranged sequentially along the first direction by their orthogonal projections onto the substrate. The ninth N-type transistor and the ninth P-type transistor are staggered along the second direction when projected onto the substrate. The tenth N-type transistor and the tenth P-type transistor are aligned along the second direction when projected onto the substrate.

19. The display substrate according to claim 12, wherein, The fourth NOT gate circuit includes an eleventh N-type transistor and an eleventh P-type transistor; the gate of the eleventh P-type transistor and the top gate of the eleventh N-type transistor are connected to the output terminal of the third NOT gate circuit, the first terminal of the eleventh P-type transistor is connected to the first power supply terminal, the first terminal of the eleventh N-type transistor is connected to the second power supply terminal, and the second terminals of the eleventh P-type transistor and the eleventh N-type transistor are connected to the output terminal of the shift register circuit. The bottom gate of the eleventh N-type transistor is connected to the third voltage line; The eleventh N-type transistor and the eleventh P-type transistor are aligned and arranged along the second direction when projected onto the substrate. The orthographic projections of the eleventh N-type transistor and the tenth P-type transistor on the substrate are adjacent in the first direction, and the orthographic projections of the eleventh P-type transistor and the tenth N-type transistor on the substrate are adjacent in the first direction.

20. The display substrate according to claim 19, wherein, The first voltage line, the second voltage line, and the third voltage line are located in the same conductive layer; The orthogonal projection of the third voltage line onto the substrate is located on the side of the eleventh N-type transistor away from the tenth P-type transistor in the first direction; The orthogonal projections of the first voltage line and the second voltage line onto the substrate are located on the side of the input shift circuit away from the transmission control circuit in the first direction.

21. A display device, comprising a display substrate as claimed in any one of claims 1 to 20.

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