Scalable fault-tolerant quantum architectures using erasure qubits

Abstract

A system and method for providing a fault tolerant quantum computer that is implemented using erasure qubits is disclosed. Erasure qubits provide flexibility in terms of mapping of different energy states such that computational basis states of a qubit may be mapped to two energy states of the system and such that detection of amplitude damping decay events may be heralded. By additionally implementing periodic erasure qubit checks and conditional and / or unconditional erasure qubit resets during an overall process of performing a quantum circuit using such a quantum computer, erasure errors can be detected and corrected mid-performance, therefore ensuring that a decoding process that is completed post-performance results in higher gate fidelity.

Description

SCALABLE FAULT-TOLERANT QUANTUM ARCHITECTURES USING ERASURE QUBITS BACKGROUND Background of the Invention

[0001] Quantum computing utilizes the laws of quantum physics to process information. Quantum physics is a theory that describes the behavior of reality at the fundamental level. It is currently the only physical theory that is capable of consistently predicting the behavior of microscopic quantum objects like photons, molecules, atoms, and electrons.

[0002] A quantum computer is a device that utilizes quantum physics to allow one to write, store, process and read out information encoded in quantum states, e.g., the states of quantum objects. A quantum object is a physical object that behaves according to the laws of quantum physics. The state of a physical object is a description of the object at a given time.

[0003] In quantum physics, the state of a two-level quantum system, or simply, a qubit, is a list of two complex numbers whose squares sum up to one. Each of the two numbers is called an amplitude, or quasi-probability, and their squared absolute values are probabilities that a measurement of the qubit results in zero or one. A fundamental and counterintuitive difference between a probabilistic bit (e.g., a classical zero or one bit) and the qubit is that a probabilistic bit represents a lack of information about a two-level classical system, while a qubit contains maximal information about a two-level quantum system.

[0004] Quantum computers are based on such quantum bits (qubits), which may experience the phenomena of “superposition” and “entanglement.” Superposition allows a quantum system to be in multiple states at the same time. For example, whereas a classical computer is based on bits that are either zero or one, a qubit may be both zero and one at the same time, with different probabilities assigned to zero and one. Entanglement is a strong correlation between quantum systems, such that the quantum systems are inextricably linked even if separated by great distances.

[0005] A quantum algorithm comprises a reversible transformation acting on qubits in a desired and controlled way, followed by a measurement on one or multiple qubits. For example, if a system has two qubits, a transformation may modify four numbers; with three qubits this becomes eight numbers, and so on. As such, a quantum algorithm acts on a list of numbers exponentially large as dictated by the number of qubits. To implement a transform, the transform may be decomposed into small operations acting on a single qubit, or a pair of qubits, as an example. Such small operations may be called quantum gates and a specific arrangement of the quantum gates implements a quantum circuit.

[0006] There are different types of qubits that may be used in quantum computers, each having different advantages and disadvantages. For example, some quantum computers may include qubits built from superconductors, trapped ions, semiconductors, photonics, etc. Each may experience different levels of interference, errors and decoherence. Also, some may be more useful for generating particular types of quantum circuits or quantum algorithms, while others may be more useful for generating other types of quantum circuits or quantum algorithms. Also, costs, run-times, error rates, availability, etc. may vary across quantum computing technologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG. 1A illustrates a hardware layout of quantum hardware components that are configured to implement an erasure qubit, according to some embodiments.

[0008] FIG. 1B illustrates an energy state diagram of the quantum hardware components which are shown in FIG.1A, according to some embodiments.

[0009] FIG.2A illustrates another hardware layout of quantum hardware components that are configured to implement an erasure qubit, according to some embodiments.

[0010] FIG. 2B illustrates an energy state diagram of the quantum hardware components which are shown in FIG.2A, according to some embodiments.

[0011] FIG. 3 illustrates an example quantum circuit being performed between two erasure qubits, wherein the steps include at least a reset (e.g., initialization) step of the erasure qubits, performance of one or more quantum gates between the two erasure qubits, and performance of readout step of quantum superposition states of the two erasure qubits, according to some embodiments.

[0012] FIG.4 illustrates an example of a surface code that may be implemented using erasure qubits, according to some embodiments.

[0013] FIG. 5A illustrates a continuation of an example of a surface code that may be implemented using erasure qubits, according to some embodiments.

[0014] FIGs.5B and 5C illustrate examples of performance of respective rounds of ^^-type and^^-type stabilizer measurements using a surface code, such as that which is shown in FIGs. 4 and5A, and wherein said rounds incorporate periodic erasure checks and / or resets, according to some embodiments.

[0015] FIG. 6A illustrates a continuation of an example of a surface code that may be implemented using erasure qubits, according to some embodiments.

[0016] FIGs. 6B and 6C illustrate additional examples of performance of respective rounds of^^-type and ^^-type stabilizer measurements using a surface code, such as that which is shown inFIGs.4, 5A, and 6A, and wherein said rounds incorporate periodic erasure checks and / or resets, according to some embodiments.

[0017] FIG. 7A illustrates a continuation of an example of a surface code that may be implemented using erasure qubits, according to some embodiments.

[0018] FIGs.7B and 7C illustrate further examples of performance of respective rounds of ^^- type and ^^-type stabilizer measurements using a surface code, such as that which is shown in FIGs. 4, 5A, 6A, and 7A, and wherein said rounds incorporate periodic erasure checks and / or resets, according to some embodiments.

[0019] FIG. 8 illustrates another example of a surface code that may be implemented using dual-rail erasure qubits, according to some embodiments.

[0020] FIG.9 illustrates an example of a Floquet code that may be implemented using dual- rail erasure qubits, according to some embodiments.

[0021] FIG.10 illustrates examples of performance of respective rounds of ^^-type and ^^-type stabilizer measurements using a Floquet code, such as that which is shown in FIG.8, and wherein said rounds incorporate periodic erasure checks and / or resets, according to some embodiments.

[0022] FIG. 11 is a flow chart that illustrates a process of executing quantum computations (e.g., quantum gates) between erasure qubits, and to perform error correction steps for such an architecture, according to some embodiments.

[0023] FIG.12 is a block diagram illustrating an example quantum hardware device that may be configured to execute quantum computations (e.g., quantum gates) between erasure qubits, and to perform error correction steps for such an architecture, according to some embodiments.

[0024] FIG.13 is a block diagram illustrating an example classical computing device that may be used in at least some embodiments.

[0025] While embodiments are described herein by way of example for several embodiments and illustrative drawings, those skilled in the art will recognize that embodiments are not limited to the embodiments or drawings described. It should be understood, that the drawings and detailed description thereto are not intended to limit embodiments to the particular form disclosed, but on the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope as defined by the appended claims. The headings used herein are for organizational purposes only and are not meant to be used to limit the scope of the description or the claims. As used throughout this application, the word “may” is used in a permissive sense (i.e., meaning having the potential to), rather than the mandatory sense (i.e., meaning must). Similarly, the words “include,” “including,” and “includes” mean including, but not limited to. When usedin the claims, the term “or” is used as an inclusive or and not as an exclusive or. For example, the phrase “at least one of x, y, or z” means any one of x, y, and z, as well as any combination thereof. DETAILED DESCRIPTION

[0026] The present disclosure relates to methods and apparatus for providing high gate fidelity and fault tolerance for a quantum computer that is implemented using erasure qubits. In embodiments described herein, quantum hardware components that may be used to implement erasure qubits may be configured to allow for quantum computation to be performed between said erasure qubits while also providing heralding signals when amplitude damping decay events have occurred. By optimizing, tuning, and / or implementing periodic erasure checks and erasure qubit resets throughout performance of a quantum circuit, a propagation of logical errors may be avoided and / or minimized, and a decoding process may more efficiently correct for such types of errors.

[0027] Within the noisy intermediate-scale quantum (NISQ) hardware regime, quantum error correction and / or mitigation techniques are faced with the difficult task of developing methods for correcting single and multi-qubit errors, logical errors, and / or additional quantum processing unit (QPU) specific qubit coherence time concerns, crosstalk noise levels, etc. Current quantum error correction and / or mitigation techniques have limited numbers of errors that they may compensate for within performance of a given quantum task. Therefore, ensuring that known sources of leakage from a computational subspace of an erasure qubit, defined by various energy states of the system and according to a given implementation of an erasure qubit, are signaled prior to commencing of a decoding of syndrome measurements provides a larger bandwidth to correct for other unforeseen errors and / or errors that may not be as successfully pre-treated (e.g., errors occurring due to tolerance levels of microwave pulse generators that emit control sequences to influence quantum states of the qubits, etc.), and which occur during execution of various quantum gates of the given quantum computation.

[0028] Therefore, as customers that are utilizing such quantum computing resources may be concerned with repeatability, reliability, and efficiency of quantum task executions, providing quantum hardware devices that are configured to be fault tolerant, such as through the use of erasure qubits and corresponding erasure qubit checks and resets, is of importance. Similarly, a successful and periodic reset of erasure qubits ensures that a next stage in the given quantum computation (e.g., one or more additional quantum gates between such erasure qubits) may proceed without error propagation from the previous stage. Moreover, by performing erasure qubit checks that are implemented using non-destructive measurements, such periodic checks do not interfere with an ongoing round of syndrome extraction for a given stabilizer. For example, and asadditionally described below, an erasure qubit check protocol may be inserted at an intermediate point within a given round of a syndrome extraction circuit for a given stabilizer, but, when performed, does not interfere with entangling gates that are being performed afterwards onto one or more erasure qubits within the given stabilizer, and still within the given round of the syndrome extraction circuit. This is as opposed to a readout measurement step which may be performed at the end of the syndrome extraction circuit, for example, which may be considered herein to be a destructive measurement, according to some embodiments.

[0029] As related to the description herein, it may be understood that quantum hardware, such as quantum hardware devices, may be used to implement quantum computers, and / or various components of quantum computers (e.g., quantum processing units / cores, routing spaces, magic state distillation factories, other components used to perform logical quantum computations, etc.). For example, a given quantum hardware device may resemble “building blocks” of a quantum computer, such as a grid (e.g., a one-dimensional grid, a two-dimensional grid, etc.) of qubits that may be initialized in various ways in order to form various components of a quantum computer, such as topological quantum codes. Quantum hardware devices may be further configured such that single qubit gates, multi-qubit gates, and / or other operations of quantum circuits may be performed between qubits of the quantum hardware devices (according to a given physical qubit connectivity graph of the quantum hardware device which details which physical qubits are connected to respective other physical qubits via edges). Quantum hardware devices may also comprise and / or be connected to various control devices (e.g., microwave pulse generators, devices for temperature, magnetic, and / or other environmental controls pertaining to local environments of the physical qubits, etc.) that may be used to maintain and / or transform various properties of the qubits and / or other physical components of a given quantum computer.

[0030] Moreover, as related to the description herein, a qubit may refer to both a logical bit (e.g., a one or a zero with some probability) and to one or more physical components used to construct the given qubit based, at least in part, on the type of qubit technology being applied. For example, a superconducting qubit, such as a transmon qubit, may be constructed using at least a superconducting material and a non-superconducting material in which the non-superconducting material is located in between sections of superconducting material (see also description herein pertaining to quantum hardware components used to implement an erasure qubit). With regard to this understanding, it should also be understood that quantum hardware may therefore be used to implement physical qubits, in ways such as those as described above, that may again be combined in various ways to implement one or more logical qubits such that logical quantum operations may be performed using said physical elements of said quantum hardware. Further examples ofinteractions between hardware layouts of quantum hardware devices and associated classical measurement and control devices are discussed with regard to at least FIG.12 herein.

[0031] FIG. 1A illustrates a hardware layout of quantum hardware components that are configured to implement an erasure qubit, according to some embodiments.

[0032] As shown in FIG. 1A, an erasure qubit may be implemented using a single superconducting qubit, such as transmon 102, according to some embodiments. Transmon 102 may include a capacitor and a Josephson junction that are arranged in parallel, and, when applied using various techniques such as those described herein, may be used to define computational basis states of an erasure qubit.

[0033] In some embodiments, a hardware layout such as quantum hardware components 100, which may be used to implement an erasure qubit using methods described herein, may more specifically implement a “^^-^^” type erasure qubit (see also the illustration of energy states 154 in FIG.1B).

[0034] FIG. 1B illustrates an energy state diagram of the quantum hardware components which are shown in FIG.1A, according to some embodiments.

[0035] As shown in FIG.1B, various energy states of transmon 102 may be logically mapped such that computational basis states of an erasure qubit may be defined, as illustrated using energy states 154 in the figure, and such that an additional energy state as illustrated using energy state 152 in the figure, may be mapped for heralding detection of amplitude-damping type errors. In some embodiments, energy state 152 may be used to detect leakage outside of the computational basis states of the erasure qubit, defined by energy states 154, at various moments during performance of quantum circuit (see also an example of a quantum circuit in FIG.3 herein).

[0036] For example, energy states 154 may be logically mapped to computational basis states|0^ and |1^ of the erasure qubit such that a ground state of transmon 102 is mapped to |^^^ = |0^and a second excited state of transmon 102 is mapped to |^^^ = |1^. However, additional logicalmappings that allow for an implementation of an erasure qubit using quantum hardware components 100 are also meant to be encompassed in the discussion herein. Furthermore, and continuing with example embodiments such as those shown in FIG. 1B, a first excited state of transmon 102,|^^^, may be logically mapped as an energy state used to detect amplitude-damping type errors.

[0037] FIG.2A illustrates another hardware layout of quantum hardware components that are configured to implement an erasure qubit, according to some embodiments.

[0038] As shown in FIG. 2A, an erasure qubit may be implemented using multiple superconducting qubits that are capacitively coupled together, such as capacitively coupledtransmons 202 and 204, according to some embodiments. In some embodiments, a hardware layout such as quantum hardware components 200, which may be used to implement an erasure qubit using methods described herein, may more specifically implement a “dual-rail” type erasure qubit.

[0039] FIG. 2B illustrates an energy state diagram of quantum hardware components which are shown in FIG.2A, according to some embodiments.

[0040] As shown in FIG.2B, various energy states of a system defined by capacitively coupled transmons 102 and 104 may be logically mapped such that computational basis states of an erasure qubit may be defined, as illustrated using energy states 254 in the figure, and such that an additional energy state, as illustrated using energy state 252 in the figure, may be mapped for heralding detection of amplitude-damping type errors.

[0041] For example, energy states 254 of a system defined by capacitively coupled transmons 202 and 204 may be logically mapped to computational basis states |0^ and |1^ of the erasure qubitsuch that an energy state |^^^^ − ^^^^^ is mapped to |0^, and such that a higher energy state |^^^^ + ^^^^^is mapped to|1^. However, additional logical mappings that allow for an implementation of an erasure qubit using quantum hardware components 200 are also meant to be encompassed in the discussion herein. Furthermore, and continuing with example embodiments such as those shown in FIG. 2B, a ground state of a system defined by capacitively coupled transmons 202 and 204, namely energy state 252 defined as|^^^^^in the figure, may be mapped as an energy state used to detect amplitude-damping type errors.

[0042] In some embodiments, quantum hardware components that may be used to implement erasure qubits, such as those shown in FIGs.1A – 2B, may additionally be configured to enable a large erasure noise bias. A large erasure noise bias may be defined herein as, for a given erasure qubit implemented using quantum hardware components, a ratio of the probability of an erasure to the probability of other residual error(s) within the computational subspace bounded by the mapped computational basis states of the energy state diagram that corresponds to the given erasure qubit. In some embodiments, the large erasure noise bias may be inherent due to the particular configuration of quantum hardware components, while in other embodiments, the quantum hardware components may particularly enable and / or be engineered to establish and preserve the large erasure noise bias. As additionally discussed with regard to quantum circuit 300 herein, the large erasure noise bias is preserved throughout performance of rounds of syndrome extraction, which respectively include quantum state preparation (see resets 306 and 308), various unitary gates (see quantum gates 310 and 320), and readout measurements (see readout 312 and 314).

[0043] In some embodiments in which physical quantum hardware components, such as those shown in FIGs.1A and 2A, are used to implement erasure qubits, quantum hardware components 100 and 200 may also be referred to herein as the “unit cell” for a larger quantum processing unit. Such a unit cell may then be repeated to scale up such hardware configurations to quantum processing units (QPUs), quantum computers, or other such quantum devices for computation (see also description herein regarding FIG. 12, wherein a “unit cell” illustrated in FIGs. 1A and 2A may be repeated multiple times within quantum processing core 1220).

[0044] In some embodiments, an erasure event may resemble a heralded signal that may be used to interpret that the corresponding qubit is not to be considered during a process of decoding of syndrome measurements in a matching graph for a quantum low-density parity-check code. For example, in a minimum weight perfect matching (MWPM) graph, data edges for qubits that are associated with a heralding event may be erased, or weighted differently (e.g., given less weight with respect to other redundant erasure qubits that did not have corresponding heralding signals, meaning that no amplitude-damping decay event has occurred for said other qubits) with the knowledge that they are likely to have been affected by amplitude damping decay, as indicated by said heralding signal.

[0045] In some embodiments, the one or more heralding signals may be described by an amplitude damping channel, ^^, wherein ^^ is defined as a quantum channel within a generalized form of a quantum channel, ^^, and its Kraus operators^^^^^^, such that an action of ^^ on a densitymatrix ^^ is:^^^^^^ = ∑ †^ ^^^^^^^^ .

[0046] In some embodiments of a two-level system, for example, ^^ is defined as thefollowing:

[0047] In some embodiments of a three-level system, for example, ^^ is defined as thefollowing, wherein ^^^^, ^^^ଶ, and ^^^ଶ describe the probabilities of an amplitude damping decayevent occurring between levels 0 and 1, 1 and 2, or 0 and 2, respectively:

[0048] Furthermore, in some embodiments, a probability of decaying between levels 0 and 1 or 1 and 2 of a given set of energy states of a system described by FIGs.1A – 2B, are equal, suchthat the symmetrized amplitude damping channel, ^^ᇱଷ , is defined as:^^ᇱଷ = ^^1 − ^^|0^^0| + ^1 − 2^^|1^^1| +^1 − ^^|2^^2|, √^^|0^^1|, √^^|1^^2|, √^^|1^^0|, √^^|2^^1|^.

[0049] In some embodiments, a process of checking that the erasure event has occurred (e.g., during a decoding process) may be described by the following paragraphs.

[0050] In some embodiments, an erasure event may be diagnosed by performing a two- outcome positive operator valued measurement. An erasure event may be confirmed as having occurred when the outcome of the two-outcome positive operator valued measurement is 1, according to some embodiments. An erasure event is confirmed to not have occurred when the outcome of the two-outcome positive operator valued measurement is 0, according to some embodiments.

[0051] In some embodiments, such as in that which is shown in FIGs. 1A and 1B, a two- outcome positive operator valued measurement may be performed onto an erasure qubit that has been encoded into a single three-level system, which may be referred to as single-qutrit code. Insuch embodiments, a corresponding mapping comprises:ℰ^: |0^ ↦ |0^, |1^ ↦ |2^.An erasure channel according to such mapping is then defined as:^^ᇱଷ ∘ ℰ^^^^ = ^1 − ^^^ℰ^^^^ + ^^|1^^1|.In such embodiments, the two-outcome positive operator valued measurement is defined as the following, wherein a measurement outcome of 0 corresponds to ^^^and a measurement outcomeof 1 corresponds towhich is defined as ^^^ subtracted from identity matrix I:^^^ = |0^^0| + |2^^2|,^^^ = ^^ − ^^^.

[0052] In some embodiments, a two-outcome positive operator valued measurement may be performed onto an erasure qubit that has been encoded into two three-level systems, which may be referred to as a double-qutrit code. In some embodiments, a corresponding mapping thereforecomprises:ℰ^: |0^ ↦ |+ +^, |1^ ↦ |− −^, wherein ±^ = |0^ ± |2^.An erasure channel according to such mapping is then defined as:In such embodiments, the two-outcome positive operator valued measurement is defined as the following, wherein a measurement outcome of 0 corresponds to ^^^and a measurement outcomeof 1 corresponds towhich is defined as ^^^ subtracted from identity matrix I:^^^ = |0^^0| + |2^^2|,^^^ = ^^ − ^^^.

[0053] In some embodiments, such as in that which is shown in FIGs. 2A and 2B, a two- outcome positive operator valued measurement may be performed onto a qubit that has beenencoded into two two-level systems, which may be referred to as quantum dual-rail code. Acorresponding mapping therefore comprises:ℰ: |0^ ↦ |01^, |1^ ↦ |10^.An erasure channel according to such mapping is then defined as:In such embodiments, the two-outcome positive operator valued measurement may be defined as the following, wherein a measurement outcome of 0 corresponds to ^^^and a measurementoutcome of 1 corresponds towhich is defined as ^^^ subtracted from identity matrix I:^^^ = |01^^01| + |10^^10|,

[0054] FIG. 3 illustrates an example quantum circuit being performed between two erasure qubits, wherein the steps include at least a reset (e.g., initialization) step of the erasure qubits, performance of one or more quantum gates between the two erasure qubits, and performance of readout step of quantum superposition states of the two erasure qubits, according to some embodiments.

[0055] In some embodiments, performance of a quantum gate on an erasure qubit may influence a quantum state of the erasure qubit with respect to how the quantum state was initialized during reset and prior to performance of the quantum gate, due to a logical quantum operation that is being performed on the erasure qubit for a duration of the gate. Therefore, in order to extract quantum states of such erasure qubits following performance of the gate, readout may be performed by coupling a quantum hardware layout such as those shown in quantum hardware components 100 and 200 to a classical measurement device, according to some embodiments. Performance of quantum gates followed by readout and reset of the corresponding qubits may be portioned into rounds, and a number of rounds may be performed until an overall quantum circuit, algorithm, or other computation has been completed.

[0056] As shown in FIG.3, quantum circuit 300 involves two erasure qubits, such as erasure qubits 302 and 304. A first timestep of quantum circuit 300 may resemble reset 306 and 308, wherein erasure qubits 302 and 304 are initialized into some arbitrary quantum state, such as the ground state. In some embodiments, the ground state of the respective erasure qubits may be represented by |0^ or by |^^^ when mapped to a computational basis state of a given qubit, as additionally shown in FIGs.1B and 2B with regard to the respective energy states in energy state diagrams 150 and 250. Furthermore, reset 306 and 308 may occur simultaneously or sequentially, depending upon various embodiments of quantum circuit execution instructions provided to a quantum hardware device and used for execution of quantum circuit 300.

[0057] Following initialization of erasure qubits 302 and 304, one or more quantum gates 310 may be performed using erasure qubits 302 and 304. In some embodiments, one or more of quantum gates 310 may include a two-qubit quantum gate that is performed using both erasure qubits 302 and 304 (e.g., a CNOT gate, a CZ gate, a CX gate, a SWAP gate, any other entangling gate, etc.). In other embodiments, one or more of quantum gates 310 may include two separate single-qubit gates that are respectively performed using erasure qubits 302 and 304 (e.g., Pauli-X, -Y, or -Z gates, a Hadamard gate, a Phase gate, etc.). In yet other embodiments, one or more quantum gates 310 may include combinations of single and / or multi-qubit quantum gates that are performed using erasure qubits 302 and 304. Furthermore, single and / or multi-qubit quantum gates that are performed during a block represented by one or more quantum gates 310 resemble logical quantum operations that may influence quantum states of erasure qubits 302 and 304, and, therefore, a next timestep of quantum circuit 300 may involve performance of readout in order to detect those influences to the quantum states.

[0058] According to various implementations of some embodiments described herein, readouts 312 and 314 may refer to moments in time when erasure qubit check protocols are performed, such as at an intermediate step within a given round of a syndrome extraction circuit for a given stabilizer (see also surface code 400, blocks 502 – 540, blocks 552 – 590, etc.), or to when readouts of quantum states are performed, such as at the conclusion of a given round of a syndrome extraction circuit for a given stabilizer (see also surface code 400 and also FIGs.5B and 5C, 6B and 6C, and 7B and 7C for additional illustrations pertaining to stabilizers and syndrome extraction circuits for various types of stabilizers).

[0059] In a first example, readouts 312 and 314 may refer to an intermediate step within a given round of a syndrome extraction circuit for a given stabilizer, as introduced in the proceeding paragraph, which is referred to herein as an erasure qubit check protocol. In such an example, an erasure qubit check protocol may refer to repeated parity measurements, or any other quantum non-destructive (QND) measurements, which allow for detection of amplitude damping decay events that are measured indirectly and without collapsing a quantum state of the erasure qubit. If a heralding signal indicates that a current energy state of the erasure qubit has moved from the energy states that are mapped to computational basis states of the erasure qubit, such as from energy states 154 to energy state 152, or from energy states 254 to energy state 252, then the erasure qubit check protocol has non-destructively confirmed that an amplitude damping decay event has occurred. If a signal emitted following the erasure qubit check protocol indicates that a current energy state of the erasure qubit is still within the energy states that are mapped to thecomputational basis states of the erasure qubit, then the erasure qubit check protocol has non- destructively confirmed that an amplitude damping decay event has not occurred.

[0060] In a second example, readouts 312 and 314 may refer to when a readout of a quantum state of an erasure qubit, such as at the conclusion of a given round of a syndrome extraction circuit for a given stabilizer, and as introduced in the proceeding paragraph. In such an example, a readout measurement step may refer to repeated ^^ or ^^-based parity measurements (e.g., depending upon a given ^^ or ^^ type of stabilizer that quantum circuit 300 refers to), or any other quantum non- destructive (QND) measurements, or it may refer to destructive measurements, which collapse the quantum state of the erasure qubit.

[0061] Following performance of readouts 312 and 314, erasure qubits 302 and 304 may be reinitialized into the ground state during a next timestep, as shown in FIG.3 with regard to resets 316 and 318. As additionally described above, resets 316 and 318 may occur simultaneously or sequentially. Moreover, and continuing the description above with regard to multiple embodiments of readouts 312 and 314, resets 316 and 318 may refer herein to conditional erasure qubit reset protocols, to unconditional erasure qubit reset protocols, and / or to reset timesteps at the beginning of a subsequent round of a syndrome extraction circuit, such as those illustrated using resets 306 and 308).

[0062] In a first example, and when readouts 312 and 314 refer to erasure qubit check protocols, one or both of erasure qubits 302 and 304 may herald a measurement outcome of the erasure qubit check protocol that indicates that an amplitude damping decay event has occurred on the corresponding qubit. Erasure qubit resets 316 and 318 may then refer to “conditional” erasure qubit reset protocols in this first example, wherein a reinitialization, or not, into the ground state of a given erasure qubit is dependent upon an amplitude damping decay event occurring, or not. As execution of erasure qubit reset protocols 316 and 318 is conditional upon notification that the measurement outcome indicates that the amplitude damping decay event has occurred, the corresponding one or both erasure qubits that heralded the amplitude damping decay event may then be reset to an arbitrary quantum state, such as the ground state. As shown in FIG. 3, boxes enclosing resets 316 and 318 have been bounded by dashed lines in order to additionally encompass embodiments herein in which one, or neither erasure qubit heralds an amplitude damping decay event, in which case the corresponding erasure qubit(s) are not reset, and the overall performance of quantum circuit 300 continues on to one or more additional quantum gates 320. Moreover, as execution of erasure qubit resets 316 and 318 is conditional, in this example, upon a heralding signal indicating that an amplitude damping decay event has occurred, a “conditional” erasure qubit check protocol may also be referred to herein as an “active” erasurequbit check protocol. In addition, the conditional resetting of an erasure qubit based on measurement outcomes of a conditional erasure qubit check protocol may refer to measurement outcomes of a current round, namely round ^^, of a syndrome extraction circuit (e.g., blocks 306 – 318, illustrated in FIG.3), and may also refer to measurement outcomes of a conditional erasurequbit check protocol that was performed during a previous round, namely round ^^ − 1, of asyndrome extraction circuit within an overall performance of quantum circuit 300, according to some embodiments.

[0063] In a second example, and when readouts 312 and 314 refer to erasure qubit check protocols, one or both of erasure qubits 302 and 304 may herald a measurement outcome of the erasure qubit check protocol that indicates that an amplitude damping decay event has occurred on the corresponding qubit. Erasure qubit resets 316 and 318 may refer to “unconditional” erasure qubit reset protocols if and when unconditional erasure qubit reset steps have been pre-configured into an execution of quantum circuit 300, independent of measurement outcomes of readouts 312 and 314. Classical computing devices may determine a frequency and a periodicity of such unconditional erasure qubit reset steps in order to provide additional protection against the propagation of logical errors within an overall execution of quantum circuit 300. In addition, as execution of unconditional erasure qubit reset protocols 316 and 318 is not conditional upon notification that the measurement outcome indicates that the amplitude damping decay event has occurred in this second example, both erasure qubits 302 and 304 are reset to an arbitrary quantum state, such as the ground state. Moreover, as execution of erasure qubit resets 316 and 318 is unconditional, in this example, an “unconditional” erasure qubit check protocol may also be referred to herein as a “passive” erasure qubit check protocol.

[0064] In a third example, and when readouts 312 and 314 marked parity measurements performed at the conclusion of a given round of a syndrome extraction circuit, then resets 316 and 318 refer to reset timesteps at the beginning of a subsequent round of a syndrome extraction circuit, wherein erasure qubits 302 and 304 are reinitialized into their ground states, and the subsequent round of one or more additional quantum gates 320 proceeds.

[0065] As depicted in FIG. 3 with one or more additional quantum gates 320 and the subsequent ellipses, quantum circuit 300 may include two or more rounds of syndrome extraction circuits that are performed using erasure qubits 302 and 304. Furthermore, it may be understood that a given configuration of quantum circuit 300 shown in FIG.3, which includes performance of multiple sets of quantum gates between two erasure qubits, is meant to be illustrative in nature. Additional embodiments of quantum circuits that involve one erasure qubit, or more than two erasure qubits, are also meant to be encompassed in the discussion herein, and may similarly applyto methods for performing quantum computation and error correction using quantum hardware device architectures for implementing erasure qubits described herein.

[0066] FIG.4 illustrates an example of a surface code that may be implemented using erasure qubits, according to some embodiments.

[0067] A surface code, such as surface code 400, may resemble a two-dimensional planar version of the toric code. The code parameters of a surface code, such as surface code 400, maybe defined as ^^^௫^^௭, 1, min^^^௫, ^^௭^^, where ^^௫ and ^^௭ are the distances of minimum-weightrepresentatives of the logical ^^ and ^^ operators of the surface code (which may be referred to asthe ^^ and ^^ distance of the surface code). For example, surface code 400 may be referred to as a^^௫ = ^^௭ = 5 surface code, according to some embodiments. Furthermore, the logical ^ത^ operator402 and logical ^̅^ operator 404 of a surface code may form vertical and horizontal string-like excitations.

[0068] The surface code belongs to the family of Calderbank-Shor-Steane (CSS) codes, wherein ^^-type and ^^-type stabilizers in the bulk of the surface code lattice (which may also referred to as ^^-type and ^^-type “plaquettes” of the surface code lattice) correspond to weight- four operators, and ^^-type and ^^-type stabilizers at the boundary correspond to weight-two operators. Data qubits are placed at vertices of the respective stabilizers, and ancilla qubits are placed at the center of the respective stabilizers, as shown in FIG.4.

[0069] Moreover, surface code 400 is meant to be illustrative in nature. Embodiments wherein surface code 400 comprises more or less X and Z-type stabilizers are also meant to be encompassed in a discussion herein of implementations using erasure qubits, as well as embodiments of single- transmon-type erasure qubits and to dual-rail-type erasure qubits that are implemented into surface codes of various sizes. In addition, and in other embodiments, other 2D topological codes may also be incorporated into the following discussion herein regarding FIGs.4 – 7C, wherein a given 2D topological code may refer to a Floquet code, a 2D toric code on a square lattice with open boundary conditions, a 9-qubit Shor’s code, a surface code with a twist, a XZZX surface code, a rotated surface code, a Pauli code, a color code, and amongst other various topological quantum codes with and without Clifford-deformed variants.

[0070] Furthermore, the reader is meant to refer to Keys within the various figures illustrated in the present disclosure in order to follow a selected convention with regard to which stabilizersare “^^-type” and “^^-type” stabilizers, a first directionality for ^^௫ and a second directionality for^^௭, etc. The selected convention is illustrated for ease of discussion, and is not meant to berestrictive with regard to selection of a different convention of “^^-type” and “^^-type” stabilizers, etc.

[0071] As shown in FIG. 4, surface code 400 may be implemented using erasure qubits, wherein respective ones of the erasure qubits represent data qubits and respective other ones of the erasure qubits represent ancilla qubits (see also the Key shown in FIG.4). To provide consistency across multiple figure descriptions in the present disclosure, it may be understood that erasure qubits 302 and 304 may resemble two erasure qubits within a given stabilizer of surface code 400, such as a data qubit and an ancilla qubit.

[0072] In the following description regarding FIGs. 5A – 7C, three separate examples (e.g., FIGs.5A – 5C, FIGs.6A – 6C, and FIGs.7A – 7C) of gate scheduling sequences that incorporate erasure qubit check protocols and conditional / unconditional erasure qubit reset protocols are provided. The gate scheduling sequences have been illustrated as syndrome extraction circuits for ease of discussion regarding surface code 400. However, other formats and forms for gate scheduling sequences that correspond to other 2D topological codes that are implemented using erasure qubits are also meant to be included in the discussion herein.

[0073] FIG. 5A illustrates a continuation of an example of a surface code that may be implemented using erasure qubits, according to some embodiments.

[0074] Surface code 400 is additionally represented in FIG. 5A for ease of discussion with regard to FIGs.5B and 5C, as follows.

[0075] FIGs.5B and 5C illustrate examples of performance of respective rounds of ^^-type and Z-type stabilizer measurements using a surface code, such as that which is shown in FIGs.4 and 5A, and wherein said rounds incorporate periodic erasure checks and / or resets, according to some embodiments.

[0076] In some embodiments, in order to provide higher fidelity for quantum computation performed using surface code 400, periodic erasure checks and / or conditional / unconditional resets may be performed within a given round of syndrome extraction for ^^- and ^^-type stabilizers. For example, blocks 502, 504, 506, 508, 510, 512, 514, 516, 518, 520, 522, 524, 526, 528, 530, 532, 534, 536, and 538 in syndrome extraction for ^^-type stabilizer 500 may resemble moments at which point such periodic erasure checks and / or conditional / unconditional resets that may be performed during a sequence for performing a given ^^-type stabilizer extraction circuit, using respective ones of the erasure data and ancilla qubits (see also the Key shown in FIG. 5A). In another example, blocks 552, 554, 556, 558, 560, 562, 564, 566, 568, 570, 572, 574, 576, 578, 580, 582, 584, 586, and 588 in syndrome extraction for ^^-type stabilizer 550 may resemble moments at which point such periodic erasure checks and / or conditional / unconditional resets that may be performed during a sequence for performing a given ^^-type stabilizer extraction circuit, using respective ones of the erasure data and ancilla qubits (see also the Key shown in FIG.5A).

[0077] Referring once again to example embodiments discussed above with regard to FIG.3 and quantum circuit 300, a block 502 within syndrome extraction for ^^-type stabilizer 500 may refer to a segment of time that includes multiple timesteps, such as readout 312 and reset 316 of erasure qubit 302. For example, block 502 may refer to execution of both an erasure qubit check protocol, followed by a conditional erasure qubit reset protocol, according to some embodiments. In a second example, block 502 may refer to execution of both an erasure qubit check protocol, followed by an unconditional erasure qubit reset protocol. In a third example, block 502 may refer to an unconditional erasure qubit reset protocol, in embodiments in which classical computing devices have determined that a location of block 502, along with blocks 504, 506, 508, and 510 that occur at a same moment in time, provides additional security against a propagation of logical errors.

[0078] In some embodiments, blocks 502, 504, 506, 508, and 510 may simultaneously be used to perform erasure qubit check protocols across the five erasure qubits in a given stabilizer, as shown in syndrome extraction for ^^-type stabilizer 500. Performing erasure qubit check protocols onto respective erasure qubits before and / or after execution of a two-qubit gate that utilizes said erasure qubits (e.g., block 502 in the example regarding the first, top-most data qubit and the ancilla qubit in syndrome extraction for ^^-type stabilizer 500) can help detect and / or limit the propagation of amplitude damping decay type errors. Furthermore, performing erasure qubit check protocols onto respective erasure qubits at a moment in time that is not just before and / or after execution of a two-qubit gate that utilizes said a given erasure qubit (e.g., blocks 504, 506, and 508 in examples regarding the second, third, and fourth data qubits in syndrome extraction for ^^- type stabilizer 500) can also help detect and / or limit the propagation of amplitude damping decay type errors, especially when those types of errors would have / have already begun to propagate and affect other erasure qubits besides the qubit that was the source of the error. Moreover, the ancilla qubit within in syndrome extraction for ^^-type stabilizer 500 is utilized to perform two- qubit gates between respective ones of the data qubits at each timestep within in syndrome extraction for ^^-type stabilizer 500, and therefore installing erasure qubit check protocols onto the five qubits within the stabilizer may provide additional and useful information during a decoding process.

[0079] Furthermore, blocks 540 and 590, specifically, may refer to an erasure qubit check protocol of the erasure ancilla qubits, and no subsequent conditional or unconditional erasure qubit reset protocol. As blocks 540 and 590 occur just before ^^ or ^^ type parity measurements, respectively, that are to be executed onto the erasure ancilla qubits, and that mark measurement outcomes of the given round of syndrome extraction circuits being illustrated in FIGs.5B and 5C,no erasure qubit reset protocol occurs that would reset said ancilla qubits back to their ground states just prior to the syndrome measurement step, as it is of interest to measure the current states of the respective erasure ancilla qubits following an erasure qubit check protocol illustrated using blocks 540 and 590.

[0080] FIG. 6A illustrates a continuation of an example of a surface code that may be implemented using erasure qubits, according to some embodiments.

[0081] Surface code 400 is additionally represented in FIG. 6A for ease of discussion with regard to FIGs.6B and 6C, as follows.

[0082] FIGs. 6B and 6C illustrate additional examples of performance of respective rounds of^^-type and ^^-type stabilizer measurements using a surface code, such as that which is shown inFIGs.4, 5A, and 6A, and wherein said rounds incorporate periodic erasure checks and / or resets, according to some embodiments.

[0083] In some embodiments, in order to provide higher fidelity for quantum computation performed using surface code 400, periodic erasure checks and / or conditional / unconditional resets may be performed within overall sequences for ^^- and ^^-type stabilizer measurement circuits. Continuing the discussion from FIGs.5B and 5C, another example of syndrome extraction circuits for a 2D topological surface code may resemble that which is shown in FIGs. 6B and 6C. For example, blocks 602, 604, 606, 608, 610, 612, 614, 616, and 618 in syndrome extraction for ^^- type stabilizer 600 may resemble moments at which point such periodic erasure checks and / orconditional / unconditional resets that may be performed during a sequence for performing a given^^-type stabilizer extraction circuit, using respective ones of the erasure data and ancilla qubits (seealso the Key shown in FIG.6A). In another example, blocks 652, 654, 656, 658, 660, 662, 664, 666, and 668 in syndrome extraction for ^^-type stabilizer 650 may resemble moments at which point such periodic erasure checks and / or conditional / unconditional resets that may be performed during a sequence for performing a given ^^-type stabilizer extraction circuit, using respective ones of the erasure data and ancilla qubits (see also the Key shown in FIG.6A).

[0084] Furthermore, blocks 620 and 670, specifically, may refer to an erasure qubit check protocol of the erasure ancilla qubits, and no subsequent conditional or unconditional erasure qubit reset protocol. As blocks 620 and 670 occur just before ^^ or ^^ type parity measurements, respectively, that are to be executed onto the erasure ancilla qubits, and that mark measurement outcomes of the given round of syndrome extraction circuits being illustrated in FIGs.6B and 6C, no erasure qubit reset protocol occurs that would reset said ancilla qubits back to their ground states just prior to the syndrome measurement step, as it is of interest to measure the current statesof the respective erasure ancilla qubits following an erasure qubit check protocol illustrated using blocks 620 and 670.

[0085] FIG. 7A illustrates a continuation of an example of a surface code that may be implemented using erasure qubits, according to some embodiments.

[0086] Surface code 400 is additionally represented in FIG. 7A for ease of discussion with regard to FIGs.7B and 7C, as follows.

[0087] FIGs.7B and 7C illustrate further examples of performance of respective rounds of ^^- type and ^^-type stabilizer measurements using a surface code, such as that which is shown in FIGs. 4, 5A, 6A, and 7A, and wherein said rounds incorporate periodic erasure checks and / or resets, according to some embodiments.

[0088] In some embodiments, in order to provide higher fidelity for quantum computation performed using surface code 400, periodic erasure checks and / or conditional / unconditional resets may be performed within overall sequences for ^^- and ^^-type stabilizer measurement circuits. Continuing the discussion from FIGs.5B and 5C, and from FIGs.6B and 6C, yet another example of syndrome extraction circuits for a 2D topological surface code may resemble that which is shown in FIGs.7B and 7C. For example, blocks 702, 704, 706, and 708 in syndrome extraction for ^^-type stabilizer 700 may resemble moments at which point such periodic erasure checks and / or conditional / unconditional resets that may be performed during a sequence for performing a given ^^-type stabilizer extraction circuit, using respective ones of the erasure data and ancilla qubits (see also the Key shown in FIG.7A). In another example, blocks 752, 754, 756, and 758 in syndrome extraction for ^^-type stabilizer 750 may resemble moments at which point such periodic erasure checks and / or conditional / unconditional resets that may be performed during a sequence for performing a given ^^-type stabilizer extraction circuit, using respective ones of the erasure data and ancilla qubits (see also the Key shown in FIG.7A).

[0089] Furthermore, blocks 710 and 760, specifically, may refer to an erasure qubit check protocol of the erasure ancilla qubits, and no subsequent conditional or unconditional erasure qubit reset protocol. As blocks 710 and 760 occur just before ^^ or ^^ type parity measurements, respectively, that are to be executed onto the erasure ancilla qubits, and that mark measurement outcomes of the given round of syndrome extraction circuits being illustrated in FIGs.6B and 6C, no erasure qubit reset protocol occurs that would reset said ancilla qubits back to their ground states just prior to the syndrome measurement step, as it is of interest to measure the current states of the respective erasure ancilla qubits following an erasure qubit check protocol illustrated using blocks 710 and 760.

[0090] FIG. 8 illustrates another example of a surface code that may be implemented using dual-rail erasure qubits, according to some embodiments.

[0091] As introduced above, a dual-rail encoding, such as that which is illustrated using energystate diagram 250, may be defined as the following:

[0092] When implemented using superconducting qubits, such as transmons, the dominant type of noise for this type of qubit architecture may be referred to as the amplitude damping noise,wherein amplitude damping noise is defined as the energy relaxation from the first excited state,|1^, to the ground state, |0^. As additionally illustrated in energy state diagram 250, a singleamplitude damping event is detectable, as it maps any state of the corresponding erasure qubit to|00^, which is outside of the computational subspace defined by ^|01^, |10^^. This encoding thenallows the effective noise within the local environment of the qubit to be dominated by detectable erasures. In the following paragraphs, examples of dual-rail encodings are provided with regards to surface code 800 and Floquet code 900.

[0093] In some embodiments, surface code 800 may resemble an additional example of a planar, topological code, wherein reductions to quantum hardware layout requirements may be made by using dual-rail erasure qubits rather than single-transmon-type erasure qubits. As shown in FIG.8, a number of physical qubit connectivities per erasure qubit may be reduced by applying such a hardware layout, in contrast to a hardware layout such as that which is shown in surface code 400 and which is implemented using single-transmon-type erasure qubits. As indicated with the Key in FIG. 8, each dual-rail, data or ancilla erasure qubit includes quantum hardware components such as quantum hardware components 200, illustrated in FIG.2A, wherein quantum hardware components for two transmons that have been capacitively or inductively coupled to one another enable a mapping of energy states 254 to computational basis states of the dual-rail-type erasure qubit. Two-qubit gates may be performed between two dual-rail erasure qubits by adiabatically turning on and off couplings, which are denoted by the solid lines in FIG. 8 that connect respective qubits to one another.

[0094] As additionally illustrated in FIG.8, each half (e.g., transmon 202 in the illustration of an implementation 206 of a dual-rail erasure qubit in FIG.2A) of a given dual-rail qubit is coupled to the other half (e.g., transmon 204) of the given dual-rail erasure qubit, and is coupled to two other dual-rail erasure qubits, according to the connectivities shown in FIG. 8. Thus, minimum requirements pertaining to qubit connectivities are reduced when implementing a surface code using dual-rail erasure qubits, with respect to implementing a surface code using single-transmon- type erasure qubits. Additional examples of reduced quantum hardware components whenimplementing codes using dual-rail erasure qubits are also discussed herein with regard to FIG.9, as follows.

[0095] FIG.9 illustrates an example of a Floquet code that may be implemented using dual- rail erasure qubits, according to some embodiments. In addition, FIG.10 illustrates examples of performance of respective rounds of ^^-type and ^^-type stabilizer measurements using a Floquet code, such as that which is shown in FIG.8, and wherein said rounds incorporate periodic erasure checks and / or resets, according to some embodiments.

[0096] As introduced above, heralding signals may indicate an amplitude damping decay event without collapsing the erasure qubit out of a superposition quantum state. Additionally, the heralding signal may not reveal additional information about a quantum state of the erasure qubit other than the fact that it has decayed out of the computational subspace defined by a mapping of energy states to computational basis states of the erasure qubit, according to some embodiments. Such concepts, which were introduced above with regard to surface codes, may additionally be applied to other 2D topological codes, such as Floquet codes. Moreover, projective measurements, which is additionally discussed in the following paragraphs with regard to FIGs.9 and 10, may be conducted using a dispersive syndrome measurement, according to some embodiments. In other embodiments, the projective measurements may be conducted using ^^ matching techniques or catch-disperse-release methods. Further embodiments may comprise the use of an ancilla qubit in which the one of the one or more intermediate states outside of the computational subspace is mapped to the ancilla qubit and driven in this manner. In some embodiments, the heralding signal may be indicated via a quantum state of the ancilla qubit.

[0097] In some embodiments, Floquet code 900 may resemble an additional example of a planar, topological code, wherein reductions to quantum hardware layout requirements may be made by using dual-rail erasure qubits rather than single-transmon-type erasure qubits. As shown in FIG.9, superconducting qubits 902 and 904 are coupled to one another in order to implement a dual-rail erasure qubit, and superconducting qubits 906 and 908 similarly implement another dual- rail erasure qubit. Furthermore, and in order to implement erasure qubit check protocols using the Floquet code, projective measurements of Pauli operator ^^^వబమ^^^వబర, which is illustrated with block 910 in FIG.9, implements an erasure qubit check protocol for the dual-rail erasure qubit definedby superconducting qubits 902 and 904. Similarly, projective measurements of Pauli operatorwhich is illustrated with block 912 in FIG. 9, implements an erasure qubit checkprotocol for the dual-rail erasure qubit defined by superconducting qubits 906 and 908. In addition, projective measurements of Pauli operator ^^^వబర^^^వబల, which is illustrated with block 914 in FIG.9, implement a Pauli ^^^వబమ^వబర^^^వబల^వబ^measurement on the computational subspace of the two dual-rail erasure qubits collectively defined by superconducting qubits 902, 904, 906, and 908.

[0098] In the description introduced in the proceeding paragraph, a +1 measurement outcome of an erasure qubit check protocol, executed by performing the Pauli ^^^వబమ^^^వబరmeasurement, heralds an indication that an amplitude damping decay event has occurred on the dual-rail erasure qubit defined by superconducting qubits 902 and 904. Moreover, and as illustrated with projective measurements block 914 in FIG.9, the hardware layout for Floquet code 900 enables performance of projective measurements of Pauli ^^^^ operators, together with single-qubit Hadamard and phase gates on the computational subspace which, in turn, is sufficient to implement erasure qubit check protocols and Pauli ^^^^, ^^^^, and ^^^^ measurements on the computational subspace. As such, the Floquet code hardware layout may be further used to implement a 2D honeycomb code and the CSS honeycomb code, such as that which is illustrated in FIG. 8 with surface code 800, and in FIG.10 with Floquet code 1000.

[0099] In some embodiments, syndrome extraction circuits for ^^-type and ^^-type stabilizers that include erasure qubit checks and / or erasure qubit resets, such as examples provided herein with regard to FIGs. 5A – 7C, may be similarly configured for additional types of low-density parity-check quantum codes, such as the Floquet code 900, shown in FIG.9, and the Floquet code 1000, shown in FIG. 10. Floquet code 1000 may be implemented using quantum hardware components that enable a hexagonal lattice with either periodic, such as in FIG.10, or with open boundary conditions. Syndrome extraction sequence 1002 illustrates a sequence of measurements of two-qubit Pauli operators, which are illustrated in block 1002 using different patterns of lines, onto respective sets of qubits.

[0100] FIG. 11 is a flow chart that illustrates a process of executing quantum computations (e.g., quantum gates) between erasure qubits, and to perform error correction steps for such an architecture, according to some embodiments.

[0101] In some embodiments, FIG. 11 may further illustrate a process of encoding computational basis states of an erasure qubit such that a computational subspace is defined and such that leakage outside of said computational subspace may be heralded, signaling that an amplitude damping decay event has occurred, according to some embodiments.

[0102] In block 1100, one or more transmons are used to encode a qubit into a computational subspace, such as in the embodiments shown in FIGs.1A-2B, wherein the computational subspace comprises a first level and a second level selected from the available levels of the one or more transmons according to the configuration used, according to some embodiments. The one or moreavailable levels not already mapped to the computational subspace may be used to signal an amplitude damping decay event, according to some embodiments.

[0103] In some embodiments, blocks 1102, 1104, 1106, 1108, and 1110 may be used to illustrate a given round of a syndrome extraction circuit within an overall performance of a logical quantum circuit. For example, blocks 1102, 1104, 1106, 1108, and 1110 may be repeated if more than one round of syndrome extraction circuits are used to complete the execution of the logical quantum circuit. In block 1102, two-qubit gates are performed using respective ones of the erasure qubits, such as in one or more quantum gates 310 between erasure qubits 302 and 304, illustrated in FIG.3.

[0104] In block 1104, an erasure qubit check protocol may be executed onto the erasure qubits, such as in some embodiments of blocks 502, 504, 506, 508, and 510, illustrated in FIG. 5B. If leakage outside of the computational subspaces of one or more of the erasure qubits is detected in block 1106, then a heralding signal may indicate that the amplitude damping decay event(s) has occurred in block 1108. If no amplitude damping decay events were detected in the erasure qubit check protocol illustrated using blocks 1104 and 1106, then measurement outcomes of the erasure qubit check protocol may indicate that the respective erasure qubits are still within their computational subspaces and no leakage has occurred. In block 1110, a conditional erasure qubit reset protocol or an unconditional erasure qubit reset protocol may be executed. Additional examples of such reset protocols are described herein with regard to FIGs.5A – 7C.

[0105] The process of blocks 1106-1110 may be repeated for one or more rounds of syndrome extraction circuits, as shown in block 1112. After the final round of syndrome extraction circuits has been completed, the syndrome measurements and heralding signals, if indeed leakage was detected outside of the computational subspace during the one or more rounds of syndrome measurements, are then provided in block 1114 (e.g., provided to a classical measurement device such that an error correction protocol may be performed post-execution of a given quantum computation). The following paragraphs provide additional detail regarding decoding processes for erasure-qubit-based architectures.

[0106] In some embodiments, in order to simulate quantum error correction (QEC) protocols with erasure qubits and to engineer corresponding decoding algorithms, locations of where erasures may happen within a given architecture may be enumerated, such that quantum circuit operations, such as qubit initializations, qubit state readouts, unitary gates between qubits, erasure qubit check and reset protocols, may be accurately simulated with noise profiles. In order to incorporate noise into simulations of QEC protocols that may then be used to design and engineer decoding algorithms, an amount of Pauli noise ^^ and an erasure event ℰ is incorporated into eachtype of operation, and an amount of bit-flip noise ^^ is incorporated into measurement outcomes. Moreover, noise strengths may be considered to be based on three parameters in the description that follows: the classical bit-flip noise rate, ^^, the erasure rate, ^^, and the Pauli error rate, ^^.

[0107] In order to engineer a QEC protocol for an erasure qubit based architecture, it may be considered that erasure qubits have both Pauli noise and erasures that take a quantum state from the computational subspace to some orthogonal subspace (e.g., energy state 152, energy state 252, etc.) which is defined herein as an erasure subspace. Moreover, erasure errors may spread, probabilistically, via two-qubit operations, such as through an erasure-to-erasure spread, wherein the erasure error spreads to another erasure error, or through an erasure-Pauli spread, wherein the erasure error spreads to a Pauli error. For example, an erasure-Pauli spread may resemble anerasure error that spreads to either Pauli ^^, Pauli ^^, or Pauli ^^, each with respective probability1⁄ 4. In such an example, any erasure qubit that is affected by the erasure error causes fulldepolarization of any other erasure qubit that is involved in the same two-qubit operation. In the description that follows, ^^ and ^^ continue to represent arbitrary Pauli and binary channels,wherein ^^^^^^ denotes a single-qubit or two-qubit depolarizing channel with an error rate ^^, and^^^^^^ denotes a binary symmetric channel that flips the measurement outcome with an error rate^^.

[0108] In some embodiments, decoding algorithms for syndrome extraction circuits, such as circuits illustrated in figures herein, are simulated by distributing Pauli errors at spacetime locations between qubit operations within the circuit and by simulating a set of detectors, ^^^^^, wherein a detector is a product of measurement outcomes of the syndrome extraction circuit that are deterministic in the absence of errors, and which gives information about possible errors when triggered. The syndrome extraction circuit, therefore, may describe the implementation of a stabilizer-based code, wherein detectors are products of consecutive stabilizer measurements, or may similarly describe the implementation of a Floquet code. A decoding algorithm, therefore, may be used to find a Pauli recovery which undoes the errors, post-performance of a logical quantum circuit, that occurred during performance of the logical quantum circuit. In some embodiments, the decoding algorithm may be defined as a hypergraph matching problem, in order to describe a distribution of Pauli errors that is either equal to or approximated by a product distribution of binary random variables, or error mechanisms.

[0109] In some embodiments, and error mechanism is a pair, ^^^^, ^^^^, such that the Pauli error^^^ is inserted at specified spacetime locations in the circuit with probability ^^^. Thus, when Paulierror ^^^ occurs, it causes a subset of detectors ^^^ ⊆ ^^^^^ to be triggered. A weighted hypergraph,^^ = ^^^^^^, ^^^^^^, may then be defined, wherein each hyperedge ^^^ has a weight ^^^^^^^ =log^^1 − ^^^^⁄ ^^^ ^, and the decoding problem is then, at a high-level, summarized as finding themost likely error triggering a subset of detectors which is equivalent to the minimum-weighthypergraph matching problem on ^^: for a given subset of vertices ^^ ⊆ ^^^^^, find a subset ofhyperedges ^^ ⊆ ^^^^^ with the lowest total weight ∑^^∈ఛ ^^^^^^ , such that^^ = ^^, where ⊕denotes the symmetric difference of sets. The recovery operator is then the product of all Pauli errors, propagated to the end of the given round of the syndrome extraction circuit, that correspond to the hyperedges in ^^.

[0110] In some embodiments, the decoding problem for erasure-based circuits is thus to find a Pauli recovery. In the paragraphs that follow, description pertaining to a mapping of erasure circuits, ^^ா, to stabilizer circuits is further detailed, wherein erasure errors are converted into independent Pauli error mechanisms. Such a mapping allows for a decoding algorithm for erasure- based circuits to be described as a hypergraph matching problem.

[0111] In some embodiments, a given erasure circuit, ^^ா, may be decomposed into segments, wherein a segment ^^ is the worldline of a single qubit ^^ between two consecutive reset operations.Moreover, entangling operations of ^^ may be further defined as those with nontrivial support on^^, and the spacetime locations associated with ^^ as those immediately following the entanglingoperations of ^^. To map ^^ாto a stabilizer circuit with independent Pauli error mechanisms, each segment ^^ of ^^ாis modified such that erasure qubit check and reset operations are removed, while appropriate error mechanisms are added at locations associated with ^^. Such a mapping may be guaranteed by Lemma 1.

[0112] Lemma 1: Let ^^ா be an erasure circuit and ^^ be a segment of ^^ா. Given the outcomes^^ of erasure checks in ^^, the distribution of errors introduced by erasures in ^^ is equivalent to adistribution of spacetime correlated Pauli errors ^^ that can be described by independent errormechanisms ^൫^^^,^, ^^^൯^.

[0113] The following paragraphs provide further description of a proof of Lemma 1.

[0114] The proof proceeds in three steps. First, the distribution of Pauli errors caused by erasure in the segment is found. This distribution can be described by disjoint events which are correlated depolarizing channels applied at different spacetime locations, caused by the erasure- depolarization spread. Second, this distribution is shown to be also described by a product of independent events which are spacetime correlated depolarizing channels. Third, each of the spacetime correlated depolarizing channels is decomposed into independent error mechanisms.

[0115] In some embodiments, ^^ may be defined as a segment of the qubit ^^, ^^^may be defined as the ^^-th entangling operation in ^^, may be defined as the spacetime location associatedwith ^^, placed after ^^^, and defined via suppℱ^ = supp ^^^⁄ ^^^^ , wherein ^^ ∈ ^1, … , ^^^. In examplesthat follow, ^^^and ^^^ା^denote the first and second reset operations in ^^, and ℱ^ା^is defined to be the location at ^^ after the second reset. In the case when ^^^is a two-qubit projective measurement, then the classical bit containing the outcome is interpreted to be a qubit and ℱ^to include that qubit. Thus,

[0116] In order to find the distribution of Pauli errors ^^ caused by erasures in ^^, ^^^is denotedto be the event that a qubit was first erased at any time between ^^^ି^ and ^^^, wherein ^^ ∈^1, … , ^^ + 1^. When ^^^ occurs, it causes all qubits connected to ^^ through subsequent entanglingoperations to be fully depolarized, i.e., fully depolarizing channels are added at spacetime locationsℱ^. It may also be noted thatare disjoint events. Given the erasure check outcomes ^^, whoseprobability distribution depends on the erasure probabilities and on the false positive and false negative detection rates of the erasure checks in the segment ^^, the posterior probabilities may bedefined as:The distribution of Pauli errors ^^ may then be obtained by sampling disjoint events with probability ^^^and by inserting fully depolarizing channels atwhenever the corresponding event is sampled.

[0117] Moreover, within the description of ^^, there may be disjoint events rather than independent ones. Thus, to obtain the description, it is shown herein that ^^ can also be obtainedby sampling ^^ + 1 independent events ^^^^^, wherein ^^^ is defined as a binary random variablewith probabilityand by placing full depolarizing channels at spacetime locationswhenever ^^^is sampled. Todo that, one may observe that, for ^^ < ^^, a composition of fully depolarizing channels atand ℱ^is equivalent to the fully depolarizing channelssince⊇ ℱ^. Therefore, fully depolarizingchannels are placed exclusively atif and only if ^^^ is sampled, but no other ^^^ for ^^ < ^^, whichoccurs with probability

[0118] Next, the depolarizing channels resulting from events^^^^^are further decomposed intoindependent error mechanisms. Namely, for each ^^^, 4หℱ^ห − 1 error mechanisms are introduced,each corresponding to a different nontrivial Pauli error ^^^,^, that can be placed at spacetimelocations with probability

[0119] The resulting product distribution of independent error mechanismsisequivalent to ^^. Thus, Lemma 1 is proven.

[0120] FIG.12 is a block diagram illustrating an example quantum hardware device that may be configured to execute quantum computations (e.g., quantum gates) between erasure qubits, and to perform error correction steps for such an architecture, according to some embodiments.

[0121] As shown in FIG. 12, a quantum hardware device 1200 may comprise one or more central quantum processing units (QPUs) and / or quantum processing cores 1220 that, collectively, implement a quantum computer 1230. Various configurations of physical qubits may be included in implementation of quantum computer 1230 wherein a given subset of a total number of qubits may represent quantum processing core 1220 and another given subset of qubits may be used to implement magic state factories, additional routing space, and / or additional quantum processing cores that are accessible via lattice surgery, as shown in block 1210. Portions of quantum computations and / or operations may be performed in quantum processing core 1220, wherein computationally intensive logical computations may use magic state factories within block 1210 in order to produce magic states that may be used to store intermediate computations such that they are held in memory during such quantum computations. In some embodiments, a given magic state factory of block 1210 may be merged with quantum processing core 1220 during a procedure such as lattice surgery in order for information to pass between such components of the quantum computer.

[0122] As related to the description herein, one or more erasure qubits within implementation of quantum computer 1230 may additionally be coupled to a quantum readout device for measurements of quantum states following performance of one or more quantum gates such as two-qubit entangling gates described herein. The given quantum readout device may be locally connected to various qubits of quantum processing core 1220, as shown by interaction arrows to / from block 1240. Furthermore, and as related to embodiments described herein, quantum readout devices 1240 may include parity measurements, or any other type of QND measurement that may be configured for erasure qubit check protocols and / or syndrome measurements at a conclusion of a given round of a syndrome extraction circuit.

[0123] Depending upon factors such as type(s) of qubit technologies used (e.g., superconducting architectures), type(s) of gates performed between said qubits (e.g., entangling gates, QND measurements), etc., quantum hardware device 1200 may also comprise various control devices (e.g., microwave pulse generators, lasers, devices for temperature, magnetic, and / or other environmental controls pertaining to local environments of the grid of qubits within implementation of quantum computer 1230, etc.) that may be used to maintain and / or transform various properties of the qubits and / or other physical components of a given quantum computer, as shown via local environmental control devices within block 1240. For example, a drive may be locally coupled to one or more quantum hardware components within quantum processing core 1220, such that various control sequences emitted from the drive may be used to perform readout and / or reinitialize various qubits of quantum processing core 1220 into their respective ground states.

[0124] In some embodiments in which local environmental control devices 1240 include a processor such as processors 1310, local environmental control devices 1240 may additionally be configured to interact with other devices 1260 via network 1250. In some embodiments, other devices 1260 may include classical computing devices such as classical computing device 1300, which may be configured to interact with quantum hardware device 1200 either locally or remotely in order to provide drive control instructions for performance of a logical quantum circuit. Illustrative computer system

[0125] FIG.13 is a block diagram illustrating an example classical computing device that may be used in at least some embodiments.

[0126] FIG.13 illustrates such a general-purpose classical computing device 1300 as may be used in any of the embodiments described herein. In the illustrated embodiment, classical computing device 1300 includes one or more processors 1310 coupled to a system memory 1320 (which may comprise both non-volatile and volatile memory modules) via an input / output (I / O) interface 1330. Classical computing device 1300 further includes a network interface 1340 coupled to I / O interface 1330.

[0127] In various embodiments, classical computing device 1300 may be a uniprocessor system including one processor 1310, or a multiprocessor system including several processors 1310 (e.g., two, four, eight, or another suitable number). Processors 1310 may be any suitable processors capable of executing instructions. For example, in various embodiments, processors 1310 may be general-purpose or embedded processors implementing any of a variety of instruction set architectures (ISAs), such as the x86, PowerPC, SPARC, or MIPS ISAs, or any other suitable ISA. In multiprocessor systems, each of processors 1310 may commonly, but not necessarily,implement the same ISA. In some implementations, graphics processing units (GPUs) may be used instead of, or in addition to, conventional processors.

[0128] System memory 1320 may be configured to store instructions and data accessible by processor(s) 1310. In at least some embodiments, the system memory 1320 may comprise both volatile and non-volatile portions; in other embodiments, only volatile memory may be used. In various embodiments, the volatile portion of system memory 1320 may be implemented using any suitable memory technology, such as static random-access memory (SRAM), synchronous dynamic RAM or any other type of memory. For the non-volatile portion of system memory (which may comprise one or more NVDIMMs, for example), in some embodiments flash-based memory devices, including NAND-flash devices, may be used. In at least some embodiments, the non-volatile portion of the system memory may include a power source, such as a supercapacitor or other power storage device (e.g., a battery). In various embodiments, memristor based resistive random access memory (ReRAM), three-dimensional NAND technologies, Ferroelectric RAM, magnetoresistive RAM (MRAM), or any of various types of phase change memory (PCM) may be used at least for the non-volatile portion of system memory. In the illustrated embodiment, program instructions and data implementing one or more desired functions, such as those methods, techniques, and data described above, are shown stored within system memory 1320 as code 1325 and data 1326.

[0129] In some embodiments, I / O interface 1330 may be configured to coordinate I / O traffic between processor 1310, system memory 1320, and any peripheral devices in the device, including network interface 1340 or other peripheral interfaces such as various types of persistent and / or volatile storage devices. In some embodiments, I / O interface 1330 may perform any necessary protocol, timing or other data transformations to convert data signals from one component (e.g., system memory 1320) into a format suitable for use by another component (e.g., processor 1310). In some embodiments, I / O interface 1330 may include support for devices attached through various types of peripheral buses, such as a variant of the Peripheral Component Interconnect (PCI) bus standard or the Universal Serial Bus (USB) standard, for example. In some embodiments, the function of I / O interface 1330 may be split into two or more separate components, such as a north bridge and a south bridge, for example. Also, in some embodiments some or all of the functionality of I / O interface 1330, such as an interface to system memory 1320, may be incorporated directly into processor 1310.

[0130] Network interface 1340 may be configured to allow data to be exchanged between classical computing device 1300 and other devices 1360 attached to a network or networks 1350, such as other computer systems or devices as illustrated in FIG.1A through FIG.12, for example.In various embodiments, network interface 1340 may support communication via any suitable wired or wireless general data networks, such as types of Ethernet network, for example. Additionally, network interface 1340 may support communication via telecommunications / telephony networks such as analog voice networks or digital fiber communications networks, via storage area networks such as Fibre Channel SANs, or via any other suitable type of network and / or protocol.

[0131] In some embodiments, system memory 1320 may represent one embodiment of a computer-accessible medium configured to store at least a subset of program instructions and data used for implementing the methods and apparatus discussed in the context of FIG. 1A through FIG.12. However, in other embodiments, program instructions and / or data may be received, sent or stored upon different types of computer-accessible media. Generally speaking, a computer- accessible medium may include non-transitory storage media or memory media such as magnetic or optical media, e.g., disk or DVD / CD coupled to classical computing device 1300 via I / O interface 1330. A non-transitory computer-accessible storage medium may also include any volatile or non-volatile media such as RAM (e.g., SDRAM, DDR SDRAM, RDRAM, SRAM, etc.), ROM, etc., that may be included in some embodiments of classical computing device 1300 as system memory 1320 or another type of memory. In some embodiments, a plurality of non- transitory computer-readable storage media may collectively store program instructions that when executed on or across one or more processors implement at least a subset of the methods and techniques described above. A computer-accessible medium may further include transmission media or signals such as electrical, electromagnetic, or digital signals, conveyed via a communication medium such as a network and / or a wireless link, such as may be implemented via network interface 1340. Portions or all of multiple classical computing devices such as that illustrated in FIG. 13 may be used to implement the described functionality in various embodiments; for example, software components running on a variety of different devices and servers may collaborate to provide the functionality. In some embodiments, portions of the described functionality may be implemented using storage devices, network devices, or special- purpose computer systems, in addition to or instead of being implemented using general-purpose computer systems. The term “classical computing device”, as used herein, refers to at least all these types of devices, and is not limited to these types of devices.

[0132] Embodiments of the present disclosure can be described in view of the following clauses: Clause 1. A system, comprising:one or more classical computing devices, configured to provide drive control instructions to one or more quantum hardware devices, wherein the drive control instructions comprise instructions for performance of erasure qubit check protocols and conditional erasure qubit reset protocols during execution of a quantum circuit; and one or more quantum hardware devices comprising sets of quantum hardware components configured to respectively implement erasure qubits, wherein the one or more quantum hardware devices are configured to: receive the drive control instructions; execute the quantum circuit using respective ones of the erasure qubits, wherein to execute the quantum circuit, the one or more quantum hardware devices are further configured to: for a given round of syndrome extraction, perform one or more two-qubit gates between respective ones of the erasure qubits; perform an erasure qubit check protocol on the respective ones of the erasure qubits; and perform a conditional erasure qubit reset protocol of one or more of the respective ones of the erasure qubits based, at least in part, on measurement outcomes of the erasure qubit check protocol; provide the measurement outcomes of the erasure qubit check protocol to a classical measurement device; and provide additional measurement outcomes of the one or more quantum gates performed between the respective ones of the erasure qubits to the classical measurement device. Clause 2. The system of clause 1, wherein, to perform the erasure qubit check protocol during the given round of syndrome extraction, the one or more quantum hardware devices are configured to: emit a measurement outcome comprising a heralding signal, for the respective ones of the erasure qubits, when an amplitude damping decay event has occurred on the respective erasure qubit. Clause 3. The system of clause 2, wherein, to perform the conditional erasure qubit reset protocol of the one or more of the respective ones of the erasure qubits during the given round of syndrome extraction, the one or more quantum hardware devices are configured to:reset the one or more of the respective ones of the erasure qubits, conditional on the emission of the heralding signal. Clause 4. The system of any of clauses 1 through 3, wherein: the drive control instructions further comprise instructions for performance of unconditional erasure qubit reset protocols during the execution of the quantum circuit; and to execute the quantum circuit, the one or more quantum hardware devices are further configured to: for the given round of syndrome extraction, perform an unconditional erasure qubit reset protocol on the respective ones of the erasure qubits. Clause 5. The system of clause 4, wherein the one or more classical computing devices are further configured to: determine a frequency with which to perform the unconditional erasure qubit reset protocols during the given round of syndrome extraction; and generate the drive control instructions based, at least in part, on the determined frequency of the unconditional erasure qubit reset protocols. Clause 6. The system of any of clauses 1 through 5, wherein the one or more classical computing devices are further configured to: receive the measurement outcomes of the erasure qubit check protocol; and perform an error correction protocol based, at least in part, on the measurement outcomes. Clause 7. The system of clause 6, wherein the one or more classical computing devices are further configured to: receive the additional measurement outcomes of the one or more quantum gates; adjust one or more weights corresponding to respective ones of the additional measurement outcomes based, at least in part, on the measurement outcomes of the erasure qubit check protocol; and perform a minimum weight perfect matching (MWPM) error correction protocol additionally based, at least in part, on the additional measurement outcomes of the one or more quantum gates with the adjusted one or more weights. Clause 8. The system of any of clauses 1 through 7, wherein the sets of quantum hardware components are configured to respectively implement dual-rail erasure qubits. Clause 9. The system of clause 8, wherein:the one or more quantum hardware devices further comprise connectivities that couple respective ones of the dual-rail erasure qubits to one another; and the dual-rail erasure qubits and the connectivities are configured to implement a surface code. Clause 10. The system of clause 8, wherein: the one or more quantum hardware devices further comprise connectivities that couple respective ones of the dual-rail erasure qubits to one another; and the dual-rail erasure qubits and the connectivities are configured to implement a Floquet code. Clause 11. The system of any of clauses 1 through 10, wherein the sets of quantum hardware components are configured to respectively implement single-transmon-type erasure qubits. Clause 12. A method, comprising: executing a quantum circuit using one or more quantum hardware devices that are configured to implement erasure qubits, wherein said executing the quantum circuit comprises: for a given round of syndrome extraction, performing one or more two-qubit gates between respective ones of the erasure qubits; performing an erasure qubit check protocol on the respective ones of the erasure qubits; and performing a conditional or unconditional erasure qubit reset protocol on one or more of the respective ones of the erasure qubits; providing measurement outcomes of the erasure qubit check protocol that was performed to a classical measurement device; and providing additional measurement outcomes of the one or more two-qubit gates performed between the respective ones of the erasure qubits to the classical measurement device. Clause 13. The method of clause 12, wherein said performing the erasure qubit check protocol for the given round of syndrome extraction comprises: emitting a measurement outcome comprising a heralding signal, for the respective ones of the erasure qubits, when an amplitude damping decay event has occurred on the respective erasure qubit.Clause 14. The method of clause 13, wherein said performing the conditional or unconditional erasure qubit reset protocol for the given round of syndrome extraction comprises: performing the conditional erasure qubit reset protocol, wherein said performing the conditional erasure qubit reset protocol comprises: resetting the one or more of the respective ones of the erasure qubits, conditional on the emission of the heralding signal. Clause 15. The method of any of clauses 12 through 14, wherein said performing the conditional or unconditional erasure qubit reset protocol for the given round of syndrome extraction comprises: performing the unconditional erasure qubit reset protocol, wherein said performing the unconditional erasure qubit reset protocol comprises: resetting the respective ones of the erasure qubits. Clause 16. One or more non-transitory, computer-readable, media storing program instructions that, when executed on or across one or more processors, cause the one or more processors to: generate drive control instructions that are to be provided to one or more quantum hardware devices for execution of a quantum circuit using erasure qubits that have been implemented using the one or more quantum hardware devices, wherein the drive control instructions comprise: for a given round of syndrome extraction, a first set of instructions for performance of one or more two-qubit gates between respective ones of the erasure qubits; a second set of instructions for performance of an erasure qubit check protocol on the respective ones of the erasure qubits; and a third set of instructions for performance of a conditional or unconditional erasure qubit reset protocol of one or more of the respective ones of the erasure qubits; and provide the generated drive control instructions to the one or more quantum hardware devices. Clause 17. The one or more non-transitory, computer-readable media of clause 16, wherein, to generate the third set of drive control instructions, the program instructions further cause the one or more processors to:generate drive control instructions within the third set of instructions to reset the one or more of the respective ones of the erasure qubits, conditional on emission of a heralding signal that indicates that an amplitude damping decay event has occurred. Clause 18. The one or more non-transitory, computer-readable media of clause 16 or clause 17, wherein, to generate the third set of drive control instructions, the program instructions further cause the one or more processors to: generate drive control instructions within the third set of instructions to periodically reset the respective ones of the erasure qubits. Clause 19. The one or more non-transitory, computer-readable media of any of clauses 16 through18, wherein the program instructions further cause the one or more processors to: receive measurement outcomes of the erasure qubit check protocol; and perform an error correction protocol based, at least in part, on the measurement outcomes. Clause 20. The one or more non-transitory, computer-readable media of clause 19, wherein the program instructions further cause the one or more processors to: receive the additional measurement outcomes of the one or more quantum gates; adjust one or more weights corresponding to respective ones of the additional measurement outcomes based, at least in part, on the measurement outcomes of the erasure qubit check protocol; and perform a minimum weight perfect matching (MWPM) error correction protocol additionally based, at least in part, on the additional measurement outcomes of the one or more quantum gates with the adjusted one or more weights. Conclusion

[0133] Various embodiments may further include receiving, sending or storing instructions and / or data implemented in accordance with the foregoing description upon a computer-accessible medium. Generally speaking, a computer-accessible medium may include storage media or memory media such as magnetic or optical media, e.g., disk or DVD / CD-ROM, volatile or non- volatile media such as RAM (e.g. SDRAM, DDR, RDRAM, SRAM, etc.), ROM, etc., as well as transmission media or signals such as electrical, electromagnetic, or digital signals, conveyed via a communication medium such as network and / or a wireless link.

[0134] The various methods as illustrated in the Figures and described herein, represent exemplary embodiments of methods. The methods may be implemented in software, hardware, or a combination thereof. The order of method may be changed, and various elements may be added, reordered, combined, omitted, modified, etc.

[0135] It will also be understood that, although the terms first, second, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first item could be termed a second item, and, similarly, a second item could be termed a first item, without departing from the scope of the present invention. The first item and the second item are both items, but they are not the same item.

[0136] Various modifications and changes may be made as would be obvious to a person skilled in the art having the benefit of this disclosure. It is intended to embrace all such modifications and changes and, accordingly, the description is to be regarded in an illustrative rather than a restrictive sense.

Claims

CLAIMS WHAT IS CLAIMED IS:

1. A system, comprising: one or more classical computing devices, configured to provide drive control instructions to one or more quantum hardware devices, wherein the drive control instructions comprise instructions for performance of erasure qubit check protocols and conditional erasure qubit reset protocols during execution of a quantum circuit; and one or more quantum hardware devices comprising sets of quantum hardware components configured to respectively implement erasure qubits, wherein the one or more quantum hardware devices are configured to: receive the drive control instructions; execute the quantum circuit using respective ones of the erasure qubits, wherein to execute the quantum circuit, the one or more quantum hardware devices are further configured to: for a given round of syndrome extraction, perform one or more two-qubit gates between respective ones of the erasure qubits; perform an erasure qubit check protocol on the respective ones of the erasure qubits; and perform a conditional erasure qubit reset protocol of one or more of the respective ones of the erasure qubits based, at least in part, on measurement outcomes of the erasure qubit check protocol; provide the measurement outcomes of the erasure qubit check protocol to a classical measurement device; and provide additional measurement outcomes of the one or more two-qubit gates performed between the respective ones of the erasure qubits to the classical measurement device.

2. The system of claim 1, wherein, to perform the erasure qubit check protocol during the given round of syndrome extraction, the one or more quantum hardware devices are configured to:emit a measurement outcome comprising a heralding signal, for the respective ones of the erasure qubits, when an amplitude damping decay event has occurred on the respective erasure qubit.

3. The system of claim 2, wherein, to perform the conditional erasure qubit reset protocol of the one or more of the respective ones of the erasure qubits during the given round of syndrome extraction, the one or more quantum hardware devices are configured to: reset the one or more of the respective ones of the erasure qubits, conditional on the emission of the heralding signal.

4. The system of claim 1, wherein: the drive control instructions further comprise instructions for performance of unconditional erasure qubit reset protocols during the execution of the quantum circuit; and to execute the quantum circuit, the one or more quantum hardware devices are further configured to: for the given round of syndrome extraction, perform an unconditional erasure qubit reset protocol on the respective ones of the erasure qubits.

5. The system of claim 4, wherein the one or more classical computing devices are further configured to: determine a frequency with which to perform the unconditional erasure qubit reset protocols during the given round of syndrome extraction; and generate the drive control instructions based, at least in part, on the determined frequency of the unconditional erasure qubit reset protocols.

6. The system of any one of claims 1 through 5, wherein the one or more classical computing devices are further configured to: receive the measurement outcomes of the erasure qubit check protocol; and perform an error correction protocol based, at least in part, on the measurement outcomes.

7. The system of claim 6, wherein the one or more classical computing devices are further configured to:receive the additional measurement outcomes of the one or more two-qubit gates; adjust one or more weights corresponding to respective ones of the additional measurement outcomes based, at least in part, on the measurement outcomes of the erasure qubit check protocol; and perform a minimum weight perfect matching (MWPM) error correction protocol additionally based, at least in part, on the additional measurement outcomes of the one or more two-qubit gates with the adjusted one or more weights.

8. The system of any one of claims 1 through 7, wherein the sets of quantum hardware components are configured to respectively implement dual-rail erasure qubits.

9. The system of claim 8, wherein: the one or more quantum hardware devices further comprise connectivities that couple respective ones of the dual-rail erasure qubits to one another; and the dual-rail erasure qubits and the connectivities are configured to implement a surface code.

10. The system of claim 8, wherein: the one or more quantum hardware devices further comprise connectivities that couple respective ones of the dual-rail erasure qubits to one another; and the dual-rail erasure qubits and the connectivities are configured to implement a Floquet code.

11. The system of any one of claims 1 through 10, wherein the sets of quantum hardware components are configured to respectively implement single-transmon-type erasure qubits.

12. A method, comprising: executing a quantum circuit using one or more quantum hardware devices that are configured to implement erasure qubits, wherein said executing the quantum circuit comprises: for a given round of syndrome extraction, performing one or more two-qubit gates between respective ones of the erasure qubits;performing an erasure qubit check protocol on the respective ones of the erasure qubits; and performing a conditional or unconditional erasure qubit reset protocol on one or more of the respective ones of the erasure qubits; providing measurement outcomes of the erasure qubit check protocol that was performed to a classical measurement device; and providing additional measurement outcomes of the one or more two-qubit gates performed between the respective ones of the erasure qubits to the classical measurement device.

13. The method of claim 12, wherein said performing the erasure qubit check protocol for the given round of syndrome extraction comprises: emitting a measurement outcome comprising a heralding signal, for the respective ones of the erasure qubits, when an amplitude damping decay event has occurred on the respective erasure qubit.

14. The method of claim 13, wherein said performing the conditional or unconditional erasure qubit reset protocol for the given round of syndrome extraction comprises: performing the conditional erasure qubit reset protocol, wherein said performing the conditional erasure qubit reset protocol comprises: resetting the one or more of the respective ones of the erasure qubits, conditional on the emission of the heralding signal.

15. The method of claim 12, wherein said performing the conditional or unconditional erasure qubit reset protocol for the given round of syndrome extraction comprises: performing the unconditional erasure qubit reset protocol, wherein said performing the unconditional erasure qubit reset protocol comprises: resetting the respective ones of the erasure qubits.

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