Semiconductor device and manufacturing method therefor, and electronic device

Abstract

The present disclosure relates to the field of semiconductors, and relates to a semiconductor device and a manufacturing method therefor, and an electronic device, used for reducing the area of a memory cell. The semiconductor device comprises memory cells (30). Each memory cell (30) comprises a write transistor (500) and a read transistor (300). The write transistor (500) comprises a write gate extending in a second direction, and a write gate dielectric layer (510) and a write channel layer (520) successively surrounding the write gate, and the write channel layer (520) is connected to a write bit line. The read transistor (300) and the write transistor (500) are arranged in a first direction. The read transistor (300) comprises a read channel layer (330), a first gate dielectric layer (320), a read floating gate (310), a second gate dielectric layer, and a read control gate. The read channel layer (330) is in an annular configuration, and the axis of the annular configuration extends in the second direction. The first gate dielectric layer (320) and the read floating gate (310) successively surround the outer sidewall of the read channel layer (330). The second gate dielectric layer and the read control gate are successively located on the outer sidewall of the read floating gate (310) in a third direction.

Description

Semiconductor device, method of manufacturing the same, and electronic device

[0001] Cross Reference to Related Applications

[0002] The present disclosure claims priority to the Chinese patent application No. 2024105859710, filed on May 11, 2024, and entitled “Semiconductor device, method of manufacturing the same, and electronic device”, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to the technical field of semiconductor technology, and in particular, to a semiconductor device, a method of manufacturing the same, and an electronic device. BACKGROUND

[0004] With the development of integrated circuit technology, the critical dimension of devices is increasingly reduced, and the types and quantities of devices contained in a single chip are also increased, so that any slight difference in process production can affect the performance of the devices.

[0005] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, various semiconductor structure designs and process optimizations have been proposed in the industry to meet people's current product needs.

[0006] SUMMARY

[0007] Based on this, the present disclosure provides a semiconductor device, a method of manufacturing the same, and an electronic device.

[0008] According to various embodiments of the present disclosure, a semiconductor device is provided, the semiconductor device comprising a memory cell;

[0009] The memory cell comprises a write transistor and a read transistor;

[0010] The write transistor comprises a write gate extending along a second direction, a write gate dielectric layer and a write channel layer successively surrounding the write gate, and the write channel layer is connected to a write bit line;

[0011] The read transistor and the write transistor are arranged in sequence along a first direction, the read transistor comprises a read channel layer, a first gate dielectric layer, a read floating gate, a second gate dielectric layer and a read control gate, the read channel layer is annular, the first gate dielectric layer and the read floating gate are arranged in sequence outside the outer sidewall of the read channel layer, and the second gate dielectric layer and the read control gate are arranged in sequence on the outer sidewall of the read floating gate in a third direction; wherein the read floating gate is connected to the write channel layer, and the read floating gate and the write bit line are arranged in a spaced manner in the first direction, and the first direction, the second direction and the third direction intersect with each other.

[0012] In some embodiments, the semiconductor device further comprises:

[0013] A substrate, the memory cell stack is arranged on the substrate, the second direction is perpendicular to the substrate, and the first direction and the third direction are parallel to the substrate;

[0014] A stack layer is located on the substrate and comprises alternately stacked first dielectric layers and second dielectric layers;

[0015] A first hole comprises a first through hole and a plurality of first lateral holes spaced from each other, the first through hole penetrates the stack layer along the second direction, and a plurality of first lateral holes recessed from the first through hole to a plurality of second dielectric layers, the first lateral hole and the first through hole are in communication, and the read floating gate, the first gate dielectric layer and the read channel layer are arranged in sequence in the first lateral hole;

[0016] A second hole is arranged in sequence with the first hole along the first direction, comprising a second through hole and a plurality of second lateral holes spaced from each other, the second through hole penetrates the stack layer along the second direction, and a plurality of second lateral holes spaced from each other are recessed from the second through hole to a plurality of second dielectric layers, the second lateral hole and the second through hole are in communication, and the second lateral hole communicates with the first lateral hole, and the write channel layer and the write gate dielectric layer are arranged in sequence in the second lateral hole;

[0017] A write word line is located in the second through hole, a plurality of write transistors are stacked along the second direction, and in the plurality of write transistors stacked along the second direction, the write gate of each write transistor is a part of the write word line, and the write gates of different write transistors are different parts of the same write word line;

[0018] A third hole penetrates the stack layer along the second direction, is located between two first holes adjacent in the third direction, and is arranged in a spaced manner with the first hole;

[0019] A read word line is located in the third hole, and a plurality of the read transistors are stacked along a second direction; and in the plurality of the read transistors stacked along the second direction, the read control gate of each of the read transistors is a part of the read word line, and the read control gates of different read transistors are different parts of the same read word line; and the read word line is located between adjacent read transistors in the third direction.

[0020] In some embodiments, the semiconductor device further comprises:

[0021] A reference signal line is located in the first via, an outer sidewall of the read channel layer surrounds the reference signal line, an outer sidewall of the first gate dielectric layer surrounds the read channel layer, and the first gate dielectric layer has a first opening away from the region of the write transistor in a first direction, the read floating gate surrounds an outer sidewall of the first gate dielectric layer and is arranged in isolation from the reference signal line, and the read floating gate has a second opening away from one side of the write transistor in the first direction, the first opening and the second opening exposing the read channel layer;

[0022] A first slot is located on a side of the first hole away from the second hole, extends in a third direction, and the first slot includes a first isolation slot and a plurality of first lateral slots spaced apart from each other in the second direction, the first isolation slot extends through the stacked layers in the second direction, the plurality of first lateral slots spaced apart from each other extend laterally from the first isolation slot, and the first lateral slots expose the read channel layer in the corresponding regions of the first opening and the second opening;

[0023] A read bit line is located in the first lateral slot and connected to the read channel layer exposed by the first lateral slot.

[0024] In some embodiments, the second gate dielectric layer includes a gate insulating layer located on the hole inner wall of the third hole, and the gate insulating layer surrounds the sidewall of the read word line.

[0025] In some embodiments, the first gate dielectric layer is also located on the sidewall and the bottom of the first via.

[0026] In some embodiments, the reference signal line includes an extension and a protrusion, the extension is located in the first via, and the protrusion is located in the first lateral hole.

[0027] In some embodiments,

[0028] The first lateral slot exposes the read floating gate in the corresponding region of the second opening;

[0029] The semiconductor device further comprises:

[0030] A first isolation structure is located between the first dielectric layers and between the read bit line and the read floating gate, and the first isolation structure shields the read floating gate exposed by the first lateral slot, so that the read floating gate is isolated from the read bit line.

[0031] In some embodiments,

[0032] Two storage units adjacent in the first direction are mirror-symmetrically arranged;

[0033] The semiconductor device further comprises a second isolation structure, which is located in the first isolation slot, and which isolates the read bit lines corresponding to two adjacent storage units.

[0034] In some embodiments, the semiconductor device further comprises:

[0035] A second slot is located on a side of the second hole away from the first hole in the first direction and extends in a third direction, the second slot comprises a second isolation slot and a plurality of second lateral slots spaced from each other in the second direction, the second isolation slot extends through the stack layer in the second direction, and the plurality of second lateral slots spaced from each other extend laterally from the second isolation slot to the write channel layer;

[0036] A write bit line is located in the second lateral slot;

[0037] A third isolation structure is located in the second isolation slot; the third isolation structure isolates the write bit lines corresponding to two adjacent storage units.

[0038] According to various embodiments of the present disclosure, a manufacturing method of a semiconductor device is also provided, the method comprising:

[0039] A substrate is provided, and a stack material layer is formed on the substrate, the stack material layer comprising first dielectric material layers and second dielectric material layers alternately stacked;

[0040] The stack material layer is etched to form a plurality of first holes, the plurality of first holes have a plurality of rows and a plurality of columns in the orthographic projection on the substrate, the row direction is the first direction, and the column direction is the third direction, the first hole comprises a first through hole and a plurality of first lateral holes spaced from each other, the first through hole extends through the stack material layer in the second direction, the plurality of first lateral holes are recessed from the first through hole to a plurality of the second dielectric material layers, and the first lateral hole is in communication with the first through hole;

[0041] In the first lateral hole, a read floating gate, a first gate dielectric layer, and a read channel layer are sequentially formed, wherein the read floating gate and the read channel layer in the first lateral hole of different layers are isolated from each other;

[0042] between two of the first holes adjacent in a third direction, etching the stack material layer in a second direction to form a third hole in the third hole, and forming a read word line in the third hole, the read word line being spaced apart from the read floating gate, the second direction being perpendicular to the substrate, and the third direction being parallel to the substrate;

[0043] etching the stack material layer to form a second hole corresponding to each of the first holes, the first holes and the corresponding second holes being arranged in sequence in a first direction; the second hole including a second through hole and a plurality of second lateral holes spaced apart from each other, the second through hole extending through the stack material layer in the second direction, the plurality of second lateral holes being recessed from the second through hole to the plurality of second dielectric material layers, the second lateral holes being in communication with the second through hole, and the second lateral holes being in communication with the first lateral holes in the first direction, the first direction being parallel to the substrate, and intersecting the third direction;

[0044] forming a write channel layer and a write gate dielectric layer in the second lateral hole in sequence, and forming a write word line in the second through hole, the outer sidewall of the write channel layer being connected to the read floating gate and the write bit line respectively, and the read floating gate and the write bit line being spaced apart.

[0045] In some embodiments, the forming, in the first lateral hole, the read floating gate, the first gate dielectric layer, and the read channel layer in sequence includes:

[0046] depositing, in the first lateral hole, a floating gate material layer, a first gate dielectric material layer, and a read channel layer in sequence;

[0047] etching the stack material layer to form a first groove extending in the third direction away from the second hole on a side of the first hole, the first groove including a first isolation groove and a plurality of first lateral grooves spaced apart from each other, the first isolation groove extending through the stack material layer in the second direction, and the plurality of first lateral grooves extending laterally from the first isolation groove to the floating gate material layer in the first hole;

[0048] sequentially etching the floating gate material layer and the first gate dielectric material layer from the first lateral groove to form the read floating gate with a second opening and the first gate dielectric layer with a first opening.

[0049] In some embodiments, after the depositing, in the first lateral hole, the floating gate material layer, the first gate dielectric material layer, and the read channel layer in sequence, the method further includes:

[0050] and filling the first through hole with a reference signal line, the reference signal line being spaced apart from the floating gate material layer and being electrically connected to each of the read channel layers;

[0051] after the reading floating gate with the second opening and the first gate dielectric layer with the first opening are formed, comprising:

[0052] forming a reading bit line in the first lateral slot and insulated from the reading floating gate;

[0053] forming a second isolation structure in the first isolation slot.

[0054] In some embodiments, the floating gate material layer, the first gate dielectric material layer and the reading channel layer are sequentially deposited in the first lateral hole, comprising:

[0055] depositing a floating gate initial material layer along the first through hole hole wall and the first lateral hole hole wall;

[0056] forming a sacrificial layer only in the first lateral hole to expose the floating gate initial material layer on the first dielectric material layer between the first lateral holes;

[0057] using the sacrificial layer as an etching stop layer to remove the exposed floating gate initial material layer, and the floating gate initial material layer in the first lateral hole forms the floating gate material layer;

[0058] removing the sacrificial layer, and depositing a first gate dielectric material layer on the surface of the floating gate material layer and the hole wall of the first through hole;

[0059] forming the reading channel layer spaced from each other in each of the first lateral holes.

[0060] In some embodiments, after the reading floating gate with the second opening and the first gate dielectric layer with the first opening are formed, the reading channel layer protrudes from the first opening and the second opening to the direction of the first isolation slot;

[0061] the reading bit line formed in the first lateral slot and insulated from the reading floating gate, comprising:

[0062] forming a first isolation structure material layer on the inner wall of the first isolation slot and the exposed structure surface in the first lateral slot;

[0063] removing the first isolation structure material layer located on the inner wall of the first isolation slot and the sidewall of the reading channel layer to form a first isolation structure extending in the third direction;

[0064] forming a reading bit line in the first lateral slot after the first isolation structure is formed.

[0065] In some embodiments, the etching the stack material layer to form the first slot extending along the third direction on a side of the first hole away from the second hole comprises:

[0066] forming the first isolation slot on a side of the first hole away from the second hole in the first direction;

[0067] laterally etching the second dielectric material layer from the first isolation slot to form the first lateral slot symmetrically on both sides of the first isolation slot in the first direction.

[0068] In some embodiments, before forming the read word line in the third hole, the method comprises:

[0069] forming a gate insulating layer on a hole wall of the third hole.

[0070] In some embodiments, after forming the write channel layer and the write gate dielectric layer in the second lateral hole and the write word line in the second via, the method comprises:

[0071] etching the stack material layer to form a second slot extending along the third direction on a side of the second hole away from the first hole in the first direction, the second slot comprising a second isolation slot and a plurality of second lateral slots spaced apart from each other, the second isolation slot penetrating the stack material layer along the second direction, and the plurality of second lateral slots spaced apart from each other in the second direction extending laterally to the write channel layer from the second isolation slot;

[0072] forming a write bit line in the second lateral slot;

[0073] forming a third isolation structure in the second isolation slot.

[0074] According to various embodiments of the present disclosure, an electronic device is also provided, which includes the semiconductor device of any of the above embodiments.

[0075] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF DRAWINGS

[0076] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the accompanying drawings needed to be used in the embodiments or the description of the prior art will be briefly introduced. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0077] FIG. 1 is a flowchart of a manufacturing method of a storage structure provided in an embodiment;

[0078] Fig. 2 is a flowchart of step S31 in Fig. 1;

[0079] Figs. 3-18 are schematic structural diagrams of structures obtained at respective steps in a preparation process of a storage structure provided in an embodiment, and in each of the drawings, (a) is a plan view, (b) is a cross-sectional view, and (c) is a cross-sectional view;

[0080] Fig. 19 is a schematic structural diagram of a storage structure provided in an embodiment.

[0081] For a better understanding of the embodiments and / or examples of the inventions disclosed herein, reference can be made to one or more of the accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the presently described embodiments and / or examples, and the best mode presently contemplated of these inventions. DETAILED DESCRIPTION

[0082] For the purpose of the present disclosure, a more complete description of the preferred embodiments of the present disclosure will be presented in connection with the accompanying drawings. The preferred embodiments of the present disclosure are illustrated in the drawings. However, the present disclosure can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present disclosure to those skilled in the art.

[0083] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.

[0084] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to", or "directly coupled to" another element or layer, then there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

[0085] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and / or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The devices can be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0086] As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0087] The related structure of the embodiments of the present disclosure should not be limited to the specific shape shown in the drawings of the specification, but includes shape deviations due to, for example, manufacturing techniques. The shapes shown in the figures are substantially schematic and do not limit the scope of the present disclosure.

[0088] In one embodiment, referring to FIG. 1, a method for manufacturing a semiconductor device is provided, comprising the following steps:

[0089] At step S10, referring to FIG. 3, a substrate 100 is provided, and a stack material layer 2001 is formed on the substrate 100, the stack material layer 2001 comprising first dielectric material layers 2101 and second dielectric material layers 2201 alternately stacked.

[0090] At step S20, referring to FIG. 3, the stack material layer is etched to form a plurality of first holes, the orthographic projection of the plurality of first holes on the substrate is distributed in multiple rows and multiple columns (e.g., the first holes in FIG. 3 are arranged in two rows and two columns), the row direction is a first direction, and the column direction is a third direction. The first holes comprise a first via and a plurality of first lateral holes spaced apart from each other. The first via penetrates the stack material layer along a second direction. The plurality of first lateral holes are recessed from the first via to the plurality of second dielectric material layers. The first lateral holes are in communication with the first via.

[0091] The first via hole and the first lateral hole are formed in sequence, the first via hole has a same aperture in the second direction, and the first via hole can be obtained by dry etching in actual manufacturing.

[0092] The first lateral hole is formed by laterally etching the second dielectric material layer after the first via hole is formed.

[0093] In step S30, referring to FIG. 11, a reading floating gate, a first gate dielectric layer and a reading channel layer are sequentially formed in the first lateral hole 12, wherein the reading floating gate and the reading channel layer in the first lateral hole of different layers are isolated from each other; the first lateral hole 12 includes a side wall parallel to the substrate and a side wall perpendicular to the substrate, and the reading floating gate, the first gate dielectric layer and the reading channel layer are all film layers, and the main surfaces of the film layers are deposited on the side wall parallel to the substrate and the side wall perpendicular to the substrate in the first lateral hole 12.

[0094] In step S50, referring to FIGS. 16 and 17, a third hole 13 is formed by etching the stacked material layer 2001 in the second direction between two first holes adjacent in the third direction, and a reading word line 410 is formed in the third hole 13, the reading word line 410 is arranged in insulation with the reading floating gate 310, the second direction is perpendicular to the substrate, and the third direction is parallel to the substrate; the third hole 13 and the first hole include the stacked first dielectric material layer 2101 and the second dielectric material layer 2201.

[0095] In step S60, the stacked material layer 2001 is etched to form a second hole arranged in the first direction along the first hole, the second hole includes a second via hole and a plurality of second lateral holes spaced from each other, the second via hole penetrates the stacked material layer in the second direction, the plurality of second lateral holes are recessed from the second via hole to the plurality of second dielectric material layers, the second lateral hole is communicated with the second via hole, and the second lateral hole is communicated with the first lateral hole in the first direction, the first direction is parallel to the substrate and intersects the third direction.

[0096] As an example, the first hole and the second hole can be arranged in the form of a periodic cycle ABBA (such as ABBAABBA) in the first direction. Wherein A and B respectively represent the first hole and the second hole. In this way, the first hole and the second hole are arranged, and each two adjacent AB or BA is included in a storage unit. Of course, the first hole and the second hole can also be arranged in the form of a periodic cycle AB (such as ABABABAB) in the first direction.

[0097] In step S70, referring to FIG. 18, a writing channel layer 520 and a writing gate dielectric layer 510 are sequentially formed in each second lateral hole, and a writing word line 620 is formed in the second via hole, the outer side wall of the writing channel layer 520 is connected to the reading floating gate 310 and the writing bit line 610 respectively, and the reading floating gate 310 and the writing bit line 610 are spaced apart.

[0098] In step S10, referring to FIG. 3, the substrate 100 can be a single-layer structure or a multi-layer structure.

[0099] For example, the substrate 100 can include a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrate or II / VI semiconductor substrate. Alternatively, for example, the substrate 100 can also include a Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator substrate.

[0100] In some cases, the substrate 100 can also include a logic circuit or the like structure, which is omitted as it is not related to the point of the present application.

[0101] The first dielectric material layer 2101 and the second dielectric material layer 2201 can be alternately stacked on the substrate 100 by deposition or the like process to form a stack material layer 2001. The materials of the first dielectric material layer 2101 and the second dielectric material layer 2201 can include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride, or the like. The materials of the first dielectric material layer 2101 and the second dielectric material layer 2201 are different. For example, the material of the first dielectric material layer 2101 can be silicon oxide for insulation, and the material of the second dielectric material layer 2201 can be silicon nitride for a sacrificial layer.

[0102] In step S20, referring to FIG. 3, for example, the stack material layer 2001 can be etched along the second direction first to form a first via hole 11 penetrating through the stack material layer 2001. Then, the second dielectric material layer 2201 can be laterally etched from the first via hole 11 to form a first lateral hole 12.

[0103] Of course, in other examples, the formation of the first via hole 11 and the first lateral hole 12 is not limited to this, for example, in the etching process of the stack material layer 2001, the first dielectric material layer 2101 can be anisotropically vertically etched and the second dielectric material layer 2201 can be isotropically etched by changing the etching conditions, so that after the etching of each of the first dielectric material layer 2101 and the second dielectric material layer 2201 is completed, the first via hole 11 penetrating through the stack material layer 2001 along the second direction and the first lateral hole 12 recessed from the first via hole 11 to the second dielectric material layer 2201 are formed.

[0104] In step S30, the material of the read floating gate 310 is a conductive material, for example, titanium nitride. The material of the first gate dielectric layer 320 can include, but is not limited to, an oxide or a nitride, etc. The material of the read channel layer 330 can include, but is not limited to, a semiconductor material such as polysilicon, metal oxide, etc.

[0105] The read floating gate 310 and the read channel layer 330 are located in the first lateral hole 12, so that the read floating gate 310 and the read channel layer 330 in the first lateral hole 12 of different layers are insulatively and separately arranged.

[0106] As an example, step S30 can include:

[0107] In step S31, the floating gate material layer, the first gate dielectric material layer, and the read channel layer are sequentially deposited in the first lateral hole.

[0108] In step S32, the stack material layer is etched on the side of the first hole away from the second hole to form a first groove extending in the third direction, the first groove including a first isolation groove and a plurality of first lateral grooves spaced from each other, the first isolation groove penetrating the stack material layer in the second direction to expose the stacked first and second dielectric material layers, and each second dielectric material layer is laterally etched to obtain a plurality of first lateral grooves spaced from each other, the first lateral groove exposing the floating gate material layer.

[0109] In step S33, the floating gate material layer and the first gate dielectric material layer are sequentially etched from the first lateral groove to form an opening, specifically, the read floating gate with a second opening and the first gate dielectric layer with a first opening.

[0110] Referring to FIG. 9, step S31 can first form the floating gate material layer 3101 on the hole wall of the first lateral hole 12. Then the first gate dielectric material layer 3201 is formed on the surface of the floating gate material layer 3101. Then the read channel layer 330 is formed on the surface of the first gate dielectric material layer 3201.

[0111] After step S31 forms the read channel layer 330, the reference signal line 420 can also be filled in the first through hole 11, so that the reference signal line 420 is electrically connected with each read channel layer 330. And the reference signal line 420 is insulatively arranged with the floating gate material layer 3101, so as to prevent the reference signal line 420 from short-circuiting with the read floating gate 310 subsequently formed by the floating gate material layer 3101. The material of the reference signal line 420 is a conductive material. And the reference signal line 420 can be a single-layer structure or a multi-layer structure.

[0112] The reference signal line 420 can include, for example, a first diffusion barrier layer 421 and a first metal layer 422. The first diffusion barrier layer 421 can block diffusion of the metal in the first metal layer 422. The material of the first diffusion barrier layer 421 can include, but is not limited to, titanium nitride, etc., and the material of the first metal layer 422 can include, but is not limited to, tungsten, etc.

[0113] At this time, the first diffusion barrier layer 421 can be formed first on the surface of the first gate dielectric material layer 3201 located at the hole wall of the first via 11 and on the surface of the read channel layer 330. Then, the first metal material layer filling the first via 11 is formed on the surface of the first diffusion barrier layer 421 and above the stack material layer 2001. After that, the first metal material layer is subjected to chemical mechanical polishing processing, and the first metal material layer above the stack material layer 2001 is removed, thereby forming the first metal layer 422.

[0114] When the read channel material layer is recessed at the portion opposite to the first lateral hole 12, the read channel layer 330 formed by the read channel material layer in the first lateral hole 12 is also recessed at the portion opposite to the first lateral hole 12. At this time, after the reference signal line 420 is formed, the reference signal line 420 includes an extension part located in the first via and a protruding part located in the first lateral hole, and the protruding part protrudes from the extension part to the recessed area in the read channel layer 330. At this time, the contact area between the reference signal line 420 and the read channel layer 330 can be effectively increased, thereby reducing the contact resistance therebetween.

[0115] In step S32, referring to FIG. 10, the stack material layer 2001 can be etched first on one side of the reference signal line 420 in the first direction to form a first isolation groove 21 extending along the third direction and penetrating through the stack material layer 2001, and the first isolation groove 21 is arranged spaced apart from the floating gate material layer 3101. Then, referring to FIG. 11, the second dielectric material layer 2201 is etched laterally from the first isolation groove 21 to form a first lateral groove 22.

[0116] In step S33, the floating gate material layer 3101 exposed in the first lateral hole 12 exposed by the first lateral groove 22 is etched to expose the first gate dielectric material layer 3201, and the first gate dielectric material layer 3201 is etched to expose the read channel layer 330, to form the etched floating gate material layer 3101 and the first gate dielectric material layer 3201, to form the read floating gate 310 with the second opening and the first gate dielectric layer 320 with the first opening.

[0117] The first gate dielectric layer 320 and the read floating gate 310 are located in the first lateral hole 12, and include a sidewall extending in a direction perpendicular to the substrate and a sidewall extending in a direction parallel to the substrate, the sidewall surrounding the first lateral hole 12, and the first opening and the second opening are located on the sidewall of the sidewall extending in the direction perpendicular to the substrate.

[0118] After step S33, the following steps can also be included:

[0119] In step S41, a read bit line 430 insulated from the read floating gate 310 is formed in the first lateral groove 22.

[0120] In step S42, a second isolation structure 820 is formed in the first isolation groove 21.

[0121] The plurality of memory cells stacked in the direction perpendicular to the substrate are connected to different read bit lines 430 respectively.

[0122] The read channel layer 330 between the read bit line 430 and the reference signal line 420 can serve as a channel region of the read transistor 300.

[0123] The second isolation structure 820 is an insulating isolation layer, which can be used to isolate the memory cells in the first direction.

[0124] Referring to FIG. 14, the read bit line 430 can be formed in the first lateral groove 22 extending in the third direction, so as to extend in the third direction. The material of the read bit line 430 can be a single-layer structure or a multi-layer structure.

[0125] The read bit line 430 can include a second diffusion barrier layer 431 and a second metal layer 432. The second diffusion barrier layer 431 can block the diffusion of the metal in the second metal layer 432. The material of the second diffusion barrier layer 431 can include, but is not limited to, titanium nitride, etc., and the material of the second metal layer 432 can include, but is not limited to, tungsten, etc.

[0126] As an example, the material of the read channel layer 330 can include polysilicon, and the material of the read bit line 430 can include a metal material. Before forming the read bit line 430, a metal silicide can also be formed on the surface of the read channel layer 330, so as to reduce the contact resistance between the read channel layer 330 and the read bit line 430.

[0127] In step S50, referring to FIG. 16, a third hole 13 spaced apart from the read floating gate 310 is formed on one side of the read floating gate 310 in the third direction. The read bit line extends in the third direction, and the first hole and the third hole of the reference signal line are spaced apart in the third direction, and the third hole is closer to the read bit line.

[0128] Referring to FIG. 17, a second gate dielectric layer and a read word line 410 are formed in the third hole 13. Since the third hole 13 is spaced apart from the read floating gate 310, the read word line 410 formed in the third hole 13 is spaced apart from the read floating gate 310.

[0129] The read word line material layer can be formed first on the hole wall (side wall and bottom) of the third hole 13 and on the stack material layer 2001, and then the read word line material layer formed on the stack material layer 2001 is removed by a chemical mechanical polishing process to form the read word line 410. The read word line 410 can include a third diffusion barrier layer 411 and a third metal layer 412.

[0130] The read word line 410 and the read floating gate 310 are both disposed on the outer side wall of the read channel layer 330, and the read floating gate 310 is located between the read word line 410 and the read channel layer 330. The read floating gate stores electric charges, and the read word line 410 controls the read floating gate to achieve charge reading on the side of the read floating gate.

[0131] The above steps form the read transistor 300, which includes two gates, one of which is the read floating gate, and the read floating gates of the read transistors 300 of the plurality of storage units stacked and distributed are insulated from each other. The other of the two gates is the read control gate, which is part of the read word line 410. The other gate (read control gate) of the read transistors 300 of the plurality of storage units stacked and distributed is part of the same read word line 410. That is, the read word line 410 can include the read control gates of the plurality of read transistors 300 stacked in the second direction. The read control gate and the read floating gate 310 include the second gate dielectric layer and the stack material layer therebetween.

[0132] For example, the second dielectric material layer 2201 between the read word line 410 and the read floating gate 310 can also be used as the second gate dielectric layer of the read transistor 300.

[0133] Alternatively, a gate insulating layer can be formed on the hole wall of the third hole 13 first, and then the read word line 410 is formed. At this time, the gate insulating layer can simultaneously serve as the second gate dielectric layer with the second dielectric material layer 2201 between the read word line 410 and the read floating gate 310.

[0134] Based on this, the read transistor 300 includes the read control gate, the second gate dielectric layer, the read floating gate 310, the first gate dielectric layer 320, and the read channel layer 330.

[0135] The material of the read word line 410 is a conductive material, which can be a single-layer structure or a multi-layer structure.

[0136] As an example, the read word line 410 can include a third diffusion barrier layer 411 and a third metal layer 412. The third diffusion barrier layer 411 can block diffusion of the metal in the third metal layer 412. The material of the third diffusion barrier layer 411 can include, but is not limited to, titanium nitride, etc., and the material of the third metal layer 412 can include, but is not limited to, metal tungsten, etc.

[0137] In step S60, referring to FIG. 18, the stack material layer 2001 can be etched first along the second direction to form a second via. Then, the second dielectric material layer 2201 is etched laterally from the side of the second via with the read floating gate 310 as the etching stop layer, thereby forming a second lateral hole.

[0138] In step S70, referring to FIG. 18, a write channel layer 520 can be formed first on the wall of the second lateral hole. The material of the write channel layer 520 can include, for example, indium gallium zinc oxide (IGZO). It should be noted that the material of the write channel layer 520 can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx, etc. as long as the drain current of the transistor can meet the requirements, and the specific adjustment can be made according to the actual situation.

[0139] Then, a write gate dielectric layer 510 is formed on the surface of the write channel layer 520 and the wall (including the sidewall and the bottom wall) of the second via. The material of the write gate dielectric layer 510 can include silicon oxide, silicon nitride, silicon oxynitride, etc. The material of the write gate dielectric layer 510 can be the same as that of the first dielectric material layer 2101. Of course, the two can also be different.

[0140] After that, a write word line 620 in a single-layer structure or a multi-layer structure can be formed in the second via.

[0141] The write word line 620 can include, for example, a fourth diffusion barrier layer and a fourth metal layer. The fourth diffusion barrier layer can block diffusion of the metal in the fourth metal layer. The material of the fourth diffusion barrier layer can include, but is not limited to, titanium nitride, etc., and the material of the fourth metal layer can include, but is not limited to, metal tungsten, etc.

[0142] At this time, the read transistor 300 can be formed first, and then the write transistor 500 can be formed. Of course, the write transistor 500 can also be formed before the read transistor 300, or formed synchronously with the read transistor 300, which is not limited herein.

[0143] The write transistor 500 includes a write gate, and a write gate dielectric layer 510 and a write channel layer 520 arranged in sequence around the write gate. The write gates of the plurality of write transistors 500 stacked in the second direction are part of a write word line. The write transistor 500 is a channel full-encircling transistor, and the write channel layer 520 forms a closed ring shape around the sidewall of the write word line.

[0144] The write transistor 500 and the read transistor 300 can be included in a 2T0C type storage unit 30, and the read of the storage information 0 and 1 is realized by effectively controlling the charge reading process of the floating gate by the read word line 410 (read control gate).

[0145] In the method of the embodiment, the read floating gate, the first gate dielectric layer, and the read channel layer of the read transistor are formed in the first hole. The write transistor 500 is formed in the second hole arranged in the first direction with the first hole. And the read word line is formed in the third hole on the side of the first hole in the third direction. At this time, the read control gate can be formed on the side of the read transistor 300, so that the unit area of the storage unit 30 can be effectively reduced. In the embodiment of the disclosure, each storage unit includes a read transistor and a write transistor arranged in sequence in the first direction; the two adjacent storage units in the first direction are mirror-symmetrically distributed. The two storage units distributed in the first direction are periodically distributed in the first direction, and the storage units distributed in the first direction are periodically distributed in the third direction. Each layer of storage units includes the above-mentioned storage units distributed in the first direction and the third direction. Each layer of storage units is periodically stacked in the second direction.

[0146] In one embodiment, referring to FIG. 2, step S31 includes:

[0147] Step S311, referring to FIG. 4, a floating gate initial material layer 3102 is formed along the hole wall of the first through hole 11 and the hole wall of the first lateral hole 12;

[0148] Step S312, referring to FIG. 5, a sacrificial layer 700 is formed in the first lateral hole 12;

[0149] Step S313, referring to FIG. 6, taking the sacrificial layer 700 as an etching stop layer, the floating gate initial material layer 3102 outside the first lateral hole 12 is removed to form a floating gate material layer 3101;

[0150] Step S314, referring to FIG. 7, the sacrificial layer 700 is removed, and a first gate dielectric material layer 3201 is formed on the surface of the floating gate material layer 3101 and the hole wall of the first via 11;

[0151] Step S315, referring to FIG. 8, a read channel layer 330 is formed in the first lateral hole 12.

[0152] In step S311, referring to FIG. 4, a 4nm-6nm (e.g. 5nm) thick floating gate initial material layer 3102 can be formed on the hole wall of the first via 11 and the hole wall of the first lateral hole 12 by atomic layer deposition or the like.

[0153] In step S312, referring to FIG. 5, a sacrificial material layer can be first formed on the surface of the floating gate initial material layer 3102. The sacrificial material layer can fill the first lateral hole 12. For example, a 18nm-22nm (e.g. 20nm) thick sacrificial material layer can be formed.

[0154] Then, the sacrificial material layer outside the first lateral hole 12 can be removed. For example, a 21nm-25nm (e.g. 23nm) thick sacrificial material layer can be removed, thereby forming a sacrificial layer 700 in the first lateral hole 12. The material of the sacrificial layer 700 can include but is not limited to polysilicon or the like.

[0155] It can be understood that the specific thickness of the floating gate initial material layer 3102, the sacrificial material layer and the like in the present disclosure can be set according to actual conditions, and the above thickness is only an enumeration and does not constitute a limitation on the present disclosure.

[0156] In step S313, referring to FIG. 6, after etching the floating gate initial material layer 3102 with the sacrificial layer 700 as an etching stop layer, the remaining floating gate initial material layer 3102 forms a floating gate material layer 3101.

[0157] In step S314, referring to FIG. 7, after removing the sacrificial layer 700, the floating gate material layer 3101 in the first lateral hole 12 is exposed. Then, a first gate dielectric material layer 3201 can be formed on the hole wall of the first via 11 and the surface of the floating gate material layer 3101 by atomic layer deposition or the like. The thickness of the first gate dielectric material layer 3201 can be, for example, 5nm-7nm (e.g. 6nm). The material of the first gate dielectric material layer 3201 can include silicon oxide, silicon nitride or silicon oxynitride or the like.

[0158] As an example, the material of the first gate dielectric material layer 3201 can be the same as that of the first dielectric material layer 2101.

[0159] In step S315, referring to FIG. 8, a reading channel material layer can be first formed on the surface of the first gate dielectric material layer 3201 by a deposition process or the like. The thickness of the reading channel material layer can be, for example, 9-11 nm (e.g., 10 nm).

[0160] By way of example, the reading channel material layer can be controlled in thickness or the like so that the reading channel material layer is recessed at a portion opposite the first lateral hole 12.

[0161] Then, the reading channel material layer outside the first lateral hole 12 is etched away, while the reading channel material layer within the first lateral hole 12 is not etched away due to being shielded by the first dielectric material layer 2101. The reading channel material layer remaining within the first lateral hole 12 forms a reading channel layer 330. The thickness of the etched away portion can be 11-13 nm (e.g., 12 nm).

[0162] In the present embodiment, by simultaneously forming the first gate dielectric material layer 3201 on the surface of the floating gate material layer 3101 within the first lateral hole 12 and the hole wall of the first via 11, the reference signal line 420 can be insulated from the floating gate material layer 3101 by the first gate dielectric material layer 3201 on the sidewall of the first via 11 after the reference signal line 420 is subsequently formed. Meanwhile, the first gate dielectric material layer 3201 on the bottom wall of the first via 11 can effectively insulate and isolate the reference signal line 420 from the substrate 100.

[0163] At this point, after the floating gate material layer 3101 is etched to form the reading floating gate 310 and the first gate dielectric material layer 3201 is etched to form the first gate dielectric layer 320, the reading floating gate 310 and the reference signal line 420 can be effectively insulated by the first gate dielectric layer 320 on the sidewall of the first via 11. Meanwhile, the reference signal line 420 can be effectively insulated from the substrate 100 by the first gate dielectric layer 320 on the bottom wall of the first via 11.

[0164] Of course, in other embodiments, the reading floating gate 310 and the reference signal line 420 can be insulated and isolated in other ways. For example, a sacrificial layer 700 can be prepared to expose the sidewall of the first lateral hole 12 near the first via 11 when the reading floating gate 310 is formed, and then the floating gate material layer 3101 exposes the sidewall of the first lateral hole 12 near the first via 11 after the floating gate material layer 3101 is formed by etching the floating gate initial material layer 3102 with the sacrificial layer 700 as an etching stop layer. After that, even if only the first gate dielectric material layer 3201 is formed within the first lateral hole 12, the first gate dielectric material layer 3201 (the first gate dielectric layer 320 formed after a subsequent etching step) on the sidewall of the first lateral hole 12 can insulate and isolate the reading floating gate 310 from the reference signal line 420.

[0165] In one embodiment, referring to FIG. 11, after the step S40 of forming the read floating gate 310 with the second opening and the first gate dielectric layer 320 with the first opening, the read channel layer 330 protrudes from the first opening and the second opening towards the first isolation trench 21.

[0166] At this time, when the first lateral trench 22 is etched from the first isolation trench 21, after the floating gate material layer 3101 and the first gate dielectric material layer 3201 are etched to expose the read channel layer 330, the floating gate material layer 3101 and the first gate dielectric material layer 3201 can also be etched for a period of time, so that the read channel layer 330 protrudes from the first opening and the second opening towards the first isolation trench 21.

[0167] Meanwhile, the step S41 includes:

[0168] Step S411, referring to FIG. 12, a first isolation structure material layer 8101 is formed on the structure surface exposed in the inner wall of the first isolation trench 21 and the first lateral trench 22;

[0169] Step S412, referring to FIG. 13, the first isolation structure material layer 8101 located on the inner wall of the first isolation trench 21 and the sidewall of the read channel layer 330 is removed to form the first isolation structure 810 extending in the third direction;

[0170] Step S4133, referring to FIG. 14, the read bit line 430 is formed in the first lateral trench 22 after the first isolation structure 810 is formed.

[0171] In step S411, referring to FIG. 12, the first isolation structure material layer 8101 can be formed on the structure surface exposed in the inner wall of the first isolation trench 21 and the first lateral trench 22 above the stacked material layer 2001 by atomic layer deposition or other processes.

[0172] Meanwhile, the read channel layer 330 protrudes from the first opening and the second opening towards the first isolation trench 21. Therefore, in the area between the read channel layer 330 and the first dielectric material layer 2101 above and below it, as the deposition thickness of the first isolation structure material layer 8101 increases, the first isolation structure material layer 8101 formed on the surface of the read channel layer 330 and the first isolation structure material layer 8101 formed on the surface of the first dielectric material layer 2101 can be connected to each other, and have a relatively long length in the first direction. The thickness of the first isolation structure material layer 8101 can be, for example, 4-6 nm (e.g., 5 nm).

[0173] Then, the first isolation structure material layer 8101 is removed by a chemical mechanical polishing process or the like. At this time, the read floating gate 310, the first gate dielectric layer 320 and the read channel layer 330 exposed in the first lateral trench 22 are covered by the first isolation structure material layer 8101.

[0174] The material of the first isolation structure material layer 8101 can include, but is not limited to, silicon oxide, silicon nitride or the like. As an example, the material of the first isolation structure material layer 8101 can be the same as the material of the first dielectric material layer 2101, and of course, the two can also be different.

[0175] In step S412, referring to FIG. 13, the first isolation structure material layer 8101 on the hole wall of the first isolation trench 21 and the sidewall of the read channel layer 330 can be removed by an isotropic etching process. The first isolation structure material layer 8101 filled in the region between the read channel layer 330 and the first dielectric material layer 2101 above and below it has a long length, as described above. Therefore, this part of the first isolation structure material layer 8101 can have a remaining after etching, thereby forming the first isolation structure 810 extending in the third direction.

[0176] As an example, the etching removal thickness of the first isolation structure material layer 8101 can be 5nm-7nm (such as 6nm).

[0177] In step S413, referring to FIG. 14, as an example, the read bit line 430 can include a second diffusion barrier layer 431 and a second metal layer 432.

[0178] When the read channel layer 330 is polysilicon, a metal silicide can be first formed on the surface of the read channel layer 330 exposed in the first lateral trench 22. Then, a second diffusion barrier material layer is formed on the exposed structure surface along the first isolation trench 21 and the first lateral trench 22, and then a second metal material layer is formed on the surface of the second diffusion barrier material layer. After that, the second diffusion barrier material layer and the second metal material layer are etched to remove the second diffusion barrier material layer and the second metal material layer outside the first lateral trench 22, so as to form the second diffusion barrier layer 431 and the second metal layer 432.

[0179] In this embodiment, by setting the read channel layer 330 to be exposed from the first opening and the second opening to the direction of the first isolation trench 21 when the first lateral trench 22 is etched from the first isolation trench 21, the first isolation structure 810 extending in the third direction can be formed in the region between the read channel layer 330 and the first dielectric material layer 2101 above and below it. At this time, the read floating gate 310 and the read bit line 430 can be effectively insulated and isolated by the first isolation structure 810.

[0180] Of course, in other embodiments, the read floating gate 310 and the read bit line 430 can be insulated by other means. For example, after the step S40 of forming the read floating gate 310 with the second opening and the first gate dielectric layer 320 with the first opening, the read channel layer 330 is protruded from the first opening and the second opening towards the first isolation trench 21, and then the deposition method and the deposition condition are adjusted to form the read bit line 430, so that an air gap is formed between the read bit line 430 and the read floating gate 310. Alternatively, in some embodiments, the surface oxidation between the effective read floating gate 310 and the ineffective read floating gate or the parasitic read floating gate between the effective read floating gate 310 can be used to achieve the insulation between the effective read floating gate 310 and the read floating gate 310, and the insulation region is the isolation region formed by the oxidation of the parasitic floating gate.

[0181] In one embodiment, the step S32 etches the stacked material layer to form a first trench extending along the third direction on the side of the first hole away from the second hole, including:

[0182] The step S321, please refer to FIG. 10, forms the first isolation trench 21 on the side of the first hole away from the second hole in the first direction;

[0183] The step S322, please refer to FIG. 11, laterally etches the second dielectric material layer from the side of the first isolation trench 21 to form the first lateral trench 22 symmetrically on both sides of the first isolation trench 21 in the first direction.

[0184] At this time, two columns of storage units 30 can be formed with the read bit lines 430 formed based on the same first isolation trench 21, so that the storage density can be effectively improved.

[0185] In one embodiment, please refer to FIG. 18, after the step S70 of sequentially forming the write channel layer and the write gate dielectric layer in the second lateral hole and forming the write word line in the second via, further including:

[0186] The step S81 etches the stacked material layer 2001 to form a second trench extending along the third direction on the side of the second hole away from the first hole in the first direction, the second trench including a second isolation trench and a plurality of second lateral trenches spaced from each other, the second isolation trench penetrating through the stacked material layer along the second direction, and the plurality of second lateral trenches extending laterally from the second isolation trench to the write channel layer, the remaining first dielectric material layer 2101 forms the first dielectric layer 210, the remaining second dielectric material layer 2201 forms the second dielectric layer 220, and the second dielectric layer 220 and the first dielectric layer 210 form the stacked layer 200;

[0187] The step S82 forms the write bit line 610 in the second lateral trench;

[0188] In step S83, a third isolation structure 830 is formed in the second isolation groove.

[0189] In step S81, the stack material layer 2001 can be etched first to form a second isolation groove extending along the third direction. Then the second dielectric material layer 2201 is etched from the second isolation groove to form a second lateral groove.

[0190] In step S82, a single-layer structure or a multi-layer structure of write bit lines 610 can be formed in the second lateral groove.

[0191] In step S83, the third isolation structure 830 can be formed by deposition or other processes. The material of the third isolation structure 830 can include silicon oxide, silicon nitride, silicon oxynitride, etc. The material of the third isolation structure 830 can be the same as that of the second dielectric layer 220. Of course, the two can also be different.

[0192] The material of the third isolation structure 830 is an insulating material, and the third isolation structure 830 and the second isolation structure 820 are respectively located on both sides of the storage unit 30 in the first direction, thereby isolating the storage unit. And the third isolation structure 830 and the second isolation structure 820 extend along the third direction, thereby isolating the same column of storage units arranged along the third direction in each layer of storage units between the two.

[0193] It should be understood that although each step in the flowchart of FIG. 1 is shown in sequence according to the direction of the arrow, these steps are not necessarily executed in sequence according to the direction of the arrow. Unless otherwise explicitly stated herein, there is no strict order limitation for the execution of these steps, and these steps can be executed in other orders. Moreover, at least part of the steps in FIG. 1 can include multiple steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but can be executed alternately or alternately with at least part of other steps or steps or stages in other steps.

[0194] In one embodiment, a semiconductor device is also provided, please refer to FIG. 18 and FIG. 19, the semiconductor device includes a storage unit 30.

[0195] The storage unit 30 includes a read transistor 300 and a write transistor 500 arranged in sequence along the first direction.

[0196] The write transistor 500 includes a write gate extending along the second direction, a write gate dielectric layer 510, and a write channel layer 520. The write gate dielectric layer 510 surrounds the write gate. The write channel layer 520 surrounds the write gate dielectric layer 510. The write channel layer 520 is connected to the write bit line 610.

[0197] The material of the write gate is a conductive material, for example, including a metal material (such as tungsten metal) and the like. The material of the write gate dielectric layer 510 can include, but is not limited to, an oxide or a nitride and the like. The write channel layer 520 can include, but is not limited to, a metal oxide semiconductor layer, such as a semiconductor material of indium gallium zinc oxide (IGZO) and the like. It should be noted that the material of the metal oxide semiconductor layer can also be ITO, IWO, ZnOx, InOx, In2O3, InWO, SnO2, TiOx, InSnOx, ZnxOyNz, MgxZnyOz, InxZnyOz, InxGayZnzOa, ZrxInyZnzOa, HfxInyZnzOa, SnxInyZnzOa, AlxSnyInzZnaOd, SixInyZnzOa, ZnxSnyOz, AlxZnySnzOa, GaxZnySnzOa, ZrxZnySnzOa, InGaSiO, IAZO, IGO, IZO (indium-zinc-oxide), IZOx and the like, as long as the leakage current of the transistor can meet the requirements, which can be adjusted according to the actual situation.

[0198] The read transistor and the write transistor are arranged in sequence along the first direction.

[0199] The read transistor 300 includes, arranged in sequence from inside to outside, a read channel layer 330, a first gate dielectric layer 320, a read floating gate 310, a second gate dielectric layer, and a read control gate. It can be understood that in the perspective view shown in FIG. 19, the read channel layer 330 is wrapped inside by the first gate dielectric layer 320, so the read channel layer 330 is not shown in FIG. 19.

[0200] The material of the read channel layer 330 can include, but is not limited to, a semiconductor material such as polysilicon or a metal oxide semiconductor material. The material of the first gate dielectric layer 320 can include, but is not limited to, an oxide or a nitride and the like, which can be a low-K material or a high-K material. The material of the read floating gate 310 is a conductive material, for example, including titanium nitride and the like. The material of the second gate dielectric layer can include, but is not limited to, an oxide or a nitride and the like. The material of the read control gate is a conductive material, for example, including a metal material (such as tungsten metal) and the like.

[0201] The read channel layer 330 is annular, and the axis of the annular shape extends in the second direction. The first gate dielectric layer 320 is disposed around the outer sidewall of the read channel layer 330. The read floating gate 310 is disposed around the outer sidewall of the first gate dielectric layer 320. The second gate dielectric layer is located in the third direction on the outer sidewall of the read floating gate. The read control gate is located in the third direction on the side of the second gate dielectric layer away from the read floating gate. The read floating gate 310 is connected to the write channel layer 520 in the first direction and is spaced apart from the write bit line 610. The first direction, the second direction, and the third direction are perpendicular to each other, for example, the three directions are perpendicular to each other.

[0202] In the embodiment, the read transistor 300 and the write transistor are arranged in the first direction, and the read word line 410 is formed on the side of the read floating gate 310 in the third direction intersecting the first direction, so that the read control gate can be formed on the side of the read transistor 300, thereby effectively reducing the cell area of the memory cell 30.

[0203] In one embodiment, the semiconductor device further includes a substrate 100, a stack layer 200, a write word line 620, and a read word line 410. The semiconductor device further includes a first hole, a second hole, and a third hole.

[0204] The memory cell stack is disposed on the substrate 100. The second direction is perpendicular to the substrate 100, and the first direction and the third direction are parallel to the substrate 100.

[0205] The stack layer 200 is located on the substrate 100 and includes alternately stacked first dielectric layers 210 and second dielectric layers 220. The materials of the first dielectric layers 210 and the second dielectric layers 220 can include, but are not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride, etc. The materials of the first dielectric layers 210 and the second dielectric layers 220 are different. As an example, the material of the first dielectric layer 210 can be silicon oxide, and the material of the second dielectric layer 220 can be silicon nitride.

[0206] The first hole includes a first through hole 11 and a plurality of first lateral holes 12 spaced apart from each other. The first through hole 11 penetrates the stack layer 200 in the second direction. The plurality of first lateral holes 12 are recessed from the first through hole 11 to the plurality of second dielectric layers 220. The first lateral hole 12 is in communication with the first through hole 11. The read floating gate 310, the first gate dielectric layer 320, and the read channel layer 330 are sequentially disposed in the first lateral hole 12.

[0207] The second holes are arranged along the first direction with the first holes. The second holes include a second via hole and a plurality of second lateral holes spaced apart from each other. The second via hole penetrates the stack 200 along the second direction. The plurality of second lateral holes are recessed from the second via hole to the plurality of second dielectric layers 220. The second lateral holes are in communication with the second via hole. The second lateral holes are in communication with the first lateral holes in the first direction. The write channel layer 520 and the write gate dielectric layer 510 are disposed in the second lateral holes in sequence. Thus, the write channel layer 520 can be connected to the read floating gate 310.

[0208] The write word line 620 is located in the second via hole, and the write gate of the plurality of write transistors 500 stacked in the second direction is part of the write word line.

[0209] The third hole penetrates the stack 200 along the second direction and is located between two first holes adjacent in the third direction. The third hole is spaced apart from the first holes.

[0210] The read word line 410 is located in the third hole. The read control gate of the plurality of read transistors 300 stacked in the second direction is part of the read word line 410. The read word line 410 is located between adjacent read transistors 300 in the third direction.

[0211] In one embodiment, the semiconductor device further includes a reference signal line 420 and a read bit line 430, and includes a first slot.

[0212] The reference signal line 420 is located in the first via hole 11, and the read channel layer 330 surrounds the outer sidewall of the reference signal line 420. The first gate dielectric layer 320 surrounds the outer sidewall of the read channel layer 330. The first gate dielectric layer 320 has a first opening away from the region of the write transistor 500 in the first direction. The read floating gate 310 surrounds the outer sidewall of the first gate dielectric layer 320 and is disposed in isolation from the reference signal line 420. The read floating gate 310 has a second opening away from one side of the write transistor 500 in the first direction. The first opening and the second opening expose the read channel layer 330.

[0213] The first slot is located on the side of the first hole away from the second hole. The first slot extends along the third direction. The first slot includes a first isolation slot 21 and a plurality of first lateral slots 22 spaced apart from each other. The first isolation slot 21 penetrates the stack along the second direction. The plurality of first lateral slots 22 extend laterally from the first isolation slot 21, and the first lateral slots 22 expose the read channel layer 330 in the region corresponding to the first opening and the second opening.

[0214] The read bit line 430 is located in the first lateral slot 22 and is connected to the read channel layer 330 exposed by the first lateral slot 22.

[0215] A second isolation structure 820 can be provided in the first isolation slot 21.

[0216] In one embodiment, the second gate dielectric layer includes the second dielectric layer 220 between the read word line 410 and the read floating gate 310, and a gate insulating layer located on the inner wall of the third hole. The gate insulating layer surrounds the sidewall of the read word line 410.

[0217] In other embodiments, the second gate dielectric layer can also only include the second dielectric layer 220 between the read word line 410 and the read floating gate 310. At this time, only the read word line 410 is formed in the third hole, and the second gate dielectric layer does not need to be separately provided, thereby simplifying the process.

[0218] In one embodiment, the first gate dielectric layer 320 is located on the sidewall and bottom of the first through hole 11 in addition to the first lateral hole 12. That is, the first gate dielectric layer 320 extends from the first lateral hole 12 to the sidewall and bottom of the first through hole 11.

[0219] At this time, the first gate dielectric layer 320 effectively isolates the reference signal line 420 from the read channel layer 330 on the one hand, and effectively isolates the reference signal line 420 from the substrate 100 below the storage unit 30 on the other hand.

[0220] In one embodiment, the reference signal line 420 includes an extension and a protrusion. The extension is located in the first through hole 11. The protrusion is located in the first lateral hole 12 and protrudes from the extension into the read channel layer 330. At this time, the contact area of the reference signal line 420 and the read channel layer 330 can be effectively increased, thereby reducing the contact resistance therebetween.

[0221] In one embodiment, the semiconductor device further includes a first isolation structure 810. The first isolation structure 810 is located between the first dielectric layer 210 and between the read bit line 430 and the read floating gate 310 in the first direction. And the first isolation structure 810 covers the side end of the read floating gate 310 with the second opening and the side end of the first gate dielectric layer 210 with the first opening.

[0222] As an example, the first isolation structure 810 can extend in the third direction.

[0223] The material of the first isolation structure 810 layer can include, but is not limited to, silicon oxide, silicon nitride, etc. As an example, the material of the first isolation structure 810 layer can be the same as the material of the first dielectric layer 210, of course, they can also be different.

[0224] In this embodiment, the read bit line 430 and the read floating gate 310 can be effectively insulated by the first isolation structure 810.

[0225] In one embodiment, the semiconductor device further includes a second isolation structure 820. The second isolation structure 820 is located in the first isolation trench 21. Thus, the second isolation structure 820 extends along the third direction and penetrates the stack 200. And the second isolation structure 820 is symmetrically arranged with two columns of memory cells 30 on opposite sides in the first direction.

[0226] The material of the second isolation structure 820 layer can include, but is not limited to, silicon oxide, silicon nitride, etc. As an example, the material of the second isolation structure 820 layer can be the same as the material of the second dielectric layer 220, of course, they can also be different.

[0227] In one embodiment, the semiconductor further includes a second trench, a write bit line 610, and a third isolation structure 830.

[0228] The second trench is located on a side of the second hole away from the first hole in the first direction and extends along the third direction. The second trench includes a second isolation trench and a plurality of mutually spaced second lateral trenches. The second isolation trench penetrates the stack along the second direction, and the plurality of mutually spaced second lateral trenches extend laterally from the second isolation trench to the write channel layer.

[0229] The write bit line 610 is located in the second lateral trench. The third isolation structure 830 is located in the second isolation trench.

[0230] In one embodiment, an electronic device is also provided, which includes one or more semiconductor devices as in the above embodiments. The electronic device includes, for example, a data storage device, a photocopier, a network device, a household appliance, an instrument, a mobile phone, a computer, and the like, which has a data storage function. The electronic device can include a housing and a circuit board arranged in the housing, a memory or a data read / write circuit integrated on the circuit board. The structure of the memory can refer to the related description in some of the above embodiments. The electronic device can also include other necessary elements or components, which are not limited by the embodiments of the present disclosure.

[0231] The technical features of the above embodiments can be combined in any manner. In order to make the description concise, not all possible combinations of the technical features of the above embodiments are described, however, as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present disclosure.

[0232] The above-described embodiments only express several implementation manners of the present disclosure, and the description is relatively specific and detailed, but it should not be understood as a limitation on the patent scope of the application. It should be noted that for those skilled in the art, without departing from the concept of the present disclosure, a number of modifications and improvements can be made, which are within the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure should be subject to the appended claims.

Claims

1. A semiconductor device, comprising a memory cell; The storage unit includes: a write transistor and a read transistor; the write transistor comprises a write gate extending along a second direction, a write gate dielectric layer and a write channel layer successively surrounding the write gate, and the write channel layer is connected to a write bit line; the read transistor and the write transistor are successively arranged along a first direction, the read transistor comprises a read channel layer, a first gate dielectric layer, a read floating gate, a second gate dielectric layer and a read control gate, the read channel layer is annular, the first gate dielectric layer and the read floating gate are successively arranged on the outer sidewall of the read channel layer, the second gate dielectric layer and the read control gate are successively arranged on the outer sidewall of the read floating gate along a third direction; wherein the read floating gate is connected to the write channel layer, and the read floating gate and the write bit line are spaced apart along the first direction, the first direction, the second direction and the third direction intersect with each other.

2. The semiconductor device of claim 1, wherein, The semiconductor device further comprises: a substrate, the memory cell is stacked on the substrate, the second direction is perpendicular to the substrate, and the first direction and the third direction are parallel to the substrate; a stack layer on the substrate, comprising first dielectric layers and second dielectric layers stacked alternately; a first hole comprising a first through hole and a plurality of first lateral holes spaced apart from each other, the first through hole penetrates the stack layer along the second direction, and a plurality of first lateral holes recessed from the first through hole to a plurality of second dielectric layers, the first lateral hole and the first through hole are in communication, and the read floating gate, the first gate dielectric layer and the read channel layer are successively arranged in the first lateral hole; a second hole successively arranged along the first direction with the first hole, comprising a second through hole and a plurality of second lateral holes spaced apart from each other, the second through hole penetrates the stack layer along the second direction, and a plurality of second lateral holes recessed from the second through hole to a plurality of second dielectric layers, the second lateral hole and the second through hole are in communication, and the second lateral hole communicates with the first lateral hole, the write channel layer and the write gate dielectric layer are successively arranged in the second lateral hole; a write word line in the second through hole, a plurality of write transistors are stacked along the second direction, and in a plurality of write transistors stacked along the second direction, the write gate of each write transistor is a part of the write word line, and the write gates of different write transistors are different parts of the same write word line; a third hole penetrating the stack layer along the second direction, located between two first holes adjacent in the third direction, and the third hole is spaced apart from the first hole. A read word line is located in the third hole, and a plurality of the read transistors are stacked along a second direction; and in the plurality of the read transistors stacked along the second direction, the read control gate of each of the read transistors is a part of the read word line, and the read control gates of different read transistors are different parts of the same read word line; and the read word line is located between adjacent read transistors in the third direction.

3. The semiconductor device of claim 2, wherein, The semiconductor device further comprises: A reference signal line is located in the first via, the read channel layer surrounds the outer sidewall of the reference signal line, the first gate dielectric layer surrounds the outer sidewall of the read channel layer, and the first gate dielectric layer has a first opening away from the region of the write transistor in the first direction, the read floating gate surrounds the outer sidewall of the first gate dielectric layer and is arranged in isolation from the reference signal line, and the read floating gate has a second opening away from one side of the write transistor in the first direction, and the first opening and the second opening expose the read channel layer; A first slot is located on the side of the first hole away from the second hole, extends in a third direction, and the first slot comprises a first isolation slot and a plurality of first lateral slots spaced apart from each other in the second direction, the first isolation slot extends through the stacked layers in the second direction, a plurality of first lateral slots spaced apart from each other extend laterally from the first isolation slot, and the first lateral slots expose the read channel layer in the corresponding regions of the first opening and the second opening; A read bit line is located in the first lateral slot and connected to the read channel layer exposed by the first lateral slot.

4. The semiconductor device according to claim 2 or 3, wherein The second gate dielectric layer comprises a gate insulating layer located on the hole inner wall of the third hole, and the gate insulating layer surrounds the sidewall of the read word line.

5. The semiconductor device according to claim 2 or 3, wherein The first gate dielectric layer is also located on the sidewall and bottom of the first via.

6. The semiconductor device of claim 3, wherein, The reference signal line comprises an extension and a protrusion, the extension is located in the first via, and the protrusion is located in the first lateral hole.

7. The semiconductor device of claim 3, wherein The first lateral slot exposes the read floating gate in the corresponding region of the second opening; The semiconductor device further comprises: A first isolation structure is located between the first dielectric layers and between the read bit line and the read floating gate, and the first isolation structure shields the read floating gate exposed by the first lateral slot, so that the read floating gate is isolated from the read bit line.

8. The semiconductor device of claim 3, wherein Two adjacent storage units in the first direction are arranged in mirror symmetry; The semiconductor device further comprises a second isolation structure, the second isolation structure is located in the first isolation slot, and the second isolation structure isolates the read bit lines corresponding to the two adjacent storage units.

9. The semiconductor device of claim 8, wherein, The semiconductor device further comprises: a second slot located on a side of the second hole away from the first hole in the first direction and extending in a third direction, the second slot comprising a second isolation slot and a plurality of second lateral slots spaced apart from each other in a second direction, the second isolation slot extending through the stack of layers in the second direction, and the plurality of second lateral slots extending laterally from the second isolation slot to the write channel layer; a write bit line located in the second lateral slot; a third isolation structure located in the second isolation slot, the third isolation structure isolating the write bit lines corresponding to two adjacent memory cells.

10. A method for manufacturing a semiconductor device, comprising: providing a substrate and forming a stack of layers of materials on the substrate, the stack of layers of materials comprising first dielectric material layers and second dielectric material layers alternately stacked; etching the stack of layers of materials to form a plurality of first holes, the plurality of first holes having a footprint on the substrate in a plurality of rows and a plurality of columns, a row direction being a first direction and a column direction being a third direction, the first hole comprising a first via and a plurality of first lateral holes spaced apart from each other, the first via extending through the stack of layers of materials in a second direction, and the plurality of first lateral holes being recessed from the first via to a plurality of the second dielectric material layers, the first lateral hole being in communication with the first via; forming, in the first lateral hole, a read floating gate, a first gate dielectric layer, and a read channel layer in sequence, wherein the read floating gate and the read channel layer in the first lateral hole of different layers are isolated from each other; etching the stack of layers of materials in the second direction between two first holes adjacent in the third direction to form a third hole, and forming a read word line in the third hole, the read word line being spaced apart from the read floating gate, the second direction being perpendicular to the substrate, and the third direction being parallel to the substrate; etching the stack of layers of materials to form a second hole corresponding to each first hole, the first hole and the corresponding second hole being arranged in sequence in the first direction; the second hole comprising a second via and a plurality of second lateral holes spaced apart from each other, the second via extending through the stack of layers of materials in the second direction, and the plurality of second lateral holes being recessed from the second via to a plurality of the second dielectric material layers, the second lateral hole being in communication with the second via, and the second lateral hole being in communication with the first lateral hole in the first direction, the first direction being parallel to the substrate and intersecting the third direction; forming, in the second lateral hole, a write channel layer and a write gate dielectric layer in sequence, and forming a write word line in the second via, an outer sidewall of the write channel layer being connected to the read floating gate and the write bit line, respectively, the read floating gate and the write bit line being spaced apart.

11. The method of manufacturing a semiconductor device according to claim 10, wherein the forming, in the first lateral hole, a read floating gate, a first gate dielectric layer, and a read channel layer in sequence, comprises: depositing, in the first lateral hole, a floating gate material layer, a first gate dielectric material layer, and a read channel layer in sequence; etching the stack material layer on the side of the first hole away from the second hole to form a first groove extending along the third direction, the first groove comprising a first isolation groove and a plurality of first lateral grooves spaced apart from each other, the first isolation groove penetrating through the stack material layer along the second direction, and the plurality of first lateral grooves extending laterally from the first isolation groove into the floating gate material layer within the first hole; sequentially etching the floating gate material layer and the first gate dielectric material layer from the first lateral groove to form a read floating gate with a second opening and the first gate dielectric layer with a first opening.

12. The method of manufacturing a semiconductor device according to claim 11, wherein After the step of sequentially depositing the floating gate material layer, the first gate dielectric material layer and the read channel layer within the first lateral hole, the method further comprises: filling a reference signal line in the first via, the reference signal line being insulated from the floating gate material layer and electrically connected to each of the read channel layers; and After the step of sequentially etching the floating gate material layer and the first gate dielectric material layer from the first lateral groove to form a read floating gate with a second opening and the first gate dielectric layer with a first opening, the method further comprises: forming a read bit line insulated from the read floating gate within the first lateral groove; and forming a second isolation structure within the first isolation groove.

13. The method of manufacturing a semiconductor device according to Claim 11, wherein The step of sequentially depositing the floating gate material layer, the first gate dielectric material layer and the read channel layer within the first lateral hole comprises: depositing a floating gate initial material layer along the hole wall of the first via and the hole wall of the first lateral hole; forming a sacrificial layer only within the first lateral hole to expose the floating gate initial material layer on the first dielectric material layer between the first lateral holes; using the sacrificial layer as an etching stop layer to remove the exposed floating gate initial material layer, and the floating gate initial material layer within the first lateral hole forms the floating gate material layer; removing the sacrificial layer and depositing a first gate dielectric material layer on the surface of the floating gate material layer and the hole wall of the first via; and forming the read channel layers spaced apart from each other within each of the first lateral holes.

14. The method of manufacturing a semiconductor device according to Claim 11, wherein After the step of forming a read floating gate with a second opening and the first gate dielectric layer with a first opening, the read channel layer protrudes in the direction of the first isolation groove from the first opening and the second opening; The step of forming a read bit line insulated from the read floating gate within the first lateral groove comprises: forming a first isolation structure material layer on the inner wall of the first isolation groove and the exposed structure surface within the first lateral groove; removing the first isolation structure material layer on the inner wall of the first isolation groove and the sidewall of the read channel layer to form a first isolation structure extending along the third direction; and forming a read bit line within the first lateral groove after forming the first isolation structure. The step of etching the stack material layer on the side of the first hole away from the second hole to form a first groove extending along the third direction comprises: forming the first isolation groove on the side of the first hole away from the second hole in the first direction; and 15. The method of manufacturing a semiconductor device according to Claim 11, wherein laterally etching the second dielectric material layer from the first isolation groove to form the first lateral grooves symmetrically on both sides of the first isolation groove in the first direction. The step of etching the stack material layer on the side of the first hole away from the second hole to form a first groove extending along the third direction comprises: forming the first isolation groove on the side of the first hole away from the second hole in the first direction; and laterally etching the second dielectric material layer from the first isolation groove to form the first lateral grooves symmetrically on both sides of the first isolation groove in the first direction.

16. The method of manufacturing a semiconductor device according to claim 10, wherein Before forming a read word line in the third hole, comprising: forming a gate insulating layer in the third hole.

17. The method of manufacturing a semiconductor device according to Claim 10, wherein After forming the write channel layer and the write gate dielectric layer in the second lateral hole in sequence, and forming a write word line in the second via, comprising: etching the stack material layer to form a second groove extending along a third direction on a side of the second hole away from the first hole in a first direction, the second groove comprising a second isolation groove and a plurality of second lateral grooves spaced from each other, the second isolation groove penetrating through the stack material layer along a second direction, and a plurality of second lateral grooves spaced from each other in the second direction extending laterally from the second isolation groove to the write channel layer; forming a write bit line in the second lateral groove; forming a third isolation structure in the second isolation groove.

18. An electronic device comprising the semiconductor device of any one of claims 1-9.

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