Spin orbit torque magnetic memory circuit and layout thereof
By designing a spin-orbit torque magnetic memory circuit with a 4T1M architecture, using parallel transistor pairs and active regions of different widths, the problems of large layout area and low current efficiency of SOT-MRAM are solved, achieving higher current efficiency and smaller layout area.
CN116741218BActive Publication Date: 2026-06-02UNITED MICROELECTRONICS CORP
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- UNITED MICROELECTRONICS CORP
- Filing Date
- 2022-03-04
- Publication Date
- 2026-06-02
Smart Images
Figure CN116741218B_ABST
Abstract
A spin-orbit torque magnetic memory circuit and layout thereof are provided, wherein the spin-orbit torque magnetic memory circuit includes a read transistor pair having two parallel read transistors, a write transistor pair having two parallel write transistors, a spin-orbit torque magnetic memory cell having a magnetic tunnel junction and a spin-orbit torque layer, wherein one end of the magnetic tunnel junction is connected to a source of the read transistor pair and the other end is connected to the spin-orbit torque layer, one end of the spin-orbit torque layer is connected to a source line and the other end is connected to a source of the write transistor pair, a read bit line connected to drains of the read transistor pair, and a write bit line connected to drains of the write transistor pair.
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