Semiconductor memory device

Abstract

A semiconductor memory device can include a write bit line, a write transistor electrically connected with the write bit line and stacked above the write bit line, a unidirectional switch stacked above the write transistor, and a read transistor stacked above the unidirectional switch.

Description

Cross-references to related applications

[0001] This application claims priority to Korean Application No. 10-2025-0011319, filed on January 24, 2025, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The embodiments of this disclosure generally relate to an electronic device, and more specifically, to a semiconductor memory device including a memory cell. Background Technology

[0003] DRAM devices, which can represent semiconductor memory devices, can include multiple memory cells, each typically comprising a transistor and a capacitor. Currently, to improve the performance of DRAM devices, methods are being investigated for integrating a large number of memory cells within a limited area, as well as for fabricating capacitors with large capacitance within a limited area.

[0004] In recent years, in order to reduce the footprint of memory cells, extensive research has been conducted on memory cell structures that are configured to achieve higher cell density by reducing the size of capacitors or omitting capacitors, thereby reducing the footprint of memory cells. Summary of the Invention

[0005] Embodiments of this disclosure, in their broadest aspect, relate to a semiconductor memory device comprising a memory cell without a capacitor (hereinafter referred to as a "capacitor-free memory cell"). The memory cell includes a write transistor and a read transistor.

[0006] Embodiments of this disclosure provide a semiconductor memory device including a capacitor-free memory cell that can prevent data loss.

[0007] According to various embodiments, a semiconductor memory device is provided, comprising a write transistor, a read transistor, and a unidirectional switch. The write transistor can output a write bit line signal as data in response to a write word line signal. The read transistor can store data. The read transistor can output the stored data to a read bit line in response to a read word line signal. The unidirectional switch can transfer data in one direction from the write transistor to the read transistor.

[0008] According to embodiments of this disclosure, a semiconductor memory device is provided, including a write bit line, a write transistor, a unidirectional switch, and a read transistor. The write transistor may be stacked on and electrically connected to the write bit line. The unidirectional switch may be stacked on top of the write transistor. The read transistor may be stacked on top of the unidirectional switch.

[0009] In some embodiments, the write transistor may include a first channel pillar, a first gate insulating layer, a first gate, a first source, and a first drain. The first channel pillar may extend in a direction perpendicular to the surface of the write bit line. The first channel pillar may include a semiconductor material. The first gate insulating layer may be formed to surround the outer peripheral surface of the first channel pillar. The first gate may be formed to surround the outer peripheral surface of the first gate insulating layer. The first gate may be electrically connected to the write word line. The first source may be formed in the lower region of the first channel pillar. The first source may be electrically connected to the write bit line. The first drain may be formed in the upper region of the first channel pillar. The first drain may be electrically connected to a unidirectional switch.

[0010] In some embodiments, the unidirectional switch may include a first drain contact electrode and an n-type semiconductor layer. The first drain contact electrode may be formed on a first drain. The first drain contact electrode may include a metal. The n-type semiconductor layer may be formed on the first drain contact electrode.

[0011] In some embodiments, the unidirectional switch may include a p-type semiconductor layer and an n-type semiconductor layer. The p-type semiconductor layer may be formed on a first drain. The p-type semiconductor layer may be electrically connected to the first drain. The n-type semiconductor layer may be formed on the p-type semiconductor layer and in contact with the p-type semiconductor layer.

[0012] In some embodiments, the read transistor may include a second gate, a second gate insulating layer, a second channel layer, a second source, and a second drain. The second gate may be stacked on top of a unidirectional switch. The second gate may be electrically connected to the unidirectional switch. The second gate insulating layer may be formed on the second gate. The second channel layer may be formed on the second gate insulating layer. The second source may be located on one side of the second channel layer. The second source may be electrically connected to a read word line. The second drain may be located on the other side of the second channel layer. The second drain may be electrically connected to a read bit line.

[0013] According to embodiments of this disclosure, a semiconductor memory device is provided, comprising a write transistor, a forward diode, and a read transistor. The write transistor may include a first source connected to a write bit line, a vertical channel layer formed on the first source, a first drain formed on the vertical channel layer, a first gate insulating layer configured to surround the outer peripheral surfaces of the first source, the vertical channel layer, and the first drain, and a first gate configured to surround the outer peripheral surface of the first gate insulating layer. The forward diode may be stacked on top of the first drain of the write transistor. The read transistor may include a second gate stacked on top of the forward diode, a second gate insulating layer formed on the second gate, a horizontal channel layer positioned on the second gate insulating layer, a second source positioned on one side of the horizontal channel layer, and a second drain positioned on the other side of the horizontal channel layer.

[0014] According to some embodiments, a one-way switch can be formed between the write transistor and the read transistor. The one-way switch prevents data stored in the read transistor from flowing into the write bit line connected to the write transistor, which is in an unselected mode. Therefore, the data retention rate of capacitor-less memory cells can be improved. Attached Figure Description

[0015] The above and other aspects, features, and advantages of embodiments of the present disclosure will be more readily understood from the following detailed description taken in conjunction with the accompanying drawings, wherein: Figure 1 This is a circuit diagram illustrating a capacitor-free memory cell of a semiconductor memory device according to an embodiment of the present disclosure; Figure 2 This is a circuit diagram showing a semiconductor memory device including capacitor-less memory cells; Figure 3 This is a circuit diagram illustrating a semiconductor memory device including a capacitor-less memory cell according to an embodiment of the present disclosure; Figure 4A and Figure 4B This is a plan view illustrating a two-dimensional storage cell according to an embodiment of the present disclosure; Figure 5A and Figure 5B It is along Figure 4A A cross-sectional view taken by line A-A'; and Figure 6A and Figure 6B This is a cross-sectional view showing a three-dimensional capacitor-free memory cell according to an embodiment of the present disclosure. Detailed Implementation

[0016] The advantages and features of the embodiments of this disclosure, as well as the methods for achieving these advantages and features, will become apparent when the embodiments are described in detail with reference to the accompanying drawings. However, these embodiments are not limited to those disclosed herein, but may be implemented in many variations or different forms, and are provided merely to complete this disclosure and to give a full description of the scope of this disclosure to those skilled in the art. For clarity, the dimensions and relative sizes of layers and regions in the drawings may be exaggerated. Throughout the specification, the same reference numerals denote the same parts.

[0017] Figure 1 This is a circuit diagram illustrating a capacitor-free memory cell of a semiconductor memory device according to an embodiment of the present disclosure.

[0018] refer to Figure 1The semiconductor memory device 10 may include a write word line WWL, a read word line RWL, a write bit line WBL, a read bit line RBL, and a memory cell MC electrically connected therebetween.

[0019] The memory cell MC may include a write transistor WT, a read transistor RT, and a one-way switch USW.

[0020] In some embodiments, the write word line WWL and the read word line RWL may extend parallel to a first direction "X". The write bit line WBL and the read bit line RBL may extend parallel to a second direction "Y" perpendicular to the first direction "X".

[0021] The write transistor WT can be connected between the write word line WWL and the write bit line WBL. When the write word line WWL is enabled, the write transistor WT can output the voltage of the write bit line WBL as the write data. For example, the gate of the write transistor WT can be connected to the write word line WWL. The source of the write transistor WT can be connected to the write bit line WBL. The drain of the write transistor WT can output the write data. The write data flows from the write bit line WBL through the write transistor WT and is transmitted to the read transistor RT via the drain of the write transistor.

[0022] The read transistor RT can be connected between the read word line RWL and the read bit line RBL. In response to write data output from the write transistor WT, the read transistor RT can transfer the voltage of the read word line RWL to the read bit line RBL. For example, the gate of the read transistor RT can be connected to a one-way switch USW. The source of the read transistor RT can be connected to the read word line RWL. The drain of the read transistor RT can be connected to the read bit line RBL.

[0023] A one-way switch USW can be connected between the write transistor WT and the read transistor RT. The one-way switch USW can be turned on when the output voltage of the write transistor WT is greater than a threshold voltage (i.e., the input voltage of the read transistor RT). For example, when the memory cell MC is in a deselected state, current is prevented from flowing from the gate of the read transistor RT to the source of the write transistor WT, even if a write enable voltage is applied to the gate of the write transistor WT. The one-way switch USW can be a forward diode and can be connected between the drain of the write transistor WT and the gate of the read transistor RT. In some embodiments, the forward diode can be at least one of a rectifier diode, a Schottky barrier diode, and a PN diode.

[0024] When the write enable voltage is applied to the gate of the write transistor WT via the write word line WWL and the write voltage is applied to the source of the write transistor WT via the write bit line WBL, the write transistor WT can be turned on. Therefore, the drain of the write transistor WT can have a write voltage level.

[0025] The unidirectional switch USW can be turned on when the drain voltage level of the write transistor WT is higher than the gate voltage level of the read transistor RT by a threshold voltage. The unidirectional switch USW can be activated when the drain voltage of the write transistor WT is higher than the gate voltage of the read transistor RT by a threshold voltage. Therefore, the drain voltage of the write transistor WT can be transferred to the gate of the read transistor RT, thereby charging the gate insulating layer (not shown) of the read transistor RT. For example, the gate insulating layer of the read transistor RT can be used as a charge storage layer for the memory cell. This means that the gate insulating layer can retain charge that can represent data stored in the memory cell.

[0026] On the other hand, when the gate insulating layer of the read transistor RT is charged and the read voltage is transmitted to the source of the read transistor RT via the read word line RWL, the read voltage can then be transmitted to the read bit line RBL based on the amount of charge in the gate insulating layer.

[0027] A sense amplifier S / A can be connected to each read bit line RBL. The sense amplifier S / A can sense the voltage of the read bit line RBL based on the data stored in the memory cell MC.

[0028] Figure 2 This is a circuit diagram showing a semiconductor memory device including a typical capacitor-less memory cell. Figure 3 This is a circuit diagram illustrating a semiconductor memory device including a capacitor-less memory cell according to an embodiment of the present disclosure.

[0029] like Figure 2 As shown, the first memory cells MC1 to the fourth memory cells MC4, arranged in a matrix, can be connected between the first write word line WWL1 and the second write word line WWL2, the first write bit line WBL1 and the second write bit line WBL2, the first read word line RWL1 and the second read word line RWL2, and the first read bit line RBL1 and the second read bit line RBL2. Each of the first memory cells MC1 to the fourth memory cells MC4 may include a write transistor WT and a read transistor RT, without a unidirectional switch.

[0030] For example, a data write operation can be performed on the first memory cell MC1 when a write enable voltage can be applied to the first write word line WWL1 and a write voltage can be applied to the first write bit line WBL1. For reference, in Figure 2In this configuration, the first write word line WWL1, which can be enabled by a write voltage, can be marked as selected, while the second write word line WWL2, which can be deselected, can be marked as unselected. Similarly, the first write bit line WBL1, which can be enabled by a write voltage, can be marked as selected, while the second write bit line WBL2, which can be deselected, can be marked as unselected.

[0031] For example, before a write operation is performed in the first storage unit MC1, "high" data can be pre-stored in the second storage unit MC2.

[0032] The write transistor WT2 of the second memory cell MC2 can be turned on through the selected first write word line WWL1, even if it is an unselected memory cell. As a result, the charge stored in the read transistor RT2 can flow into the unselected second write bit line WBL2, causing data loss in the second memory cell MC2.

[0033] However, as Figure 3 As shown, one-way switches USW1 to USW4, each with a forward diode, are connected between the write transistors WT1 to WT4 of the first memory cells MC1 to the fourth memory cells MC4 and the read transistors RT1 to RT4. Even if "high" data is stored in the unselected second memory cell MC2 connected to the selected first write word line WWL1, the one-way switch USW2 can prevent the charge stored in the read transistor RT2 from flowing back to the second write bit line WBL2, thus preserving the data.

[0034] Figure 4A and Figure 4B This is a plan view illustrating a two-dimensional storage cell according to an embodiment of the present disclosure, and Figure 5A and Figure 5B It is along Figure 4A A cross-sectional view taken from line A-A'.

[0035] refer to Figure 4A An isolation layer 110 may be formed in a semiconductor substrate (not shown) to define a first active region ACT1 and a second active region ACT2. The semiconductor substrate may include, for example, silicon, germanium, gallium arsenide, molybdenum selenide (MoSe2), hafnium selenide (HfSe2), indium selenide (InSe), gallium selenide (GaSe), black phosphorus, indium gallium zinc oxide (IGZO), or combinations thereof. The substrate 101 may be doped with n-type or p-type dopants.

[0036] In some embodiments, the first active region ACT1 may be a region in which a write transistor can be integrated. The second active region ACT2 may be a region in which a read transistor can be formed. The first active region ACT1 and the second active region ACT2 may have the same size. Alternatively, the first active region ACT1 and the second active region ACT2 may have different sizes. The first active region ACT1 and the second active region ACT2 may be spaced apart by a set gap g1. The first active region ACT1 and the second active region ACT2 may be disposed two-dimensionally on the semiconductor substrate 101. Furthermore, the first active region ACT1 and the second active region ACT2 may be along... Figure 4A and Figure 4B The channels of the write transistor and the read transistor extend horizontally in the X-axis direction, meaning that the channels of the write transistor and the read transistor can extend horizontally in the X-axis direction.

[0037] The first gate 120a can be disposed on the first active region ACT1. The second gate 130a can be disposed on the second active region ACT2. For example, the first gate 120a and the second gate 130a can be disposed along... Figure 4A and Figure 4B It extends along the Y-axis. The first gate 120a and the second gate 130a can be electrically isolated from each other.

[0038] In some embodiments, the first source 120b may be formed in the first active region ACT1, located on one side of the first gate 120a. The first drain 120c may be formed in the first active region ACT1, located on the other side of the first gate 120a. The first source 120b and the first drain 120c may include, for example, n-type conductive impurities. Therefore, the write transistor 120 may be integrated in the first active region ACT1.

[0039] The second source 130b can be disposed in the second active region ACT2, located on one side of the second gate 130a. The second drain 130c can be disposed in the second active region ACT2, located on the other side of the second gate 130a. The second source 130b and the second drain 130c may also include n-type conductive impurities. Therefore, the write transistor 130 can be integrated in the second active region ACT2.

[0040] In some embodiments, the first gate 120a may be in contact with the write word line WWL. The first source 120b may be in contact with the write bit line WBL.

[0041] The second source 130b can contact the read word line RWL. The second drain 130c can contact the read bit line RBL. Figure 4A and Figure 4B In the attached diagram, the CT symbol can indicate the contact area.

[0042] Furthermore, despite Figure 4A As not shown, a second source electrode, a second drain electrode, a first source electrode, and a first drain electrode, comprising metals, can be formed on the first source electrode 120b, the first drain electrode 120c, the second source electrode 130b, and the second drain electrode 130c, respectively. For example, the second source electrode, the second drain electrode, the first source electrode, and the first drain electrode can be used as an ohmic contact layer.

[0043] Furthermore, the one-way switch 140 can have a wiring structure, electrically connected between the first drain 120c and the second gate 130a. The one-way switch 140 can be positioned in a set gap G1.

[0044] Furthermore, such as Figure 4B As shown, the first source 120b electrically connected to the write bit line WBL can be formed in the first active region ACT1, located on the other side of the first gate 120a. The first drain 120c electrically connected to the second gate 130a can be formed in the first active region ACT1, located on one side of the first gate 120a. Similarly, the second source 130b electrically connected to the read word line RWL can be formed in the second active region ACT2, located on the other side of the second gate 130a. The second drain 130c electrically connected to the read bit line RBL can be formed in the second active region ACT2, located on one side of the second gate 130a.

[0045] However, it should be noted that these embodiments are not limited to the described layout structure, and in some embodiments, the layout structure of the write transistor and read transistor can be changed without departing from the scope of this disclosure.

[0046] In some embodiments, such as Figure 5A As shown, the one-way switch 140a may include an n-type semiconductor layer 141. The n-type semiconductor layer 141 may be a polycrystalline silicon layer including n-type conductive impurities. The n-type semiconductor layer 141 may be connected between a second gate 130a including metal and a first drain electrode 120c-1 to form a wiring structure in the form of a Schottky barrier diode. Therefore, when the memory cell is not selected, the one-way switch 140a can prevent data stored in the read transistor 130 from flowing into the write bit line WBL.

[0047] In another embodiment, such as Figure 5BAs shown, the unidirectional switch 140b can be a wiring structure comprising an n-type semiconductor layer 141 and a p-type semiconductor layer 142 stacked on top of each other. For example, the n-type semiconductor layer 141 can contact the second gate 130a, while the p-type semiconductor layer 142 can form a pn junction with the n-type semiconductor layer 141 and can contact the first drain contact electrode 120c-1 on the surface of the first drain 120c. Therefore, the unidirectional switch 140b can be operated as a PN diode, thereby preventing the loss of data stored in the read transistor.

[0048] Each of the read transistor 130 and write transistor 120 according to various embodiments may have a horizontal channel in a two-dimensional shape. A one-way switch 140 may be configured to connect a wire between the second gate 130a of the read transistor 130 and the first drain contact electrode 120c-1 of the write transistor 120.

[0049] Figure 6A and Figure 6B This is a cross-sectional view showing a three-dimensional capacitor-free memory cell according to an embodiment of the present disclosure.

[0050] refer to Figure 6A The capacitorless storage cell 20 may include a write transistor 210 with a vertical channel, a unidirectional switch 250, and a read transistor 260 with a flat channel.

[0051] The write transistor 210 may include a first channel post 220, a first gate insulating layer 225, a first gate 230, a first source 235, and a first drain 240.

[0052] The first channel pillar 220 can face... Figure 6A Extending in the z-direction. The first channel pillar 220 may include a semiconductor material, such as a semiconductor, a conductive metal oxide, a transition metal chalcogenide, or a combination of two or more thereof. In some embodiments, the semiconductor may include doped silicon. In some embodiments, the conductive metal oxide may include indium oxide (In2O3), doped indium oxide (In2O3), indium gallium zinc oxide (InGaZnO4), zinc oxide (ZnO), indium gallium oxide (InGaO3), etc. The dopant may include titanium (Ti), tungsten (W), silicon (Si), or any combination of two or more thereof. For example, the first channel pillar 220 may be a region in which a channel for forming a write transistor can be formed, and may include a first conductivity type (e.g., p-type) impurity.

[0053] The first gate insulating layer 225 can be formed to surround the sidewall of the first channel post 220. For example, the first gate insulating layer 225 can be formed to surround the entire outer wall of the first channel post 220 and can be in contact with the outer wall of the first channel post 220. For example, the first gate insulating layer 225 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, or a combination of two or more thereof.

[0054] The first gate 230 may be formed as an outer wall surrounding the first gate insulating layer 225; that is, the first gate 230 may have a ring gate structure and may be electrically connected to a write word line (not shown) extending in the x-axis direction. The first gate 230 may contact the outer wall of the first gate insulating layer 225. The first gate 230 may include a conductive layer, for example, a polysilicon layer or a metal layer including conductive impurities. The first gate 230 and the write word line may include, for example, the same conductive material, but the embodiments are not limited thereto. For example, the first gate 230 and the write word line may include doped semiconductors, metals, conductive metal nitrides, conductive metal carbides, conductive metal silicides, conductive metal oxides, or combinations of two or more of these.

[0055] The first source 235 may be a conductive impurity region located in the lower region of the first channel post 220. The first drain 240 may be a conductive impurity region located in the upper region of the first channel post 220. The first source 235 and the first drain 240 may include a second conductive impurity opposite to the first conductive impurity, for example, a high concentration of n-type impurities. In some embodiments, the first source 235 and the first drain 240 may be formed by an impurity ion implantation process.

[0056] The first source electrode 237 may be formed on the surface of the first source electrode 235. The first drain electrode 242 may be formed on the surface of the first drain electrode 240. For example, the first source electrode 237 and the first drain electrode 242 may each be an ohmic contact layer to reduce contact resistance. For example, the ohmic contact layer may include a metal silicide material.

[0057] The write bit line 245 can be formed below the write transistor 210 to contact the first source electrode 237. For example, as Figure 6A As shown, the write bit line 245 can be disposed below and in contact with the first source electrode 237. For example, the write bit line 245 may comprise metal. The write bit line 245 may extend along the Y direction. The write bit line 245 may be formed before the write transistor 210 is formed, or in some cases, after the write transistor 210 is formed.

[0058] A one-way switch 250 can be stacked on top of a write transistor 210. The one-way switch 250 may include an n-type semiconductor material layer 255 in contact with the first drain electrode 242, such as... Figure 6A As shown. The n-type semiconductor material layer 255 can operate as a cathode, while the first drain electrode 242 can operate as an anode to form a forward Schottky barrier diode. The forward Schottky barrier diode can operate as a unidirectional switch 250.

[0059] Furthermore, the unidirectional switch 250 may include a stacked structure of a p-type semiconductor material layer 252 and an n-type semiconductor material layer 255, such as Figure 6B As shown. The p-type semiconductor material layer 252, serving as the anode, can be electrically contacted with the first drain electrode 242. The n-type semiconductor material layer 255, serving as the cathode, can be electrically connected to the readout transistor 260, particularly to the second gate 265 of the readout transistor, thereby configuring the unidirectional switch 250 as a forward PN diode.

[0060] The read transistor 260 can be stacked on top of the unidirectional switch 250. For example, the read transistor 260 may include a second gate 265, a second gate insulating layer 270 above the second gate 265, a horizontal channel layer 275 above the second gate insulating layer 270, a second source 280, and a second drain 285.

[0061] The second gate 265 may be electrically connected to the upper surface of the unidirectional switch 250. The second gate 265 may include a conductive material. For example, the conductive material may include at least one of conductive metal nitrides, conductive metal carbides, conductive metal silicides, and conductive metal oxides. The conductive material may include, for example, n-type doped silicon, platinum, gold, palladium, molybdenum, nickel, tungsten, titanium, copper, aluminum, ruthenium, iridium, iridium oxide, tungsten nitride, titanium nitride, tantalum nitride, tungsten carbide, titanium carbide, tungsten silicide, titanium silicide, tantalum silicide, ruthenium oxide, or combinations of two or more of these.

[0062] A horizontal channel layer 275 may be disposed above the second gate 265. For example, the horizontal channel layer 275 may be made of a semiconductor material. In some embodiments, the horizontal channel layer 275 may include a semiconductor, a conductive metal oxide, a transition metal chalcogenide, or a combination of two or more thereof. In some embodiments, the semiconductor may include doped silicon. In another embodiment, the conductive metal oxide may include indium oxide (In2O3), doped indium oxide (In2O3), indium gallium zinc oxide (InGaZnO4), zinc oxide (ZnO), indium gallium oxide (InGaO3), etc. The dopant may include titanium (Ti), tungsten (W), silicon (Si), or any combination of two or more thereof. For example, the semiconductor material layer may include a first conductive impurity.

[0063] The second gate insulating layer 270 may be located between the second gate 265 and the horizontal channel layer 275. The second gate insulating layer 270 may be used as a storage node that can store the charge transferred from the write transistor 210. For example, the second gate insulating layer 270 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, or a combination of two or more thereof.

[0064] The second source 280 may be located on one side of the horizontal channel layer 275. The second drain 285 may be located on the other side of the horizontal channel layer 275. In some embodiments, a second conductivity type impurity, such as a high-concentration n-type impurity, may be implanted into the semiconductor material layer for the horizontal channel layer 275 exposed by the second gate insulating layer 270 to form the second source 280 and the second drain 285.

[0065] The read word line 290 can be connected to the sidewall of the second source 280. The read bit line 295 can be connected to the sidewall of the second drain 285.

[0066] exist Figure 6B In the accompanying drawings, reference numeral 300 denotes a peripheral circuit layer. For example, the peripheral circuit layer 300 may be located below the write bit line 245, but embodiments are not limited to this. Furthermore, the peripheral circuit layer 300 can generate various control signals to be provided to the memory cells, as well as various input and output voltages. The peripheral circuit layer 300 may be integrated on a separate die, and then that die is bonded to a die on which the memory cells are integrated.

[0067] Furthermore, while these embodiments illustrate that read transistors are stacked on top of write transistors, vertical channel write transistors can be stacked on top of horizontal channel read transistors without limitation.

[0068] As described in the embodiments, a one-way switch can be formed between the write transistor and the read transistor. When the write transistor is in an unselected state, the one-way switch can prevent data stored in the read transistor from flowing to the write bit line connected to the write transistor. Therefore, the data retention rate of the capacitor-less memory cell can be improved.

[0069] Furthermore, the unidirectional switch can be configured to include an n-type semiconductor layer and a metal layer, or an n-type semiconductor layer and a p-type semiconductor layer, making it possible to prevent data loss of the memory cell through a simple structure and manufacturing method.

[0070] Although the present invention has been described in detail with reference to specific embodiments, the present invention is not limited to the above embodiments, and those skilled in the art can implement the present invention through many modifications without departing from the scope and technical concept of this disclosure. Furthermore, these embodiments can be combined to form additional embodiments.

Claims

1. A semiconductor memory device, comprising: A write transistor that outputs a write bit line signal as data in response to a write word line signal; A read transistor that stores the data and outputs the stored data to the read bit line in response to a signal from the read word line; as well as A one-way switch that transmits data in one direction from the write transistor to the read transistor.

2. The semiconductor memory device as claimed in claim 1, wherein, The unidirectional switch includes a diode, and the diode includes an anode connected to the write transistor and a cathode connected to the read transistor.

3. The semiconductor memory device as claimed in claim 2, wherein, The unidirectional switch includes a Schottky barrier diode or a PN diode.

4. The semiconductor memory device according to claim 1, in, The unidirectional switch includes a diode having an anode and a cathode. The write transistor includes a first gate, a first source, and a first drain. The first gate is connected to the write word line, the first source is connected to the write bit line, and the first drain is connected to the anode. The read transistor includes a second gate, a second source, and a second drain. The second gate is connected to the cathode, the second source is connected to the read word line, and the second drain is connected to the read bit line.

5. The semiconductor memory device according to claim 1, in, Each of the write transistor and the read transistor is arranged in two dimensions and includes a horizontal channel. The unidirectional switch includes a wiring structure connecting the drain of the write transistor and the gate of the read transistor, and The wiring structure includes either a Schottky barrier diode structure or a pn junction diode structure. The Schottky barrier diode structure includes a drain electrode that contacts the drain of the write transistor and an n-type semiconductor layer that contacts the drain electrode. The pn junction diode structure includes a p-type semiconductor layer that contacts the drain of the write transistor and an n-type semiconductor layer that contacts the p-type semiconductor layer and the gate of the read transistor.

6. The semiconductor memory device according to claim 1, in, The write transistor and the read transistor are stacked in three dimensions, and Each of the write transistors has a vertical channel, and each of the read transistors has a horizontal channel.

7. The semiconductor memory device according to claim 1, in, The write word line and the read word line extend parallel to each other along a first direction, and The write bit line and the read bit line extend parallel to each other along a second direction perpendicular to the first direction.

8. A semiconductor memory device, comprising: Write to the bit line; A write transistor, which is electrically connected to the write bit line and is stacked on the write bit line; A one-way switch, which is stacked on top of the write transistor; as well as A read transistor is stacked on top of the unidirectional switch.

9. The semiconductor memory device of claim 8, wherein, The write transistor includes: A first channel post, comprising a semiconductor material and extending in a direction perpendicular to the surface of the write bit line; A first gate insulating layer is formed to surround the outer peripheral surface of the first channel post; A first gate is formed to surround the outer peripheral surface of the first gate insulating layer and is electrically connected to a write word line; A first source electrode is formed in the lower region of the first channel post and electrically coupled to the write bit line; and A first drain is formed in the upper region of the first channel post and is electrically connected to the unidirectional switch.

10. The semiconductor memory device of claim 9, wherein, A first source contact electrode, comprising metal, is formed between the first source and the write bit line.

11. The semiconductor memory device of claim 8, wherein, The one-way switch includes: A first drain contact electrode, the first drain contact electrode being formed on the first drain, and comprising a metal; and An n-type semiconductor layer is formed on the first drain contact electrode.

12. The semiconductor memory device of claim 9, wherein, The one-way switch includes: A p-type semiconductor layer, wherein the p-type semiconductor layer is formed on the first drain and electrically connected to the first drain; and An n-type semiconductor layer is formed on the p-type semiconductor layer and positioned adjacent to the p-type semiconductor layer.

13. The semiconductor memory device of claim 12, wherein, The unidirectional switch further includes a first drain contact electrode located between the first drain and the p-type semiconductor layer.

14. The semiconductor memory device of claim 8, wherein, The read transistor includes: A second gate, which is electrically connected to the one-way switch and is stacked on top of the one-way switch; A second gate insulating layer is formed on the second gate; A second channel layer is formed on the second gate insulating layer; The second source, located on one side of the second channel layer and electrically coupled to the read word line; and The second drain is located on the other side of the second channel layer and is electrically connected to the read bit line.

15. The semiconductor memory device of claim 8, further comprising: Peripheral circuitry, positioned below the write bit line, provides at least one control signal and at least one drive voltage to the write bit line, the write transistor, and the read transistor.

16. A semiconductor memory device, comprising: A write transistor, the write transistor including a first source connected to a write bit line, a vertical channel layer formed on the first source, a first drain formed on the vertical channel layer, a first gate insulating layer surrounding the outer peripheral surface of the first source, the vertical channel layer and the first drain, and a first gate surrounding the outer peripheral surface of the first gate insulating layer. A forward diode, which is stacked on top of the first drain of the write transistor; as well as The read transistor includes a second gate stacked on the forward diode, a second gate insulating layer formed on the second gate, a horizontal channel layer positioned on the second gate insulating layer, a second source positioned on one side of the horizontal channel layer, and a second drain positioned on the other side of the horizontal channel layer.

17. The semiconductor memory device of claim 16, further comprising: A read word line is connected to the second source electrode on one side; as well as Read the bit line, which is in contact with the second drain on the other side.

18. The semiconductor memory device of claim 16, wherein, The forward diode includes: A first drain contact electrode, the first drain contact electrode comprising a metal in contact with the first drain electrode; and An n-type semiconductor layer is formed on the first drain contact electrode.

19. The semiconductor memory device of claim 16, wherein, The forward diode includes: A p-type semiconductor layer, wherein the p-type semiconductor layer is formed on the first drain and electrically connected to the first drain; and An n-type semiconductor layer is formed on the p-type semiconductor layer and positioned adjacent to the p-type semiconductor layer.

20. A semiconductor memory device, comprising: Write to the bit line; A write transistor, the write transistor being electrically connected to the write bit line; A read transistor, which is electrically connected to the read word line and the read bit line; as well as A one-way switch, operably connected between the first drain of the write transistor and the gate of the read transistor. The write transistor includes a first channel, a first source electrically coupled to the write bit line, and a first drain.

Images