Dual-read port latch array bit cell

Abstract

This invention discloses apparatus and methods for providing efficient planar planning, power, and performance tradeoffs for memory access. Dual-read-port and single-write-port memory bit cells use two asymmetric read access circuits to transfer stored data on two read bit lines. The two read bit lines are pre-charged to different voltage reference levels. The layout of the memory bit cell places the two read bit lines on edges opposite to the single write bit line. The layout uses dummy gates placed above both P-type and N-type diffusions between these edges. Despite using asymmetric read access circuitry, the layout has the same number of P-type transistors as the N-type transistors. The layout also has one more contact gate pitch than the number of P-type transistors.

Description

Background Technology

[0001] Description of related technologies

[0002] Generally, many semiconductor chips include at least one processing unit coupled to memory. The processing unit processes instructions by fetching instructions and data, decoding instructions, executing instructions, and storing results. The processing unit sends memory access requests to the memory for fetching instructions, fetching data, and storing computation results. In some designs, the processing unit and memory reside on the same die (such as a system-on-a-chip (SoC)), while in other designs, they reside on different dies within the same package (such as a system-in-package (SIP) multi-chip module). For this memory, static random-access memory (SRAM) is typically used. SRAM comprises an array of memory bit cells and surrounding circuitry for accessing the values ​​stored in that array.

[0003] A die or package may include other units or components besides the processing unit and memory. The size of each component is limited to accommodate all components within the same die or package. For some types of memory, such as SRAM, the size may exceed the effective placement limits. The size of the memory (such as height and / or width) may be large enough to interfere with the placement of other components. In some cases, other components may not even be able to be mounted within the same die or package. Therefore, the chip may become inoperable without extensive redesign.

[0004] In view of the above, there is a need for efficient planar planning, power and performance trade-offs for memory access. Attached Figure Description

[0005] Figure 1 It is a generalized diagram of a memory bit cell that includes asymmetric read access circuitry and dual read ports.

[0006] Figure 2 It is a generalized diagram of a specific implementation of a semiconductor layout of a memory bit cell including asymmetric read access circuitry and dual read ports.

[0007] Figure 3 It is a generalized diagram of a specific implementation of adjacent memory bit cells including asymmetric read access circuitry and dual read ports.

[0008] Figure 4 It is a generalized diagram of a specific implementation of a semiconductor layout including asymmetric read access circuitry and adjacent memory bit cells with dual read ports.

[0009] Figure 5This is a generalized diagram of a specific implementation of a precharge circuit for a memory bit cell that utilizes an asymmetric read access circuit and dual read ports.

[0010] Figure 6 It is a block diagram of a specific implementation of a memory bank using memory bit cells with asymmetric read access circuitry and dual read ports.

[0011] Figure 7 It is a generalized diagram of a specific implementation of a method for efficiently accessing data stored in memory bit cells that include asymmetric read access circuitry and dual read ports.

[0012] Figure 8 This is a generalized diagram of a specific implementation of a method for efficiently forming a semiconductor layout of memory bit cells including asymmetric read access circuitry and dual read ports.

[0013] While the invention may have various modifications and alternatives, specific embodiments are shown by way of example in the accompanying drawings and are described in detail herein. However, it should be understood that the drawings and the detailed description thereof are not intended to limit the invention to the specific forms disclosed, but rather, the invention covers all modifications, equivalents, and alternatives falling within the scope of the invention as defined by the appended claims. Detailed Implementation

[0014] In the following description, numerous specific details are set forth to provide a thorough understanding of the invention. However, those skilled in the art will recognize that the invention can be practiced without these specific details. In some instances, well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring the invention. Furthermore, it should be understood that, for the sake of simplicity and clarity, the elements shown in the figures are not necessarily drawn to scale. For example, the dimensions of some elements are enlarged relative to other elements.

[0015] Devices and methods for providing efficient planar planning, power, and performance tradeoffs for memory access are envisioned. A memory array (or array) utilizes multiple memory bit cells arranged in multiple rows and columns. At least a portion of these multiple memory bit cells utilize asymmetric read access circuitry and dual read ports. As used herein, "asymmetric circuitry" refers to circuitry that includes a number of P-type transistors different from the number of N-type transistors. The memory bit cell utilizes at least a first asymmetric read access circuitry and a second asymmetric read access circuitry to provide requested data on a corresponding read bit line. In some embodiments, the first asymmetric read access circuitry of the memory bit cell transmits the requested data on a first read bit line. This first read bit line is previously pre-charged to a ground potential reference level. The first asymmetric read access circuitry includes more P-type transistors than N-type transistors. In some embodiments, the first asymmetric read access circuitry includes only P-type transistors.

[0016] The second asymmetric read access circuit of the memory bit cell transmits the requested data on the second read bit line, which has been previously pre-charged to the power source reference level. This second asymmetric read access circuit includes more N-type transistors than P-type transistors. By not using a symmetric read access circuit that includes the same number of P-type transistors as the number of N-type transistors, the memory bit cell reduces the on-chip area required for its placement in a planar layout. Furthermore, each read bit line is connected to a diffusion region that shares the single transistor drain connection of each pair of bit cells along the edge of the bit cell (P-type or N-type transistor). Therefore, the capacitive load on the corresponding read bit line is reduced.

[0017] The semiconductor layout (or arrangement) of a memory bit cell including asymmetric read access circuitry uses drain regions on the outermost edge of the layout to place the two read bit lines. The placement of these drain regions allows for node sharing between adjacent memory bit cells. Furthermore, the layout uses a dummy gate, which is a structure comprising an insulating layer instead of an active region beneath a metal gate. This insulating layer provides electrical isolation between the source / drain regions on either side of the metal gate of the dummy gate structure. The placement of metal layers and other structures in the layout provides the number of contact gate pitches (CPPs) of the layout, which is one more than the number of P-type transistors in the layout. Further descriptions of both the circuitry and layout of adjacent memory bit cells are provided in the discussion below.

[0018] Turning Figure 1This diagram illustrates a generalized block diagram of a specific embodiment of a memory bit cell 100 including asymmetric read access circuitry and dual read ports. In the illustrated embodiment, memory bit cell 100 provides data storage for latching elements. For example, devices 102 through 112 use a back-to-back configuration of inverters and tri-state inverters to provide data storage. Inverters are implemented by devices 102 through 104. Tri-state inverters are implemented by devices 106 through 112. Devices 140, 142, 150, and 152 provide two read access circuits for memory bit cell 100, making memory bit cell 100 a dual read port bit cell. In various embodiments, the devices in memory bit cell 100 are transistors. In some embodiments, the transistors are planar metal-oxide-semiconductor (MOS) field-effect transistors (FETs). In other embodiments, the devices (or transistors) in memory bit cell 100 are non-planar transistors. Non-planar transistors represent a recent development in semiconductor fabrication for reducing short-channel effects. Tri-gate transistors, finned field-effect transistors (FETs), and gate-all-around (GAA) transistors are examples of non-planar transistors.

[0019] Memory bit cell 100 is a specific implementation of static RAM (SRAM). In other implementations, another type of RAM cell is used. This "memory bit cell" may also be referred to as a "memory bit cell" and an "SRAM bit cell". In various implementations, memory bit cell 100 is copied multiple times and arranged in an array of rows and columns of memory. This array includes external circuitry (not shown), such as one or more of a row decoder, column decoder, sense amplifier, and precharge circuitry, as well as sequential elements, such as latches or flip-flops for storing read access data and write access data.

[0020] As used herein, a Boolean logic high level is also referred to as a logic high level. Similarly, a Boolean logic low level is also referred to as a logic low level. In various specific implementations, a logic high level is equal to a power source reference level, and a logic low level is equal to a ground potential reference level. As used herein, a circuit node or line is "asserted" when it stores a voltage level that enables a transistor receiving that voltage level. For example, an N-type transistor is enabled when it receives a positive non-zero voltage level at its gate terminal that is at least a threshold voltage higher than the voltage level at its source terminal. As used herein, a circuit node or line is "negated" when it stores a voltage level that disables a transistor receiving that voltage level. An N-type transistor is disabled when it receives a voltage level at its gate terminal that is below a threshold voltage lower than the voltage level at its source terminal. Similarly, a P-type transistor is enabled when it receives a voltage level at its gate terminal that is at least a threshold voltage lower than the voltage level at its source terminal. A P-type transistor is negated when it receives a voltage level at its gate terminal that is at least a threshold voltage higher than the voltage level at its source terminal.

[0021] When the data storage node D 130 of memory bit cell 100 has a logic high level, N-type transistor 104 is enabled and P-type transistor 102 is disabled. The enabled N-type transistor 104 discharges node DX 132, which enables P-type transistor 110 and disables N-type transistor 108. When the data storage node D 130 of memory bit cell 100 has a logic low level, N-type transistor 104 is disabled and P-type transistor 102 is enabled. The enabled P-type transistor 102 charges node DX 132, which enables N-type transistor 108 and disables P-type transistor 110. As used herein, "N-type transistor" is also referred to as "N-type device", "N-type MOSFET", and "nfet". Similarly, "P-type transistor" is also referred to as "P-type device", "P-type MOSFET", and "pfet". Therefore, N-type transistor 108 is also referred to as nfet 108, and P-type transistor 110 is also referred to as pfet 110. Note that nfet 108 is... Figure 1 It is also marked as NFB0108. Figure 1 The markers used (such as "NFB0 108") help with identification. Figure 1 The transistors and circuit nodes in the circuit diagram, as well as those described later (such as at least) Figure 2 The equivalent transistors and nodes used in the semiconductor layout diagram.

[0022] When no write operation occurs, each of the write word line (WWL) 160 and the complementary write word line (WWLX) 162 is negated. Therefore, each of the N-type transistor 122 and P-type transistor 120 of the transmission gate is disabled, which disconnects word line WBL 164 from node D 130 of memory bit cell 100. Additionally, each of the N-type transistor 106 and P-type transistor 112 is enabled, allowing one of the N-type transistor 108 and P-type transistor 110 to drive a specific voltage level on node D 130 based on the voltage level of node DX 132 and close the data storage loop of memory bit cell 100. For example, when node DX 132 stores a logic high level, N-type transistor 108 is enabled and P-type transistor 110 is disabled. N-type transistor 106 is enabled due to a logic high level of WWLX 162 (which is negated). The enabled N-type transistors 106 and 108 provide a discharge path between data storage node D 130 and the ground potential reference level indicated by "VSS", maintaining a logic low level on data storage node D 130 and closing the data storage loop. Conversely, when node DX 132 stores a logic low level, N-type transistor 108 is disabled and P-type transistor 110 is enabled. P-type transistor 112 is enabled due to a logic low level of WWL 160 (which is negated). The enabled P-type transistors 110 and 112 provide a charging path between data storage node D 130 and the power source reference level indicated by "VDD", maintaining a logic high level on data storage node D 130 and closing the data storage loop.

[0023] When a write operation is occurring, a row decoder (not shown) receives address information and enables a single row word line among multiple row word lines. In a specific implementation utilizing memory, the row decoder (not shown) receives address information and enables a specific word line of the target memory containing multiple row word lines. When memory bit cell 100 is in the row corresponding to an enabled row word line, each of WWL 160 and WWLX 162 of memory bit cell 100 is asserted by an external access circuit. Therefore, each of the P-type transistor 120 and N-type transistor 122 of the transmission gate is enabled. The enabled transistors 120 and 122 of the transmission gate electrically connect word line WBL 164 to node D 130 of memory bit cell 100. Therefore, WBL 164 drives the voltage level to be stored on node D 130. Write word line WWL 160 is also connected to other memory bit cells in the corresponding row of the array. Each of the N-type transistor 106 and the P-type transistor 112 is disabled, thus disconnecting the data storage nodes D130 and DX 132 from each other electrically. In this specific embodiment, memory bit cell 100 is a single-ended write bit cell with a single write port. Bit line WBL 164 is driven by external sequential elements and buffer circuitry that drive the write data on the column of the drive array. For write access operations, external circuitry drives a specific voltage level (such as a logic high or logic low level corresponding to the input data) onto bit line WBL 164, which is routed throughout the column. Note that for memory bit cells not targeted by write operations, the data storage remains unchanged.

[0024] For read access operations, in some specific implementations, the external precharge transistor is disabled, the read word line is asserted, the external sense amplifier is enabled, and the external read latch is enabled to capture data read from the target memory bit cell. Data stored by the latch elements (transistors 102 to 112) of memory bit cell 100 is selected from the read bit line RBL0 176 by the asymmetric read access circuit 180. Similarly, data stored by the latch elements (transistors 102 to 112) of memory bit cell 100 is selected from the read bit line RBL1 178 by the asymmetric read access circuit 182. As used herein, "asymmetric" means a circuit that includes a different number of P-type transistors than the number of N-type transistors.

[0025] In various embodiments, the asymmetric read access circuit 180 includes more P-type transistors than N-type transistors. In some embodiments, the asymmetric read access circuit 180 includes only P-type transistors. In such embodiments, the asymmetric read access circuit 180 does not include any N-type transistors. In an illustrated embodiment, the asymmetric read access circuit 180 includes two P-type transistors 140 and 142 connected in a series stacked topology and zero N-type transistors. Therefore, the asymmetric read access circuit 180 utilizes a different number (in this case, 2) of P-type transistors than the number of N-type transistors (0 in this case). The inputs of the asymmetric read access circuit 180 are node DX 132 and read word line RWL0 170. The output of the asymmetric read access circuit 180 is read bit line RBL0 176.

[0026] In various embodiments, the asymmetric read access circuit 182 includes more N-type transistors than P-type transistors. In some embodiments, the asymmetric read access circuit 182 includes only N-type transistors. In such embodiments, the asymmetric read access circuit 182 does not include any P-type transistors. In the illustrated embodiment, the asymmetric read access circuit 182 includes two N-type transistors 150 and 152 connected in a series stacked topology and zero P-type transistors. Therefore, the asymmetric read access circuit 182 utilizes a different number (in this case, 0) of P-type transistors than the number of N-type transistors (2 in this case). The inputs of the asymmetric read access circuit 182 are node DX 132 and read word line RWL1 172. The output of the asymmetric read access circuit 182 is read bit line RBL1 178.

[0027] Bit line RBL0 176 is precharged to a logic low level, such as the ground reference level "VSS". After the precharge cycle (or phase) has ended, P-type transistor 140 becomes enabled when word line RWL0 170 is asserted. Whether P-type transistor 142 is enabled is based on the binary value stored on node DX 132. When both P-type transistors 140 and 142 are enabled and node DX 132 stores a logic low level, this cascaded stack of P-type transistors 140 and 142 charges bit line RBL0 176 to a logic high level.

[0028] For other asymmetric read access circuitry of memory bit cell 100, bit line RBL1 178 is precharged to a logic high level, such as the power source reference level "VDD". After the precharge cycle (or phase) has ended, N-type transistor 150 becomes enabled when word line RWL1 172 is asserted. Whether N-type transistor 152 is enabled is based on the binary value stored on node DX 132. When both N-type transistors 150 and 152 are enabled and node DX 132 stores a logic high level, this series stack of N-type transistors 150 and 152 discharges bit line RBL1 178 to a logic low level. Therefore, P-type transistors 140 and 142 provide an asymmetric read access circuitry that relies solely on P-type transistors. This asymmetric read access circuitry does not use N-type transistors. N-type transistors 150 and 152 provide an asymmetric read access circuitry that relies solely on N-type transistors. This asymmetric read access circuitry does not use P-type transistors. This topology of memory bit cell 100 uses fewer transistors than a bit cell that uses a fully complementary tri-state inverter to implement dual read ports.

[0029] refer to Figure 2 This diagram shows a generalized block diagram of a specific embodiment of a semiconductor standard cell layout 200 including asymmetric read access circuitry and dual read ports for memory bit cells. The signals and circuits previously described are numbered identically. Note that the dashed boxes for the asymmetric read access circuits 180 and 182 are used to highlight the layout elements of these circuits and are not part of layout 200. Here, P-type transistors are located at the top of standard cell layout 200 (or layout 200), and N-type transistors are located at the bottom of standard cell layout 200. In the illustrated embodiment, standard cell layout 200 is used for dual read ports and single write ports for memory bit cells with single-ended read and single-ended write capabilities. In various embodiments, standard cell layout 200 is used for ( Figure 1 The circuit topology of the memory bit cell 100 is shown in the figure. The standard cell layout 200 uses a metal gate 206 in the vertical direction and diffusion regions 202 and 204 in the horizontal direction to define the active region. For example, the P-type diffusion region 202 defines the P-type active region in the layout 200, while the N-type diffusion region 204 defines the N-type active region in the layout 200. Note that the standard cell layout 200 can be rotated to have different orientations.

[0030] Similar to ( Figure 1The transistors in the memory bit cell 100 are, in some embodiments, planar metal-oxide-semiconductor (MOS) field-effect transistors (FETs). In other embodiments, the devices (or transistors) in layout 200 are non-planar transistors, such as tri-gate transistors, finned field-effect transistors (FETs), and gate-all-around (GAA) transistors. In some embodiments, the source / drain regions are implemented using trench silicide contacts. For ease of illustration, trench silicide contacts for the source / drain regions, signal paths in different metal layers, contacts, and vias are not shown in layout 200. As shown, P-type transistors 102, 110, 112, 120, 140, and 142 are arranged in a specific order. Similarly, N-type transistors 104, 106, 108, 122, 150, and 152 are arranged in a specific order. Although using asymmetric read access circuitry, standard cell layout 200 includes an equal number of P-type transistors to the number of N-type transistors and provides one more contact gate pitch than the number of P-type transistors (or N-type transistors). The number of contact gate (polysilicon) pitches (CPPs) is a measure used to characterize the density of a semiconductor layout. In the illustrated specific embodiment, layout 200 has six P-type transistors and six N-type transistors, despite the use of asymmetric read access circuitry. Layout 200 has a density equivalent to seven CPPs.

[0031] A dummy gate is typically used to provide electrical isolation between regions. Although in various implementations the dummy gate uses a metal gate, the gate region is formed over an insulating layer, not over an active silicon layer (such as an N-type or P-type diffusion layer). The insulating layer uses a silicon nitride layer, a silicon oxide layer (such as a silicon dioxide layer), or another type of dielectric layer. Therefore, if a voltage level is applied to the dummy gate and one or more regions (such as source / drain regions) on either side of the dummy gate, no electrical path is provided and no current flows between the source / drain regions. The fabrication steps of the dummy gate ensure that active transistors are not formed at locations in the layout of the dummy gate. In some implementations, a standard cell layout uses dummy gates at the edges of the cell layout. In these cases, the dummy gate is used to separate the cells from each other. For example, the edge of the cell has a final active metal gate, followed by an active diffusion layer, and then the dummy gate. In some designs, two adjacent cells share a dummy gate. However, as illustrated in the specific implementation, the standard cell layout 200 does not have dummy gates at the edges. In contrast, the standard cell layout 200 uses a virtual gate 270 in the middle of the layout.

[0032] Write bit lines are placed at the left edge of the standard cell layout 200. For example, the source / drain region WBL 210 of a P-type transistor 120 is placed at the left edge of layout 200. Similarly, the source / drain region WBL 212 of an N-type transistor 122 is placed at the left edge of layout 200. Two read bit lines are placed at the right edge of the standard cell layout 200. For example, the drain region RBL0240 of a P-type transistor 140 is placed at the top right edge of layout 200. Similarly, the drain region RBL1242 of an N-type transistor 150 is placed at the bottom right edge of layout 200. A dummy gate is not placed at the left or right edge of layout 200.

[0033] The source / drain regions 210 to 242 of layout 200 are electrically equivalent to those named in a similar manner and in memory bit cell 100 ( Figure 1 The signals used in ) Similarly, the metal gates 250 to 284 of layout 200 are electrically equivalent to those named in a similar manner and used in memory bit cell 100 ( Figure 1 The signals used in ) are physically disconnected at the source / drain regions and at the metal gate until additional layers and contacts are placed to electrically connect the nodes to each other. Therefore, due to the signals identifying the different physical elements of layout 200, Figure 2 They are named the same as each other and are consistent with those previously mentioned in ( Figure 1 Signals described in memory bit cell 100 with the same names are numbered differently in layout 200. For example, data storage nodes D 214 and D 216 are logically equivalent, but the P-type active region forming the source / drain region of node D 214 is not physically adjacent to the N-type active region forming the source / drain region of node D 216. Therefore, nodes D 214 and D 216 are not physically connected at the source / drain regions. However, after additional metal layers, vias, and contacts are placed through semiconductor manufacturing steps, nodes D 214 and D 216 are physically connected.

[0034] When additional metal layers, vias, and contacts (not shown for illustration) are placed during the semiconductor manufacturing process, nodes D 214 and D 216 become physically connected. This physical connection allows nodes D 214 and D 216 to become electrically connected when a voltage level is applied to layout 200. Similarly, write word lines WWL 252 and WWL 256 are logically equivalent, but the metal gate of WWL 252 is not physically adjacent to the metal gate of WWL 256. Therefore, write word lines WWL 252 and WWL 256 are not physically connected at their metal gates. However, after additional layers and contacts are placed during the semiconductor manufacturing process, write word lines WWL 252 and WWL 256 become physically connected. When a voltage level is applied to layout 200, this physical connection allows write word lines WWL 252 and WWL 256 to become electrically connected.

[0035] Turn now Figure 3 This diagram shows a generalized block diagram of a specific embodiment of adjacent memory bit cells 300, including asymmetric read access circuitry and dual read ports. The signals and circuitry previously described are numbered the same. In the illustrated embodiment, two memory bit cells 380 and 382 are placed adjacent to each other. In some embodiments, bit cells 380 and 382 are two adjacent bits in two different rows of the same column of an array. In one example, bit cell 380 is a bit of a data word stored in row 9 of a multi-row array [4], and bit cell 382 is a bit of another data word stored in row 10 of the same multi-row array [4]. Bit cells 380 and 382 share read bit lines RBL0 176 and RBL1 178. Similarly, the bit cells share write bit line WBL 164. Bit cell 380 uses ( Figure 1 The memory bit cell 382 uses the same transistors and topology as memory bit cell 100, but in a mirror image. As shown, bit cell 382 includes transistors 302 to 352 that use the same electrical topology as transistors 102 to 152 in bit cell 380. Similarly, bit cell 382 receives control signals 360 to 372 in a similar manner to bit cell 380 receiving control signals 160 to 172.

[0036] refer to Figure 4This diagram illustrates a generalized block diagram of a specific embodiment of a semiconductor layout 400 including asymmetric read access circuitry and adjacent memory bit cells with dual read ports. The signals and circuits previously described are numbered identically. Here, P-type transistors are located at the top of the standard cell layout 400, and N-type transistors are located at the bottom of the standard cell layout 400. In the illustrated embodiment, the standard cell layout 400 is used for two dual read ports, single write port memory bit cells with single-ended write capability. In some embodiments, these bit cells are two adjacent bits in two different rows of the same column of an array. In this embodiment, the standard cell layout 400 provides ( Figure 3 The layout of the memory bit cell 300. As shown, the standard cell layout 400 (or layout 400) includes transistors 102 to 152 and 302 to 352 that utilize source / drain regions 210 to 242 and 410 to 436 and receive control signals 250 to 284 and 450 to 484 received on a metal gate.

[0037] Similar to layout 200, due to the signals identifying different physical elements of semiconductor layout 400, Figure 4 They are named the same as each other and are consistent with those previously mentioned in ( Figure 1 (of) memory bit unit 100 and ( Figure 3 Signals described in memory bit cell 300 with the same names are numbered differently in semiconductor layout 400. For example, write word lines WWL 452 and WWL 456 are logically equivalent, but the metal gate of WWL 452 is not physically adjacent to the metal gate of WWL 456. Therefore, write word lines WWL 452 and WWL 456 are not physically connected at their metal gates. However, after additional layers and contacts are placed through semiconductor manufacturing steps, write word lines WWL 452 and WWL 456 are physically connected. When additional metal layers, vias, and contacts are placed through semiconductor manufacturing steps, write word lines WWL 452 and WWL 456 become physically connected. When a voltage level is applied to layout 400, this physical connection allows write word lines WWL 452 and WWL 456 to become electrically connected.

[0038] Similar to standard cell layout 200 (or layout 200), layout 400 does not use dummy gates at the outermost edge. Instead, layout 400 uses dummy gates 270 and 470 in individual memory bit cells. In various embodiments, dummy gate 270 is formed using similar manufacturing steps to form dummy gate 470. Similar to dummy gate 270, dummy gate 470 floats to the left in some embodiments, while in other embodiments, one or more of dummy gates 270 and 470 are connected to one of VDD and VSS. Although metal gates are used, dummy gates 270 and 470 are formed above the dielectric layer and therefore cannot conduct current. Thus, source / drain region DX 226 is electrically isolated from source / drain region VDD 230. Similarly, source / drain region DX 228 is electrically isolated from source / drain region VSS 232. Furthermore, source / drain region DX 426 is electrically isolated from source / drain region VDD430, and source / drain region DX 428 is electrically isolated from source / drain region VSS 432. Layout 400 provides shared drain regions RBL0 240 and RBL1 242 for reading bit lines. For example, two P-type transistors 140 and 340 share drain region RBL0 240. In a similar manner, two N-type transistors 150 and 350 share drain region RBL1 242. Further sharing may occur on both the left and right edges with other bit cells sharing drain regions WBL 210, WBL 212, WBL 410, and WBL 412 in other layouts.

[0039] Turn now Figure 5 A generalized block diagram of a specific implementation of the precharge circuit 500 is shown. The signal names previously described are numbered the same. For example, read bit lines RBL0 176 and RBL1 178 are from ( Figure 1 The read bit line of memory bit cell 100. As shown, circuit 500 includes a precharge circuit (or circuitry) for the two read bit lines. Circuit 520 precharges read bit line RBL1 178. Read bit line RBL1 178 is connected to an asymmetric read access circuit (not shown) using only N-type transistors. As previously shown, an example of this asymmetric read access circuit using only N-type transistors is ( Figure 1The asymmetric read access circuit 182. Circuit 520 includes a precharged P-type transistor 502, an inverter 510, and P-type transistors 512 and 514 in a series stacked topology. The precharged P-type transistor 502 receives a precharge control signal PCH1 504. Transistor 514 receives a control signal LE1 516. Circuit 540 precharges the read bit line RBL0 176. The read bit line RBL0 176 is connected to an asymmetric read access circuit (not shown) that uses only P-type transistors. As previously shown, an example of this asymmetric read access circuit using only P-type transistors is ( Figure 1 The asymmetric read access circuit 180 is described. Circuit 540 includes a precharge transistor 522, an inverter 530, and N-type transistors 532 and 534 in a series stacked topology. Precharge transistor 522 receives a precharge control signal PCH0 524, and transistor 522 receives a control signal PCH0 524. Further description of the operation of circuit 520 is provided in the discussion below. Similar steps are used to operate circuit 540.

[0040] During the precharge phase, control signal PCH1 504 is asserted, enabling P-type transistor 502, and the enabled transistor 502 forms a conductive path between the power source voltage reference level "VDD" and the read bit line RBL1 178. When RBL1 178 is precharged to the power source reference level, inverter 510 discharges the gate terminal of P-type transistor 512, enabling transistor 512. Transistor 512 acts as a holder transistor. In some embodiments, circuit 520 uses a single holder transistor, such as transistor 512, instead of transistor 514. In other embodiments, circuit 520 uses a series stack as shown, where two P-type transistors 512 and 514 provide one of several split holder (or dual holder) schemes. For example, two P-type transistors 512 and 514 provide one of several delayed-start holder circuits. During the evaluation phase, control signal PCH1 504 is negated, and transistor 502 is disabled. The voltage level on the read bit line RBL1 178 is based at least on the voltage level provided by the asymmetric read access circuitry of the selected bit cell.

[0041] Turn now Figure 6This diagram illustrates a generalized block diagram of a specific embodiment of memory bank 600. In various embodiments, the memory is organized into multiple memory banks, and a memory macroblock includes both a left memory bank and a right memory bank. In some embodiments, memory bank 600 is one of the left or right memory banks of a memory macroblock. Although "left" and "right" are used to describe memory banks, other notations such as "top memory bank" and "bottom memory bank" may be used. As shown, memory bank 600 includes arrays 610A to 610B, row decoders 620A to 620B, sense amplifiers 630A to 630B between arrays 610A to 610B, read and write timing control logic 640A to 640B, and read latches and write latches in block 650. Note that in some embodiments, multiple memory banks are accessed simultaneously in the same clock cycle or the same pipeline stage. Access includes either read access or write access. In this specific implementation, the memory address decoder selects the corresponding memory to be accessed.

[0042] In various embodiments, each of blocks 610A to 610B, 620A to 620B, 630A to 630B, 640A to 640B, and 650 in memory bank 600 is communicatively coupled to another block. For example, a direct connection is used, where routing occurs through another block. Alternatively, segmented signal transmission is performed in an intermediate block. In various embodiments, each of arrays 610A to 610B includes a plurality of memory bit cells 660 arranged in a tiled format. In some embodiments, one or more bit cells include asymmetric read access circuitry. For example, one or more of arrays 610A and 610B provide dual read port and single write port functionality. Thus, the memory bit cell includes a stack of P-type transistors, such as ( Figure 1 P-type transistors 140 and 142 control whether the stored binary value affects the pre-charged read bit line 166. Furthermore, the memory bit cell includes a stack of N-type transistors, such as (…). Figure 1 P-type transistors 150 and 152 control whether the stored binary value affects the precharged read bit line 168.

[0043] The row decoders and word line drivers in blocks 620A to 620B receive address information corresponding to the access request. For example, each of blocks 620A to 620B receives information provided by access request address 670. Each of blocks 620A to 620B selects a specific row or entry from among multiple rows in an associated row of arrays 620A to 620B. In some implementations, blocks 620A to 620B use the index portion of address 660 to select a given row or entry in an associated row of arrays 620A to 620B. Each row or entry stores one or more memory lines.

[0044] In the illustrated embodiment, rows or entries in arrays 620A to 620B are arranged in a vertical orientation. However, in other embodiments, a horizontal orientation is used to store memory lines. For write access requests, a write latch is located in block 650. Write data is driven into arrays 610A to 610B. Timing control logics 640A to 640B update the write latch in block 650 with the new data and set the write word line driver logic. The write data is written to the row of bit cells selected by one of the associated cells in blocks 620A to 620B. In some embodiments, a precharge circuit is included in block 650.

[0045] For read access requests, block 650 is used to precharge the read bit lines routed to arrays 610A to 610B. Timing circuitry in blocks 640A to 640B is used for precharging and setting the sense amplifiers in blocks 630A to 630B. Timing circuitry 640A to 640B sets the read word line driver logic. One of the row decoders 620A to 620B selects a row to read data, which will be provided on the read bit lines read by the sense amplifiers. A read latch captures the read data.

[0046] Now for reference Figure 7 This illustrates a specific embodiment of a method 700 for efficiently accessing data stored in memory bit cells. For the purposes of discussion, this specific embodiment (and) are shown in sequence. Figure 8 The steps in the diagram are shown. However, in other specific implementations, some steps occur in a different order than those shown, some steps are performed simultaneously, some steps are combined with other steps, and some steps are not present.

[0047] An array of memory bit cells arranged in multiple rows and columns stores data (box 702). In various embodiments, the value of the stored data is maintained by a data storage loop within the memory bit cell. Furthermore, the value of the stored data is updated via write operations. In some embodiments, the memory bit cell includes a transmission gate and a feedback inverter (and a feedback tri-state inverter) to implement the data storage loop and allow the stored value to be updated during a write operation. In some embodiments, the memory bit cell uses ( Figure 1 (of) memory bit unit 100 and ( Figure 3 The transmission gates and feedback inverters of memory bit cells 380 and 382.

[0048] External circuitry precharges the first read bit line to a ground reference level (box 704). Circuitry precharges the second read bit line to a power source reference level (box 706). If the array receives a first read operation targeting the first row of the array and with data to be read from the first read bit line (the "Yes" branch of condition box 708), a first asymmetric read access circuit, comprising more P-type transistors than N-type transistors, transfers the data stored in the bit cell in the first row to the first read bit line (box 710). In some implementations, the first asymmetric read access circuit comprises only P-type transistors. For example, a memory bit cell is similar to ( Figure 1 The memory bit cell 100 includes an asymmetric read access circuit 180. The asymmetric read access circuit 180 includes a stack of P-type transistors, such as P-type transistors 140 and 142, which control whether the stored binary value affects the precharged read bit line 176.

[0049] If the array does not receive a first read operation targeting the first row of the array and data to be read from the first read bit line (the "No" branch of condition block 708), the control flow of method 700 skips box 710 and moves to condition block 712. If the array receives a second read operation targeting the first row and data to be read from the second read bit line (the "Yes" branch of condition block 712), a second asymmetric read access circuit, comprising more N-type transistors than P-type transistors, transfers the data stored in the bit cells of the first row to the second read bit line (box 714). In some specific implementations, the second asymmetric read access circuit comprises only N-type transistors. For example, a memory bit cell is similar to ( Figure 1 The memory bit cell 100 includes an asymmetric read access circuit 182. The asymmetric read access circuit 182 includes a stack of N-type transistors, such as N-type transistors 150 and 152, which control whether the stored binary value affects the precharged read bit line 178.

[0050] If the array does not receive a second read operation targeting the first row of the array and the data to be read from the second read bit line (the "No" branch of condition box 712), the control flow of method 700 skips box 714 and moves to box 716. The bit cell holds the stored binary value (box 716). As previously described, the bit cell includes a latch element for storing the binary value until it is modified by a write access operation.

[0051] Now for reference Figure 8This illustrates a specific embodiment of a method 800 for efficiently forming a semiconductor layout of a memory bit cell. A first metal gate is placed over a P-type diffusion only at a first edge of the memory bit cell layout to receive a first read word line (box 802). Thus, the first metal gate is placed over a P-type active region for generating a P-type transistor. A second metal gate is placed over an N-type diffusion only at the first edge of the memory bit cell layout to receive a second read word line different from the first read word line (box 804). Thus, the second metal gate is placed over an N-type active region for generating an N-type transistor. A dummy gate is placed over both the P-type and N-type diffusions away from the edge within the cell layout (box 806).

[0052] The first read bit line is placed at the first edge as the drain region above the P-type diffusion only (box 808). A second read bit line, different from the first read bit line, is placed at the first edge as the drain region above the N-type diffusion only (box 810). The write bit line is placed at the second edge as the drain region above both the P-type and N-type diffusions (box 812).

[0053] The contact gate pitch of the layout of a single memory bit cell is provided to be one more than the number of P-type transistors (box 814). The first memory bit cell is positioned such that its first edge is adjacent to the first edge of the second memory bit cell, and the second memory bit cell is positioned in a mirror image of the first memory bit cell, thereby allowing the first memory bit cell and the second memory bit cell to share the first read bit line and the second read bit line (box 816).

[0054] It should be noted that one or more of the above-described embodiments include software. In such embodiments, program instructions implementing the method and / or mechanism are delivered or stored on a computer-readable medium. Many types of media configured to store program instructions are available and include hard disks, floppy disks, CD-ROMs, DVDs, flash memory, programmable ROMs (PROMs), random access memory (RAMs), and various other forms of volatile or non-volatile storage devices. Generally, computer-accessible storage media include any storage medium that can be accessed by a computer during use to provide instructions and / or data to the computer. For example, computer-accessible storage media include storage media such as magnetic or optical media, such as magnetic disks (fixed or removable), magnetic tape, CD-ROMs or DVD-ROMs, CD-Rs, CD-RWs, DVD-Rs, DVD-RWs, or Blu-ray discs. Storage media also include volatile or non-volatile storage media, such as RAM (e.g., Synchronous Dynamic RAM (SDRAM), Dual Data Rate (DDR, DDR2, DDR3, etc.) SDRAM, Low Power DDR (LPDDR2, etc.) SDRAM, Rambus DRAM (RDRAM), Static RAM (SRAM), etc.), ROM accessible via a peripheral device interface (such as a Universal Serial Bus (USB) interface), flash memory, and non-volatile memory (e.g., flash memory). Storage media include microelectromechanical systems (MEMS), and storage media accessible via communication media such as networks and / or wireless links.

[0055] Additionally, in various specific implementations, program instructions include behavioral-level or register-transfer-level (RTL) descriptions of hardware functionality in a high-level programming language (such as C) or design language (HDL) (such as Verilog, VHDL, or database formats such as GDSII streaming format (GDSII)). In some cases, the description is read by a synthesis tool that synthesizes the description to produce a netlist comprising a list of gates from a synthesis library. The netlist includes gate sets, which also represent the functionality of the hardware comprising the system. The netlist is then placed and routed to produce a dataset describing the geometry to be applied to a mask. The mask is then used in various semiconductor manufacturing steps to produce semiconductor circuits or circuits corresponding to the system. Alternatively, computer-accessible instructions on a storage medium are, as desired, netlists (with or without synthesis libraries) or datasets. Furthermore, the instructions are used by, for example... and Mentor The purpose of this type of supplier's hardware-based type simulator is to perform simulation.

[0056] Although the specific embodiments described above have been described in considerable detail, many variations and modifications will become apparent to those skilled in the art once the foregoing disclosure is fully understood. The following claims are intended to be interpreted as covering all such variations and modifications.

Claims

1. A circuit comprising: An array of memory bit cells for storing data, wherein a given memory bit cell in the array comprises: Data storage circuit; A first asymmetric read access circuit is configured to receive the complementary value of the data and transmit it to a first read bit line; and A second asymmetric read access circuit is configured to receive the complementary value of the data and transmit it to a second read bit line different from the first read bit line, wherein the second asymmetric read access circuit includes more N-type transistors or P-type transistors than the first asymmetric read access circuit; and In response to receiving an indication for a first read operation, the first asymmetric read access circuit is configured as follows: Access the complementary value of the data stored by the data storage circuit; and The data stored by the data storage circuit is transmitted to the first read bit line.

2. The circuit of claim 1, wherein the circuit further comprises a first precharge circuit configured to precharge the first read bit line to a ground reference level.

3. The circuit of claim 1, wherein the second asymmetric read access circuit comprises only N-type transistors.

4. The circuit of claim 3, wherein in response to receiving a second read operation targeting the same row of the array targeted by the first read operation simultaneously with the first read operation, the given memory bit cell is configured via the second asymmetric read access circuit to: Simultaneously with the first asymmetric read access circuit, the complementary value of the data stored by the data storage circuit is accessed; and The data stored by the data storage circuit is transmitted to the second read bit line using more N-type or P-type transistors than the first asymmetric read access circuit.

5. The circuit of claim 1, wherein the data storage circuit is coupled to the write bit line via a transmission gate comprising an N-type transistor and a P-type transistor.

6. The circuit of claim 1, wherein the first asymmetric read access circuit comprises only P-type transistors including the following: A first P-type transistor is configured to receive, at its gate terminal, the complementary value of the data stored by the data storage circuit; and A second P-type transistor is connected in series with the first P-type transistor, and the second P-type transistor is configured as follows: It receives a read word line at its gate terminal as an indication of the first read operation; as well as The first read bit line is received on its drain terminal.

7. The circuit of claim 5, wherein the gate of the N-type transistor of the transmission gate is coupled to receive a write word line, and the gate of the P-type transistor of the transmission gate is coupled to receive a signal having a complementary value to the write word line.

8. The circuit of claim 7, wherein the signal having the complementary value of the write word line is coupled to the gate of the N-type transistor.

9. A method comprising: Data is stored in an array of memory bit cells, wherein a given memory bit cell in the array comprises: Data is stored by data storage circuitry; The complementary value of the data is received by the first asymmetric read access circuit and transmitted to the first read bit line; and The complementary value of the data received by the second asymmetric read access circuit is transmitted to a second read bit line different from the first read bit line, wherein the second asymmetric read access circuit includes more N-type transistors or P-type transistors than the first asymmetric read access circuit; and The first asymmetric read access circuitry of the given memory bit cell in the array is executed in response to receiving an indication for a first read operation. Disable transmission gates that include both N-type and P-type transistors; Access the complementary value of the data stored by the data storage circuit of the given memory bit cell; and The data stored by the data storage circuit is transmitted to the first read bit line.

10. The method of claim 9, further comprising precharging the first read bit line to a ground reference level by a first precharge circuit.

11. The method of claim 9, further comprising receiving the complementary value of the data stored by the data storage circuit by a second asymmetric read access circuit comprising only N-type transistors.

12. The method of claim 11, further comprising pre-charging the second read bit line to a power source reference level.

13. The method of claim 12, wherein in response to receiving a second read operation targeting the same row of the array targeted by the first read operation simultaneously with the first read operation, the method further comprises being performed by the second asymmetric read access circuitry: Access the complementary value of the data stored by the data storage circuit; and The data stored by the data storage circuit is transmitted to the second read bit line using more N-type or P-type transistors than the first asymmetric read access circuit.

14. The method of claim 9, further comprising: The complementary value of the data stored by the data storage circuit is received by the gate terminal of the first P-type transistor of the first asymmetric read access circuit, which includes only P-type transistors; A read word line, serving as an indication of the first read operation, is received at the gate terminal of a second P-type transistor connected in series with the first P-type transistor. as well as The first read bit line is received by the drain terminal of the second P-type transistor.

15. The method of claim 9, wherein disabling the transmission gate comprises receiving a write word line on the gate of the N-type transistor of the transmission gate and receiving a complementary value of the write word line on the gate of the P-type transistor of the transmission gate.

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