Storage unit, memory and method for manufacturing the same, and electronic device

Abstract

This disclosure relates to a memory cell, a memory, a method for fabricating the same, and an electronic device, relating to the field of storage technology, to improve the performance and reliability of the memory cell and the memory. The memory cell includes a write transistor and a read transistor. The write transistor includes a first gate, a first source-drain, and a second source-drain. The read transistor includes a second gate, a third source-drain, and a fourth source-drain. The first gate is electrically connected to the write word line, the first source-drain is electrically connected to the write bit line, and the second source-drain and the second gate are electrically connected. The read transistor further includes a third gate, insulated on one side of the connection between the second source-drain and the second gate. The third gate is electrically connected to the read word line, the fourth source-drain is electrically connected to the read bit line, and the third source-drain is electrically connected to the common source line.

Description

Technical Field

[0001] This disclosure relates to the field of storage technology, and in particular to a storage unit, a memory, a method for manufacturing the same, and an electronic device. Background Technology

[0002] With the development of communication and digital technologies, people are constantly pursuing products with lower power consumption, lighter weight, and better performance. Memory, which can easily achieve higher integration density and larger storage capacity, has gradually become one of the important research directions in the current storage field. For example, in the example of dynamic random access memory using 2T0C memory cells, problems such as read current multipathing and read current congestion are easily encountered during data reading, thus adversely affecting the performance of the dynamic random access memory. Summary of the Invention

[0003] Based on this, the present disclosure provides a storage unit, a memory, a method for manufacturing the same, and an electronic device, which helps to improve the performance and reliability of the storage unit and the memory.

[0004] According to some embodiments, this disclosure provides a memory cell, including: a write transistor and a read transistor; the write transistor includes a first gate, a first source-drain, and a second source-drain; the read transistor includes a second gate, a third source-drain, and a fourth source-drain; the first gate is electrically connected to a write word line, the first source-drain is electrically connected to a write bit line, and the second source-drain and the second gate are electrically connected. The read transistor further includes: a third gate, insulated on one side of the connection between the second source-drain and the second gate; wherein the third gate is electrically connected to the read word line, the fourth source-drain is electrically connected to the read bit line, and the third source-drain is electrically connected to a common source line.

[0005] According to some embodiments, read bit lines and write bit lines are arranged parallel to each other and extend along a first direction. Write transistors and read transistors are arranged side by side in a second direction and disposed within the interval between the read bit lines and write bit lines; the second direction intersects the first direction. A common source line surrounds the periphery of the read transistor and extends in a direction away from the read transistor. The center line of the common source line extends along the second direction.

[0006] According to some embodiments, the write transistor includes a first semiconductor layer; the read transistor includes a second semiconductor layer. A first gate and a write word line extend along a third direction; the third direction intersects both the first and second directions. The first semiconductor layer is disposed around the periphery of the first gate, and the center line of the first semiconductor layer extends along the third direction; the portion of the first semiconductor layer extending along the first direction and electrically connected to the write bit line is a first source / drain, and the portion of the first semiconductor layer contacting the second gate and located on the side of the first gate away from the first source / drain is a second source / drain. The second gate extends along a second direction and includes: a first portion electrically connected to the second source / drain, and a second portion located on the side of the first portion away from the second source / drain and electrically connected to the first portion. The second semiconductor layer is disposed around the periphery of the second portion and on the side of the second portion away from the first portion. The center line of the second semiconductor layer extends along the second direction. The portion of the second semiconductor layer disposed around the periphery of the second portion and connected to a common source line is a third source / drain; the portion of the second semiconductor layer located on the side of the second portion away from the first portion is a fourth source / drain.

[0007] According to some embodiments, the third gate extends along a third direction. The third gate is insulated on one side of the first portion in the first direction.

[0008] According to some embodiments, the write transistor further includes a first gate dielectric layer; the read transistor further includes a second gate dielectric layer and a third gate dielectric layer connected together. The first gate dielectric layer is located between the first gate and the first semiconductor layer. The second gate dielectric layer is located between the second portion and the second semiconductor layer. The third gate dielectric layer is disposed around the periphery of the third gate and is connected to both the second gate dielectric layer and the second gate.

[0009] According to some embodiments, the write word line is multiplexed as the read word line during the data read phase. The first gate is multiplexed as the third gate during the data read phase.

[0010] According to some embodiments, the dimension of the first part in the first direction is larger than the dimension of the second part in the first direction. The dimension of the first part in the second direction is smaller than the dimension of the second part in the second direction.

[0011] According to some embodiments, the write transistor further includes a first gate dielectric layer. The read transistor further includes a second gate dielectric layer and a third gate dielectric layer connected together. The first gate dielectric layer is located between the first gate and the first semiconductor layer. The second gate dielectric layer is located between the second portion and the second semiconductor layer. The third gate dielectric layer is located between the first portion and the second semiconductor layer.

[0012] According to some embodiments, the dimension of the first semiconductor layer in the first direction is larger than the maximum dimension of the second gate in the first direction.

[0013] According to some embodiments, this disclosure also provides a memory, including one or more storage cells as described in any of the foregoing embodiments.

[0014] According to some embodiments, this disclosure further provides a data read / write method applied to a memory as described in any of the foregoing embodiments; the connection between the second source / drain of the write transistor and the second gate of the read transistor forms a storage node of the memory cell. The data read / write method includes:

[0015] During the data writing phase, in response to a write command, the write bit line provides a data voltage to the write transistor; the write word line controls the write transistor to turn on, and the storage node discharges to a stable state in order to write the data corresponding to the data voltage.

[0016] During the data reading phase, in response to the read command, the read word line in the selected memory cell is set to a normal potential, and the read word line in the unselected memory cell is set to a low potential. This causes the third gate connected to the read word line with the low potential to attract more positive charge from the channel of the read transistor, and the read transistor in the unselected memory cell is electrically deactivated.

[0017] According to some embodiments, the write line is multiplexed as the read line during the data read phase; the first gate is multiplexed as the third gate during the data read phase.

[0018] During the data reading phase, in response to the read command, the read word line in the selected memory cell is set to a normal potential, and the read word line in the unselected memory cell is set to a low potential. This causes the first gate connected to the read word line with the low potential to attract more positive charge from the channel of the read transistor, and the read transistor in the unselected memory cell is electrically deactivated.

[0019] According to some embodiments, this disclosure also provides a method for fabricating a memory, comprising the following steps:

[0020] A first conductive material layer and an insulating material layer are sequentially deposited on a wafer to form a stacked structure;

[0021] The read and write lines are arranged in parallel intervals and extend along the first direction;

[0022] A read transistor and a write transistor are formed side-by-side in a second direction within the gap between the read bit line and the write bit line; the write transistor includes a first gate, a first source-drain, and a second source-drain; the read transistor includes a second gate, a third gate, a third source-drain, and a fourth source-drain; wherein the first source-drain is electrically connected to the write bit line, the second source-drain is electrically connected to the second gate, and the fourth source-drain is electrically connected to the read bit line; the third gate is insulated and disposed on one side of the connection between the second source-drain and the second gate; the first direction and the second direction intersect, and both the first direction and the second direction are parallel to the wafer surface;

[0023] Form a write line electrically connected to the first gate;

[0024] Forming a read line electrically connected to the third gate;

[0025] A common source line is formed that is electrically connected to the third source drain.

[0026] According to some embodiments, forming read bit lines and write bit lines that are arranged in parallel intervals and extend along a first direction, and forming read transistors and write transistors arranged side by side in a second direction within the interval between the read bit lines and write bit lines, includes the following steps:

[0027] A first conductive material layer is formed and patterned to form read bit lines and write bit lines that are arranged in parallel and spaced apart, and a virtual gate located between and connecting the read bit lines and write bit lines; wherein the read bit lines and write bit lines extend along a first direction, and the virtual gate extends along a second direction.

[0028] Dielectric material is filled on both sides of the virtual gate opposite each other in the first direction;

[0029] The virtual gate and dielectric material are etched in the first target region near the write bit line to form an etching hole;

[0030] Based on the etched hole, the virtual gate is selectively etched along the second direction by wet etching to remove the retained virtual gate and form a receiving trench; the receiving trench exposes the corresponding sidewall of the read bit line;

[0031] A semiconductor material layer, a gate dielectric material layer, and a second conductive material layer are sequentially deposited on the inner wall of the containment tank using an atomic layer deposition process.

[0032] Remove the semiconductor material layer, the gate dielectric material layer, and the second conductive material layer inside the etched hole, such that the remaining gate dielectric material layer constitutes the second gate dielectric layer and the remaining second conductive material layer constitutes the second gate; and remove the semiconductor material layer in the second target region near the etched hole, such that the remaining semiconductor material layer constitutes the second semiconductor layer and exposes the sidewall of the second gate dielectric layer.

[0033] Remove the semiconductor material layer in the second target area near the etched hole, so that the remaining semiconductor material layer constitutes the second semiconductor layer and exposes the sidewalls of the second gate dielectric layer;

[0034] A dielectric material is etched outside the sidewall of the second gate exposed on one side in the first direction to form a receiving hole; the receiving hole exposes the sidewall of the second gate dielectric layer and the second semiconductor layer away from the read bit line;

[0035] A third gate dielectric layer and a third gate are sequentially formed within the accommodating hole;

[0036] A first semiconductor layer, a first gate dielectric layer, and a first gate are sequentially formed on the wall of the etched hole to obtain a write transistor.

[0037] In this configuration, the portion of the second semiconductor layer surrounding the second gate and connected to the common source line constitutes the third source / drain. The portion of the second semiconductor layer located on the side of the second gate away from the first gate constitutes the fourth source / drain. The portion of the first semiconductor layer extending along the first direction and electrically connected to the write bit line constitutes the first source / drain. The portion of the first semiconductor layer extending along the first direction and located on the side of the first gate away from the first source / drain constitutes the second source / drain. The write word line is formed synchronously with the first gate. The read word line is formed synchronously with the third gate.

[0038] According to some embodiments, the write word line is multiplexed as the read word line during the data read phase, and the first gate is multiplexed as the third gate during the data read phase. Forming parallel-spaced read bit lines and write bit lines extending along a first direction, and forming read transistors and write transistors arranged side-by-side in a second direction within the interval between the read bit lines and write bit lines, includes the following steps:

[0039] A first conductive material layer is formed and patterned to form read bit lines and virtual write bit lines that are arranged in parallel and spaced apart, and a virtual gate located between and connecting the read bit lines and virtual write bit lines; wherein the read bit lines and virtual write bit lines extend along a first direction, and the virtual gate extends along a second direction.

[0040] Dielectric material is filled on both sides of the virtual gate opposite each other in the first direction;

[0041] The virtual gate and dielectric material are etched in the first target region near the virtual write bit line to form an etching hole;

[0042] Based on the etched holes, the virtual write bit lines and the remaining virtual gates are removed to form an accommodating space including the etched holes; the accommodating space exposes the corresponding sidewalls of the read bit lines;

[0043] A semiconductor material layer, a gate dielectric material layer, and a second conductive material layer are sequentially deposited within the accommodating space;

[0044] Remove the semiconductor material layer, gate dielectric material layer, and second conductive material layer in the first target region, as well as the semiconductor material layer, gate dielectric layer, and second conductive material layer in the third and fourth target regions adjacent to the first target region along the second direction, so that the remaining semiconductor material layer constitutes the second semiconductor layer, the remaining gate dielectric material layer constitutes the second gate dielectric layer, the second conductive material layer retained in the third target region near the read bit line is the second part of the second gate, and the second conductive material layer retained in the fourth target region away from the read bit line is the write bit line;

[0045] A third gate dielectric layer is formed on the sidewall of the second semiconductor layer and the second gate dielectric layer away from the read bit line;

[0046] The first part of the second gate is formed in the third target region on the sidewall of the second part and the third gate dielectric layer away from the read bit line;

[0047] A first semiconductor layer, a first gate dielectric layer, and a first gate are sequentially formed on the wall of the etched hole between the first part and the write bit line to obtain a write transistor.

[0048] The portion of the second semiconductor layer surrounding the second portion and connected to the common source line is the third source / drain. The portion of the second semiconductor layer located on the side of the second portion away from the first portion is the fourth source / drain. The portion of the first semiconductor layer extending along the first direction and electrically connected to the write bit line is the first source / drain. The portion of the first semiconductor layer extending along the first direction and located on the side of the first gate away from the first source / drain is the second source / drain. The write word line is formed synchronously with the first gate.

[0049] According to some embodiments, based on the etched holes, the virtual write bit lines and the retained virtual gates are removed to form an accommodating space, and the method further includes: performing a wet etching process along a second direction and a first direction on the virtual write bit lines and the retained virtual gates to form the accommodating space.

[0050] According to some embodiments, another aspect of this disclosure provides an electronic device, including: one or more memories as described in the foregoing embodiments.

[0051] The embodiments disclosed herein may have, or at least have, the following advantages:

[0052] In some embodiments of this disclosure, a third gate is added to the read transistor of the memory cell, and the third gate is insulated and disposed on one side of the connection between the second source / drain of the write transistor and the second gate of the read transistor (i.e., the memory node), and the third gate is electrically connected to the read word line. Thus, during a read operation, the read word line in the selected memory cell is at a normal potential, and the read word line in the unselected memory cell is at a low potential. The third gate connected to the low-potential read word line can attract more positive charge from the channel of the read transistor, ensuring that the read transistor of the unselected memory cell is electrically de-energized. This solves the multi-path problem caused by the read current bypassing multiple memory nodes when the same read word line controls multiple read transistors during a read operation. It also avoids the voltage drop problem caused to the target read bit line if leakage current flows out from different read bit lines under the control of the same read word line, and avoids interference between different memory cells, thereby improving the performance and reliability of the memory cell and the memory.

[0053] Furthermore, in some embodiments of this disclosure, the third source drain of the read transistor and the common source line are electrically connected, which facilitates connecting multiple adjacent memory cells into a single sheet via the common source line, thereby solving the problem of current congestion and optimizing the memory structure.

[0054] In other embodiments of this disclosure, the write word line is multiplexed as the read word line during the data reading phase, and the first gate of the write transistor is multiplexed as the third gate of the read transistor during the data reading phase, which helps to further simplify the structure and process of the memory cell and the memory. Attached Figure Description

[0055] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0056] Figure 1 This is a schematic diagram of the structure of a storage unit provided in some embodiments of this disclosure;

[0057] Figure 2 for Figure 1 The diagram shows a cross-sectional view of the structure at section M1.

[0058] Figure 3 This is a schematic diagram of the equivalent circuit of a memory cell provided in some embodiments of this disclosure;

[0059] Figure 4 This is a schematic diagram of the structure of another storage unit provided in some embodiments of this disclosure;

[0060] Figure 5 for Figure 4 The diagram shows a cross-sectional view of the structure at section M1.

[0061] Figure 6 This is a schematic flowchart of a method for manufacturing a memory provided in some embodiments;

[0062] Figure 7 This is a schematic diagram of a process for forming read transistors and write transistors in a method of manufacturing a memory provided in some embodiments;

[0063] Figure 8 This is a cross-sectional schematic diagram of a structure obtained in step S20 of a method for manufacturing a memory provided in some embodiments;

[0064] Figure 9 This is a cross-sectional schematic diagram of the structure obtained in step S31 of a method for manufacturing a memory provided in some embodiments;

[0065] Figure 10 This is a cross-sectional schematic diagram of the structure obtained in step S32 of a method for manufacturing a memory provided in some embodiments;

[0066] Figure 11 This is a cross-sectional schematic diagram of the structure obtained in step S33 of a method for manufacturing a memory provided in some embodiments;

[0067] Figure 12 This is a cross-sectional schematic diagram of the structure obtained in step S34 of a method for manufacturing a memory provided in some embodiments;

[0068] Figure 13 This is a cross-sectional schematic diagram of the structure obtained in step S35 of a method for manufacturing a memory provided in some embodiments;

[0069] Figure 14 This is a cross-sectional schematic diagram of the structure obtained in step S36 of a method for manufacturing a memory provided in some embodiments;

[0070] Figure 15 This is a cross-sectional schematic diagram of the structure obtained in step S37 of a method for manufacturing a memory provided in some embodiments;

[0071] Figure 16 This is a cross-sectional schematic diagram of a structure obtained in step S50 of a method for manufacturing a memory provided in some embodiments;

[0072] Figure 17 This is a cross-sectional schematic diagram of a structure obtained in step S60 of a method for manufacturing a memory provided in some embodiments;

[0073] Figure 18 This is a schematic diagram illustrating another process for forming read transistors and write transistors in a method of manufacturing a memory provided in some embodiments;

[0074] Figure 19 This is a cross-sectional schematic diagram of another structure obtained in step S20 of a method for manufacturing a memory provided in some embodiments;

[0075] Figure 20 This is a cross-sectional schematic diagram of the structure obtained in step S31' of a method for manufacturing a memory provided in some embodiments;

[0076] Figure 21 This is a schematic cross-sectional view of the structure obtained in step S32' of a method for manufacturing a memory provided in some embodiments;

[0077] Figure 22 This is a cross-sectional schematic diagram of the structure obtained in step S33' of a method for manufacturing a memory provided in some embodiments;

[0078] Figure 23 This is a cross-sectional schematic diagram of the structure obtained in step S34' of a method for manufacturing a memory provided in some embodiments;

[0079] Figure 24 This is a schematic cross-sectional view of the structure obtained in step S35' of a method for manufacturing a memory provided in some embodiments;

[0080] Figure 25 This is a cross-sectional schematic diagram of the structure obtained in step S36' of a method for manufacturing a memory provided in some embodiments;

[0081] Figure 26 This is a schematic cross-sectional view of the structure obtained in step S37' of a method for manufacturing a memory provided in some embodiments;

[0082] Figure 27 This is a cross-sectional schematic diagram of another structure obtained in step S50 of a method for manufacturing a memory provided in some embodiments;

[0083] Figure 28 This is a cross-sectional schematic diagram of another structure obtained in step S60 of a method for manufacturing a memory provided in some embodiments.

[0084] Figure label:

[0085] 11-First gate; 12-First source / drain; 13-Second source / drain; 14-First semiconductor layer; 15-First gate dielectric layer;

[0086] 21-Second gate; 22-Third source / drain; 23-Fourth source / drain; 24-Second semiconductor layer; 25-Second gate dielectric layer;

[0087] 31-Third gate; 32-Third gate dielectric layer;

[0088] 1-Semiconductor material layer; 2-Gate dielectric material layer; 3-Second conductive material layer;

[0089] T W - Write transistor; T R - Read transistor; WL1 - Write word line; WL2 - Read word line; BL1 - Write bit line; VBL1 - Virtual write bit line; BL2 - Read bit line; SL - Common source line; A - First part; B - Second part; K1 - Etched hole; K2 - Receptacle hole; V G - Virtual gate; C1 - Receiving groove; C2 - Receiving space; L1 - Dielectric material; L2 - Insulating material. Detailed Implementation

[0090] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, which illustrate embodiments of the present disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0091] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0092] The term "embodiment" in this document means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this disclosure. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0093] It is understood that the terms "first," "second," "third," "fourth," etc., used herein may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first transistor may be referred to as a second transistor, and similarly, a second transistor may be referred to as a first transistor. Both the first transistor and the second transistor are transistors, but they are not the same transistor.

[0094] It is understood that the term "connection" in the following embodiments should be understood as "electrical connection," "communication connection," etc., if the connected circuits, modules, units, etc., have electrical signal or data transmission with each other.

[0095] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0096] When used here, "deposition" processes include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD).

[0097] Currently, various 3D dynamic random access memories (DRAMs) are widely studied. Among them, the 2TOC (Total Transistor) structure DRAM operates by using a write transistor to control the write operation. The gate of the write transistor is connected to the write word line. When the write word line is high, a certain voltage is input through the write bit line connected to the source and drain of the write transistor. This transistor typically uses a wide-bandgap oxide semiconductor to ensure that a small amount of charge is locked on the gate of the read transistor and the connected wires after it is turned off, serving as a storage node. Data is then read based on the read word line and read bit line connected to the source and drain of the read transistor. However, the 2TOC structure DRAM is prone to problems such as read current multipathing and read current congestion during data reading, which adversely affects the performance of the DRAM.

[0098] Based on this, the present disclosure provides a storage unit, a memory, a method for manufacturing the same, and an electronic device, which can help improve the performance and reliability of the storage unit and the memory.

[0099] Please see Figures 1-3 The memory unit provided in some embodiments of this disclosure includes: a write transistor T W and read transistor T R Write transistor T W Includes a first gate 11, a first source / drain 12, and a second source / drain 13. Read transistor T R It includes a second gate 21, a third source-drain 22, and a fourth source-drain 23; the first gate 11 is electrically connected to the write word line WL1, the first source-drain 12 is electrically connected to the write bit line BL1, and the second source-drain 13 is electrically connected to the second gate 21. The read transistor T... R It also includes: a third gate 31, which is insulated and disposed on one side of the connection between the second source / drain 13 and the second gate 21; wherein the third gate 31 is electrically connected to the read word line WL2, the fourth source / drain 23 is electrically connected to the read bit line BL2, and the third source / drain 22 is electrically connected to the common source line SL.

[0100] In this embodiment of the disclosure, through the read transistor T of the memory cell R A third gate 31 is added internally, and the third gate 31 is isolated from the write transistor T. W The second source / drain 13 and the read transistor T RThe third gate 31 is connected to the second gate 21 on one side of the connection portion (i.e., the memory node), and the third gate 31 is electrically connected to the read word line WL2. Thus, during a read operation, the read word line WL2 in the selected memory cell is at a normal potential, and the read word line WL2 in the unselected memory cell is at a low potential. The third gate 31, connected to the low-potential read word line WL2, can transfer more positive charge from the read transistor T. R The channel is drawn away to ensure that the read transistor T of the unselected memory cell is not selected. R This is an electrically inactive state, thus solving the problem of multiple read transistors T being controlled by the same read word line WL2 during read operations. R The read current caused by the storage nodes will bypass the multipath problem caused by multiple storage nodes. It can avoid the voltage drop problem caused by leakage current flowing out of different read bit lines BL2 under the control of the same read word line WL2, as well as avoid the problem of interference between different storage cells, thereby improving the performance and reliability of storage cells and memory.

[0101] Furthermore, in this embodiment of the disclosure, the read transistor T is... R The third source drain 22 and the common source line SL are electrically connected, which facilitates the connection of multiple adjacent memory cells into a single chip through the common source line SL, so as to solve the problem of current congestion and optimize the structure of the memory.

[0102] For example, the write word line WL1 and the first gate 11 can be formed synchronously. The read word line WL2 and the third gate 31 can be formed synchronously. For instance, the write word line WL1 and the first gate 11 can be an integral structure formed synchronously using a synchronous process. The read word line WL2 and the third gate 31 can be an integral structure formed synchronously using a synchronous process.

[0103] In some embodiments, please refer to Figure 1 and Figure 2 The read bit line BL2 and the write bit line BL1 are arranged in parallel and spaced apart, extending along a first direction (e.g., the X direction). Write transistor T W and read transistor T R The transistors are arranged side-by-side in a second direction (e.g., the Y direction) and within the gap between read bit line BL2 and write bit line BL1; the second direction (e.g., the Y direction) intersects with the first direction (e.g., the X direction). A common source line SL surrounds the read transistor T. R The periphery, and along the back of the read transistor T R The common source line SL extends along the center line in the second direction (e.g., the Y direction); the third direction (e.g., the Z direction) intersects both the first direction (e.g., the X direction) and the second direction (e.g., the Y direction).

[0104] In some embodiments, please refer to Figure 2Write transistor T W Includes the first semiconductor layer 14. Read transistor T R The system includes a second semiconductor layer 24. A first gate 11 and a write bit line WL1 extend along a third direction (e.g., the Z direction). A first semiconductor layer 14 is disposed around the periphery of the first gate 11, and the center line of the first semiconductor layer 14 extends along a third direction (e.g., the Z direction). The portion of the first semiconductor layer 14 extending along a first direction (e.g., the X direction) and electrically connected to the write bit line BL1 is the first source / drain 12. The portion of the first semiconductor layer 14 that contacts the second gate 21 and is located on the side of the first gate 11 opposite to the first source / drain 12 is the second source / drain 13. The second gate 21 extends along a second direction (e.g., the Y direction) and includes: a first portion A electrically connected to the second source / drain 13, and a second portion B located on the side of the first portion A opposite to the second source / drain 13 and electrically connected to the first portion A. The second semiconductor layer 24 is disposed around the periphery of the second portion B and on the side of the second portion B opposite to the first portion A. The center line of the second semiconductor layer 24 extends along a second direction (e.g., the Y direction). The portion of the second semiconductor layer 24 surrounding the second part B and connected to the common source line SL is the third source / drain 22. The portion of the second semiconductor layer 24 located on the side of the second part B away from the first part A is the fourth source / drain 23.

[0105] In some embodiments, the third gate 31 extends along a third direction (e.g., the Z direction). The third gate 31 is insulated on one side of the first portion A in the first direction (e.g., the X direction).

[0106] In some embodiments, the write transistor T W It also includes a first gate dielectric layer 15. Read transistor T R It also includes a second gate dielectric layer 25 and a third gate dielectric layer 32 connected to each other. The first gate dielectric layer 15 is located between the first gate 11 and the first semiconductor layer 14. The second gate dielectric layer 25 is located between the second portion B and the second semiconductor layer 24. The third gate dielectric layer 32 is disposed around the periphery of the third gate 31 and is connected to both the second gate dielectric layer 25 and the second gate 21.

[0107] In some embodiments, please refer to Figure 3 The first gate 11 is electrically connected to the write word line WL1, the first source-drain 12 is electrically connected to the write bit line BL1, the second source-drain 13 is electrically connected to the second gate 21, the third gate 31 is electrically connected to the read word line WL2, the fourth source-drain 23 is electrically connected to the read bit line BL2, and the third source-drain 22 is electrically connected to the common source line SL.

[0108] In other embodiments, please refer to Figure 4 and Figure 5The write word line WL1 is multiplexed as the read word line WL2 during the data read phase. The first gate 11 is multiplexed as the third gate 31 during the data read phase.

[0109] In this embodiment of the disclosure, the write word line WL1 is multiplexed into the read word line WL2 during the data reading phase, and the write transistor T... W The first gate 11 is multiplexed as the read transistor T during the data read phase. R The third gate 31 is beneficial to further simplify the structure and process of the memory cell and memory.

[0110] In some embodiments, please refer to Figure 5 The dimension of the first part A in the first direction (e.g., the X direction) is greater than the dimension of the second part B in the first direction (e.g., the X direction). The dimension of the first part A in the second direction (e.g., the Y direction) is smaller than the dimension of the second part B in the second direction (e.g., the Y direction).

[0111] In this embodiment of the disclosure, the size of the first part A in the first direction (e.g., the X direction) is larger than the size of the second part B in the first direction (e.g., the X direction), and the size of the first part A in the second direction (e.g., the Y direction) is smaller than the size of the second part B in the second direction (e.g., the Y direction). Thus, the read transistor T... R With write transistor T W Wider contact area, read transistor T R的 The groove is narrower, which gives the writing line WL1 greater control over the reading line WL2.

[0112] In some embodiments, the write transistor T W It also includes a first gate dielectric layer 15. Read transistor T R It also includes a second gate dielectric layer 25 and a third gate dielectric layer 32 that are connected to each other. The first gate dielectric layer 15 is located between the first gate 11 and the first semiconductor layer 14. The second gate dielectric layer 25 is located between the second portion B and the second semiconductor layer 24. The third gate dielectric layer 32 is located between the first portion A and the second semiconductor layer 24.

[0113] In some embodiments, the size of the first semiconductor layer 14 in a first direction (e.g., the X direction) is greater than the maximum size of the second gate 21 in the first direction (e.g., the X direction).

[0114] In some embodiments, this disclosure also provides a memory, including one or more memory cells as described in any of the foregoing embodiments. The memory also possesses all the technical advantages of the aforementioned memory cells, and will not be detailed here.

[0115] This disclosure also provides a data read / write method in some embodiments, applied to a memory as described in any of the foregoing embodiments. This data read / write method possesses all the technical advantages of the aforementioned memory, and will not be detailed here. Write transistor T W The second source / drain 13 and the read transistor T R The connection portion of the second gate 21 is the storage node of the memory cell. Data read / write methods include:

[0116] S1: During the data writing phase, in response to the write command, the write bit line BL1 is connected to the write transistor T. W Provides data voltage; write word line WL1 controls write transistor T W When the circuit is turned on, the storage node discharges to a stable state in order to write the data corresponding to the data voltage.

[0117] S2: During the data reading phase, in response to the read command, the read word line WL2 in the selected memory cell is set to a normal potential, and the read word line WL2 in the unselected memory cell is set to a low potential. This causes the third gate 31, which is connected to the read word line WL2 with the low potential, to transfer more positive charge from the read transistor T. R The channel draws away the read transistor T from the unselected memory cell. R It is in a state of electrical non-continuity.

[0118] In other embodiments, the write word line WL1 is multiplexed as the read word line WL2 during the data read phase. The first gate 11 is multiplexed as the third gate 31 during the data read phase.

[0119] During the data reading phase, in response to a read command, the read word line WL2 in the selected memory cell is set to a normal potential, while the read word line WL2 in the unselected memory cell is set to a low potential. This causes the first gate 11 connected to the read word line WL2 with the low potential to transfer more positive charge from the read transistor T. R The channel draws away the read transistor T from the unselected memory cell. R It is in a state of electrical non-continuity.

[0120] This disclosure also provides a method for fabricating a memory in some embodiments, for fabricating the memory described in the above embodiments. This manufacturing method also possesses all the technical advantages of the aforementioned memory.

[0121] Please see Figure 6 and combined Figures 1-3 It is understood that the manufacturing method includes the following steps.

[0122] S10: A first conductive material layer and an insulating material layer are sequentially deposited on the wafer to form a stacked structure.

[0123] S20: Forming read bit lines and write bit lines that are arranged in parallel intervals and extend along the first direction.

[0124] S30: A read transistor and a write transistor are formed side by side in a second direction within the interval between the read bit line and the write bit line; the write transistor includes a first gate, a first source drain, and a second source drain; the read transistor includes a second gate, a third gate, a third source drain, and a fourth source drain; wherein the first source drain is electrically connected to the write bit line, the second source drain is electrically connected to the second gate, and the fourth source drain is electrically connected to the read bit line; the third gate is insulated and disposed on one side of the connection between the second source drain and the second gate; the first direction and the second direction intersect, and both the first direction and the second direction are parallel to the wafer surface.

[0125] S40: Form a write line electrically connected to the first gate.

[0126] S50: Forms a read line electrically connected to the third gate.

[0127] S60: Forms a common source line that is electrically connected to the third source drain.

[0128] In some embodiments, step S20, forming read bit lines and write bit lines arranged in parallel and extending along a first direction, includes: forming a first conductive material layer and patterning the first conductive material layer, forming read bit lines and write bit lines arranged in parallel and spaced apart, and a virtual gate located between the read bit lines and write bit lines and connecting the read bit lines and write bit lines; wherein the read bit lines and write bit lines extend along the first direction, and the virtual gate extends along a second direction.

[0129] In some embodiments, please refer to Figure 7 Step S30 involves forming a read transistor and a write transistor arranged side-by-side in the second direction within the interval between the read bit line and the write bit line, including the following steps:

[0130] S31: The two sides of the virtual gate opposite each other in the first direction are filled with dielectric material.

[0131] S32: Etch the virtual gate and dielectric material in the first target area near the write bit line to form an etching hole.

[0132] S33: Based on the etched hole, the retained virtual gate is removed to form a receiving groove; the receiving groove exposes the corresponding sidewall of the read bit line.

[0133] S34: A semiconductor material layer, a gate dielectric material layer, and a second conductive material layer are sequentially deposited on the inner wall of the receiving tank.

[0134] S35: Remove the semiconductor material layer, gate dielectric material layer, and second conductive material layer inside the etched hole, such that the remaining gate dielectric material layer constitutes the second gate dielectric layer and the remaining second conductive material layer constitutes the second gate; and remove the semiconductor material layer in the second target region near the etched hole, such that the remaining semiconductor material layer constitutes the second semiconductor layer and exposes the sidewall of the second gate dielectric layer.

[0135] S36: Etch dielectric material on the sidewall of the second gate dielectric layer exposed on one side in the first direction to form a receiving hole; the receiving hole exposes the sidewall of the second semiconductor layer away from the read bit line.

[0136] S37: A third gate dielectric layer and a third gate are sequentially formed within the accommodating hole.

[0137] S38: A first semiconductor layer, a first gate dielectric layer, and a first gate are sequentially formed on the wall of the etched hole to obtain a write transistor.

[0138] To more clearly illustrate the memory fabrication methods in some of the above embodiments, the following embodiments provide illustrative examples of some possible specific implementations of certain steps.

[0139] In step S20, please refer to Figure 8 A first conductive material layer (not shown) is formed and patterned to form a read bit line BL2 and a write bit line BL1 arranged in parallel and spaced apart, and a virtual gate V located between the read bit line BL2 and the write bit line BL1 and connecting the read bit line BL2 and the write bit line BL1. G Among them, read bit line BL2 and write bit line BL1 extend along a first direction (e.g., the X direction), and the virtual gate V G Extend along a second direction (e.g., the Y direction).

[0140] It is important to note here that in the three-dimensional stacked structure, the first semiconductor layers corresponding to different first conductive material layers are separated. That is, multiple layers of first conductive material layers and multiple sacrificial layers are formed in alternating layers. The sacrificial layers are removed as needed to correspond to the subsequent lateral etching of the first semiconductor material layers to obtain the first semiconductor layer of each write transistor.

[0141] For example, the first conductive material layer includes a metal layer, such as a tungsten metal layer.

[0142] For example, the sacrificial layer includes, but is not limited to, a silicon nitride layer.

[0143] Here, each first conductive material layer and each sacrificial layer can be formed using a deposition process.

[0144] In step S31, please refer to Figure 9 At the virtual gate V GMedium material L1 is filled on opposite sides in a first direction (e.g., the X direction).

[0145] For example, the dielectric material L1 includes, but is not limited to, silicon oxide.

[0146] Here, the dielectric material L1 can be formed using a deposition process. Furthermore, after the dielectric material L1 is formed using a deposition process, a chemical mechanical polishing (CMP) process can be used to grind the upper surface of the dielectric material L1 to ensure that the upper surface of the dielectric material L1 is smooth.

[0147] In step S32, please refer to Figure 10 At the virtual gate V G The virtual gate V is etched in the first target region near the write bit line BL1. G Together with the dielectric material L1, an etched hole K1 is formed.

[0148] Here, dry etching can be used to form the etched hole K1.

[0149] In step S33, please refer to Figure 11 Based on the etched hole K1, the virtual gate V is selectively etched along the second direction (e.g., the Y direction) by wet etching. G Remove the retained virtual gate V G This forms a receiving groove C1; the receiving groove C1 exposes the corresponding sidewall of the read line BL2.

[0150] Here, wet etching can be used to remove the retained dummy gate V. G This forms the receiving groove C1.

[0151] In step S34, please refer to Figure 12 Semiconductor material layer 1, gate dielectric material layer 2, and second conductive material layer 3 are sequentially deposited on the inner wall of the accommodating tank C1 using atomic layer deposition technology.

[0152] Here, atomic layer deposition (ALD) can be used to sequentially deposit semiconductor material layer 1, gate dielectric material layer 2, and second conductive material layer 3.

[0153] For example, the semiconductor material layer 1 includes, but is not limited to, a metal oxide semiconductor layer, such as an indium gallium zinc oxide (IGZO) layer.

[0154] For example, the gate dielectric material layer 2 includes, but is not limited to, an HK (high-K) dielectric layer. An HK dielectric layer refers to a dielectric layer with a high dielectric constant K, for example, greater than 3.9.

[0155] For example, the material of the second conductive material layer 3 includes, but is not limited to, tungsten metal.

[0156] In step S35, please refer to Figure 13 Remove the semiconductor material layer 1, the gate dielectric material layer 2, and the second conductive material layer 3 within the etched hole K1, such that the remaining gate dielectric material layer 2 constitutes the second gate dielectric layer 25, and the remaining second conductive material layer 3 constitutes the second gate 21; and remove the semiconductor material layer 1 in the second target area near the etched hole K1, such that the remaining semiconductor material layer 1 constitutes the second semiconductor layer 24, and expose the sidewalls of the second gate dielectric layer 25.

[0157] Here, after removing the semiconductor material layer 1 in the second target area near the etched hole K1, it is necessary to backfill with insulating material L2.

[0158] For example, the insulating material L2 includes, but is not limited to, silicon oxide.

[0159] For example, step S35 further includes: backfilling the area of ​​the etched hole K1 near the write bit line BL1 with a second conductive material layer 3.

[0160] In step S36, please refer to Figure 14 The dielectric material is etched on the sidewall of the second gate 21 exposed in the first direction (e.g., the X direction) to form a accommodating hole K2; the accommodating hole K2 exposes the sidewall of the second gate dielectric layer 25 and the second semiconductor layer 24 away from the read bit line BL2.

[0161] Here, the receiving hole K2 and the etched hole K1 are spaced apart along a second direction (e.g., the Y direction).

[0162] For example, dry etching can be used to form the etched hole K2.

[0163] In step S37, please refer to Figure 15 A third gate dielectric layer 32 and a third gate 31 are sequentially formed within the accommodating hole K2.

[0164] For example, the third gate dielectric layer 32 includes, but is not limited to, an HK (high-K) dielectric layer. An HK dielectric layer refers to a dielectric layer having a high dielectric constant K, for example, greater than 3.9. The material of the third gate 31 includes, but is not limited to, tungsten.

[0165] In step S38, please refer to Figure 16 A first semiconductor layer 14, a first gate dielectric layer 15, and a first gate 11 are sequentially formed on the wall of the etched hole K1 to obtain a write transistor T. W .

[0166] For example, the first semiconductor layer 14 includes, but is not limited to, a metal oxide semiconductor layer, such as an IGZO layer. The first gate dielectric layer 15 includes, but is not limited to, an HK dielectric layer. The material of the first gate 11 includes, but is not limited to, tungsten.

[0167] Please continue reading. Figure 16 Understanding, writing about transistor T W The system includes a first gate 11, a first source-drain 12, and a second source-drain 13; the read transistor includes a second gate 21, a third gate 31, a third source-drain 22, and a fourth source-drain 23; wherein the first source-drain 12 is electrically connected to the write bit line BL1, the second source-drain 13 is electrically connected to the second gate 21, and the fourth source-drain 23 is electrically connected to the read bit line BL2; the third gate 31 is insulated and disposed on one side of the connection between the second source-drain 13 and the second gate 21. The portion of the second semiconductor layer 24 located on the side of the second gate 21 opposite to the first gate 11 is the fourth source-drain 23. The portion of the first semiconductor layer 14 extending along a first direction (e.g., the X direction) and electrically connected to the write bit line BL1 is the first source-drain 12, and the portion of the first semiconductor layer 14 extending along a first direction (e.g., the X direction) located on the side of the first gate 11 opposite to the first source-drain 12 is the second source-drain 13.

[0168] In step S40, please refer to Figure 16 This forms a write line WL1 that is electrically connected to the first gate 11.

[0169] Here, the writing line WL1 is formed synchronously with the first gate 11.

[0170] In step S50, please continue reading. Figure 16 This forms a read line WL2 that is electrically connected to the third gate 31.

[0171] Here, the word line WL2 is formed synchronously with the third gate 31.

[0172] In step S60, please refer to Figure 17 This forms a common source line SL that is electrically connected to the third source drain 22.

[0173] Here, the common source line SL includes, but is not limited to, metallic tungsten.

[0174] For example, forming a common source line SL electrically connected to the third source drain 22 includes: first etching the dielectric material L1 to expose the periphery of the second semiconductor layer 24, and then backfilling the material to form the common source line SL.

[0175] The portion of the second semiconductor layer 24 that surrounds the second gate 21 and is connected to the common source line SL is the third source / drain 22.

[0176] In other embodiments, the write line WL1 is multiplexed as the read line WL2 during the data reading phase, and the first gate 11 is multiplexed as the third gate 31 during the data reading phase.

[0177] Accordingly, in some other embodiments, forming the parallel-spaced read bit lines and write bit lines extending along the first direction in step S20 includes: forming a first conductive material layer and patterning the first conductive material layer; forming the parallel-spaced read bit lines and virtual write bit lines; and a virtual gate V located between the read bit lines and virtual write bit lines and connecting the read bit lines and virtual write bit lines. G Among them, the read bit line and the virtual write bit line extend along the first direction, and the virtual gate V G Extend along a second direction (e.g., the Y direction).

[0178] Accordingly, in some other embodiments, please refer to Figure 18 and combined Figure 4 , Figure 5 It is understood that step S30, which involves forming read transistors and write transistors arranged side-by-side in the second direction within the interval between the read bit line and the write bit line, may further include the following steps:

[0179] S31': Dielectric material is filled on both sides of the virtual gate opposite each other in the first direction;

[0180] S32': Etch the virtual gate and dielectric material in the first target region near the virtual write bit line to form an etching hole;

[0181] S33': Based on the etched hole, the virtual write bit line and the retained virtual gate are removed to form an accommodating space including the etched hole; the accommodating space exposes the corresponding sidewall of the read bit line;

[0182] S34': Sequentially deposit a semiconductor material layer, a gate dielectric material layer, and a second conductive material layer within the accommodating space;

[0183] S35': Remove the semiconductor material layer, gate dielectric material layer, and second conductive material layer in the first target region, as well as the semiconductor material layer, gate dielectric layer, and second conductive material layer in the third and fourth target regions adjacent to the first target region along the second direction, so that the retained semiconductor material layer constitutes the second semiconductor layer, the retained gate dielectric material layer constitutes the second gate dielectric layer, the second conductive material layer retained in the third target region near the read bit line is the second part of the second gate, and the second conductive material layer retained in the fourth target region away from the read bit line is the write bit line;

[0184] S36': A third gate dielectric layer is formed on the sidewall of the second semiconductor layer and the second gate dielectric layer away from the read bit line;

[0185] S37': A first part of the second gate is formed in the third target region on the sidewall of the second part and the third gate dielectric layer away from the read bit line;

[0186] S38': A first semiconductor layer, a first gate dielectric layer, and a first gate are sequentially formed on the hole wall between the first part and the write bit line to obtain a write transistor.

[0187] Similarly, to more clearly illustrate the memory fabrication methods in some of the above embodiments, the following embodiments exemplarily provide some specific implementations of certain steps.

[0188] In step S20, please refer to Figure 19 The method for forming read bit lines BL2 and write bit lines BL1 arranged in parallel and extending along a first direction (e.g., the X direction) includes: forming a first conductive material layer (not shown) and patterning the first conductive material layer; forming read bit lines BL2 and virtual write bit lines VBL1 arranged in parallel and spaced apart; and a virtual gate V located between read bit lines BL2 and virtual write bit lines VBL1 and connecting read bit lines BL2 and virtual write bit lines VBL1. G Among them, the read bit line BL2 and the virtual write bit line VBL1 extend along the first direction (e.g., the X direction), and the virtual gate V... G Extend along a second direction (e.g., the Y direction).

[0189] It is important to note here that in the three-dimensional stacked structure, the first semiconductor layers corresponding to different first conductive material layers are separated. That is, multiple layers of first conductive material layers and multiple sacrificial layers are formed in alternating layers. The sacrificial layers are removed as needed to correspond to the subsequent lateral etching of the first semiconductor material layers to obtain the first semiconductor layer of each write transistor.

[0190] For example, the first conductive material layer includes a metal layer, such as a tungsten metal layer.

[0191] For example, the sacrificial layer includes, but is not limited to, a silicon nitride layer.

[0192] Here, each first conductive material layer and each sacrificial layer can be formed using a deposition process.

[0193] In step S31', please refer to Figure 20 At the virtual gate V G Medium material L1 is filled on opposite sides in a first direction (e.g., the X direction).

[0194] For example, the dielectric material L1 includes, but is not limited to, silicon oxide.

[0195] Here, the dielectric material L1 can be formed using a deposition process. Furthermore, after forming the dielectric material L1 using a deposition process, the upper surface of the dielectric material L1 can be polished using a chemical mechanical polishing (CMP) process to ensure a smooth upper surface.

[0196] In step S32', please refer to Figure 21 At the virtual gate V G The virtual gate V is etched in the first target region near the virtual write bit line VBL1. G Together with the dielectric material L1, an etched hole K1 is formed.

[0197] Here, dry etching can be used to form the etched hole K1.

[0198] In step S33', please refer to Figure 22 Based on the etched hole K1, the virtual write bit line VBL1 and the retained virtual gate V are removed. G This forms a accommodating space C2, which includes the etched hole K1; the accommodating space exposes the corresponding sidewall of the read line BL2.

[0199] For example, based on the etched via K1, the dummy write bit line VBL1 is removed and the remaining dummy gate V is removed. G This forms a accommodating space C2, and also includes: virtual write bit line VBL1 and reserved virtual gate V G Perform a wet etching process along a second direction (e.g., the Y direction) and a first direction (e.g., the X direction) to form the accommodating space C2.

[0200] In step S34', please refer to Figure 23 Semiconductor material layer 1, gate dielectric material layer 2, and second conductive material layer 3 are sequentially deposited within the accommodating space C2.

[0201] For example, the semiconductor material layer 1 includes, but is not limited to, a metal oxide semiconductor layer, such as an indium gallium zinc oxide (IGZO) layer.

[0202] For example, the gate dielectric material layer 2 includes, but is not limited to, the HK dielectric layer.

[0203] For example, the material of the second conductive material layer 3 includes, but is not limited to, tungsten metal.

[0204] Here, an ALD process can be used to sequentially deposit a semiconductor material layer 1, a gate dielectric material layer 2, and a second conductive material layer 3.

[0205] In step S35', please refer to Figure 24The semiconductor material layer 1, gate dielectric material layer 2, and second conductive material layer 3 in the first target region, as well as the semiconductor material layer 1, gate dielectric layer 2, and second conductive material layer 3 in the third and fourth target regions adjacent to the first target region along the second direction (e.g., the Y direction), are removed, so that the retained semiconductor material layer 1 constitutes the second semiconductor layer 24, the retained gate dielectric material layer 2 constitutes the second gate dielectric layer 25, the second conductive material layer 3 retained in the third target region near the read bit line is the second part B of the second gate 21, and the second conductive material layer 3 retained in the fourth target region away from the read bit line BL2 is the write bit line BL1.

[0206] Here, dry etching can be used to remove the semiconductor material layer 1, the gate dielectric material layer 2, and the second conductive material layer 3 in the first target area. Then, wet etching can be used to remove the semiconductor material layer 1, the gate dielectric material layer 2, and the second conductive material layer 3 in the third and fourth target areas along the second direction (e.g., the Y direction). The second conductive material layer 3 retained in the third target area near the read bit line is the second part B of the second gate 21, and the second conductive material layer 3 retained in the fourth target area away from the read bit line BL2 is the write bit line BL1.

[0207] In step S36', please refer to Figure 25 A third gate dielectric layer 32 is formed on the sidewall of the second semiconductor layer 24 and the second gate dielectric layer 25 away from the read bit line BL2.

[0208] For example, the third gate dielectric layer 32 includes, but is not limited to, the HK dielectric layer.

[0209] In step S37', please refer to Figure 26 The first part A of the second gate 21 is formed in the third target region, on the sidewall of the second part B and the third gate dielectric layer 32 away from the read bit line BL2.

[0210] Here, while forming the first part A of the second gate 21, the second conductive material layer 3 is backfilled in the fourth target region.

[0211] In step S38', please refer to Figure 27 A first semiconductor layer 14, a first gate dielectric layer 15, and a first gate 11 are sequentially formed on the wall of the hole K1 etched between the first part A and the write bit line BL1 to obtain the write transistor T. W .

[0212] For example, the first semiconductor layer 14 includes, but is not limited to, a metal oxide semiconductor layer, such as an indium gallium zinc oxide (IGZO) layer.

[0213] For example, the first gate dielectric layer 15 includes, but is not limited to, the HK dielectric layer.

[0214] For example, the material of the first gate 11 includes, but is not limited to, tungsten metal.

[0215] Here, the first semiconductor layer 14, the first gate dielectric layer 15, and the first gate 11 can be deposited sequentially using the ALD process.

[0216] Please continue reading. Figure 27 Understanding, writing about transistor T W The system includes a first gate 11, a first source-drain 12, and a second source-drain 13; the read transistor includes a second gate 21, a third gate 31, a third source-drain 22, and a fourth source-drain 23; wherein the first source-drain 12 is electrically connected to the write bit line BL1, the second source-drain 13 is electrically connected to the second gate 21, and the fourth source-drain 23 is electrically connected to the read bit line BL2; the third gate 31 is insulated and disposed on one side of the connection between the second source-drain 13 and the second gate 21. The portion of the second semiconductor layer 24 located on the side of the second part B away from the first part A is the fourth source-drain 23. The portion of the first semiconductor layer 14 extending along a first direction (e.g., the X direction) and electrically connected to the write bit line BL1 is the first source-drain 12, and the portion of the first semiconductor layer 14 extending along a first direction (e.g., the X direction) located on the side of the first gate 11 away from the first source-drain 12 is the second source-drain 13.

[0217] In step S40, please refer to Figure 27 This forms a write line WL1 that is electrically connected to the first gate 11.

[0218] Here, the writing line WL1 is formed synchronously with the first gate 11.

[0219] In step S50, please continue reading. Figure 27 This forms a read line WL2 that is electrically connected to the third gate 31.

[0220] Here, the write word line WL1 is multiplexed as the read word line WL2 during the data reading phase, and the first gate 11 is multiplexed as the third gate 31 during the data reading phase. The read word line WL2 and the third gate 31 are formed synchronously.

[0221] In step S60, please refer to Figure 28 This forms a common source line SL that is electrically connected to the third source drain 22.

[0222] Here, the common source line SL includes, but is not limited to, metallic tungsten.

[0223] For example, forming a common source line SL electrically connected to the third source drain 22 includes: first etching the dielectric material L1 to expose the periphery of the second semiconductor layer 24, and then backfilling the material to form the common source line SL.

[0224] The portion of the second semiconductor layer 24 that surrounds the second part B and is connected to the common source line SL is the third source / drain electrode 22.

[0225] This disclosure also provides an electronic device in some embodiments, including one or more memories as described in the foregoing embodiments. Examples include data storage devices, photocopiers, network devices, home appliances, instruments, mobile phones, computers, and other devices with data storage functions. The electronic device may include a housing and a circuit board disposed within the housing, and a memory or data read / write circuit integrated on the circuit board. The structure of the memory can be referred to the relevant descriptions in the foregoing embodiments. The electronic device may also include other necessary elements or components, which are not limited in this disclosure.

[0226] In some embodiments, the memory may be coupled to an external control device such as a processor or actuator. The processor is coupled to the memory, and the processor is able to control the read and write operations of the memory.

[0227] In some embodiments, the memory is a 3D dynamic random access memory.

[0228] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0229] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A storage unit, characterized in that, include: A write transistor and a read transistor; the write transistor includes a first gate, a first source-drain, and a second source-drain; the read transistor includes a second gate, a third source-drain, and a fourth source-drain; the first gate is electrically connected to the write word line, the first source-drain is electrically connected to the write bit line, and the second source-drain is electrically connected to the second gate; The read transistor further includes: The third gate is insulated and disposed on one side of the connection between the second source / drain and the second gate; The third gate is electrically connected to the read word line, the fourth source / drain is electrically connected to the read bit line, and the third source / drain is electrically connected to the common source line.

2. The storage unit according to claim 1, characterized in that, The read bit lines and the write bit lines are arranged in parallel at intervals and extend along the first direction; The write transistor and the read transistor are arranged side by side in the second direction and are disposed within the interval between the read bit line and the write bit line; The second direction intersects with the first direction; The common source line surrounds the periphery of the read transistor and extends in a direction away from the read transistor; the center line of the common source line extends in the second direction.

3. The storage unit according to claim 2, characterized in that, The write transistor includes a first semiconductor layer; the read transistor includes a second semiconductor layer; The first gate and the writing line extend along a third direction; the third direction intersects both the first direction and the second direction; The first semiconductor layer is disposed around the periphery of the first gate, and the center line of the first semiconductor layer extends along the third direction; the portion of the first semiconductor layer extending along the first direction and electrically connected to the write bit line is the first source / drain, and the portion of the first semiconductor layer that contacts the second gate and is located on the side of the first gate away from the first source / drain is the second source / drain. The second gate extends along the second direction and includes: a first portion electrically connected to the second source and drain, and a second portion located on the side of the first portion away from the second source and drain and electrically connected to the first portion; The second semiconductor layer is disposed around the periphery of the second part and on the side of the second part away from the first part; the center line of the second semiconductor layer extends along the second direction; the portion of the second semiconductor layer disposed around the periphery of the second part and connected to the common source line is the third source / drain; the portion of the second semiconductor layer located on the side of the second part away from the first part is the fourth source / drain.

4. The storage unit according to claim 3, characterized in that, The third gate extends along the third direction; The third gate insulation is disposed on one side of the first part in the first direction.

5. The storage unit according to claim 4, characterized in that, The write transistor further includes a first gate dielectric layer; the read transistor further includes a second gate dielectric layer and a third gate dielectric layer connected to each other; wherein... The first gate dielectric layer is located between the first gate and the first semiconductor layer; The second gate dielectric layer is located between the second portion and the second semiconductor layer; The third gate dielectric layer is disposed around the periphery of the third gate and is connected to both the second gate dielectric layer and the second gate.

6. The storage unit according to claim 3, characterized in that, The write line is reused as the read line during the data reading phase; the first gate is reused as the third gate during the data reading phase.

7. The storage unit according to claim 6, characterized in that, The dimension of the first part in the first direction is larger than the dimension of the second part in the first direction; The dimension of the first part in the second direction is smaller than the dimension of the second part in the second direction.

8. The storage unit according to claim 6, characterized in that, The write transistor further includes a first gate dielectric layer; the read transistor further includes a second gate dielectric layer and a third gate dielectric layer connected to each other; wherein... The first gate dielectric layer is located between the first gate and the first semiconductor layer; The second gate dielectric layer is located between the second portion and the second semiconductor layer; The third gate dielectric layer is located between the first part and the second semiconductor layer.

9. The storage unit according to claim 4 or 6, characterized in that, The dimension of the first semiconductor layer in the first direction is greater than the maximum dimension of the second gate in the first direction.

10. A memory, characterized in that, include: One or more storage units as described in any one of claims 1 to 9.

11. A data read / write method, characterized in that, Applied to the memory as described in claim 10; the connection between the second source / drain of the write transistor and the second gate of the read transistor constitutes the storage node of the memory cell; the data read / write method includes: During the data writing phase, in response to a write command, the write bit line provides a data voltage to the write transistor; the write word line controls the write transistor to turn on, and the storage node discharges to a stable state to write the data corresponding to the data voltage. During the data reading phase, in response to a read command, the read word line in the selected memory cell is set to a normal potential, and the read word line in the unselected memory cell is set to a low potential, so that the third gate connected to the read word line with the low potential attracts more positive charge from the channel of the read transistor, and the read transistor in the unselected memory cell is electrically deactivated.

12. The data read / write method according to claim 11, characterized in that, The writing line is multiplexed as the reading line during the data reading phase; the first gate is multiplexed as the third gate during the data reading phase; During the data reading phase, in response to a read command, the read word line in the selected memory cell is set to a normal potential, and the read word line in the unselected memory cell is set to a low potential, so that the first gate connected to the read word line with the low potential attracts more positive charge from the channel of the read transistor, and the read transistor in the unselected memory cell is electrically deactivated.

13. A method for fabricating a memory, characterized in that, include: A first conductive material layer and an insulating material layer are sequentially deposited on a wafer to form a stacked structure; The read and write lines are arranged in parallel intervals and extend along the first direction; A read transistor and a write transistor are formed side-by-side in a second direction within the interval between the read bit line and the write bit line; the write transistor includes a first gate, a first source-drain, and a second source-drain; the read transistor includes a second gate, a third gate, a third source-drain, and a fourth source-drain; wherein the first source-drain is electrically connected to the write bit line, the second source-drain is electrically connected to the second gate, and the fourth source-drain is electrically connected to the read bit line; the third gate is insulated and disposed on one side of the connection between the second source-drain and the second gate; the first direction and the second direction intersect, and both the first direction and the second direction are parallel to the wafer surface; A write line is formed that is electrically connected to the first gate; Forming a read line electrically connected to the third gate; A common source line is formed that is electrically connected to the third source-drain electrode.

14. The method for fabricating a memory according to claim 13, characterized in that, The read bit lines and write bit lines arranged in parallel and extending along a first direction, and the read transistors and write transistors arranged side by side in a second direction within the interval between the read bit lines and the write bit lines, include: The first conductive material layer is patterned to form the read bit lines and write bit lines that are arranged in parallel and spaced apart, and a virtual gate located between the read bit lines and write bit lines and connecting the read bit lines and write bit lines; wherein the read bit lines and write bit lines extend along the first direction, and the virtual gate extends along the second direction; The virtual gate is filled with dielectric material on both sides opposite to each other in the first direction; The virtual gate and the dielectric material are etched in a first target region near the write bit line to form an etching hole; Based on the etched hole, the virtual gate is selectively etched along the second direction by wet etching to remove the retained virtual gate and form a receiving groove; the receiving groove exposes the corresponding sidewall of the read bit line; A semiconductor material layer, a gate dielectric material layer, and a second conductive material layer are sequentially deposited on the inner wall of the accommodating tank using an atomic layer deposition process. Remove the semiconductor material layer, the gate dielectric material layer, and the second conductive material layer within the etched hole, such that the remaining gate dielectric material layer constitutes the second gate dielectric layer, and the remaining second conductive material layer constitutes the second gate; and remove the semiconductor material layer in the second target region near the etched hole, such that the remaining semiconductor material layer constitutes the second semiconductor layer, and expose the sidewalls of the second gate dielectric layer; The dielectric material is etched outside the sidewall of the second gate exposed on one side in the first direction to form a receiving hole; the receiving hole exposes the sidewall of the second gate dielectric layer and the second semiconductor layer away from the read bit line; A third gate dielectric layer and a third gate are sequentially formed within the accommodating hole; A first semiconductor layer, a first gate dielectric layer, and a first gate are sequentially formed on the wall of the etched hole to obtain the write transistor; Wherein, the portion of the second semiconductor layer surrounding the second gate and connected to the common source line is the third source / drain; the portion of the second semiconductor layer located on the side of the second gate away from the first gate is the fourth source / drain. The portion of the first semiconductor layer extending along the first direction and electrically connected to the write bit line is the first source / drain electrode, and the portion of the first semiconductor layer extending along the first direction and located on the side of the first gate opposite to the first source / drain electrode is the second source / drain electrode. The writing line is formed synchronously with the first gate; The reading line is formed synchronously with the third gate.

15. The method for fabricating a memory according to claim 13, characterized in that, The write line is reused as the read line during the data reading phase, and the first gate is reused as the third gate during the data reading phase. The read bit lines and write bit lines arranged in parallel and extending along a first direction, and the read transistors and write transistors arranged side by side in a second direction within the interval between the read bit lines and the write bit lines, include: A first conductive material layer is formed and patterned to form the read bit line and the virtual write bit line arranged in parallel and spaced apart, and a virtual gate located between the read bit line and the virtual write bit line and connecting the read bit line and the virtual write bit line; wherein the read bit line and the virtual write bit line extend along the first direction, and the virtual gate extends along the second direction; The virtual gate is filled with dielectric material on both sides opposite to each other in the first direction; The virtual gate and the dielectric material are etched in a first target region near the virtual write bit line to form an etch hole; Based on the etched hole, the virtual write bit line and the remaining virtual gate are removed to form an accommodating space including the etched hole; the accommodating space exposes the corresponding sidewall of the read bit line; A semiconductor material layer, a gate dielectric material layer, and a second conductive material layer are sequentially deposited within the accommodating space; Remove the semiconductor material layer, the gate dielectric material layer, and the second conductive material layer from the first target region, as well as the semiconductor material layer, the gate dielectric material layer, and the second conductive material layer from the third and fourth target regions adjacent to the first target region along the second direction, so that the retained semiconductor material layer constitutes the second semiconductor layer, the retained gate dielectric material layer constitutes the second gate dielectric layer, the second conductive material layer retained in the third target region near the read bit line is the second part of the second gate, and the second conductive material layer retained in the fourth target region away from the read bit line is the write bit line; A third gate dielectric layer is formed on the sidewall of the second semiconductor layer and the second gate dielectric layer away from the read bit line; In the third target region, a first portion of the second gate is formed on the sidewall of the second portion and the third gate dielectric layer opposite to the read bit line; A first semiconductor layer, a first gate dielectric layer, and a first gate are sequentially formed on the wall of the etched hole between the first part and the write bit line to obtain the write transistor; The portion of the second semiconductor layer surrounding the second part and connected to the common source line is the third source / drain electrode; the portion of the second semiconductor layer located on the side of the second part away from the first part is the fourth source / drain electrode. The portion of the first semiconductor layer extending along the first direction and electrically connected to the write bit line is the first source / drain electrode, and the portion of the first semiconductor layer extending along the first direction and located on the side of the first gate opposite to the first source / drain electrode is the second source / drain electrode. The writing lines are formed synchronously with the first gate.

16. The method for fabricating a memory according to claim 15, characterized in that, The step of removing the virtual write bit line and the retained virtual gate based on the etched hole to form an accommodating space further includes: Wet etching processes along the second direction and the first direction are performed on the virtual write bit line and the reserved virtual gate to form the accommodating space.

17. An electronic device, characterized in that, include: One or more memories as described in claim 10.

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